1/* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22 * USE OR OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25#ifndef SI_STATE_H 26#define SI_STATE_H 27 28#include "pipebuffer/pb_slab.h" 29#include "si_pm4.h" 30#include "util/u_blitter.h" 31 32#ifdef __cplusplus 33extern "C" { 34#endif 35 36#define SI_NUM_GRAPHICS_SHADERS (PIPE_SHADER_TESS_EVAL + 1) 37#define SI_NUM_SHADERS (PIPE_SHADER_COMPUTE + 1) 38 39#define SI_NUM_VERTEX_BUFFERS SI_MAX_ATTRIBS 40#define SI_NUM_SAMPLERS 32 /* OpenGL textures units per shader */ 41#define SI_NUM_CONST_BUFFERS 16 42#define SI_NUM_IMAGES 16 43#define SI_NUM_IMAGE_SLOTS (SI_NUM_IMAGES * 2) /* the second half are FMASK slots */ 44#define SI_NUM_SHADER_BUFFERS 32 45 46struct si_screen; 47struct si_shader; 48struct si_shader_ctx_state; 49struct si_shader_selector; 50struct si_texture; 51struct si_qbo_state; 52 53struct si_state_blend { 54 struct si_pm4_state pm4; 55 uint32_t cb_target_mask; 56 /* Set 0xf or 0x0 (4 bits) per render target if the following is 57 * true. ANDed with spi_shader_col_format. 58 */ 59 unsigned cb_target_enabled_4bit; 60 unsigned blend_enable_4bit; 61 unsigned need_src_alpha_4bit; 62 unsigned commutative_4bit; 63 unsigned dcc_msaa_corruption_4bit; 64 bool alpha_to_coverage : 1; 65 bool alpha_to_one : 1; 66 bool dual_src_blend : 1; 67 bool logicop_enable : 1; 68 bool allows_noop_optimization : 1; 69}; 70 71struct si_state_rasterizer { 72 struct si_pm4_state pm4; 73 /* poly offset states for 16-bit, 24-bit, and 32-bit zbuffers */ 74 struct si_pm4_state *pm4_poly_offset; 75 unsigned pa_sc_line_stipple; 76 unsigned pa_cl_clip_cntl; 77 float line_width; 78 float max_point_size; 79 unsigned ngg_cull_flags : 8; 80 unsigned ngg_cull_flags_y_inverted : 8; 81 unsigned sprite_coord_enable : 8; 82 unsigned clip_plane_enable : 8; 83 unsigned half_pixel_center : 1; 84 unsigned flatshade : 1; 85 unsigned flatshade_first : 1; 86 unsigned two_side : 1; 87 unsigned multisample_enable : 1; 88 unsigned force_persample_interp : 1; 89 unsigned line_stipple_enable : 1; 90 unsigned poly_stipple_enable : 1; 91 unsigned line_smooth : 1; 92 unsigned poly_smooth : 1; 93 unsigned uses_poly_offset : 1; 94 unsigned clamp_fragment_color : 1; 95 unsigned clamp_vertex_color : 1; 96 unsigned rasterizer_discard : 1; 97 unsigned scissor_enable : 1; 98 unsigned clip_halfz : 1; 99 unsigned polygon_mode_is_lines : 1; 100 unsigned polygon_mode_is_points : 1; 101}; 102 103struct si_dsa_stencil_ref_part { 104 uint8_t valuemask[2]; 105 uint8_t writemask[2]; 106}; 107 108struct si_dsa_order_invariance { 109 /** Whether the final result in Z/S buffers is guaranteed to be 110 * invariant under changes to the order in which fragments arrive. */ 111 bool zs : 1; 112 113 /** Whether the set of fragments that pass the combined Z/S test is 114 * guaranteed to be invariant under changes to the order in which 115 * fragments arrive. */ 116 bool pass_set : 1; 117 118 /** Whether the last fragment that passes the combined Z/S test at each 119 * sample is guaranteed to be invariant under changes to the order in 120 * which fragments arrive. */ 121 bool pass_last : 1; 122}; 123 124struct si_state_dsa { 125 struct si_pm4_state pm4; 126 struct si_dsa_stencil_ref_part stencil_ref; 127 128 /* 0 = without stencil buffer, 1 = when both Z and S buffers are present */ 129 struct si_dsa_order_invariance order_invariance[2]; 130 131 ubyte alpha_func : 3; 132 bool depth_enabled : 1; 133 bool depth_write_enabled : 1; 134 bool stencil_enabled : 1; 135 bool stencil_write_enabled : 1; 136 bool db_can_write : 1; 137}; 138 139struct si_stencil_ref { 140 struct pipe_stencil_ref state; 141 struct si_dsa_stencil_ref_part dsa_part; 142}; 143 144struct si_vertex_elements { 145 struct si_resource *instance_divisor_factor_buffer; 146 uint32_t rsrc_word3[SI_MAX_ATTRIBS]; 147 uint16_t src_offset[SI_MAX_ATTRIBS]; 148 uint8_t fix_fetch[SI_MAX_ATTRIBS]; 149 uint8_t format_size[SI_MAX_ATTRIBS]; 150 uint8_t vertex_buffer_index[SI_MAX_ATTRIBS]; 151 152 /* Bitmask of elements that always need a fixup to be applied. */ 153 uint16_t fix_fetch_always; 154 155 /* Bitmask of elements whose fetch should always be opencoded. */ 156 uint16_t fix_fetch_opencode; 157 158 /* Bitmask of elements which need to be opencoded if the vertex buffer 159 * is unaligned. */ 160 uint16_t fix_fetch_unaligned; 161 162 /* For elements in fix_fetch_unaligned: whether the effective 163 * element load size as seen by the hardware is a dword (as opposed 164 * to a short). 165 */ 166 uint16_t hw_load_is_dword; 167 168 /* Bitmask of vertex buffers requiring alignment check */ 169 uint16_t vb_alignment_check_mask; 170 171 uint8_t count; 172 173 uint16_t first_vb_use_mask; 174 /* Vertex buffer descriptor list size aligned for optimal prefetch. */ 175 uint16_t vb_desc_list_alloc_size; 176 uint16_t instance_divisor_is_one; /* bitmask of inputs */ 177 uint16_t instance_divisor_is_fetched; /* bitmask of inputs */ 178}; 179 180union si_state { 181 struct si_state_named { 182 struct si_state_blend *blend; 183 struct si_state_rasterizer *rasterizer; 184 struct si_state_dsa *dsa; 185 struct si_pm4_state *poly_offset; 186 struct si_shader *ls; 187 struct si_shader *hs; 188 struct si_shader *es; 189 struct si_shader *gs; 190 struct si_pm4_state *vgt_shader_config; 191 struct si_shader *vs; 192 struct si_shader *ps; 193 } named; 194 struct si_pm4_state *array[sizeof(struct si_state_named) / sizeof(struct si_pm4_state *)]; 195}; 196 197#define SI_STATE_IDX(name) (offsetof(union si_state, named.name) / sizeof(struct si_pm4_state *)) 198#define SI_STATE_BIT(name) (1 << SI_STATE_IDX(name)) 199#define SI_NUM_STATES (sizeof(union si_state) / sizeof(struct si_pm4_state *)) 200 201static inline unsigned si_states_that_always_roll_context(void) 202{ 203 return (SI_STATE_BIT(blend) | SI_STATE_BIT(rasterizer) | SI_STATE_BIT(dsa) | 204 SI_STATE_BIT(poly_offset) | SI_STATE_BIT(vgt_shader_config)); 205} 206 207union si_state_atoms { 208 struct si_atoms_s { 209 /* The order matters. */ 210 struct si_atom render_cond; 211 struct si_atom streamout_begin; 212 struct si_atom streamout_enable; /* must be after streamout_begin */ 213 struct si_atom framebuffer; 214 struct si_atom msaa_sample_locs; 215 struct si_atom db_render_state; 216 struct si_atom dpbb_state; 217 struct si_atom msaa_config; 218 struct si_atom sample_mask; 219 struct si_atom cb_render_state; 220 struct si_atom blend_color; 221 struct si_atom clip_regs; 222 struct si_atom clip_state; 223 struct si_atom shader_pointers; 224 struct si_atom guardband; 225 struct si_atom scissors; 226 struct si_atom viewports; 227 struct si_atom stencil_ref; 228 struct si_atom spi_map; 229 struct si_atom scratch_state; 230 struct si_atom window_rectangles; 231 struct si_atom shader_query; 232 struct si_atom ngg_cull_state; 233 } s; 234 struct si_atom array[sizeof(struct si_atoms_s) / sizeof(struct si_atom)]; 235}; 236 237#define SI_ATOM_BIT(name) (1 << (offsetof(union si_state_atoms, s.name) / sizeof(struct si_atom))) 238#define SI_NUM_ATOMS (sizeof(union si_state_atoms) / sizeof(struct si_atom)) 239 240static inline unsigned si_atoms_that_always_roll_context(void) 241{ 242 return (SI_ATOM_BIT(streamout_begin) | SI_ATOM_BIT(streamout_enable) | SI_ATOM_BIT(framebuffer) | 243 SI_ATOM_BIT(msaa_sample_locs) | SI_ATOM_BIT(sample_mask) | SI_ATOM_BIT(blend_color) | 244 SI_ATOM_BIT(clip_state) | SI_ATOM_BIT(scissors) | SI_ATOM_BIT(viewports) | 245 SI_ATOM_BIT(stencil_ref) | SI_ATOM_BIT(scratch_state) | SI_ATOM_BIT(window_rectangles)); 246} 247 248struct si_shader_data { 249 uint32_t sh_base[SI_NUM_SHADERS]; 250}; 251 252/* The list of registers whose emitted values are remembered by si_context. */ 253enum si_tracked_reg 254{ 255 SI_TRACKED_DB_RENDER_CONTROL, /* 2 consecutive registers */ 256 SI_TRACKED_DB_COUNT_CONTROL, 257 258 SI_TRACKED_DB_RENDER_OVERRIDE2, 259 SI_TRACKED_DB_SHADER_CONTROL, 260 261 SI_TRACKED_CB_TARGET_MASK, 262 SI_TRACKED_CB_DCC_CONTROL, 263 264 SI_TRACKED_SX_PS_DOWNCONVERT, /* 3 consecutive registers */ 265 SI_TRACKED_SX_BLEND_OPT_EPSILON, 266 SI_TRACKED_SX_BLEND_OPT_CONTROL, 267 268 SI_TRACKED_PA_SC_LINE_CNTL, /* 2 consecutive registers */ 269 SI_TRACKED_PA_SC_AA_CONFIG, 270 271 SI_TRACKED_DB_EQAA, 272 SI_TRACKED_PA_SC_MODE_CNTL_1, 273 274 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL, 275 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL, 276 277 SI_TRACKED_PA_CL_VS_OUT_CNTL, 278 SI_TRACKED_PA_CL_CLIP_CNTL, 279 280 SI_TRACKED_PA_SC_BINNER_CNTL_0, 281 282 SI_TRACKED_DB_VRS_OVERRIDE_CNTL, 283 284 SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ, /* 4 consecutive registers */ 285 SI_TRACKED_PA_CL_GB_VERT_DISC_ADJ, 286 SI_TRACKED_PA_CL_GB_HORZ_CLIP_ADJ, 287 SI_TRACKED_PA_CL_GB_HORZ_DISC_ADJ, 288 289 SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET, 290 SI_TRACKED_PA_SU_VTX_CNTL, 291 292 SI_TRACKED_PA_SC_CLIPRECT_RULE, 293 294 SI_TRACKED_PA_SC_LINE_STIPPLE, 295 296 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE, 297 298 SI_TRACKED_VGT_GSVS_RING_OFFSET_1, /* 3 consecutive registers */ 299 SI_TRACKED_VGT_GSVS_RING_OFFSET_2, 300 SI_TRACKED_VGT_GSVS_RING_OFFSET_3, 301 302 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE, 303 SI_TRACKED_VGT_GS_MAX_VERT_OUT, 304 305 SI_TRACKED_VGT_GS_VERT_ITEMSIZE, /* 4 consecutive registers */ 306 SI_TRACKED_VGT_GS_VERT_ITEMSIZE_1, 307 SI_TRACKED_VGT_GS_VERT_ITEMSIZE_2, 308 SI_TRACKED_VGT_GS_VERT_ITEMSIZE_3, 309 310 SI_TRACKED_VGT_GS_INSTANCE_CNT, 311 SI_TRACKED_VGT_GS_ONCHIP_CNTL, 312 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP, 313 SI_TRACKED_VGT_GS_MODE, 314 SI_TRACKED_VGT_PRIMITIVEID_EN, 315 SI_TRACKED_VGT_REUSE_OFF, 316 SI_TRACKED_SPI_VS_OUT_CONFIG, 317 SI_TRACKED_PA_CL_VTE_CNTL, 318 SI_TRACKED_PA_CL_NGG_CNTL, 319 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP, 320 SI_TRACKED_GE_NGG_SUBGRP_CNTL, 321 322 SI_TRACKED_SPI_SHADER_IDX_FORMAT, /* 2 consecutive registers */ 323 SI_TRACKED_SPI_SHADER_POS_FORMAT, 324 325 SI_TRACKED_SPI_PS_INPUT_ENA, /* 2 consecutive registers */ 326 SI_TRACKED_SPI_PS_INPUT_ADDR, 327 328 SI_TRACKED_SPI_BARYC_CNTL, 329 SI_TRACKED_SPI_PS_IN_CONTROL, 330 331 SI_TRACKED_SPI_SHADER_Z_FORMAT, /* 2 consecutive registers */ 332 SI_TRACKED_SPI_SHADER_COL_FORMAT, 333 334 SI_TRACKED_CB_SHADER_MASK, 335 SI_TRACKED_VGT_TF_PARAM, 336 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL, 337 338 /* Non-context registers: */ 339 SI_TRACKED_GE_PC_ALLOC, 340 SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS, 341 SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS, 342 343 SI_NUM_TRACKED_REGS, 344}; 345 346struct si_tracked_regs { 347 uint64_t reg_saved; 348 uint32_t reg_value[SI_NUM_TRACKED_REGS]; 349 uint32_t spi_ps_input_cntl[32]; 350}; 351 352/* Private read-write buffer slots. */ 353enum 354{ 355 SI_ES_RING_ESGS, 356 SI_GS_RING_ESGS, 357 358 SI_RING_GSVS, 359 360 SI_VS_STREAMOUT_BUF0, 361 SI_VS_STREAMOUT_BUF1, 362 SI_VS_STREAMOUT_BUF2, 363 SI_VS_STREAMOUT_BUF3, 364 365 SI_HS_CONST_DEFAULT_TESS_LEVELS, 366 SI_VS_CONST_INSTANCE_DIVISORS, 367 SI_VS_CONST_CLIP_PLANES, 368 SI_PS_CONST_POLY_STIPPLE, 369 SI_PS_CONST_SAMPLE_POSITIONS, 370 371 /* Image descriptor of color buffer 0 for KHR_blend_equation_advanced. */ 372 SI_PS_IMAGE_COLORBUF0, 373 SI_PS_IMAGE_COLORBUF0_HI, 374 SI_PS_IMAGE_COLORBUF0_FMASK, 375 SI_PS_IMAGE_COLORBUF0_FMASK_HI, 376 377 GFX10_GS_QUERY_BUF, 378 379 SI_NUM_INTERNAL_BINDINGS, 380}; 381 382/* Indices into sctx->descriptors, laid out so that gfx and compute pipelines 383 * are contiguous: 384 * 385 * 0 - rw buffers 386 * 1 - vertex const and shader buffers 387 * 2 - vertex samplers and images 388 * 3 - fragment const and shader buffer 389 * ... 390 * 11 - compute const and shader buffers 391 * 12 - compute samplers and images 392 */ 393enum 394{ 395 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS, 396 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES, 397 SI_NUM_SHADER_DESCS, 398}; 399 400#define SI_DESCS_INTERNAL 0 401#define SI_DESCS_FIRST_SHADER 1 402#define SI_DESCS_FIRST_COMPUTE (SI_DESCS_FIRST_SHADER + PIPE_SHADER_COMPUTE * SI_NUM_SHADER_DESCS) 403#define SI_NUM_DESCS (SI_DESCS_FIRST_SHADER + SI_NUM_SHADERS * SI_NUM_SHADER_DESCS) 404 405#define SI_DESCS_SHADER_MASK(name) \ 406 u_bit_consecutive(SI_DESCS_FIRST_SHADER + PIPE_SHADER_##name * SI_NUM_SHADER_DESCS, \ 407 SI_NUM_SHADER_DESCS) 408 409static inline unsigned si_const_and_shader_buffer_descriptors_idx(unsigned shader) 410{ 411 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS + 412 SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS; 413} 414 415static inline unsigned si_sampler_and_image_descriptors_idx(unsigned shader) 416{ 417 return SI_DESCS_FIRST_SHADER + shader * SI_NUM_SHADER_DESCS + 418 SI_SHADER_DESCS_SAMPLERS_AND_IMAGES; 419} 420 421/* This represents descriptors in memory, such as buffer resources, 422 * image resources, and sampler states. 423 */ 424struct si_descriptors { 425 /* The list of descriptors in malloc'd memory. */ 426 uint32_t *list; 427 /* The list in mapped GPU memory. */ 428 uint32_t *gpu_list; 429 430 /* The buffer where the descriptors have been uploaded. */ 431 struct si_resource *buffer; 432 uint64_t gpu_address; 433 434 /* The maximum number of descriptors. */ 435 uint32_t num_elements; 436 437 /* Slots that are used by currently-bound shaders. 438 * It determines which slots are uploaded. 439 */ 440 uint32_t first_active_slot; 441 uint32_t num_active_slots; 442 443 /* The SH register offset relative to USER_DATA*_0 where the pointer 444 * to the descriptor array will be stored. */ 445 short shader_userdata_offset; 446 /* The size of one descriptor. */ 447 ubyte element_dw_size; 448 /* If there is only one slot enabled, bind it directly instead of 449 * uploading descriptors. -1 if disabled. */ 450 signed char slot_index_to_bind_directly; 451}; 452 453struct si_buffer_resources { 454 struct pipe_resource **buffers; /* this has num_buffers elements */ 455 unsigned *offsets; /* this has num_buffers elements */ 456 457 enum radeon_bo_priority priority : 6; 458 enum radeon_bo_priority priority_constbuf : 6; 459 460 /* The i-th bit is set if that element is enabled (non-NULL resource). */ 461 uint64_t enabled_mask; 462 uint64_t writable_mask; 463}; 464 465#define si_pm4_state_changed(sctx, member) \ 466 ((sctx)->queued.named.member != (sctx)->emitted.named.member) 467 468#define si_pm4_state_enabled_and_changed(sctx, member) \ 469 ((sctx)->queued.named.member && si_pm4_state_changed(sctx, member)) 470 471#define si_pm4_bind_state(sctx, member, value) \ 472 do { \ 473 (sctx)->queued.named.member = (value); \ 474 if (value && value != (sctx)->emitted.named.member) \ 475 (sctx)->dirty_states |= SI_STATE_BIT(member); \ 476 else \ 477 (sctx)->dirty_states &= ~SI_STATE_BIT(member); \ 478 } while (0) 479 480/* si_descriptors.c */ 481void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture *tex, 482 const struct legacy_surf_level *base_level_info, 483 unsigned base_level, unsigned first_level, unsigned block_width, 484 /* restrict decreases overhead of si_set_sampler_view_desc ~8x. */ 485 bool is_stencil, uint16_t access, uint32_t * restrict state); 486void si_update_ps_colorbuf0_slot(struct si_context *sctx); 487void si_invalidate_inlinable_uniforms(struct si_context *sctx, enum pipe_shader_type shader); 488void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader, uint slot, 489 struct pipe_constant_buffer *cbuf); 490void si_get_shader_buffers(struct si_context *sctx, enum pipe_shader_type shader, uint start_slot, 491 uint count, struct pipe_shader_buffer *sbuf); 492void si_set_ring_buffer(struct si_context *sctx, uint slot, struct pipe_resource *buffer, 493 unsigned stride, unsigned num_records, bool add_tid, bool swizzle, 494 unsigned element_size, unsigned index_stride, uint64_t offset); 495void si_init_all_descriptors(struct si_context *sctx); 496bool si_upload_graphics_shader_descriptors(struct si_context *sctx); 497bool si_upload_compute_shader_descriptors(struct si_context *sctx); 498void si_release_all_descriptors(struct si_context *sctx); 499void si_gfx_resources_add_all_to_bo_list(struct si_context *sctx); 500void si_compute_resources_add_all_to_bo_list(struct si_context *sctx); 501bool si_gfx_resources_check_encrypted(struct si_context *sctx); 502bool si_compute_resources_check_encrypted(struct si_context *sctx); 503void si_shader_pointers_mark_dirty(struct si_context *sctx); 504void si_add_all_descriptors_to_bo_list(struct si_context *sctx); 505void si_update_all_texture_descriptors(struct si_context *sctx); 506void si_shader_change_notify(struct si_context *sctx); 507void si_update_needs_color_decompress_masks(struct si_context *sctx); 508void si_emit_graphics_shader_pointers(struct si_context *sctx); 509void si_emit_compute_shader_pointers(struct si_context *sctx); 510void si_set_internal_const_buffer(struct si_context *sctx, uint slot, 511 const struct pipe_constant_buffer *input); 512void si_set_internal_shader_buffer(struct si_context *sctx, uint slot, 513 const struct pipe_shader_buffer *sbuffer); 514void si_set_active_descriptors(struct si_context *sctx, unsigned desc_idx, 515 uint64_t new_active_mask); 516void si_set_active_descriptors_for_shader(struct si_context *sctx, struct si_shader_selector *sel); 517bool si_bindless_descriptor_can_reclaim_slab(void *priv, struct pb_slab_entry *entry); 518struct pb_slab *si_bindless_descriptor_slab_alloc(void *priv, unsigned heap, unsigned entry_size, 519 unsigned group_index); 520void si_bindless_descriptor_slab_free(void *priv, struct pb_slab *pslab); 521void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf); 522/* si_state.c */ 523uint32_t si_translate_colorformat(enum chip_class chip_class, enum pipe_format format); 524void si_init_state_compute_functions(struct si_context *sctx); 525void si_init_state_functions(struct si_context *sctx); 526void si_init_screen_state_functions(struct si_screen *sscreen); 527void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing); 528void si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf, 529 enum pipe_format format, unsigned offset, unsigned size, 530 uint32_t *state); 531struct pipe_sampler_view *si_create_sampler_view_custom(struct pipe_context *ctx, 532 struct pipe_resource *texture, 533 const struct pipe_sampler_view *state, 534 unsigned width0, unsigned height0, 535 unsigned force_level); 536void si_update_fb_dirtiness_after_rendering(struct si_context *sctx); 537void si_mark_display_dcc_dirty(struct si_context *sctx, struct si_texture *tex); 538void si_update_ps_iter_samples(struct si_context *sctx); 539void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st); 540void si_restore_qbo_state(struct si_context *sctx, struct si_qbo_state *st); 541void si_set_occlusion_query_state(struct si_context *sctx, bool old_perfect_enable); 542 543struct si_fast_udiv_info32 { 544 unsigned multiplier; /* the "magic number" multiplier */ 545 unsigned pre_shift; /* shift for the dividend before multiplying */ 546 unsigned post_shift; /* shift for the dividend after multiplying */ 547 int increment; /* 0 or 1; if set then increment the numerator, using one of 548 the two strategies */ 549}; 550 551struct si_fast_udiv_info32 si_compute_fast_udiv_info32(uint32_t D, unsigned num_bits); 552 553/* si_state_binning.c */ 554void si_emit_dpbb_state(struct si_context *sctx); 555 556/* si_state_shaders.c */ 557void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es, 558 unsigned char ir_sha1_cache_key[20]); 559bool si_shader_cache_load_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20], 560 struct si_shader *shader); 561void si_shader_cache_insert_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20], 562 struct si_shader *shader, bool insert_into_disk_cache); 563bool si_shader_mem_ordered(struct si_shader *shader); 564void si_init_screen_live_shader_cache(struct si_screen *sscreen); 565void si_init_shader_functions(struct si_context *sctx); 566bool si_init_shader_cache(struct si_screen *sscreen); 567void si_destroy_shader_cache(struct si_screen *sscreen); 568void si_schedule_initial_compile(struct si_context *sctx, gl_shader_stage stage, 569 struct util_queue_fence *ready_fence, 570 struct si_compiler_ctx_state *compiler_ctx_state, void *job, 571 util_queue_execute_func execute); 572void si_get_active_slot_masks(const struct si_shader_info *info, uint64_t *const_and_shader_buffers, 573 uint64_t *samplers_and_images); 574int si_shader_select_with_key(struct si_context *sctx, struct si_shader_ctx_state *state, 575 const struct si_shader_key *key, int thread_index, 576 bool optimized_or_none); 577int si_shader_select(struct pipe_context *ctx, struct si_shader_ctx_state *state); 578void si_vs_key_update_inputs(struct si_context *sctx); 579void si_get_vs_key_inputs(struct si_context *sctx, struct si_shader_key *key, 580 struct si_vs_prolog_bits *prolog_key); 581void si_update_ps_inputs_read_or_disabled(struct si_context *sctx); 582void si_update_ps_kill_enable(struct si_context *sctx); 583void si_update_vrs_flat_shading(struct si_context *sctx); 584unsigned si_get_input_prim(const struct si_shader_selector *gs, const struct si_shader_key *key); 585bool si_update_ngg(struct si_context *sctx); 586void si_ps_key_update_framebuffer(struct si_context *sctx); 587void si_ps_key_update_framebuffer_blend(struct si_context *sctx); 588void si_ps_key_update_blend_rasterizer(struct si_context *sctx); 589void si_ps_key_update_rasterizer(struct si_context *sctx); 590void si_ps_key_update_dsa(struct si_context *sctx); 591void si_ps_key_update_sample_shading(struct si_context *sctx); 592void si_ps_key_update_framebuffer_rasterizer_sample_shading(struct si_context *sctx); 593void si_init_tess_factor_ring(struct si_context *sctx); 594bool si_update_gs_ring_buffers(struct si_context *sctx); 595bool si_update_spi_tmpring_size(struct si_context *sctx, unsigned bytes); 596 597/* si_state_draw.cpp */ 598void si_set_vertex_buffer_descriptor(struct si_screen *sscreen, struct si_vertex_elements *velems, 599 struct pipe_vertex_buffer *vb, unsigned element_index, 600 uint32_t *out); 601void si_init_draw_functions_GFX6(struct si_context *sctx); 602void si_init_draw_functions_GFX7(struct si_context *sctx); 603void si_init_draw_functions_GFX8(struct si_context *sctx); 604void si_init_draw_functions_GFX9(struct si_context *sctx); 605void si_init_draw_functions_GFX10(struct si_context *sctx); 606void si_init_draw_functions_GFX10_3(struct si_context *sctx); 607void si_init_spi_map_functions(struct si_context *sctx); 608 609/* si_state_msaa.c */ 610void si_init_msaa_functions(struct si_context *sctx); 611void si_emit_sample_locations(struct radeon_cmdbuf *cs, int nr_samples); 612 613/* si_state_streamout.c */ 614void si_streamout_buffers_dirty(struct si_context *sctx); 615void si_emit_streamout_end(struct si_context *sctx); 616void si_update_prims_generated_query_state(struct si_context *sctx, unsigned type, int diff); 617void si_init_streamout_functions(struct si_context *sctx); 618 619static inline unsigned si_get_constbuf_slot(unsigned slot) 620{ 621 /* Constant buffers are in slots [32..47], ascending */ 622 return SI_NUM_SHADER_BUFFERS + slot; 623} 624 625static inline unsigned si_get_shaderbuf_slot(unsigned slot) 626{ 627 /* shader buffers are in slots [31..0], descending */ 628 return SI_NUM_SHADER_BUFFERS - 1 - slot; 629} 630 631static inline unsigned si_get_sampler_slot(unsigned slot) 632{ 633 /* 32 samplers are in sampler slots [16..47], 16 dw per slot, ascending */ 634 /* those are equivalent to image slots [32..95], 8 dw per slot, ascending */ 635 return SI_NUM_IMAGE_SLOTS / 2 + slot; 636} 637 638static inline unsigned si_get_image_slot(unsigned slot) 639{ 640 /* image slots are in [31..0] (sampler slots [15..0]), descending */ 641 /* images are in slots [31..16], while FMASKs are in slots [15..0] */ 642 return SI_NUM_IMAGE_SLOTS - 1 - slot; 643} 644 645#ifdef __cplusplus 646} 647#endif 648 649#endif 650