101e04c3fSmrg/*
201e04c3fSmrg * Copyright © 2014-2018 NVIDIA Corporation
301e04c3fSmrg *
401e04c3fSmrg * Permission is hereby granted, free of charge, to any person obtaining a
501e04c3fSmrg * copy of this software and associated documentation files (the "Software"),
601e04c3fSmrg * to deal in the Software without restriction, including without limitation
701e04c3fSmrg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
801e04c3fSmrg * and/or sell copies of the Software, and to permit persons to whom the
901e04c3fSmrg * Software is furnished to do so, subject to the following conditions:
1001e04c3fSmrg *
1101e04c3fSmrg * The above copyright notice and this permission notice (including the next
1201e04c3fSmrg * paragraph) shall be included in all copies or substantial portions of the
1301e04c3fSmrg * Software.
1401e04c3fSmrg *
1501e04c3fSmrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1601e04c3fSmrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1701e04c3fSmrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
1801e04c3fSmrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
1901e04c3fSmrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2001e04c3fSmrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
2101e04c3fSmrg * IN THE SOFTWARE.
2201e04c3fSmrg */
2301e04c3fSmrg
2401e04c3fSmrg#include <inttypes.h>
2501e04c3fSmrg#include <stdlib.h>
2601e04c3fSmrg
2701e04c3fSmrg#include "util/u_debug.h"
287ec681f3Smrg#include "util/u_draw.h"
2901e04c3fSmrg#include "util/u_inlines.h"
3001e04c3fSmrg#include "util/u_upload_mgr.h"
3101e04c3fSmrg
3201e04c3fSmrg#include "tegra_context.h"
3301e04c3fSmrg#include "tegra_resource.h"
3401e04c3fSmrg#include "tegra_screen.h"
3501e04c3fSmrg
3601e04c3fSmrgstatic void
3701e04c3fSmrgtegra_destroy(struct pipe_context *pcontext)
3801e04c3fSmrg{
3901e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
4001e04c3fSmrg
4101e04c3fSmrg   if (context->base.stream_uploader)
4201e04c3fSmrg      u_upload_destroy(context->base.stream_uploader);
4301e04c3fSmrg
4401e04c3fSmrg   context->gpu->destroy(context->gpu);
4501e04c3fSmrg   free(context);
4601e04c3fSmrg}
4701e04c3fSmrg
4801e04c3fSmrgstatic void
4901e04c3fSmrgtegra_draw_vbo(struct pipe_context *pcontext,
507ec681f3Smrg               const struct pipe_draw_info *pinfo,
517ec681f3Smrg               unsigned drawid_offset,
527ec681f3Smrg               const struct pipe_draw_indirect_info *pindirect,
537ec681f3Smrg               const struct pipe_draw_start_count_bias *draws,
547ec681f3Smrg               unsigned num_draws)
557ec681f3Smrg{
567ec681f3Smrg   if (num_draws > 1) {
577ec681f3Smrg      util_draw_multi(pcontext, pinfo, drawid_offset, pindirect, draws, num_draws);
587ec681f3Smrg      return;
597ec681f3Smrg   }
607ec681f3Smrg
617ec681f3Smrg   if (!pindirect && (!draws[0].count || !pinfo->instance_count))
627ec681f3Smrg      return;
637ec681f3Smrg
6401e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
6501e04c3fSmrg   struct pipe_draw_indirect_info indirect;
6601e04c3fSmrg   struct pipe_draw_info info;
6701e04c3fSmrg
687ec681f3Smrg   if (pinfo && ((pindirect && pindirect->buffer) || pinfo->index_size)) {
6901e04c3fSmrg      memcpy(&info, pinfo, sizeof(info));
7001e04c3fSmrg
717ec681f3Smrg      if (pindirect && pindirect->buffer) {
727ec681f3Smrg         memcpy(&indirect, pindirect, sizeof(indirect));
737ec681f3Smrg         indirect.buffer = tegra_resource_unwrap(pindirect->buffer);
747ec681f3Smrg         indirect.indirect_draw_count = tegra_resource_unwrap(pindirect->indirect_draw_count);
757ec681f3Smrg         pindirect = &indirect;
7601e04c3fSmrg      }
7701e04c3fSmrg
7801e04c3fSmrg      if (pinfo->index_size && !pinfo->has_user_indices)
7901e04c3fSmrg         info.index.resource = tegra_resource_unwrap(info.index.resource);
8001e04c3fSmrg
8101e04c3fSmrg      pinfo = &info;
8201e04c3fSmrg   }
8301e04c3fSmrg
847ec681f3Smrg   context->gpu->draw_vbo(context->gpu, pinfo, drawid_offset, pindirect, draws, num_draws);
8501e04c3fSmrg}
8601e04c3fSmrg
8701e04c3fSmrgstatic void
8801e04c3fSmrgtegra_render_condition(struct pipe_context *pcontext,
8901e04c3fSmrg                       struct pipe_query *query,
907ec681f3Smrg                       bool condition,
9101e04c3fSmrg                       unsigned int mode)
9201e04c3fSmrg{
9301e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
9401e04c3fSmrg
9501e04c3fSmrg   context->gpu->render_condition(context->gpu, query, condition, mode);
9601e04c3fSmrg}
9701e04c3fSmrg
9801e04c3fSmrgstatic struct pipe_query *
9901e04c3fSmrgtegra_create_query(struct pipe_context *pcontext, unsigned int query_type,
10001e04c3fSmrg                   unsigned int index)
10101e04c3fSmrg{
10201e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
10301e04c3fSmrg
10401e04c3fSmrg   return context->gpu->create_query(context->gpu, query_type, index);
10501e04c3fSmrg}
10601e04c3fSmrg
10701e04c3fSmrgstatic struct pipe_query *
10801e04c3fSmrgtegra_create_batch_query(struct pipe_context *pcontext,
10901e04c3fSmrg                         unsigned int num_queries,
11001e04c3fSmrg                         unsigned int *queries)
11101e04c3fSmrg{
11201e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
11301e04c3fSmrg
11401e04c3fSmrg   return context->gpu->create_batch_query(context->gpu, num_queries,
11501e04c3fSmrg                                           queries);
11601e04c3fSmrg}
11701e04c3fSmrg
11801e04c3fSmrgstatic void
11901e04c3fSmrgtegra_destroy_query(struct pipe_context *pcontext, struct pipe_query *query)
12001e04c3fSmrg{
12101e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
12201e04c3fSmrg
12301e04c3fSmrg   context->gpu->destroy_query(context->gpu, query);
12401e04c3fSmrg}
12501e04c3fSmrg
1267ec681f3Smrgstatic bool
12701e04c3fSmrgtegra_begin_query(struct pipe_context *pcontext, struct pipe_query *query)
12801e04c3fSmrg{
12901e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
13001e04c3fSmrg
13101e04c3fSmrg   return context->gpu->begin_query(context->gpu, query);
13201e04c3fSmrg}
13301e04c3fSmrg
13401e04c3fSmrgstatic bool
13501e04c3fSmrgtegra_end_query(struct pipe_context *pcontext, struct pipe_query *query)
13601e04c3fSmrg{
13701e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
13801e04c3fSmrg
13901e04c3fSmrg   return context->gpu->end_query(context->gpu, query);
14001e04c3fSmrg}
14101e04c3fSmrg
1427ec681f3Smrgstatic bool
14301e04c3fSmrgtegra_get_query_result(struct pipe_context *pcontext,
14401e04c3fSmrg                       struct pipe_query *query,
1457ec681f3Smrg                       bool wait,
14601e04c3fSmrg                       union pipe_query_result *result)
14701e04c3fSmrg{
14801e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
14901e04c3fSmrg
15001e04c3fSmrg   return context->gpu->get_query_result(context->gpu, query, wait,
15101e04c3fSmrg                     result);
15201e04c3fSmrg}
15301e04c3fSmrg
15401e04c3fSmrgstatic void
15501e04c3fSmrgtegra_get_query_result_resource(struct pipe_context *pcontext,
15601e04c3fSmrg                                struct pipe_query *query,
1577ec681f3Smrg                                bool wait,
15801e04c3fSmrg                                enum pipe_query_value_type result_type,
15901e04c3fSmrg                                int index,
16001e04c3fSmrg                                struct pipe_resource *resource,
16101e04c3fSmrg                                unsigned int offset)
16201e04c3fSmrg{
16301e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
16401e04c3fSmrg
16501e04c3fSmrg   context->gpu->get_query_result_resource(context->gpu, query, wait,
16601e04c3fSmrg                                           result_type, index, resource,
16701e04c3fSmrg                                           offset);
16801e04c3fSmrg}
16901e04c3fSmrg
17001e04c3fSmrgstatic void
1717ec681f3Smrgtegra_set_active_query_state(struct pipe_context *pcontext, bool enable)
17201e04c3fSmrg{
17301e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
17401e04c3fSmrg
17501e04c3fSmrg   context->gpu->set_active_query_state(context->gpu, enable);
17601e04c3fSmrg}
17701e04c3fSmrg
17801e04c3fSmrgstatic void *
17901e04c3fSmrgtegra_create_blend_state(struct pipe_context *pcontext,
18001e04c3fSmrg                         const struct pipe_blend_state *cso)
18101e04c3fSmrg{
18201e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
18301e04c3fSmrg
18401e04c3fSmrg   return context->gpu->create_blend_state(context->gpu, cso);
18501e04c3fSmrg}
18601e04c3fSmrg
18701e04c3fSmrgstatic void
18801e04c3fSmrgtegra_bind_blend_state(struct pipe_context *pcontext, void *so)
18901e04c3fSmrg{
19001e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
19101e04c3fSmrg
19201e04c3fSmrg   context->gpu->bind_blend_state(context->gpu, so);
19301e04c3fSmrg}
19401e04c3fSmrg
19501e04c3fSmrgstatic void
19601e04c3fSmrgtegra_delete_blend_state(struct pipe_context *pcontext, void *so)
19701e04c3fSmrg{
19801e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
19901e04c3fSmrg
20001e04c3fSmrg   context->gpu->delete_blend_state(context->gpu, so);
20101e04c3fSmrg}
20201e04c3fSmrg
20301e04c3fSmrgstatic void *
20401e04c3fSmrgtegra_create_sampler_state(struct pipe_context *pcontext,
20501e04c3fSmrg                           const struct pipe_sampler_state *cso)
20601e04c3fSmrg{
20701e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
20801e04c3fSmrg
20901e04c3fSmrg   return context->gpu->create_sampler_state(context->gpu, cso);
21001e04c3fSmrg}
21101e04c3fSmrg
21201e04c3fSmrgstatic void
21301e04c3fSmrgtegra_bind_sampler_states(struct pipe_context *pcontext, unsigned shader,
21401e04c3fSmrg                          unsigned start_slot, unsigned num_samplers,
21501e04c3fSmrg                          void **samplers)
21601e04c3fSmrg{
21701e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
21801e04c3fSmrg
21901e04c3fSmrg   context->gpu->bind_sampler_states(context->gpu, shader, start_slot,
22001e04c3fSmrg                                     num_samplers, samplers);
22101e04c3fSmrg}
22201e04c3fSmrg
22301e04c3fSmrgstatic void
22401e04c3fSmrgtegra_delete_sampler_state(struct pipe_context *pcontext, void *so)
22501e04c3fSmrg{
22601e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
22701e04c3fSmrg
22801e04c3fSmrg   context->gpu->delete_sampler_state(context->gpu, so);
22901e04c3fSmrg}
23001e04c3fSmrg
23101e04c3fSmrgstatic void *
23201e04c3fSmrgtegra_create_rasterizer_state(struct pipe_context *pcontext,
23301e04c3fSmrg                              const struct pipe_rasterizer_state *cso)
23401e04c3fSmrg{
23501e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
23601e04c3fSmrg
23701e04c3fSmrg   return context->gpu->create_rasterizer_state(context->gpu, cso);
23801e04c3fSmrg}
23901e04c3fSmrg
24001e04c3fSmrgstatic void
24101e04c3fSmrgtegra_bind_rasterizer_state(struct pipe_context *pcontext, void *so)
24201e04c3fSmrg{
24301e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
24401e04c3fSmrg
24501e04c3fSmrg   context->gpu->bind_rasterizer_state(context->gpu, so);
24601e04c3fSmrg}
24701e04c3fSmrg
24801e04c3fSmrgstatic void
24901e04c3fSmrgtegra_delete_rasterizer_state(struct pipe_context *pcontext, void *so)
25001e04c3fSmrg{
25101e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
25201e04c3fSmrg
25301e04c3fSmrg   context->gpu->delete_rasterizer_state(context->gpu, so);
25401e04c3fSmrg}
25501e04c3fSmrg
25601e04c3fSmrgstatic void *
25701e04c3fSmrgtegra_create_depth_stencil_alpha_state(struct pipe_context *pcontext,
25801e04c3fSmrg                                       const struct pipe_depth_stencil_alpha_state *cso)
25901e04c3fSmrg{
26001e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
26101e04c3fSmrg
26201e04c3fSmrg   return context->gpu->create_depth_stencil_alpha_state(context->gpu, cso);
26301e04c3fSmrg}
26401e04c3fSmrg
26501e04c3fSmrgstatic void
26601e04c3fSmrgtegra_bind_depth_stencil_alpha_state(struct pipe_context *pcontext, void *so)
26701e04c3fSmrg{
26801e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
26901e04c3fSmrg
27001e04c3fSmrg   context->gpu->bind_depth_stencil_alpha_state(context->gpu, so);
27101e04c3fSmrg}
27201e04c3fSmrg
27301e04c3fSmrgstatic void
27401e04c3fSmrgtegra_delete_depth_stencil_alpha_state(struct pipe_context *pcontext, void *so)
27501e04c3fSmrg{
27601e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
27701e04c3fSmrg
27801e04c3fSmrg   context->gpu->delete_depth_stencil_alpha_state(context->gpu, so);
27901e04c3fSmrg}
28001e04c3fSmrg
28101e04c3fSmrgstatic void *
28201e04c3fSmrgtegra_create_fs_state(struct pipe_context *pcontext,
28301e04c3fSmrg                      const struct pipe_shader_state *cso)
28401e04c3fSmrg{
28501e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
28601e04c3fSmrg
28701e04c3fSmrg   return context->gpu->create_fs_state(context->gpu, cso);
28801e04c3fSmrg}
28901e04c3fSmrg
29001e04c3fSmrgstatic void
29101e04c3fSmrgtegra_bind_fs_state(struct pipe_context *pcontext, void *so)
29201e04c3fSmrg{
29301e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
29401e04c3fSmrg
29501e04c3fSmrg   context->gpu->bind_fs_state(context->gpu, so);
29601e04c3fSmrg}
29701e04c3fSmrg
29801e04c3fSmrgstatic void
29901e04c3fSmrgtegra_delete_fs_state(struct pipe_context *pcontext, void *so)
30001e04c3fSmrg{
30101e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
30201e04c3fSmrg
30301e04c3fSmrg   context->gpu->delete_fs_state(context->gpu, so);
30401e04c3fSmrg}
30501e04c3fSmrg
30601e04c3fSmrgstatic void *
30701e04c3fSmrgtegra_create_vs_state(struct pipe_context *pcontext,
30801e04c3fSmrg                      const struct pipe_shader_state *cso)
30901e04c3fSmrg{
31001e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
31101e04c3fSmrg
31201e04c3fSmrg   return context->gpu->create_vs_state(context->gpu, cso);
31301e04c3fSmrg}
31401e04c3fSmrg
31501e04c3fSmrgstatic void
31601e04c3fSmrgtegra_bind_vs_state(struct pipe_context *pcontext, void *so)
31701e04c3fSmrg{
31801e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
31901e04c3fSmrg
32001e04c3fSmrg   context->gpu->bind_vs_state(context->gpu, so);
32101e04c3fSmrg}
32201e04c3fSmrg
32301e04c3fSmrgstatic void
32401e04c3fSmrgtegra_delete_vs_state(struct pipe_context *pcontext, void *so)
32501e04c3fSmrg{
32601e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
32701e04c3fSmrg
32801e04c3fSmrg   context->gpu->delete_vs_state(context->gpu, so);
32901e04c3fSmrg}
33001e04c3fSmrg
33101e04c3fSmrgstatic void *
33201e04c3fSmrgtegra_create_gs_state(struct pipe_context *pcontext,
33301e04c3fSmrg                      const struct pipe_shader_state *cso)
33401e04c3fSmrg{
33501e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
33601e04c3fSmrg
33701e04c3fSmrg   return context->gpu->create_gs_state(context->gpu, cso);
33801e04c3fSmrg}
33901e04c3fSmrg
34001e04c3fSmrgstatic void
34101e04c3fSmrgtegra_bind_gs_state(struct pipe_context *pcontext, void *so)
34201e04c3fSmrg{
34301e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
34401e04c3fSmrg
34501e04c3fSmrg   context->gpu->bind_gs_state(context->gpu, so);
34601e04c3fSmrg}
34701e04c3fSmrg
34801e04c3fSmrgstatic void
34901e04c3fSmrgtegra_delete_gs_state(struct pipe_context *pcontext, void *so)
35001e04c3fSmrg{
35101e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
35201e04c3fSmrg
35301e04c3fSmrg   context->gpu->delete_gs_state(context->gpu, so);
35401e04c3fSmrg}
35501e04c3fSmrg
35601e04c3fSmrgstatic void *
35701e04c3fSmrgtegra_create_tcs_state(struct pipe_context *pcontext,
35801e04c3fSmrg                       const struct pipe_shader_state *cso)
35901e04c3fSmrg{
36001e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
36101e04c3fSmrg
36201e04c3fSmrg   return context->gpu->create_tcs_state(context->gpu, cso);
36301e04c3fSmrg}
36401e04c3fSmrg
36501e04c3fSmrgstatic void
36601e04c3fSmrgtegra_bind_tcs_state(struct pipe_context *pcontext, void *so)
36701e04c3fSmrg{
36801e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
36901e04c3fSmrg
37001e04c3fSmrg   context->gpu->bind_tcs_state(context->gpu, so);
37101e04c3fSmrg}
37201e04c3fSmrg
37301e04c3fSmrgstatic void
37401e04c3fSmrgtegra_delete_tcs_state(struct pipe_context *pcontext, void *so)
37501e04c3fSmrg{
37601e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
37701e04c3fSmrg
37801e04c3fSmrg   context->gpu->delete_tcs_state(context->gpu, so);
37901e04c3fSmrg}
38001e04c3fSmrg
38101e04c3fSmrgstatic void *
38201e04c3fSmrgtegra_create_tes_state(struct pipe_context *pcontext,
38301e04c3fSmrg                       const struct pipe_shader_state *cso)
38401e04c3fSmrg{
38501e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
38601e04c3fSmrg
38701e04c3fSmrg   return context->gpu->create_tes_state(context->gpu, cso);
38801e04c3fSmrg}
38901e04c3fSmrg
39001e04c3fSmrgstatic void
39101e04c3fSmrgtegra_bind_tes_state(struct pipe_context *pcontext, void *so)
39201e04c3fSmrg{
39301e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
39401e04c3fSmrg
39501e04c3fSmrg   context->gpu->bind_tes_state(context->gpu, so);
39601e04c3fSmrg}
39701e04c3fSmrg
39801e04c3fSmrgstatic void
39901e04c3fSmrgtegra_delete_tes_state(struct pipe_context *pcontext, void *so)
40001e04c3fSmrg{
40101e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
40201e04c3fSmrg
40301e04c3fSmrg   context->gpu->delete_tes_state(context->gpu, so);
40401e04c3fSmrg}
40501e04c3fSmrg
40601e04c3fSmrgstatic void *
40701e04c3fSmrgtegra_create_vertex_elements_state(struct pipe_context *pcontext,
40801e04c3fSmrg                                   unsigned num_elements,
40901e04c3fSmrg                                   const struct pipe_vertex_element *elements)
41001e04c3fSmrg{
41101e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
41201e04c3fSmrg
41301e04c3fSmrg   return context->gpu->create_vertex_elements_state(context->gpu,
41401e04c3fSmrg                                                     num_elements,
41501e04c3fSmrg                                                     elements);
41601e04c3fSmrg}
41701e04c3fSmrg
41801e04c3fSmrgstatic void
41901e04c3fSmrgtegra_bind_vertex_elements_state(struct pipe_context *pcontext, void *so)
42001e04c3fSmrg{
42101e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
42201e04c3fSmrg
42301e04c3fSmrg   context->gpu->bind_vertex_elements_state(context->gpu, so);
42401e04c3fSmrg}
42501e04c3fSmrg
42601e04c3fSmrgstatic void
42701e04c3fSmrgtegra_delete_vertex_elements_state(struct pipe_context *pcontext, void *so)
42801e04c3fSmrg{
42901e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
43001e04c3fSmrg
43101e04c3fSmrg   context->gpu->delete_vertex_elements_state(context->gpu, so);
43201e04c3fSmrg}
43301e04c3fSmrg
43401e04c3fSmrgstatic void
43501e04c3fSmrgtegra_set_blend_color(struct pipe_context *pcontext,
43601e04c3fSmrg                      const struct pipe_blend_color *color)
43701e04c3fSmrg{
43801e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
43901e04c3fSmrg
44001e04c3fSmrg   context->gpu->set_blend_color(context->gpu, color);
44101e04c3fSmrg}
44201e04c3fSmrg
44301e04c3fSmrgstatic void
44401e04c3fSmrgtegra_set_stencil_ref(struct pipe_context *pcontext,
4457ec681f3Smrg                      const struct pipe_stencil_ref ref)
44601e04c3fSmrg{
44701e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
44801e04c3fSmrg
44901e04c3fSmrg   context->gpu->set_stencil_ref(context->gpu, ref);
45001e04c3fSmrg}
45101e04c3fSmrg
45201e04c3fSmrgstatic void
45301e04c3fSmrgtegra_set_sample_mask(struct pipe_context *pcontext, unsigned int mask)
45401e04c3fSmrg{
45501e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
45601e04c3fSmrg
45701e04c3fSmrg   context->gpu->set_sample_mask(context->gpu, mask);
45801e04c3fSmrg}
45901e04c3fSmrg
46001e04c3fSmrgstatic void
46101e04c3fSmrgtegra_set_min_samples(struct pipe_context *pcontext, unsigned int samples)
46201e04c3fSmrg{
46301e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
46401e04c3fSmrg
46501e04c3fSmrg   context->gpu->set_min_samples(context->gpu, samples);
46601e04c3fSmrg}
46701e04c3fSmrg
46801e04c3fSmrgstatic void
46901e04c3fSmrgtegra_set_clip_state(struct pipe_context *pcontext,
47001e04c3fSmrg                     const struct pipe_clip_state *state)
47101e04c3fSmrg{
47201e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
47301e04c3fSmrg
47401e04c3fSmrg   context->gpu->set_clip_state(context->gpu, state);
47501e04c3fSmrg}
47601e04c3fSmrg
47701e04c3fSmrgstatic void
47801e04c3fSmrgtegra_set_constant_buffer(struct pipe_context *pcontext, unsigned int shader,
4797ec681f3Smrg                          unsigned int index, bool take_ownership,
48001e04c3fSmrg                          const struct pipe_constant_buffer *buf)
48101e04c3fSmrg{
48201e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
48301e04c3fSmrg   struct pipe_constant_buffer buffer;
48401e04c3fSmrg
48501e04c3fSmrg   if (buf && buf->buffer) {
48601e04c3fSmrg      memcpy(&buffer, buf, sizeof(buffer));
48701e04c3fSmrg      buffer.buffer = tegra_resource_unwrap(buffer.buffer);
48801e04c3fSmrg      buf = &buffer;
48901e04c3fSmrg   }
49001e04c3fSmrg
4917ec681f3Smrg   context->gpu->set_constant_buffer(context->gpu, shader, index, take_ownership, buf);
49201e04c3fSmrg}
49301e04c3fSmrg
49401e04c3fSmrgstatic void
49501e04c3fSmrgtegra_set_framebuffer_state(struct pipe_context *pcontext,
49601e04c3fSmrg                            const struct pipe_framebuffer_state *fb)
49701e04c3fSmrg{
49801e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
49901e04c3fSmrg   struct pipe_framebuffer_state state;
50001e04c3fSmrg   unsigned i;
50101e04c3fSmrg
50201e04c3fSmrg   if (fb) {
50301e04c3fSmrg      memcpy(&state, fb, sizeof(state));
50401e04c3fSmrg
50501e04c3fSmrg      for (i = 0; i < fb->nr_cbufs; i++)
50601e04c3fSmrg         state.cbufs[i] = tegra_surface_unwrap(fb->cbufs[i]);
50701e04c3fSmrg
50801e04c3fSmrg      while (i < PIPE_MAX_COLOR_BUFS)
50901e04c3fSmrg         state.cbufs[i++] = NULL;
51001e04c3fSmrg
51101e04c3fSmrg      state.zsbuf = tegra_surface_unwrap(fb->zsbuf);
51201e04c3fSmrg
51301e04c3fSmrg      fb = &state;
51401e04c3fSmrg   }
51501e04c3fSmrg
51601e04c3fSmrg   context->gpu->set_framebuffer_state(context->gpu, fb);
51701e04c3fSmrg}
51801e04c3fSmrg
51901e04c3fSmrgstatic void
52001e04c3fSmrgtegra_set_polygon_stipple(struct pipe_context *pcontext,
52101e04c3fSmrg                          const struct pipe_poly_stipple *stipple)
52201e04c3fSmrg{
52301e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
52401e04c3fSmrg
52501e04c3fSmrg   context->gpu->set_polygon_stipple(context->gpu, stipple);
52601e04c3fSmrg}
52701e04c3fSmrg
52801e04c3fSmrgstatic void
52901e04c3fSmrgtegra_set_scissor_states(struct pipe_context *pcontext, unsigned start_slot,
53001e04c3fSmrg                         unsigned num_scissors,
53101e04c3fSmrg                         const struct pipe_scissor_state *scissors)
53201e04c3fSmrg{
53301e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
53401e04c3fSmrg
53501e04c3fSmrg   context->gpu->set_scissor_states(context->gpu, start_slot, num_scissors,
53601e04c3fSmrg                                    scissors);
53701e04c3fSmrg}
53801e04c3fSmrg
53901e04c3fSmrgstatic void
5407ec681f3Smrgtegra_set_window_rectangles(struct pipe_context *pcontext, bool include,
54101e04c3fSmrg                            unsigned int num_rectangles,
54201e04c3fSmrg                            const struct pipe_scissor_state *rectangles)
54301e04c3fSmrg{
54401e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
54501e04c3fSmrg
54601e04c3fSmrg   context->gpu->set_window_rectangles(context->gpu, include, num_rectangles,
54701e04c3fSmrg                                       rectangles);
54801e04c3fSmrg}
54901e04c3fSmrg
55001e04c3fSmrgstatic void
55101e04c3fSmrgtegra_set_viewport_states(struct pipe_context *pcontext, unsigned start_slot,
55201e04c3fSmrg                          unsigned num_viewports,
55301e04c3fSmrg                          const struct pipe_viewport_state *viewports)
55401e04c3fSmrg{
55501e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
55601e04c3fSmrg
55701e04c3fSmrg   context->gpu->set_viewport_states(context->gpu, start_slot, num_viewports,
55801e04c3fSmrg                                     viewports);
55901e04c3fSmrg}
56001e04c3fSmrg
56101e04c3fSmrgstatic void
56201e04c3fSmrgtegra_set_sampler_views(struct pipe_context *pcontext, unsigned shader,
56301e04c3fSmrg                        unsigned start_slot, unsigned num_views,
5647ec681f3Smrg                        unsigned unbind_num_trailing_slots,
5657ec681f3Smrg                        bool take_ownership,
56601e04c3fSmrg                        struct pipe_sampler_view **pviews)
56701e04c3fSmrg{
56801e04c3fSmrg   struct pipe_sampler_view *views[PIPE_MAX_SHADER_SAMPLER_VIEWS];
56901e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
5707ec681f3Smrg   struct tegra_sampler_view *view;
57101e04c3fSmrg   unsigned i;
57201e04c3fSmrg
5737ec681f3Smrg   for (i = 0; i < num_views; i++) {
5747ec681f3Smrg      /* adjust private reference count */
5757ec681f3Smrg      view = to_tegra_sampler_view(pviews[i]);
5767ec681f3Smrg      if (view) {
5777ec681f3Smrg         view->refcount--;
5787ec681f3Smrg         if (!view->refcount) {
5797ec681f3Smrg            view->refcount = 100000000;
5807ec681f3Smrg            p_atomic_add(&view->gpu->reference.count, view->refcount);
5817ec681f3Smrg         }
5827ec681f3Smrg      }
5837ec681f3Smrg
58401e04c3fSmrg      views[i] = tegra_sampler_view_unwrap(pviews[i]);
5857ec681f3Smrg   }
58601e04c3fSmrg
58701e04c3fSmrg   context->gpu->set_sampler_views(context->gpu, shader, start_slot,
5887ec681f3Smrg                                   num_views, unbind_num_trailing_slots,
5897ec681f3Smrg                                   take_ownership, views);
59001e04c3fSmrg}
59101e04c3fSmrg
59201e04c3fSmrgstatic void
59301e04c3fSmrgtegra_set_tess_state(struct pipe_context *pcontext,
59401e04c3fSmrg                     const float default_outer_level[4],
59501e04c3fSmrg                     const float default_inner_level[2])
59601e04c3fSmrg{
59701e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
59801e04c3fSmrg
59901e04c3fSmrg   context->gpu->set_tess_state(context->gpu, default_outer_level,
60001e04c3fSmrg                                default_inner_level);
60101e04c3fSmrg}
60201e04c3fSmrg
60301e04c3fSmrgstatic void
60401e04c3fSmrgtegra_set_debug_callback(struct pipe_context *pcontext,
60501e04c3fSmrg                         const struct pipe_debug_callback *callback)
60601e04c3fSmrg{
60701e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
60801e04c3fSmrg
60901e04c3fSmrg   context->gpu->set_debug_callback(context->gpu, callback);
61001e04c3fSmrg}
61101e04c3fSmrg
61201e04c3fSmrgstatic void
61301e04c3fSmrgtegra_set_shader_buffers(struct pipe_context *pcontext, unsigned int shader,
61401e04c3fSmrg                         unsigned start, unsigned count,
6159f464c52Smaya                         const struct pipe_shader_buffer *buffers,
6169f464c52Smaya                         unsigned writable_bitmask)
61701e04c3fSmrg{
61801e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
61901e04c3fSmrg
62001e04c3fSmrg   context->gpu->set_shader_buffers(context->gpu, shader, start, count,
6219f464c52Smaya                                    buffers, writable_bitmask);
62201e04c3fSmrg}
62301e04c3fSmrg
62401e04c3fSmrgstatic void
62501e04c3fSmrgtegra_set_shader_images(struct pipe_context *pcontext, unsigned int shader,
62601e04c3fSmrg                        unsigned start, unsigned count,
6277ec681f3Smrg                        unsigned unbind_num_trailing_slots,
62801e04c3fSmrg                        const struct pipe_image_view *images)
62901e04c3fSmrg{
63001e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
63101e04c3fSmrg
63201e04c3fSmrg   context->gpu->set_shader_images(context->gpu, shader, start, count,
6337ec681f3Smrg                                   unbind_num_trailing_slots, images);
63401e04c3fSmrg}
63501e04c3fSmrg
63601e04c3fSmrgstatic void
63701e04c3fSmrgtegra_set_vertex_buffers(struct pipe_context *pcontext, unsigned start_slot,
6387ec681f3Smrg                         unsigned num_buffers, unsigned unbind_num_trailing_slots,
6397ec681f3Smrg                         bool take_ownership,
64001e04c3fSmrg                         const struct pipe_vertex_buffer *buffers)
64101e04c3fSmrg{
64201e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
64301e04c3fSmrg   struct pipe_vertex_buffer buf[PIPE_MAX_SHADER_INPUTS];
64401e04c3fSmrg   unsigned i;
64501e04c3fSmrg
64601e04c3fSmrg   if (num_buffers && buffers) {
64701e04c3fSmrg      memcpy(buf, buffers, num_buffers * sizeof(struct pipe_vertex_buffer));
64801e04c3fSmrg
64901e04c3fSmrg      for (i = 0; i < num_buffers; i++) {
65001e04c3fSmrg         if (!buf[i].is_user_buffer)
65101e04c3fSmrg            buf[i].buffer.resource = tegra_resource_unwrap(buf[i].buffer.resource);
65201e04c3fSmrg      }
65301e04c3fSmrg
65401e04c3fSmrg      buffers = buf;
65501e04c3fSmrg   }
65601e04c3fSmrg
65701e04c3fSmrg   context->gpu->set_vertex_buffers(context->gpu, start_slot, num_buffers,
6587ec681f3Smrg                                    unbind_num_trailing_slots,
6597ec681f3Smrg                                    take_ownership, buffers);
66001e04c3fSmrg}
66101e04c3fSmrg
66201e04c3fSmrgstatic struct pipe_stream_output_target *
66301e04c3fSmrgtegra_create_stream_output_target(struct pipe_context *pcontext,
66401e04c3fSmrg                                  struct pipe_resource *presource,
66501e04c3fSmrg                                  unsigned buffer_offset,
66601e04c3fSmrg                                  unsigned buffer_size)
66701e04c3fSmrg{
66801e04c3fSmrg   struct tegra_resource *resource = to_tegra_resource(presource);
66901e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
67001e04c3fSmrg
67101e04c3fSmrg   return context->gpu->create_stream_output_target(context->gpu,
67201e04c3fSmrg                                                    resource->gpu,
67301e04c3fSmrg                                                    buffer_offset,
67401e04c3fSmrg                                                    buffer_size);
67501e04c3fSmrg}
67601e04c3fSmrg
67701e04c3fSmrgstatic void
67801e04c3fSmrgtegra_stream_output_target_destroy(struct pipe_context *pcontext,
67901e04c3fSmrg                                   struct pipe_stream_output_target *target)
68001e04c3fSmrg{
68101e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
68201e04c3fSmrg
68301e04c3fSmrg   context->gpu->stream_output_target_destroy(context->gpu, target);
68401e04c3fSmrg}
68501e04c3fSmrg
68601e04c3fSmrgstatic void
68701e04c3fSmrgtegra_set_stream_output_targets(struct pipe_context *pcontext,
68801e04c3fSmrg                                unsigned num_targets,
68901e04c3fSmrg                                struct pipe_stream_output_target **targets,
69001e04c3fSmrg                                const unsigned *offsets)
69101e04c3fSmrg{
69201e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
69301e04c3fSmrg
69401e04c3fSmrg   context->gpu->set_stream_output_targets(context->gpu, num_targets,
69501e04c3fSmrg                                           targets, offsets);
69601e04c3fSmrg}
69701e04c3fSmrg
69801e04c3fSmrgstatic void
69901e04c3fSmrgtegra_resource_copy_region(struct pipe_context *pcontext,
70001e04c3fSmrg                           struct pipe_resource *pdst,
70101e04c3fSmrg                           unsigned int dst_level,
70201e04c3fSmrg                           unsigned int dstx,
70301e04c3fSmrg                           unsigned int dsty,
70401e04c3fSmrg                           unsigned int dstz,
70501e04c3fSmrg                           struct pipe_resource *psrc,
70601e04c3fSmrg                           unsigned int src_level,
70701e04c3fSmrg                           const struct pipe_box *src_box)
70801e04c3fSmrg{
70901e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
71001e04c3fSmrg   struct tegra_resource *dst = to_tegra_resource(pdst);
71101e04c3fSmrg   struct tegra_resource *src = to_tegra_resource(psrc);
71201e04c3fSmrg
71301e04c3fSmrg   context->gpu->resource_copy_region(context->gpu, dst->gpu, dst_level, dstx,
71401e04c3fSmrg                                      dsty, dstz, src->gpu, src_level,
71501e04c3fSmrg                                      src_box);
71601e04c3fSmrg}
71701e04c3fSmrg
71801e04c3fSmrgstatic void
71901e04c3fSmrgtegra_blit(struct pipe_context *pcontext, const struct pipe_blit_info *pinfo)
72001e04c3fSmrg{
72101e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
72201e04c3fSmrg   struct pipe_blit_info info;
72301e04c3fSmrg
72401e04c3fSmrg   if (pinfo) {
72501e04c3fSmrg      memcpy(&info, pinfo, sizeof(info));
72601e04c3fSmrg      info.dst.resource = tegra_resource_unwrap(info.dst.resource);
72701e04c3fSmrg      info.src.resource = tegra_resource_unwrap(info.src.resource);
72801e04c3fSmrg      pinfo = &info;
72901e04c3fSmrg   }
73001e04c3fSmrg
73101e04c3fSmrg   context->gpu->blit(context->gpu, pinfo);
73201e04c3fSmrg}
73301e04c3fSmrg
73401e04c3fSmrgstatic void
7357ec681f3Smrgtegra_clear(struct pipe_context *pcontext, unsigned buffers, const struct pipe_scissor_state *scissor_state,
73601e04c3fSmrg            const union pipe_color_union *color, double depth,
73701e04c3fSmrg            unsigned stencil)
73801e04c3fSmrg{
73901e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
74001e04c3fSmrg
7417ec681f3Smrg   context->gpu->clear(context->gpu, buffers, NULL, color, depth, stencil);
74201e04c3fSmrg}
74301e04c3fSmrg
74401e04c3fSmrgstatic void
74501e04c3fSmrgtegra_clear_render_target(struct pipe_context *pcontext,
74601e04c3fSmrg                          struct pipe_surface *pdst,
74701e04c3fSmrg                          const union pipe_color_union *color,
74801e04c3fSmrg                          unsigned int dstx,
74901e04c3fSmrg                          unsigned int dsty,
75001e04c3fSmrg                          unsigned int width,
75101e04c3fSmrg                          unsigned int height,
75201e04c3fSmrg                          bool render_condition)
75301e04c3fSmrg{
75401e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
75501e04c3fSmrg   struct tegra_surface *dst = to_tegra_surface(pdst);
75601e04c3fSmrg
75701e04c3fSmrg   context->gpu->clear_render_target(context->gpu, dst->gpu, color, dstx,
75801e04c3fSmrg                                     dsty, width, height, render_condition);
75901e04c3fSmrg}
76001e04c3fSmrg
76101e04c3fSmrgstatic void
76201e04c3fSmrgtegra_clear_depth_stencil(struct pipe_context *pcontext,
76301e04c3fSmrg                          struct pipe_surface *pdst,
76401e04c3fSmrg                          unsigned int flags,
76501e04c3fSmrg                          double depth,
76601e04c3fSmrg                          unsigned int stencil,
76701e04c3fSmrg                          unsigned int dstx,
76801e04c3fSmrg                          unsigned int dsty,
76901e04c3fSmrg                          unsigned int width,
77001e04c3fSmrg                          unsigned int height,
77101e04c3fSmrg                          bool render_condition)
77201e04c3fSmrg{
77301e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
77401e04c3fSmrg   struct tegra_surface *dst = to_tegra_surface(pdst);
77501e04c3fSmrg
77601e04c3fSmrg   context->gpu->clear_depth_stencil(context->gpu, dst->gpu, flags, depth,
77701e04c3fSmrg                                     stencil, dstx, dsty, width, height,
77801e04c3fSmrg                                     render_condition);
77901e04c3fSmrg}
78001e04c3fSmrg
78101e04c3fSmrgstatic void
78201e04c3fSmrgtegra_clear_texture(struct pipe_context *pcontext,
78301e04c3fSmrg                    struct pipe_resource *presource,
78401e04c3fSmrg                    unsigned int level,
78501e04c3fSmrg                    const struct pipe_box *box,
78601e04c3fSmrg                    const void *data)
78701e04c3fSmrg{
78801e04c3fSmrg   struct tegra_resource *resource = to_tegra_resource(presource);
78901e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
79001e04c3fSmrg
79101e04c3fSmrg   context->gpu->clear_texture(context->gpu, resource->gpu, level, box, data);
79201e04c3fSmrg}
79301e04c3fSmrg
79401e04c3fSmrgstatic void
79501e04c3fSmrgtegra_clear_buffer(struct pipe_context *pcontext,
79601e04c3fSmrg                   struct pipe_resource *presource,
79701e04c3fSmrg                   unsigned int offset,
79801e04c3fSmrg                   unsigned int size,
79901e04c3fSmrg                   const void *value,
80001e04c3fSmrg                   int value_size)
80101e04c3fSmrg{
80201e04c3fSmrg   struct tegra_resource *resource = to_tegra_resource(presource);
80301e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
80401e04c3fSmrg
80501e04c3fSmrg   context->gpu->clear_buffer(context->gpu, resource->gpu, offset, size,
80601e04c3fSmrg                              value, value_size);
80701e04c3fSmrg}
80801e04c3fSmrg
80901e04c3fSmrgstatic void
81001e04c3fSmrgtegra_flush(struct pipe_context *pcontext, struct pipe_fence_handle **fence,
81101e04c3fSmrg            unsigned flags)
81201e04c3fSmrg{
81301e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
81401e04c3fSmrg
81501e04c3fSmrg   context->gpu->flush(context->gpu, fence, flags);
81601e04c3fSmrg}
81701e04c3fSmrg
81801e04c3fSmrgstatic void
81901e04c3fSmrgtegra_create_fence_fd(struct pipe_context *pcontext,
82001e04c3fSmrg                      struct pipe_fence_handle **fence,
82101e04c3fSmrg                      int fd, enum pipe_fd_type type)
82201e04c3fSmrg{
82301e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
82401e04c3fSmrg
82501e04c3fSmrg   assert(type == PIPE_FD_TYPE_NATIVE_SYNC);
82601e04c3fSmrg   context->gpu->create_fence_fd(context->gpu, fence, fd, type);
82701e04c3fSmrg}
82801e04c3fSmrg
82901e04c3fSmrgstatic void
83001e04c3fSmrgtegra_fence_server_sync(struct pipe_context *pcontext,
83101e04c3fSmrg                        struct pipe_fence_handle *fence)
83201e04c3fSmrg{
83301e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
83401e04c3fSmrg
83501e04c3fSmrg   context->gpu->fence_server_sync(context->gpu, fence);
83601e04c3fSmrg}
83701e04c3fSmrg
83801e04c3fSmrgstatic struct pipe_sampler_view *
83901e04c3fSmrgtegra_create_sampler_view(struct pipe_context *pcontext,
84001e04c3fSmrg                          struct pipe_resource *presource,
84101e04c3fSmrg                          const struct pipe_sampler_view *template)
84201e04c3fSmrg{
84301e04c3fSmrg   struct tegra_resource *resource = to_tegra_resource(presource);
84401e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
84501e04c3fSmrg   struct tegra_sampler_view *view;
84601e04c3fSmrg
84701e04c3fSmrg   view = calloc(1, sizeof(*view));
84801e04c3fSmrg   if (!view)
84901e04c3fSmrg      return NULL;
85001e04c3fSmrg
8517ec681f3Smrg   view->base = *template;
8527ec681f3Smrg   view->base.context = pcontext;
85301e04c3fSmrg   /* overwrite to prevent reference from being released */
85401e04c3fSmrg   view->base.texture = NULL;
85501e04c3fSmrg   pipe_reference_init(&view->base.reference, 1);
85601e04c3fSmrg   pipe_resource_reference(&view->base.texture, presource);
8577ec681f3Smrg
8587ec681f3Smrg   view->gpu = context->gpu->create_sampler_view(context->gpu, resource->gpu,
8597ec681f3Smrg                                                 template);
8607ec681f3Smrg
8617ec681f3Smrg   /* use private reference count */
8627ec681f3Smrg   view->gpu->reference.count += 100000000;
8637ec681f3Smrg   view->refcount = 100000000;
86401e04c3fSmrg
86501e04c3fSmrg   return &view->base;
86601e04c3fSmrg}
86701e04c3fSmrg
86801e04c3fSmrgstatic void
86901e04c3fSmrgtegra_sampler_view_destroy(struct pipe_context *pcontext,
87001e04c3fSmrg                           struct pipe_sampler_view *pview)
87101e04c3fSmrg{
87201e04c3fSmrg   struct tegra_sampler_view *view = to_tegra_sampler_view(pview);
87301e04c3fSmrg
87401e04c3fSmrg   pipe_resource_reference(&view->base.texture, NULL);
8757ec681f3Smrg   /* adjust private reference count */
8767ec681f3Smrg   p_atomic_add(&view->gpu->reference.count, -view->refcount);
87701e04c3fSmrg   pipe_sampler_view_reference(&view->gpu, NULL);
87801e04c3fSmrg   free(view);
87901e04c3fSmrg}
88001e04c3fSmrg
88101e04c3fSmrgstatic struct pipe_surface *
88201e04c3fSmrgtegra_create_surface(struct pipe_context *pcontext,
88301e04c3fSmrg                     struct pipe_resource *presource,
88401e04c3fSmrg                     const struct pipe_surface *template)
88501e04c3fSmrg{
88601e04c3fSmrg   struct tegra_resource *resource = to_tegra_resource(presource);
88701e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
88801e04c3fSmrg   struct tegra_surface *surface;
88901e04c3fSmrg
89001e04c3fSmrg   surface = calloc(1, sizeof(*surface));
89101e04c3fSmrg   if (!surface)
89201e04c3fSmrg      return NULL;
89301e04c3fSmrg
89401e04c3fSmrg   surface->gpu = context->gpu->create_surface(context->gpu, resource->gpu,
89501e04c3fSmrg                                               template);
89601e04c3fSmrg   if (!surface->gpu) {
89701e04c3fSmrg      free(surface);
89801e04c3fSmrg      return NULL;
89901e04c3fSmrg   }
90001e04c3fSmrg
90101e04c3fSmrg   memcpy(&surface->base, surface->gpu, sizeof(*surface->gpu));
90201e04c3fSmrg   /* overwrite to prevent reference from being released */
90301e04c3fSmrg   surface->base.texture = NULL;
90401e04c3fSmrg
90501e04c3fSmrg   pipe_reference_init(&surface->base.reference, 1);
90601e04c3fSmrg   pipe_resource_reference(&surface->base.texture, presource);
90701e04c3fSmrg   surface->base.context = &context->base;
90801e04c3fSmrg
90901e04c3fSmrg   return &surface->base;
91001e04c3fSmrg}
91101e04c3fSmrg
91201e04c3fSmrgstatic void
91301e04c3fSmrgtegra_surface_destroy(struct pipe_context *pcontext,
91401e04c3fSmrg                      struct pipe_surface *psurface)
91501e04c3fSmrg{
91601e04c3fSmrg   struct tegra_surface *surface = to_tegra_surface(psurface);
91701e04c3fSmrg
91801e04c3fSmrg   pipe_resource_reference(&surface->base.texture, NULL);
91901e04c3fSmrg   pipe_surface_reference(&surface->gpu, NULL);
92001e04c3fSmrg   free(surface);
92101e04c3fSmrg}
92201e04c3fSmrg
92301e04c3fSmrgstatic void *
92401e04c3fSmrgtegra_transfer_map(struct pipe_context *pcontext,
92501e04c3fSmrg                   struct pipe_resource *presource,
92601e04c3fSmrg                   unsigned level, unsigned usage,
92701e04c3fSmrg                   const struct pipe_box *box,
92801e04c3fSmrg                   struct pipe_transfer **ptransfer)
92901e04c3fSmrg{
93001e04c3fSmrg   struct tegra_resource *resource = to_tegra_resource(presource);
93101e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
93201e04c3fSmrg   struct tegra_transfer *transfer;
93301e04c3fSmrg
93401e04c3fSmrg   transfer = calloc(1, sizeof(*transfer));
93501e04c3fSmrg   if (!transfer)
93601e04c3fSmrg      return NULL;
93701e04c3fSmrg
9387ec681f3Smrg   if (presource->target == PIPE_BUFFER) {
9397ec681f3Smrg      transfer->map = context->gpu->buffer_map(context->gpu, resource->gpu,
9407ec681f3Smrg                                                 level, usage, box,
9417ec681f3Smrg                                                 &transfer->gpu);
9427ec681f3Smrg   } else {
9437ec681f3Smrg      transfer->map = context->gpu->texture_map(context->gpu, resource->gpu,
9447ec681f3Smrg                                                 level, usage, box,
9457ec681f3Smrg                                                 &transfer->gpu);
9467ec681f3Smrg   }
94701e04c3fSmrg   memcpy(&transfer->base, transfer->gpu, sizeof(*transfer->gpu));
94801e04c3fSmrg   transfer->base.resource = NULL;
94901e04c3fSmrg   pipe_resource_reference(&transfer->base.resource, presource);
95001e04c3fSmrg
95101e04c3fSmrg   *ptransfer = &transfer->base;
95201e04c3fSmrg
95301e04c3fSmrg   return transfer->map;
95401e04c3fSmrg}
95501e04c3fSmrg
95601e04c3fSmrgstatic void
95701e04c3fSmrgtegra_transfer_flush_region(struct pipe_context *pcontext,
95801e04c3fSmrg                            struct pipe_transfer *ptransfer,
95901e04c3fSmrg                            const struct pipe_box *box)
96001e04c3fSmrg{
96101e04c3fSmrg   struct tegra_transfer *transfer = to_tegra_transfer(ptransfer);
96201e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
96301e04c3fSmrg
96401e04c3fSmrg   context->gpu->transfer_flush_region(context->gpu, transfer->gpu, box);
96501e04c3fSmrg}
96601e04c3fSmrg
96701e04c3fSmrgstatic void
96801e04c3fSmrgtegra_transfer_unmap(struct pipe_context *pcontext,
96901e04c3fSmrg                     struct pipe_transfer *ptransfer)
97001e04c3fSmrg{
97101e04c3fSmrg   struct tegra_transfer *transfer = to_tegra_transfer(ptransfer);
97201e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
97301e04c3fSmrg
9747ec681f3Smrg   if (ptransfer->resource->target == PIPE_BUFFER)
9757ec681f3Smrg      context->gpu->buffer_unmap(context->gpu, transfer->gpu);
9767ec681f3Smrg   else
9777ec681f3Smrg      context->gpu->texture_unmap(context->gpu, transfer->gpu);
97801e04c3fSmrg   pipe_resource_reference(&transfer->base.resource, NULL);
97901e04c3fSmrg   free(transfer);
98001e04c3fSmrg}
98101e04c3fSmrg
98201e04c3fSmrgstatic void
98301e04c3fSmrgtegra_buffer_subdata(struct pipe_context *pcontext,
98401e04c3fSmrg                     struct pipe_resource *presource,
98501e04c3fSmrg                     unsigned usage, unsigned offset,
98601e04c3fSmrg                     unsigned size, const void *data)
98701e04c3fSmrg{
98801e04c3fSmrg   struct tegra_resource *resource = to_tegra_resource(presource);
98901e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
99001e04c3fSmrg
99101e04c3fSmrg   context->gpu->buffer_subdata(context->gpu, resource->gpu, usage, offset,
99201e04c3fSmrg                                size, data);
99301e04c3fSmrg}
99401e04c3fSmrg
99501e04c3fSmrgstatic void
99601e04c3fSmrgtegra_texture_subdata(struct pipe_context *pcontext,
99701e04c3fSmrg                      struct pipe_resource *presource,
99801e04c3fSmrg                      unsigned level,
99901e04c3fSmrg                      unsigned usage,
100001e04c3fSmrg                      const struct pipe_box *box,
100101e04c3fSmrg                      const void *data,
100201e04c3fSmrg                      unsigned stride,
100301e04c3fSmrg                      unsigned layer_stride)
100401e04c3fSmrg{
100501e04c3fSmrg   struct tegra_resource *resource = to_tegra_resource(presource);
100601e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
100701e04c3fSmrg
100801e04c3fSmrg   context->gpu->texture_subdata(context->gpu, resource->gpu, level, usage,
100901e04c3fSmrg                                 box, data, stride, layer_stride);
101001e04c3fSmrg}
101101e04c3fSmrg
101201e04c3fSmrgstatic void
101301e04c3fSmrgtegra_texture_barrier(struct pipe_context *pcontext, unsigned int flags)
101401e04c3fSmrg{
101501e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
101601e04c3fSmrg
101701e04c3fSmrg   context->gpu->texture_barrier(context->gpu, flags);
101801e04c3fSmrg}
101901e04c3fSmrg
102001e04c3fSmrgstatic void
102101e04c3fSmrgtegra_memory_barrier(struct pipe_context *pcontext, unsigned int flags)
102201e04c3fSmrg{
102301e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
102401e04c3fSmrg
10259f464c52Smaya   if (!(flags & ~PIPE_BARRIER_UPDATE))
10269f464c52Smaya      return;
10279f464c52Smaya
102801e04c3fSmrg   context->gpu->memory_barrier(context->gpu, flags);
102901e04c3fSmrg}
103001e04c3fSmrg
103101e04c3fSmrgstatic struct pipe_video_codec *
103201e04c3fSmrgtegra_create_video_codec(struct pipe_context *pcontext,
103301e04c3fSmrg                         const struct pipe_video_codec *template)
103401e04c3fSmrg{
103501e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
103601e04c3fSmrg
103701e04c3fSmrg   return context->gpu->create_video_codec(context->gpu, template);
103801e04c3fSmrg}
103901e04c3fSmrg
104001e04c3fSmrgstatic struct pipe_video_buffer *
104101e04c3fSmrgtegra_create_video_buffer(struct pipe_context *pcontext,
104201e04c3fSmrg                          const struct pipe_video_buffer *template)
104301e04c3fSmrg{
104401e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
104501e04c3fSmrg
104601e04c3fSmrg   return context->gpu->create_video_buffer(context->gpu, template);
104701e04c3fSmrg}
104801e04c3fSmrg
104901e04c3fSmrgstatic void *
105001e04c3fSmrgtegra_create_compute_state(struct pipe_context *pcontext,
105101e04c3fSmrg                           const struct pipe_compute_state *template)
105201e04c3fSmrg{
105301e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
105401e04c3fSmrg
105501e04c3fSmrg   return context->gpu->create_compute_state(context->gpu, template);
105601e04c3fSmrg}
105701e04c3fSmrg
105801e04c3fSmrgstatic void
105901e04c3fSmrgtegra_bind_compute_state(struct pipe_context *pcontext, void *so)
106001e04c3fSmrg{
106101e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
106201e04c3fSmrg
106301e04c3fSmrg   context->gpu->bind_compute_state(context->gpu, so);
106401e04c3fSmrg}
106501e04c3fSmrg
106601e04c3fSmrgstatic void
106701e04c3fSmrgtegra_delete_compute_state(struct pipe_context *pcontext, void *so)
106801e04c3fSmrg{
106901e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
107001e04c3fSmrg
107101e04c3fSmrg   context->gpu->delete_compute_state(context->gpu, so);
107201e04c3fSmrg}
107301e04c3fSmrg
107401e04c3fSmrgstatic void
107501e04c3fSmrgtegra_set_compute_resources(struct pipe_context *pcontext,
107601e04c3fSmrg                            unsigned int start, unsigned int count,
107701e04c3fSmrg                            struct pipe_surface **resources)
107801e04c3fSmrg{
107901e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
108001e04c3fSmrg
108101e04c3fSmrg   /* XXX unwrap resources */
108201e04c3fSmrg
108301e04c3fSmrg   context->gpu->set_compute_resources(context->gpu, start, count, resources);
108401e04c3fSmrg}
108501e04c3fSmrg
108601e04c3fSmrgstatic void
108701e04c3fSmrgtegra_set_global_binding(struct pipe_context *pcontext, unsigned int first,
108801e04c3fSmrg                         unsigned int count, struct pipe_resource **resources,
108901e04c3fSmrg                         uint32_t **handles)
109001e04c3fSmrg{
109101e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
109201e04c3fSmrg
109301e04c3fSmrg   /* XXX unwrap resources */
109401e04c3fSmrg
109501e04c3fSmrg   context->gpu->set_global_binding(context->gpu, first, count, resources,
109601e04c3fSmrg                                    handles);
109701e04c3fSmrg}
109801e04c3fSmrg
109901e04c3fSmrgstatic void
110001e04c3fSmrgtegra_launch_grid(struct pipe_context *pcontext,
110101e04c3fSmrg                  const struct pipe_grid_info *info)
110201e04c3fSmrg{
110301e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
110401e04c3fSmrg
110501e04c3fSmrg   /* XXX unwrap info->indirect? */
110601e04c3fSmrg
110701e04c3fSmrg   context->gpu->launch_grid(context->gpu, info);
110801e04c3fSmrg}
110901e04c3fSmrg
111001e04c3fSmrgstatic void
111101e04c3fSmrgtegra_get_sample_position(struct pipe_context *pcontext, unsigned int count,
111201e04c3fSmrg                          unsigned int index, float *value)
111301e04c3fSmrg{
111401e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
111501e04c3fSmrg
111601e04c3fSmrg   context->gpu->get_sample_position(context->gpu, count, index, value);
111701e04c3fSmrg}
111801e04c3fSmrg
111901e04c3fSmrgstatic uint64_t
112001e04c3fSmrgtegra_get_timestamp(struct pipe_context *pcontext)
112101e04c3fSmrg{
112201e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
112301e04c3fSmrg
112401e04c3fSmrg   return context->gpu->get_timestamp(context->gpu);
112501e04c3fSmrg}
112601e04c3fSmrg
112701e04c3fSmrgstatic void
112801e04c3fSmrgtegra_flush_resource(struct pipe_context *pcontext,
112901e04c3fSmrg                     struct pipe_resource *presource)
113001e04c3fSmrg{
113101e04c3fSmrg   struct tegra_resource *resource = to_tegra_resource(presource);
113201e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
113301e04c3fSmrg
113401e04c3fSmrg   context->gpu->flush_resource(context->gpu, resource->gpu);
113501e04c3fSmrg}
113601e04c3fSmrg
113701e04c3fSmrgstatic void
113801e04c3fSmrgtegra_invalidate_resource(struct pipe_context *pcontext,
113901e04c3fSmrg                          struct pipe_resource *presource)
114001e04c3fSmrg{
114101e04c3fSmrg   struct tegra_resource *resource = to_tegra_resource(presource);
114201e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
114301e04c3fSmrg
114401e04c3fSmrg   context->gpu->invalidate_resource(context->gpu, resource->gpu);
114501e04c3fSmrg}
114601e04c3fSmrg
114701e04c3fSmrgstatic enum pipe_reset_status
114801e04c3fSmrgtegra_get_device_reset_status(struct pipe_context *pcontext)
114901e04c3fSmrg{
115001e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
115101e04c3fSmrg
115201e04c3fSmrg   return context->gpu->get_device_reset_status(context->gpu);
115301e04c3fSmrg}
115401e04c3fSmrg
115501e04c3fSmrgstatic void
115601e04c3fSmrgtegra_set_device_reset_callback(struct pipe_context *pcontext,
115701e04c3fSmrg                                const struct pipe_device_reset_callback *cb)
115801e04c3fSmrg{
115901e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
116001e04c3fSmrg
116101e04c3fSmrg   context->gpu->set_device_reset_callback(context->gpu, cb);
116201e04c3fSmrg}
116301e04c3fSmrg
116401e04c3fSmrgstatic void
116501e04c3fSmrgtegra_dump_debug_state(struct pipe_context *pcontext, FILE *stream,
116601e04c3fSmrg                       unsigned int flags)
116701e04c3fSmrg{
116801e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
116901e04c3fSmrg
117001e04c3fSmrg   context->gpu->dump_debug_state(context->gpu, stream, flags);
117101e04c3fSmrg}
117201e04c3fSmrg
117301e04c3fSmrgstatic void
117401e04c3fSmrgtegra_emit_string_marker(struct pipe_context *pcontext, const char *string,
117501e04c3fSmrg                         int length)
117601e04c3fSmrg{
117701e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
117801e04c3fSmrg
117901e04c3fSmrg   context->gpu->emit_string_marker(context->gpu, string, length);
118001e04c3fSmrg}
118101e04c3fSmrg
11827ec681f3Smrgstatic bool
118301e04c3fSmrgtegra_generate_mipmap(struct pipe_context *pcontext,
118401e04c3fSmrg                      struct pipe_resource *presource,
118501e04c3fSmrg                      enum pipe_format format,
118601e04c3fSmrg                      unsigned int base_level,
118701e04c3fSmrg                      unsigned int last_level,
118801e04c3fSmrg                      unsigned int first_layer,
118901e04c3fSmrg                      unsigned int last_layer)
119001e04c3fSmrg{
119101e04c3fSmrg   struct tegra_resource *resource = to_tegra_resource(presource);
119201e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
119301e04c3fSmrg
119401e04c3fSmrg   return context->gpu->generate_mipmap(context->gpu, resource->gpu, format,
119501e04c3fSmrg                                        base_level, last_level, first_layer,
119601e04c3fSmrg                                        last_layer);
119701e04c3fSmrg}
119801e04c3fSmrg
119901e04c3fSmrgstatic uint64_t
120001e04c3fSmrgtegra_create_texture_handle(struct pipe_context *pcontext,
120101e04c3fSmrg                            struct pipe_sampler_view *view,
120201e04c3fSmrg                            const struct pipe_sampler_state *state)
120301e04c3fSmrg{
120401e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
120501e04c3fSmrg
120601e04c3fSmrg   return context->gpu->create_texture_handle(context->gpu, view, state);
120701e04c3fSmrg}
120801e04c3fSmrg
120901e04c3fSmrgstatic void tegra_delete_texture_handle(struct pipe_context *pcontext,
121001e04c3fSmrg                                        uint64_t handle)
121101e04c3fSmrg{
121201e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
121301e04c3fSmrg
121401e04c3fSmrg   context->gpu->delete_texture_handle(context->gpu, handle);
121501e04c3fSmrg}
121601e04c3fSmrg
121701e04c3fSmrgstatic void tegra_make_texture_handle_resident(struct pipe_context *pcontext,
121801e04c3fSmrg                                               uint64_t handle, bool resident)
121901e04c3fSmrg{
122001e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
122101e04c3fSmrg
122201e04c3fSmrg   context->gpu->make_texture_handle_resident(context->gpu, handle, resident);
122301e04c3fSmrg}
122401e04c3fSmrg
122501e04c3fSmrgstatic uint64_t tegra_create_image_handle(struct pipe_context *pcontext,
122601e04c3fSmrg                                          const struct pipe_image_view *image)
122701e04c3fSmrg{
122801e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
122901e04c3fSmrg
123001e04c3fSmrg   return context->gpu->create_image_handle(context->gpu, image);
123101e04c3fSmrg}
123201e04c3fSmrg
123301e04c3fSmrgstatic void tegra_delete_image_handle(struct pipe_context *pcontext,
123401e04c3fSmrg                                      uint64_t handle)
123501e04c3fSmrg{
123601e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
123701e04c3fSmrg
123801e04c3fSmrg   context->gpu->delete_image_handle(context->gpu, handle);
123901e04c3fSmrg}
124001e04c3fSmrg
124101e04c3fSmrgstatic void tegra_make_image_handle_resident(struct pipe_context *pcontext,
124201e04c3fSmrg                                             uint64_t handle, unsigned access,
124301e04c3fSmrg                                             bool resident)
124401e04c3fSmrg{
124501e04c3fSmrg   struct tegra_context *context = to_tegra_context(pcontext);
124601e04c3fSmrg
124701e04c3fSmrg   context->gpu->make_image_handle_resident(context->gpu, handle, access,
124801e04c3fSmrg                                            resident);
124901e04c3fSmrg}
125001e04c3fSmrg
125101e04c3fSmrgstruct pipe_context *
125201e04c3fSmrgtegra_screen_context_create(struct pipe_screen *pscreen, void *priv,
125301e04c3fSmrg                            unsigned int flags)
125401e04c3fSmrg{
125501e04c3fSmrg   struct tegra_screen *screen = to_tegra_screen(pscreen);
125601e04c3fSmrg   struct tegra_context *context;
125701e04c3fSmrg
125801e04c3fSmrg   context = calloc(1, sizeof(*context));
125901e04c3fSmrg   if (!context)
126001e04c3fSmrg      return NULL;
126101e04c3fSmrg
126201e04c3fSmrg   context->gpu = screen->gpu->context_create(screen->gpu, priv, flags);
126301e04c3fSmrg   if (!context->gpu) {
126401e04c3fSmrg      debug_error("failed to create GPU context\n");
126501e04c3fSmrg      goto free;
126601e04c3fSmrg   }
126701e04c3fSmrg
126801e04c3fSmrg   context->base.screen = &screen->base;
126901e04c3fSmrg   context->base.priv = priv;
127001e04c3fSmrg
127101e04c3fSmrg   /*
127201e04c3fSmrg    * Create custom stream and const uploaders. Note that technically nouveau
127301e04c3fSmrg    * already creates uploaders that could be reused, but that would make the
127401e04c3fSmrg    * resource unwrapping rather complicate. The reason for that is that both
127501e04c3fSmrg    * uploaders create resources based on the context that they were created
127601e04c3fSmrg    * from, which means that nouveau's uploader will use the nouveau context
127701e04c3fSmrg    * which means that those resources must not be unwrapped. So before each
127801e04c3fSmrg    * resource is unwrapped, the code would need to check that it does not
127901e04c3fSmrg    * correspond to the uploaders' buffers.
128001e04c3fSmrg    *
128101e04c3fSmrg    * However, duplicating the uploaders here sounds worse than it is. The
128201e04c3fSmrg    * default implementation that nouveau uses allocates buffers lazily, and
128301e04c3fSmrg    * since it is never used, no buffers will every be allocated and the only
128401e04c3fSmrg    * memory wasted is that occupied by the nouveau uploader itself.
128501e04c3fSmrg    */
128601e04c3fSmrg   context->base.stream_uploader = u_upload_create_default(&context->base);
128701e04c3fSmrg   if (!context->base.stream_uploader)
128801e04c3fSmrg      goto destroy;
128901e04c3fSmrg
129001e04c3fSmrg   context->base.const_uploader = context->base.stream_uploader;
129101e04c3fSmrg
129201e04c3fSmrg   context->base.destroy = tegra_destroy;
129301e04c3fSmrg
129401e04c3fSmrg   context->base.draw_vbo = tegra_draw_vbo;
129501e04c3fSmrg
129601e04c3fSmrg   context->base.render_condition = tegra_render_condition;
129701e04c3fSmrg
129801e04c3fSmrg   context->base.create_query = tegra_create_query;
129901e04c3fSmrg   context->base.create_batch_query = tegra_create_batch_query;
130001e04c3fSmrg   context->base.destroy_query = tegra_destroy_query;
130101e04c3fSmrg   context->base.begin_query = tegra_begin_query;
130201e04c3fSmrg   context->base.end_query = tegra_end_query;
130301e04c3fSmrg   context->base.get_query_result = tegra_get_query_result;
130401e04c3fSmrg   context->base.get_query_result_resource = tegra_get_query_result_resource;
130501e04c3fSmrg   context->base.set_active_query_state = tegra_set_active_query_state;
130601e04c3fSmrg
130701e04c3fSmrg   context->base.create_blend_state = tegra_create_blend_state;
130801e04c3fSmrg   context->base.bind_blend_state = tegra_bind_blend_state;
130901e04c3fSmrg   context->base.delete_blend_state = tegra_delete_blend_state;
131001e04c3fSmrg
131101e04c3fSmrg   context->base.create_sampler_state = tegra_create_sampler_state;
131201e04c3fSmrg   context->base.bind_sampler_states = tegra_bind_sampler_states;
131301e04c3fSmrg   context->base.delete_sampler_state = tegra_delete_sampler_state;
131401e04c3fSmrg
131501e04c3fSmrg   context->base.create_rasterizer_state = tegra_create_rasterizer_state;
131601e04c3fSmrg   context->base.bind_rasterizer_state = tegra_bind_rasterizer_state;
131701e04c3fSmrg   context->base.delete_rasterizer_state = tegra_delete_rasterizer_state;
131801e04c3fSmrg
131901e04c3fSmrg   context->base.create_depth_stencil_alpha_state = tegra_create_depth_stencil_alpha_state;
132001e04c3fSmrg   context->base.bind_depth_stencil_alpha_state = tegra_bind_depth_stencil_alpha_state;
132101e04c3fSmrg   context->base.delete_depth_stencil_alpha_state = tegra_delete_depth_stencil_alpha_state;
132201e04c3fSmrg
132301e04c3fSmrg   context->base.create_fs_state = tegra_create_fs_state;
132401e04c3fSmrg   context->base.bind_fs_state = tegra_bind_fs_state;
132501e04c3fSmrg   context->base.delete_fs_state = tegra_delete_fs_state;
132601e04c3fSmrg
132701e04c3fSmrg   context->base.create_vs_state = tegra_create_vs_state;
132801e04c3fSmrg   context->base.bind_vs_state = tegra_bind_vs_state;
132901e04c3fSmrg   context->base.delete_vs_state = tegra_delete_vs_state;
133001e04c3fSmrg
133101e04c3fSmrg   context->base.create_gs_state = tegra_create_gs_state;
133201e04c3fSmrg   context->base.bind_gs_state = tegra_bind_gs_state;
133301e04c3fSmrg   context->base.delete_gs_state = tegra_delete_gs_state;
133401e04c3fSmrg
133501e04c3fSmrg   context->base.create_tcs_state = tegra_create_tcs_state;
133601e04c3fSmrg   context->base.bind_tcs_state = tegra_bind_tcs_state;
133701e04c3fSmrg   context->base.delete_tcs_state = tegra_delete_tcs_state;
133801e04c3fSmrg
133901e04c3fSmrg   context->base.create_tes_state = tegra_create_tes_state;
134001e04c3fSmrg   context->base.bind_tes_state = tegra_bind_tes_state;
134101e04c3fSmrg   context->base.delete_tes_state = tegra_delete_tes_state;
134201e04c3fSmrg
134301e04c3fSmrg   context->base.create_vertex_elements_state = tegra_create_vertex_elements_state;
134401e04c3fSmrg   context->base.bind_vertex_elements_state = tegra_bind_vertex_elements_state;
134501e04c3fSmrg   context->base.delete_vertex_elements_state = tegra_delete_vertex_elements_state;
134601e04c3fSmrg
134701e04c3fSmrg   context->base.set_blend_color = tegra_set_blend_color;
134801e04c3fSmrg   context->base.set_stencil_ref = tegra_set_stencil_ref;
134901e04c3fSmrg   context->base.set_sample_mask = tegra_set_sample_mask;
135001e04c3fSmrg   context->base.set_min_samples = tegra_set_min_samples;
135101e04c3fSmrg   context->base.set_clip_state = tegra_set_clip_state;
135201e04c3fSmrg
135301e04c3fSmrg   context->base.set_constant_buffer = tegra_set_constant_buffer;
135401e04c3fSmrg   context->base.set_framebuffer_state = tegra_set_framebuffer_state;
135501e04c3fSmrg   context->base.set_polygon_stipple = tegra_set_polygon_stipple;
135601e04c3fSmrg   context->base.set_scissor_states = tegra_set_scissor_states;
135701e04c3fSmrg   context->base.set_window_rectangles = tegra_set_window_rectangles;
135801e04c3fSmrg   context->base.set_viewport_states = tegra_set_viewport_states;
135901e04c3fSmrg   context->base.set_sampler_views = tegra_set_sampler_views;
136001e04c3fSmrg   context->base.set_tess_state = tegra_set_tess_state;
136101e04c3fSmrg
136201e04c3fSmrg   context->base.set_debug_callback = tegra_set_debug_callback;
136301e04c3fSmrg
136401e04c3fSmrg   context->base.set_shader_buffers = tegra_set_shader_buffers;
136501e04c3fSmrg   context->base.set_shader_images = tegra_set_shader_images;
136601e04c3fSmrg   context->base.set_vertex_buffers = tegra_set_vertex_buffers;
136701e04c3fSmrg
136801e04c3fSmrg   context->base.create_stream_output_target = tegra_create_stream_output_target;
136901e04c3fSmrg   context->base.stream_output_target_destroy = tegra_stream_output_target_destroy;
137001e04c3fSmrg   context->base.set_stream_output_targets = tegra_set_stream_output_targets;
137101e04c3fSmrg
137201e04c3fSmrg   context->base.resource_copy_region = tegra_resource_copy_region;
137301e04c3fSmrg   context->base.blit = tegra_blit;
137401e04c3fSmrg   context->base.clear = tegra_clear;
137501e04c3fSmrg   context->base.clear_render_target = tegra_clear_render_target;
137601e04c3fSmrg   context->base.clear_depth_stencil = tegra_clear_depth_stencil;
137701e04c3fSmrg   context->base.clear_texture = tegra_clear_texture;
137801e04c3fSmrg   context->base.clear_buffer = tegra_clear_buffer;
137901e04c3fSmrg   context->base.flush = tegra_flush;
138001e04c3fSmrg
138101e04c3fSmrg   context->base.create_fence_fd = tegra_create_fence_fd;
138201e04c3fSmrg   context->base.fence_server_sync = tegra_fence_server_sync;
138301e04c3fSmrg
138401e04c3fSmrg   context->base.create_sampler_view = tegra_create_sampler_view;
138501e04c3fSmrg   context->base.sampler_view_destroy = tegra_sampler_view_destroy;
138601e04c3fSmrg
138701e04c3fSmrg   context->base.create_surface = tegra_create_surface;
138801e04c3fSmrg   context->base.surface_destroy = tegra_surface_destroy;
138901e04c3fSmrg
13907ec681f3Smrg   context->base.buffer_map = tegra_transfer_map;
13917ec681f3Smrg   context->base.texture_map = tegra_transfer_map;
139201e04c3fSmrg   context->base.transfer_flush_region = tegra_transfer_flush_region;
13937ec681f3Smrg   context->base.buffer_unmap = tegra_transfer_unmap;
13947ec681f3Smrg   context->base.texture_unmap = tegra_transfer_unmap;
139501e04c3fSmrg   context->base.buffer_subdata = tegra_buffer_subdata;
139601e04c3fSmrg   context->base.texture_subdata = tegra_texture_subdata;
139701e04c3fSmrg
139801e04c3fSmrg   context->base.texture_barrier = tegra_texture_barrier;
139901e04c3fSmrg   context->base.memory_barrier = tegra_memory_barrier;
140001e04c3fSmrg
140101e04c3fSmrg   context->base.create_video_codec = tegra_create_video_codec;
140201e04c3fSmrg   context->base.create_video_buffer = tegra_create_video_buffer;
140301e04c3fSmrg
140401e04c3fSmrg   context->base.create_compute_state = tegra_create_compute_state;
140501e04c3fSmrg   context->base.bind_compute_state = tegra_bind_compute_state;
140601e04c3fSmrg   context->base.delete_compute_state = tegra_delete_compute_state;
140701e04c3fSmrg   context->base.set_compute_resources = tegra_set_compute_resources;
140801e04c3fSmrg   context->base.set_global_binding = tegra_set_global_binding;
140901e04c3fSmrg   context->base.launch_grid = tegra_launch_grid;
141001e04c3fSmrg   context->base.get_sample_position = tegra_get_sample_position;
141101e04c3fSmrg   context->base.get_timestamp = tegra_get_timestamp;
141201e04c3fSmrg
141301e04c3fSmrg   context->base.flush_resource = tegra_flush_resource;
141401e04c3fSmrg   context->base.invalidate_resource = tegra_invalidate_resource;
141501e04c3fSmrg
141601e04c3fSmrg   context->base.get_device_reset_status = tegra_get_device_reset_status;
141701e04c3fSmrg   context->base.set_device_reset_callback = tegra_set_device_reset_callback;
141801e04c3fSmrg   context->base.dump_debug_state = tegra_dump_debug_state;
141901e04c3fSmrg   context->base.emit_string_marker = tegra_emit_string_marker;
142001e04c3fSmrg
142101e04c3fSmrg   context->base.generate_mipmap = tegra_generate_mipmap;
142201e04c3fSmrg
142301e04c3fSmrg   context->base.create_texture_handle = tegra_create_texture_handle;
142401e04c3fSmrg   context->base.delete_texture_handle = tegra_delete_texture_handle;
142501e04c3fSmrg   context->base.make_texture_handle_resident = tegra_make_texture_handle_resident;
142601e04c3fSmrg   context->base.create_image_handle = tegra_create_image_handle;
142701e04c3fSmrg   context->base.delete_image_handle = tegra_delete_image_handle;
142801e04c3fSmrg   context->base.make_image_handle_resident = tegra_make_image_handle_resident;
142901e04c3fSmrg
143001e04c3fSmrg   return &context->base;
143101e04c3fSmrg
143201e04c3fSmrgdestroy:
143301e04c3fSmrg   context->gpu->destroy(context->gpu);
143401e04c3fSmrgfree:
143501e04c3fSmrg   free(context);
143601e04c3fSmrg   return NULL;
143701e04c3fSmrg}
1438