101e04c3fSmrg/* 201e04c3fSmrg * Copyright © 2014-2017 Broadcom 301e04c3fSmrg * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org> 401e04c3fSmrg * 501e04c3fSmrg * Permission is hereby granted, free of charge, to any person obtaining a 601e04c3fSmrg * copy of this software and associated documentation files (the "Software"), 701e04c3fSmrg * to deal in the Software without restriction, including without limitation 801e04c3fSmrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 901e04c3fSmrg * and/or sell copies of the Software, and to permit persons to whom the 1001e04c3fSmrg * Software is furnished to do so, subject to the following conditions: 1101e04c3fSmrg * 1201e04c3fSmrg * The above copyright notice and this permission notice (including the next 1301e04c3fSmrg * paragraph) shall be included in all copies or substantial portions of the 1401e04c3fSmrg * Software. 1501e04c3fSmrg * 1601e04c3fSmrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1701e04c3fSmrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1801e04c3fSmrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1901e04c3fSmrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 2001e04c3fSmrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 2101e04c3fSmrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 2201e04c3fSmrg * IN THE SOFTWARE. 2301e04c3fSmrg */ 2401e04c3fSmrg 257ec681f3Smrg#ifndef V3D_CONTEXT_H 267ec681f3Smrg#define V3D_CONTEXT_H 2701e04c3fSmrg 2801e04c3fSmrg#ifdef V3D_VERSION 2901e04c3fSmrg#include "broadcom/common/v3d_macros.h" 3001e04c3fSmrg#endif 3101e04c3fSmrg 3201e04c3fSmrg#include <stdio.h> 3301e04c3fSmrg 3401e04c3fSmrg#include "pipe/p_context.h" 3501e04c3fSmrg#include "pipe/p_state.h" 3601e04c3fSmrg#include "util/bitset.h" 3701e04c3fSmrg#include "util/slab.h" 3801e04c3fSmrg#include "xf86drm.h" 399f464c52Smaya#include "drm-uapi/v3d_drm.h" 4001e04c3fSmrg#include "v3d_screen.h" 419f464c52Smaya#include "broadcom/common/v3d_limits.h" 4201e04c3fSmrg 437ec681f3Smrg#include "broadcom/simulator/v3d_simulator.h" 447ec681f3Smrg 4501e04c3fSmrgstruct v3d_job; 4601e04c3fSmrgstruct v3d_bo; 4701e04c3fSmrgvoid v3d_job_add_bo(struct v3d_job *job, struct v3d_bo *bo); 4801e04c3fSmrg 4901e04c3fSmrg#include "v3d_bufmgr.h" 5001e04c3fSmrg#include "v3d_resource.h" 5101e04c3fSmrg#include "v3d_cl.h" 5201e04c3fSmrg 5301e04c3fSmrg#ifdef USE_V3D_SIMULATOR 5401e04c3fSmrg#define using_v3d_simulator true 5501e04c3fSmrg#else 5601e04c3fSmrg#define using_v3d_simulator false 5701e04c3fSmrg#endif 5801e04c3fSmrg 597ec681f3Smrg#define V3D_DIRTY_BLEND (1ull << 0) 607ec681f3Smrg#define V3D_DIRTY_RASTERIZER (1ull << 1) 617ec681f3Smrg#define V3D_DIRTY_ZSA (1ull << 2) 627ec681f3Smrg#define V3D_DIRTY_COMPTEX (1ull << 3) 637ec681f3Smrg#define V3D_DIRTY_VERTTEX (1ull << 4) 647ec681f3Smrg#define V3D_DIRTY_GEOMTEX (1ull << 5) 657ec681f3Smrg#define V3D_DIRTY_FRAGTEX (1ull << 6) 667ec681f3Smrg 677ec681f3Smrg#define V3D_DIRTY_SHADER_IMAGE (1ull << 9) 687ec681f3Smrg#define V3D_DIRTY_BLEND_COLOR (1ull << 10) 697ec681f3Smrg#define V3D_DIRTY_STENCIL_REF (1ull << 11) 707ec681f3Smrg#define V3D_DIRTY_SAMPLE_STATE (1ull << 12) 717ec681f3Smrg#define V3D_DIRTY_FRAMEBUFFER (1ull << 13) 727ec681f3Smrg#define V3D_DIRTY_STIPPLE (1ull << 14) 737ec681f3Smrg#define V3D_DIRTY_VIEWPORT (1ull << 15) 747ec681f3Smrg#define V3D_DIRTY_CONSTBUF (1ull << 16) 757ec681f3Smrg#define V3D_DIRTY_VTXSTATE (1ull << 17) 767ec681f3Smrg#define V3D_DIRTY_VTXBUF (1ull << 18) 777ec681f3Smrg#define V3D_DIRTY_SCISSOR (1ull << 19) 787ec681f3Smrg#define V3D_DIRTY_FLAT_SHADE_FLAGS (1ull << 20) 797ec681f3Smrg#define V3D_DIRTY_PRIM_MODE (1ull << 21) 807ec681f3Smrg#define V3D_DIRTY_CLIP (1ull << 22) 817ec681f3Smrg#define V3D_DIRTY_UNCOMPILED_CS (1ull << 23) 827ec681f3Smrg#define V3D_DIRTY_UNCOMPILED_VS (1ull << 24) 837ec681f3Smrg#define V3D_DIRTY_UNCOMPILED_GS (1ull << 25) 847ec681f3Smrg#define V3D_DIRTY_UNCOMPILED_FS (1ull << 26) 857ec681f3Smrg 867ec681f3Smrg#define V3D_DIRTY_COMPILED_CS (1ull << 29) 877ec681f3Smrg#define V3D_DIRTY_COMPILED_VS (1ull << 30) 887ec681f3Smrg#define V3D_DIRTY_COMPILED_GS_BIN (1ULL << 31) 897ec681f3Smrg#define V3D_DIRTY_COMPILED_GS (1ULL << 32) 907ec681f3Smrg#define V3D_DIRTY_COMPILED_FS (1ull << 33) 917ec681f3Smrg 927ec681f3Smrg#define V3D_DIRTY_FS_INPUTS (1ull << 38) 937ec681f3Smrg#define V3D_DIRTY_GS_INPUTS (1ull << 39) 947ec681f3Smrg#define V3D_DIRTY_STREAMOUT (1ull << 40) 957ec681f3Smrg#define V3D_DIRTY_OQ (1ull << 41) 967ec681f3Smrg#define V3D_DIRTY_CENTROID_FLAGS (1ull << 42) 977ec681f3Smrg#define V3D_DIRTY_NOPERSPECTIVE_FLAGS (1ull << 43) 987ec681f3Smrg#define V3D_DIRTY_SSBO (1ull << 44) 997ec681f3Smrg 1007ec681f3Smrg#define V3D_MAX_FS_INPUTS 64 1017ec681f3Smrg 1027ec681f3Smrg#define MAX_JOB_SCISSORS 16 10301e04c3fSmrg 1049f464c52Smayaenum v3d_sampler_state_variant { 1059f464c52Smaya V3D_SAMPLER_STATE_BORDER_0, 1069f464c52Smaya V3D_SAMPLER_STATE_F16, 1079f464c52Smaya V3D_SAMPLER_STATE_F16_UNORM, 1089f464c52Smaya V3D_SAMPLER_STATE_F16_SNORM, 1099f464c52Smaya V3D_SAMPLER_STATE_F16_BGRA, 1109f464c52Smaya V3D_SAMPLER_STATE_F16_BGRA_UNORM, 1119f464c52Smaya V3D_SAMPLER_STATE_F16_BGRA_SNORM, 1129f464c52Smaya V3D_SAMPLER_STATE_F16_A, 1139f464c52Smaya V3D_SAMPLER_STATE_F16_A_SNORM, 1149f464c52Smaya V3D_SAMPLER_STATE_F16_A_UNORM, 1159f464c52Smaya V3D_SAMPLER_STATE_F16_LA, 1169f464c52Smaya V3D_SAMPLER_STATE_F16_LA_UNORM, 1179f464c52Smaya V3D_SAMPLER_STATE_F16_LA_SNORM, 1189f464c52Smaya V3D_SAMPLER_STATE_32, 1199f464c52Smaya V3D_SAMPLER_STATE_32_UNORM, 1209f464c52Smaya V3D_SAMPLER_STATE_32_SNORM, 1219f464c52Smaya V3D_SAMPLER_STATE_32_A, 1229f464c52Smaya V3D_SAMPLER_STATE_32_A_UNORM, 1239f464c52Smaya V3D_SAMPLER_STATE_32_A_SNORM, 1249f464c52Smaya V3D_SAMPLER_STATE_1010102U, 1259f464c52Smaya V3D_SAMPLER_STATE_16U, 1269f464c52Smaya V3D_SAMPLER_STATE_16I, 1279f464c52Smaya V3D_SAMPLER_STATE_8I, 1289f464c52Smaya V3D_SAMPLER_STATE_8U, 1299f464c52Smaya 1309f464c52Smaya V3D_SAMPLER_STATE_VARIANT_COUNT, 1319f464c52Smaya}; 1329f464c52Smaya 1337ec681f3Smrgenum v3d_flush_cond { 1347ec681f3Smrg /* Flush job unless we are flushing for transform feedback, where we 1357ec681f3Smrg * handle flushing in the driver via the 'Wait for TF' packet. 1367ec681f3Smrg */ 1377ec681f3Smrg V3D_FLUSH_DEFAULT, 1387ec681f3Smrg /* Always flush the job, even for cases where we would normally not 1397ec681f3Smrg * do it, such as transform feedback. 1407ec681f3Smrg */ 1417ec681f3Smrg V3D_FLUSH_ALWAYS, 1427ec681f3Smrg /* Flush job if it is not the current FBO job. This is intended to 1437ec681f3Smrg * skip automatic flushes of the current job for resources that we 1447ec681f3Smrg * expect to be externally synchronized by the application using 1457ec681f3Smrg * glMemoryBarrier(), such as SSBOs and shader images. 1467ec681f3Smrg */ 1477ec681f3Smrg V3D_FLUSH_NOT_CURRENT_JOB, 1487ec681f3Smrg}; 1497ec681f3Smrg 15001e04c3fSmrgstruct v3d_sampler_view { 15101e04c3fSmrg struct pipe_sampler_view base; 15201e04c3fSmrg uint32_t p0; 15301e04c3fSmrg uint32_t p1; 15401e04c3fSmrg /* Precomputed swizzles to pass in to the shader key. */ 15501e04c3fSmrg uint8_t swizzle[4]; 15601e04c3fSmrg 15701e04c3fSmrg uint8_t texture_shader_state[32]; 15801e04c3fSmrg /* V3D 4.x: Texture state struct. */ 15901e04c3fSmrg struct v3d_bo *bo; 1609f464c52Smaya 1619f464c52Smaya enum v3d_sampler_state_variant sampler_variant; 1629f464c52Smaya 1639f464c52Smaya /* Actual texture to be read by this sampler view. May be different 1649f464c52Smaya * from base.texture in the case of having a shadow tiled copy of a 1659f464c52Smaya * raster texture. 1669f464c52Smaya */ 1679f464c52Smaya struct pipe_resource *texture; 16801e04c3fSmrg}; 16901e04c3fSmrg 17001e04c3fSmrgstruct v3d_sampler_state { 17101e04c3fSmrg struct pipe_sampler_state base; 17201e04c3fSmrg uint32_t p0; 17301e04c3fSmrg uint32_t p1; 17401e04c3fSmrg 17501e04c3fSmrg /* V3D 3.x: Packed texture state. */ 17601e04c3fSmrg uint8_t texture_shader_state[32]; 17701e04c3fSmrg /* V3D 4.x: Sampler state struct. */ 1789f464c52Smaya struct pipe_resource *sampler_state; 1799f464c52Smaya uint32_t sampler_state_offset[V3D_SAMPLER_STATE_VARIANT_COUNT]; 1809f464c52Smaya 1819f464c52Smaya bool border_color_variants; 18201e04c3fSmrg}; 18301e04c3fSmrg 18401e04c3fSmrgstruct v3d_texture_stateobj { 1859f464c52Smaya struct pipe_sampler_view *textures[V3D_MAX_TEXTURE_SAMPLERS]; 18601e04c3fSmrg unsigned num_textures; 1879f464c52Smaya struct pipe_sampler_state *samplers[V3D_MAX_TEXTURE_SAMPLERS]; 18801e04c3fSmrg unsigned num_samplers; 1899f464c52Smaya struct v3d_cl_reloc texture_state[V3D_MAX_TEXTURE_SAMPLERS]; 19001e04c3fSmrg}; 19101e04c3fSmrg 19201e04c3fSmrgstruct v3d_shader_uniform_info { 19301e04c3fSmrg enum quniform_contents *contents; 19401e04c3fSmrg uint32_t *data; 19501e04c3fSmrg uint32_t count; 19601e04c3fSmrg}; 19701e04c3fSmrg 19801e04c3fSmrgstruct v3d_uncompiled_shader { 19901e04c3fSmrg /** A name for this program, so you can track it in shader-db output. */ 20001e04c3fSmrg uint32_t program_id; 20101e04c3fSmrg /** How many variants of this program were compiled, for shader-db. */ 20201e04c3fSmrg uint32_t compiled_variant_count; 20301e04c3fSmrg struct pipe_shader_state base; 20401e04c3fSmrg uint32_t num_tf_outputs; 20501e04c3fSmrg struct v3d_varying_slot *tf_outputs; 20601e04c3fSmrg uint16_t tf_specs[16]; 20701e04c3fSmrg uint16_t tf_specs_psiz[16]; 20801e04c3fSmrg uint32_t num_tf_specs; 20901e04c3fSmrg}; 21001e04c3fSmrg 21101e04c3fSmrgstruct v3d_compiled_shader { 2129f464c52Smaya struct pipe_resource *resource; 2139f464c52Smaya uint32_t offset; 21401e04c3fSmrg 21501e04c3fSmrg union { 21601e04c3fSmrg struct v3d_prog_data *base; 21701e04c3fSmrg struct v3d_vs_prog_data *vs; 2187ec681f3Smrg struct v3d_gs_prog_data *gs; 21901e04c3fSmrg struct v3d_fs_prog_data *fs; 2209f464c52Smaya struct v3d_compute_prog_data *compute; 22101e04c3fSmrg } prog_data; 22201e04c3fSmrg 22301e04c3fSmrg /** 2247ec681f3Smrg * V3D_DIRTY_* flags that, when set in v3d->dirty, mean that the 22501e04c3fSmrg * uniforms have to be rewritten (and therefore the shader state 22601e04c3fSmrg * reemitted). 22701e04c3fSmrg */ 2287ec681f3Smrg uint64_t uniform_dirty_bits; 22901e04c3fSmrg}; 23001e04c3fSmrg 23101e04c3fSmrgstruct v3d_program_stateobj { 2327ec681f3Smrg struct v3d_uncompiled_shader *bind_vs, *bind_gs, *bind_fs, *bind_compute; 2337ec681f3Smrg struct v3d_compiled_shader *cs, *vs, *gs_bin, *gs, *fs, *compute; 2349f464c52Smaya 2359f464c52Smaya struct hash_table *cache[MESA_SHADER_STAGES]; 23601e04c3fSmrg 23701e04c3fSmrg struct v3d_bo *spill_bo; 23801e04c3fSmrg int spill_size_per_thread; 23901e04c3fSmrg}; 24001e04c3fSmrg 24101e04c3fSmrgstruct v3d_constbuf_stateobj { 24201e04c3fSmrg struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS]; 24301e04c3fSmrg uint32_t enabled_mask; 24401e04c3fSmrg uint32_t dirty_mask; 24501e04c3fSmrg}; 24601e04c3fSmrg 24701e04c3fSmrgstruct v3d_vertexbuf_stateobj { 24801e04c3fSmrg struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS]; 24901e04c3fSmrg unsigned count; 25001e04c3fSmrg uint32_t enabled_mask; 25101e04c3fSmrg uint32_t dirty_mask; 25201e04c3fSmrg}; 25301e04c3fSmrg 25401e04c3fSmrgstruct v3d_vertex_stateobj { 2559f464c52Smaya struct pipe_vertex_element pipe[V3D_MAX_VS_INPUTS / 4]; 25601e04c3fSmrg unsigned num_elements; 25701e04c3fSmrg 2589f464c52Smaya uint8_t attrs[16 * (V3D_MAX_VS_INPUTS / 4)]; 2599f464c52Smaya struct pipe_resource *defaults; 2609f464c52Smaya uint32_t defaults_offset; 26101e04c3fSmrg}; 26201e04c3fSmrg 2637ec681f3Smrgstruct v3d_stream_output_target { 2647ec681f3Smrg struct pipe_stream_output_target base; 2657ec681f3Smrg /* Number of transform feedback vertices written to this target */ 2667ec681f3Smrg uint32_t recorded_vertex_count; 2677ec681f3Smrg}; 2687ec681f3Smrg 26901e04c3fSmrgstruct v3d_streamout_stateobj { 27001e04c3fSmrg struct pipe_stream_output_target *targets[PIPE_MAX_SO_BUFFERS]; 27101e04c3fSmrg /* Number of vertices we've written into the buffer so far. */ 27201e04c3fSmrg uint32_t offsets[PIPE_MAX_SO_BUFFERS]; 27301e04c3fSmrg unsigned num_targets; 27401e04c3fSmrg}; 27501e04c3fSmrg 2769f464c52Smayastruct v3d_ssbo_stateobj { 2779f464c52Smaya struct pipe_shader_buffer sb[PIPE_MAX_SHADER_BUFFERS]; 2789f464c52Smaya uint32_t enabled_mask; 2799f464c52Smaya}; 2809f464c52Smaya 28101e04c3fSmrg/* Hash table key for v3d->jobs */ 28201e04c3fSmrgstruct v3d_job_key { 28301e04c3fSmrg struct pipe_surface *cbufs[4]; 28401e04c3fSmrg struct pipe_surface *zsbuf; 2857ec681f3Smrg struct pipe_surface *bbuf; 28601e04c3fSmrg}; 28701e04c3fSmrg 28801e04c3fSmrgenum v3d_ez_state { 2897ec681f3Smrg V3D_EZ_UNDECIDED = 0, 2907ec681f3Smrg V3D_EZ_GT_GE, 2917ec681f3Smrg V3D_EZ_LT_LE, 2927ec681f3Smrg V3D_EZ_DISABLED, 29301e04c3fSmrg}; 29401e04c3fSmrg 2959f464c52Smayastruct v3d_image_view { 2969f464c52Smaya struct pipe_image_view base; 2979f464c52Smaya /* V3D 4.x texture shader state struct */ 2989f464c52Smaya struct pipe_resource *tex_state; 2999f464c52Smaya uint32_t tex_state_offset; 3009f464c52Smaya}; 3019f464c52Smaya 3029f464c52Smayastruct v3d_shaderimg_stateobj { 3039f464c52Smaya struct v3d_image_view si[PIPE_MAX_SHADER_IMAGES]; 3049f464c52Smaya uint32_t enabled_mask; 3059f464c52Smaya}; 3069f464c52Smaya 3077ec681f3Smrgstruct v3d_perfmon_state { 3087ec681f3Smrg /* The kernel perfmon id */ 3097ec681f3Smrg uint32_t kperfmon_id; 3107ec681f3Smrg /* True if at least one job was submitted with this perfmon. */ 3117ec681f3Smrg bool job_submitted; 3127ec681f3Smrg /* Fence to be signaled when the last job submitted with this perfmon 3137ec681f3Smrg * is executed by the GPU. 3147ec681f3Smrg */ 3157ec681f3Smrg struct v3d_fence *last_job_fence; 3167ec681f3Smrg uint8_t counters[DRM_V3D_MAX_PERF_COUNTERS]; 3177ec681f3Smrg uint64_t values[DRM_V3D_MAX_PERF_COUNTERS]; 3187ec681f3Smrg}; 3197ec681f3Smrg 32001e04c3fSmrg/** 32101e04c3fSmrg * A complete bin/render job. 32201e04c3fSmrg * 32301e04c3fSmrg * This is all of the state necessary to submit a bin/render to the kernel. 32401e04c3fSmrg * We want to be able to have multiple in progress at a time, so that we don't 32501e04c3fSmrg * need to flush an existing CL just to switch to rendering to a new render 32601e04c3fSmrg * target (which would mean reading back from the old render target when 32701e04c3fSmrg * starting to render to it again). 32801e04c3fSmrg */ 32901e04c3fSmrgstruct v3d_job { 33001e04c3fSmrg struct v3d_context *v3d; 33101e04c3fSmrg struct v3d_cl bcl; 33201e04c3fSmrg struct v3d_cl rcl; 33301e04c3fSmrg struct v3d_cl indirect; 33401e04c3fSmrg struct v3d_bo *tile_alloc; 33501e04c3fSmrg struct v3d_bo *tile_state; 33601e04c3fSmrg 33701e04c3fSmrg struct drm_v3d_submit_cl submit; 33801e04c3fSmrg 33901e04c3fSmrg /** 34001e04c3fSmrg * Set of all BOs referenced by the job. This will be used for making 34101e04c3fSmrg * the list of BOs that the kernel will need to have paged in to 34201e04c3fSmrg * execute our job. 34301e04c3fSmrg */ 34401e04c3fSmrg struct set *bos; 34501e04c3fSmrg 34601e04c3fSmrg /** Sum of the sizes of the BOs referenced by the job. */ 34701e04c3fSmrg uint32_t referenced_size; 34801e04c3fSmrg 34901e04c3fSmrg struct set *write_prscs; 3507ec681f3Smrg struct set *tf_write_prscs; 35101e04c3fSmrg 35201e04c3fSmrg /* Size of the submit.bo_handles array. */ 35301e04c3fSmrg uint32_t bo_handles_size; 35401e04c3fSmrg 3557ec681f3Smrg /** @{ 3567ec681f3Smrg * Surfaces to submit rendering for. 3577ec681f3Smrg * For blit operations, bbuf is the source surface, and cbufs[0] is 3587ec681f3Smrg * the destination surface. 3597ec681f3Smrg */ 3607ec681f3Smrg uint32_t nr_cbufs; 36101e04c3fSmrg struct pipe_surface *cbufs[4]; 36201e04c3fSmrg struct pipe_surface *zsbuf; 3637ec681f3Smrg struct pipe_surface *bbuf; 36401e04c3fSmrg /** @} */ 36501e04c3fSmrg /** @{ 36601e04c3fSmrg * Bounding box of the scissor across all queued drawing. 36701e04c3fSmrg * 36801e04c3fSmrg * Note that the max values are exclusive. 36901e04c3fSmrg */ 37001e04c3fSmrg uint32_t draw_min_x; 37101e04c3fSmrg uint32_t draw_min_y; 37201e04c3fSmrg uint32_t draw_max_x; 37301e04c3fSmrg uint32_t draw_max_y; 3747ec681f3Smrg 3757ec681f3Smrg /** @} */ 3767ec681f3Smrg /** @{ 3777ec681f3Smrg * List of scissor rects used for all queued drawing. All scissor 3787ec681f3Smrg * rects will be contained in the draw_{min/max}_{x/y} bounding box. 3797ec681f3Smrg * 3807ec681f3Smrg * This is used as an optimization when all drawing is scissored to 3817ec681f3Smrg * limit tile flushing only to tiles that intersect a scissor rect. 3827ec681f3Smrg * If scissor is used together with non-scissored drawing, then 3837ec681f3Smrg * the optimization is disabled. 3847ec681f3Smrg */ 3857ec681f3Smrg struct { 3867ec681f3Smrg bool disabled; 3877ec681f3Smrg uint32_t count; 3887ec681f3Smrg struct { 3897ec681f3Smrg uint32_t min_x, min_y; 3907ec681f3Smrg uint32_t max_x, max_y; 3917ec681f3Smrg } rects[MAX_JOB_SCISSORS]; 3927ec681f3Smrg } scissor; 3937ec681f3Smrg 39401e04c3fSmrg /** @} */ 39501e04c3fSmrg /** @{ 39601e04c3fSmrg * Width/height of the color framebuffer being rendered to, 3977ec681f3Smrg * for V3D_TILE_RENDERING_MODE_CONFIG. 3987ec681f3Smrg */ 39901e04c3fSmrg uint32_t draw_width; 40001e04c3fSmrg uint32_t draw_height; 4017ec681f3Smrg uint32_t num_layers; 4027ec681f3Smrg 40301e04c3fSmrg /** @} */ 40401e04c3fSmrg /** @{ Tile information, depending on MSAA and float color buffer. */ 40501e04c3fSmrg uint32_t draw_tiles_x; /** @< Number of tiles wide for framebuffer. */ 40601e04c3fSmrg uint32_t draw_tiles_y; /** @< Number of tiles high for framebuffer. */ 40701e04c3fSmrg 40801e04c3fSmrg uint32_t tile_width; /** @< Width of a tile. */ 40901e04c3fSmrg uint32_t tile_height; /** @< Height of a tile. */ 41001e04c3fSmrg /** maximum internal_bpp of all color render targets. */ 41101e04c3fSmrg uint32_t internal_bpp; 41201e04c3fSmrg 41301e04c3fSmrg /** Whether the current rendering is in a 4X MSAA tile buffer. */ 41401e04c3fSmrg bool msaa; 41501e04c3fSmrg /** @} */ 41601e04c3fSmrg 41701e04c3fSmrg /* Bitmask of PIPE_CLEAR_* of buffers that were cleared before the 41801e04c3fSmrg * first rendering. 41901e04c3fSmrg */ 42001e04c3fSmrg uint32_t clear; 42101e04c3fSmrg /* Bitmask of PIPE_CLEAR_* of buffers that have been read by a draw 42201e04c3fSmrg * call without having been cleared first. 42301e04c3fSmrg */ 42401e04c3fSmrg uint32_t load; 42501e04c3fSmrg /* Bitmask of PIPE_CLEAR_* of buffers that have been rendered to 42601e04c3fSmrg * (either clears or draws) and should be stored. 42701e04c3fSmrg */ 42801e04c3fSmrg uint32_t store; 42901e04c3fSmrg uint32_t clear_color[4][4]; 43001e04c3fSmrg float clear_z; 43101e04c3fSmrg uint8_t clear_s; 43201e04c3fSmrg 43301e04c3fSmrg /** 43401e04c3fSmrg * Set if some drawing (triangles, blits, or just a glClear()) has 43501e04c3fSmrg * been done to the FBO, meaning that we need to 4367ec681f3Smrg * DRM_IOCTL_V3D_SUBMIT_CL. 43701e04c3fSmrg */ 43801e04c3fSmrg bool needs_flush; 43901e04c3fSmrg 4409f464c52Smaya /* Set if any shader has dirtied cachelines in the TMU that need to be 4419f464c52Smaya * flushed before job end. 4429f464c52Smaya */ 4439f464c52Smaya bool tmu_dirty_rcl; 4449f464c52Smaya 44501e04c3fSmrg /** 44601e04c3fSmrg * Set if a packet enabling TF has been emitted in the job (V3D 4.x). 44701e04c3fSmrg */ 44801e04c3fSmrg bool tf_enabled; 44901e04c3fSmrg 4507ec681f3Smrg bool needs_primitives_generated; 4517ec681f3Smrg 45201e04c3fSmrg /** 45301e04c3fSmrg * Current EZ state for drawing. Updated at the start of draw after 45401e04c3fSmrg * we've decided on the shader being rendered. 45501e04c3fSmrg */ 45601e04c3fSmrg enum v3d_ez_state ez_state; 45701e04c3fSmrg /** 45801e04c3fSmrg * The first EZ state that was used for drawing with a decided EZ 45901e04c3fSmrg * direction (so either UNDECIDED, GT, or LT). 46001e04c3fSmrg */ 46101e04c3fSmrg enum v3d_ez_state first_ez_state; 46201e04c3fSmrg 46301e04c3fSmrg /** 46401e04c3fSmrg * Number of draw calls (not counting full buffer clears) queued in 46501e04c3fSmrg * the current job. 46601e04c3fSmrg */ 46701e04c3fSmrg uint32_t draw_calls_queued; 46801e04c3fSmrg 4697ec681f3Smrg /** 4707ec681f3Smrg * Number of draw calls (not counting full buffer clears) queued in 4717ec681f3Smrg * the current job during active transform feedback. 4727ec681f3Smrg */ 4737ec681f3Smrg uint32_t tf_draw_calls_queued; 4747ec681f3Smrg 47501e04c3fSmrg struct v3d_job_key key; 47601e04c3fSmrg}; 47701e04c3fSmrg 47801e04c3fSmrgstruct v3d_context { 47901e04c3fSmrg struct pipe_context base; 48001e04c3fSmrg 48101e04c3fSmrg int fd; 48201e04c3fSmrg struct v3d_screen *screen; 48301e04c3fSmrg 48401e04c3fSmrg /** The 3D rendering job for the currently bound FBO. */ 48501e04c3fSmrg struct v3d_job *job; 48601e04c3fSmrg 48701e04c3fSmrg /* Map from struct v3d_job_key to the job for that FBO. 48801e04c3fSmrg */ 48901e04c3fSmrg struct hash_table *jobs; 49001e04c3fSmrg 49101e04c3fSmrg /** 49201e04c3fSmrg * Map from v3d_resource to a job writing to that resource. 49301e04c3fSmrg * 49401e04c3fSmrg * Primarily for flushing jobs rendering to textures that are now 49501e04c3fSmrg * being read from. 49601e04c3fSmrg */ 49701e04c3fSmrg struct hash_table *write_jobs; 49801e04c3fSmrg 49901e04c3fSmrg struct slab_child_pool transfer_pool; 50001e04c3fSmrg struct blitter_context *blitter; 50101e04c3fSmrg 5027ec681f3Smrg /** bitfield of V3D_DIRTY_* */ 5037ec681f3Smrg uint64_t dirty; 50401e04c3fSmrg 50501e04c3fSmrg uint32_t next_uncompiled_program_id; 50601e04c3fSmrg uint64_t next_compiled_program_id; 50701e04c3fSmrg 50801e04c3fSmrg struct v3d_compiler_state *compiler_state; 50901e04c3fSmrg 51001e04c3fSmrg uint8_t prim_mode; 51101e04c3fSmrg 51201e04c3fSmrg /** Maximum index buffer valid for the current shader_rec. */ 51301e04c3fSmrg uint32_t max_index; 51401e04c3fSmrg 5159f464c52Smaya /** Sync object that our RCL or TFU job will update as its out_sync. */ 51601e04c3fSmrg uint32_t out_sync; 51701e04c3fSmrg 5189f464c52Smaya /* Stream uploader used by gallium internals. This could also be used 5199f464c52Smaya * by driver internals, but we tend to use the v3d_cl.h interfaces 5209f464c52Smaya * instead. 5219f464c52Smaya */ 52201e04c3fSmrg struct u_upload_mgr *uploader; 5239f464c52Smaya /* State uploader used inside the driver. This is for packing bits of 5249f464c52Smaya * long-term state inside buffers, since the kernel interfaces 5259f464c52Smaya * allocate a page at a time. 5269f464c52Smaya */ 5279f464c52Smaya struct u_upload_mgr *state_uploader; 52801e04c3fSmrg 5297ec681f3Smrg struct pipe_shader_state *sand8_blit_vs; 5307ec681f3Smrg struct pipe_shader_state *sand8_blit_fs_luma; 5317ec681f3Smrg struct pipe_shader_state *sand8_blit_fs_chroma; 5327ec681f3Smrg 53301e04c3fSmrg /** @{ Current pipeline state objects */ 53401e04c3fSmrg struct pipe_scissor_state scissor; 53501e04c3fSmrg struct v3d_blend_state *blend; 53601e04c3fSmrg struct v3d_rasterizer_state *rasterizer; 53701e04c3fSmrg struct v3d_depth_stencil_alpha_state *zsa; 53801e04c3fSmrg 53901e04c3fSmrg struct v3d_program_stateobj prog; 5409f464c52Smaya uint32_t compute_num_workgroups[3]; 5419f464c52Smaya struct v3d_bo *compute_shared_memory; 54201e04c3fSmrg 54301e04c3fSmrg struct v3d_vertex_stateobj *vtx; 54401e04c3fSmrg 54501e04c3fSmrg struct { 54601e04c3fSmrg struct pipe_blend_color f; 54701e04c3fSmrg uint16_t hf[4]; 54801e04c3fSmrg } blend_color; 54901e04c3fSmrg struct pipe_stencil_ref stencil_ref; 55001e04c3fSmrg unsigned sample_mask; 55101e04c3fSmrg struct pipe_framebuffer_state framebuffer; 55201e04c3fSmrg 55301e04c3fSmrg /* Per render target, whether we should swap the R and B fields in the 55401e04c3fSmrg * shader's color output and in blending. If render targets disagree 55501e04c3fSmrg * on the R/B swap and use the constant color, then we would need to 55601e04c3fSmrg * fall back to in-shader blending. 55701e04c3fSmrg */ 55801e04c3fSmrg uint8_t swap_color_rb; 55901e04c3fSmrg 56001e04c3fSmrg /* Per render target, whether we should treat the dst alpha values as 56101e04c3fSmrg * one in blending. 56201e04c3fSmrg * 56301e04c3fSmrg * For RGBX formats, the tile buffer's alpha channel will be 56401e04c3fSmrg * undefined. 56501e04c3fSmrg */ 56601e04c3fSmrg uint8_t blend_dst_alpha_one; 56701e04c3fSmrg 56801e04c3fSmrg bool active_queries; 56901e04c3fSmrg 5707ec681f3Smrg /** 5717ec681f3Smrg * If a compute job writes a resource read by a non-compute stage we 5727ec681f3Smrg * should sync on the last compute job. 5737ec681f3Smrg */ 5747ec681f3Smrg bool sync_on_last_compute_job; 5757ec681f3Smrg 57601e04c3fSmrg uint32_t tf_prims_generated; 57701e04c3fSmrg uint32_t prims_generated; 57801e04c3fSmrg 5797ec681f3Smrg uint32_t n_primitives_generated_queries_in_flight; 5807ec681f3Smrg 58101e04c3fSmrg struct pipe_poly_stipple stipple; 58201e04c3fSmrg struct pipe_clip_state clip; 58301e04c3fSmrg struct pipe_viewport_state viewport; 5849f464c52Smaya struct v3d_ssbo_stateobj ssbo[PIPE_SHADER_TYPES]; 5859f464c52Smaya struct v3d_shaderimg_stateobj shaderimg[PIPE_SHADER_TYPES]; 58601e04c3fSmrg struct v3d_constbuf_stateobj constbuf[PIPE_SHADER_TYPES]; 5879f464c52Smaya struct v3d_texture_stateobj tex[PIPE_SHADER_TYPES]; 58801e04c3fSmrg struct v3d_vertexbuf_stateobj vertexbuf; 58901e04c3fSmrg struct v3d_streamout_stateobj streamout; 59001e04c3fSmrg struct v3d_bo *current_oq; 5917ec681f3Smrg struct pipe_resource *prim_counts; 5927ec681f3Smrg uint32_t prim_counts_offset; 5939f464c52Smaya struct pipe_debug_callback debug; 5947ec681f3Smrg struct v3d_perfmon_state *active_perfmon; 5957ec681f3Smrg struct v3d_perfmon_state *last_perfmon; 59601e04c3fSmrg /** @} */ 59701e04c3fSmrg}; 59801e04c3fSmrg 59901e04c3fSmrgstruct v3d_rasterizer_state { 60001e04c3fSmrg struct pipe_rasterizer_state base; 60101e04c3fSmrg 60201e04c3fSmrg float point_size; 60301e04c3fSmrg 60401e04c3fSmrg uint8_t depth_offset[9]; 60501e04c3fSmrg uint8_t depth_offset_z16[9]; 60601e04c3fSmrg}; 60701e04c3fSmrg 60801e04c3fSmrgstruct v3d_depth_stencil_alpha_state { 60901e04c3fSmrg struct pipe_depth_stencil_alpha_state base; 61001e04c3fSmrg 61101e04c3fSmrg enum v3d_ez_state ez_state; 61201e04c3fSmrg 61301e04c3fSmrg uint8_t stencil_front[6]; 61401e04c3fSmrg uint8_t stencil_back[6]; 61501e04c3fSmrg}; 61601e04c3fSmrg 61701e04c3fSmrgstruct v3d_blend_state { 61801e04c3fSmrg struct pipe_blend_state base; 61901e04c3fSmrg 62001e04c3fSmrg /* Per-RT mask of whether blending is enabled. */ 62101e04c3fSmrg uint8_t blend_enables; 62201e04c3fSmrg}; 62301e04c3fSmrg 62401e04c3fSmrg#define perf_debug(...) do { \ 62501e04c3fSmrg if (unlikely(V3D_DEBUG & V3D_DEBUG_PERF)) \ 62601e04c3fSmrg fprintf(stderr, __VA_ARGS__); \ 6279f464c52Smaya if (unlikely(v3d->debug.debug_message)) \ 6289f464c52Smaya pipe_debug_message(&v3d->debug, PERF_INFO, __VA_ARGS__); \ 62901e04c3fSmrg} while (0) 63001e04c3fSmrg 63101e04c3fSmrgstatic inline struct v3d_context * 63201e04c3fSmrgv3d_context(struct pipe_context *pcontext) 63301e04c3fSmrg{ 63401e04c3fSmrg return (struct v3d_context *)pcontext; 63501e04c3fSmrg} 63601e04c3fSmrg 63701e04c3fSmrgstatic inline struct v3d_sampler_view * 63801e04c3fSmrgv3d_sampler_view(struct pipe_sampler_view *psview) 63901e04c3fSmrg{ 64001e04c3fSmrg return (struct v3d_sampler_view *)psview; 64101e04c3fSmrg} 64201e04c3fSmrg 64301e04c3fSmrgstatic inline struct v3d_sampler_state * 64401e04c3fSmrgv3d_sampler_state(struct pipe_sampler_state *psampler) 64501e04c3fSmrg{ 64601e04c3fSmrg return (struct v3d_sampler_state *)psampler; 64701e04c3fSmrg} 64801e04c3fSmrg 6497ec681f3Smrgstatic inline struct v3d_stream_output_target * 6507ec681f3Smrgv3d_stream_output_target(struct pipe_stream_output_target *ptarget) 6517ec681f3Smrg{ 6527ec681f3Smrg return (struct v3d_stream_output_target *)ptarget; 6537ec681f3Smrg} 6547ec681f3Smrg 6557ec681f3Smrgstatic inline uint32_t 6567ec681f3Smrgv3d_stream_output_target_get_vertex_count(struct pipe_stream_output_target *ptarget) 6577ec681f3Smrg{ 6587ec681f3Smrg return v3d_stream_output_target(ptarget)->recorded_vertex_count; 6597ec681f3Smrg} 6607ec681f3Smrg 6617ec681f3Smrgint v3d_get_driver_query_group_info(struct pipe_screen *pscreen, 6627ec681f3Smrg unsigned index, 6637ec681f3Smrg struct pipe_driver_query_group_info *info); 6647ec681f3Smrgint v3d_get_driver_query_info(struct pipe_screen *pscreen, unsigned index, 6657ec681f3Smrg struct pipe_driver_query_info *info); 6667ec681f3Smrg 66701e04c3fSmrgstruct pipe_context *v3d_context_create(struct pipe_screen *pscreen, 66801e04c3fSmrg void *priv, unsigned flags); 66901e04c3fSmrgvoid v3d_program_init(struct pipe_context *pctx); 67001e04c3fSmrgvoid v3d_program_fini(struct pipe_context *pctx); 67101e04c3fSmrgvoid v3d_query_init(struct pipe_context *pctx); 67201e04c3fSmrg 67301e04c3fSmrgstatic inline int 67401e04c3fSmrgv3d_ioctl(int fd, unsigned long request, void *arg) 67501e04c3fSmrg{ 67601e04c3fSmrg if (using_v3d_simulator) 67701e04c3fSmrg return v3d_simulator_ioctl(fd, request, arg); 67801e04c3fSmrg else 67901e04c3fSmrg return drmIoctl(fd, request, arg); 68001e04c3fSmrg} 68101e04c3fSmrg 6827ec681f3Smrgstatic inline bool 6837ec681f3Smrgv3d_transform_feedback_enabled(struct v3d_context *v3d) 6847ec681f3Smrg{ 6857ec681f3Smrg return (v3d->prog.bind_vs->num_tf_specs != 0 || 6867ec681f3Smrg (v3d->prog.bind_gs && v3d->prog.bind_gs->num_tf_specs != 0)) && 6877ec681f3Smrg v3d->active_queries; 6887ec681f3Smrg} 6897ec681f3Smrg 69001e04c3fSmrgvoid v3d_set_shader_uniform_dirty_flags(struct v3d_compiled_shader *shader); 69101e04c3fSmrgstruct v3d_cl_reloc v3d_write_uniforms(struct v3d_context *v3d, 6927ec681f3Smrg struct v3d_job *job, 69301e04c3fSmrg struct v3d_compiled_shader *shader, 6949f464c52Smaya enum pipe_shader_type stage); 69501e04c3fSmrg 69601e04c3fSmrgvoid v3d_flush(struct pipe_context *pctx); 69701e04c3fSmrgvoid v3d_job_init(struct v3d_context *v3d); 6987ec681f3Smrgstruct v3d_job *v3d_job_create(struct v3d_context *v3d); 6997ec681f3Smrgvoid v3d_job_free(struct v3d_context *v3d, struct v3d_job *job); 70001e04c3fSmrgstruct v3d_job *v3d_get_job(struct v3d_context *v3d, 7017ec681f3Smrg uint32_t nr_cbufs, 70201e04c3fSmrg struct pipe_surface **cbufs, 7037ec681f3Smrg struct pipe_surface *zsbuf, 7047ec681f3Smrg struct pipe_surface *bbuf); 70501e04c3fSmrgstruct v3d_job *v3d_get_job_for_fbo(struct v3d_context *v3d); 70601e04c3fSmrgvoid v3d_job_add_bo(struct v3d_job *job, struct v3d_bo *bo); 70701e04c3fSmrgvoid v3d_job_add_write_resource(struct v3d_job *job, struct pipe_resource *prsc); 7087ec681f3Smrgvoid v3d_job_add_tf_write_resource(struct v3d_job *job, struct pipe_resource *prsc); 70901e04c3fSmrgvoid v3d_job_submit(struct v3d_context *v3d, struct v3d_job *job); 7107ec681f3Smrgvoid v3d_flush_jobs_using_bo(struct v3d_context *v3d, struct v3d_bo *bo); 71101e04c3fSmrgvoid v3d_flush_jobs_writing_resource(struct v3d_context *v3d, 7127ec681f3Smrg struct pipe_resource *prsc, 7137ec681f3Smrg enum v3d_flush_cond flush_cond, 7147ec681f3Smrg bool is_compute_pipeline); 71501e04c3fSmrgvoid v3d_flush_jobs_reading_resource(struct v3d_context *v3d, 7167ec681f3Smrg struct pipe_resource *prsc, 7177ec681f3Smrg enum v3d_flush_cond flush_cond, 7187ec681f3Smrg bool is_compute_pipeline); 71901e04c3fSmrgvoid v3d_update_compiled_shaders(struct v3d_context *v3d, uint8_t prim_mode); 7209f464c52Smayavoid v3d_update_compiled_cs(struct v3d_context *v3d); 72101e04c3fSmrg 72201e04c3fSmrgbool v3d_rt_format_supported(const struct v3d_device_info *devinfo, 72301e04c3fSmrg enum pipe_format f); 72401e04c3fSmrgbool v3d_tex_format_supported(const struct v3d_device_info *devinfo, 72501e04c3fSmrg enum pipe_format f); 72601e04c3fSmrguint8_t v3d_get_rt_format(const struct v3d_device_info *devinfo, enum pipe_format f); 72701e04c3fSmrguint8_t v3d_get_tex_format(const struct v3d_device_info *devinfo, enum pipe_format f); 72801e04c3fSmrguint8_t v3d_get_tex_return_size(const struct v3d_device_info *devinfo, 72901e04c3fSmrg enum pipe_format f, 73001e04c3fSmrg enum pipe_tex_compare compare); 73101e04c3fSmrguint8_t v3d_get_tex_return_channels(const struct v3d_device_info *devinfo, 73201e04c3fSmrg enum pipe_format f); 73301e04c3fSmrgconst uint8_t *v3d_get_format_swizzle(const struct v3d_device_info *devinfo, 73401e04c3fSmrg enum pipe_format f); 73501e04c3fSmrgvoid v3d_get_internal_type_bpp_for_output_format(const struct v3d_device_info *devinfo, 73601e04c3fSmrg uint32_t format, 73701e04c3fSmrg uint32_t *type, 73801e04c3fSmrg uint32_t *bpp); 7399f464c52Smayabool v3d_tfu_supports_tex_format(const struct v3d_device_info *devinfo, 7407ec681f3Smrg uint32_t tex_format, 7417ec681f3Smrg bool for_mipmap); 7427ec681f3Smrgbool v3d_format_supports_tlb_msaa_resolve(const struct v3d_device_info *devinfo, 7437ec681f3Smrg enum pipe_format f); 74401e04c3fSmrg 74501e04c3fSmrgvoid v3d_init_query_functions(struct v3d_context *v3d); 74601e04c3fSmrgvoid v3d_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info); 74701e04c3fSmrgvoid v3d_blitter_save(struct v3d_context *v3d); 7487ec681f3Smrgbool v3d_generate_mipmap(struct pipe_context *pctx, 7497ec681f3Smrg struct pipe_resource *prsc, 7507ec681f3Smrg enum pipe_format format, 7517ec681f3Smrg unsigned int base_level, 7527ec681f3Smrg unsigned int last_level, 7537ec681f3Smrg unsigned int first_layer, 7547ec681f3Smrg unsigned int last_layer); 7557ec681f3Smrg 7567ec681f3Smrgvoid 7577ec681f3Smrgv3d_fence_unreference(struct v3d_fence **fence); 75801e04c3fSmrg 75901e04c3fSmrgstruct v3d_fence *v3d_fence_create(struct v3d_context *v3d); 76001e04c3fSmrg 7617ec681f3Smrgbool v3d_fence_wait(struct v3d_screen *screen, 7627ec681f3Smrg struct v3d_fence *fence, 7637ec681f3Smrg uint64_t timeout_ns); 7647ec681f3Smrg 7657ec681f3Smrgvoid v3d_update_primitive_counters(struct v3d_context *v3d); 7667ec681f3Smrg 7677ec681f3Smrgbool v3d_line_smoothing_enabled(struct v3d_context *v3d); 7687ec681f3Smrg 7697ec681f3Smrgfloat v3d_get_real_line_width(struct v3d_context *v3d); 7707ec681f3Smrg 7717ec681f3Smrgvoid v3d_ensure_prim_counts_allocated(struct v3d_context *ctx); 7727ec681f3Smrg 7737ec681f3Smrgvoid v3d_flag_dirty_sampler_state(struct v3d_context *v3d, 7747ec681f3Smrg enum pipe_shader_type shader); 7757ec681f3Smrg 7767ec681f3Smrgvoid v3d_create_texture_shader_state_bo(struct v3d_context *v3d, 7777ec681f3Smrg struct v3d_sampler_view *so); 7787ec681f3Smrg 7797ec681f3Smrgvoid v3d_get_tile_buffer_size(bool is_msaa, 7807ec681f3Smrg uint32_t nr_cbufs, 7817ec681f3Smrg struct pipe_surface **cbufs, 7827ec681f3Smrg struct pipe_surface *bbuf, 7837ec681f3Smrg uint32_t *tile_width, 7847ec681f3Smrg uint32_t *tile_height, 7857ec681f3Smrg uint32_t *max_bpp); 7867ec681f3Smrg 78701e04c3fSmrg#ifdef v3dX 78801e04c3fSmrg# include "v3dx_context.h" 78901e04c3fSmrg#else 79001e04c3fSmrg# define v3dX(x) v3d33_##x 79101e04c3fSmrg# include "v3dx_context.h" 79201e04c3fSmrg# undef v3dX 79301e04c3fSmrg 79401e04c3fSmrg# define v3dX(x) v3d41_##x 79501e04c3fSmrg# include "v3dx_context.h" 79601e04c3fSmrg# undef v3dX 79701e04c3fSmrg#endif 79801e04c3fSmrg 7997ec681f3Smrg#endif /* V3D_CONTEXT_H */ 800