17ec681f3Smrg/*
27ec681f3Smrg * Copyright 2018 Collabora Ltd.
37ec681f3Smrg *
47ec681f3Smrg * Permission is hereby granted, free of charge, to any person obtaining a
57ec681f3Smrg * copy of this software and associated documentation files (the "Software"),
67ec681f3Smrg * to deal in the Software without restriction, including without limitation
77ec681f3Smrg * on the rights to use, copy, modify, merge, publish, distribute, sub
87ec681f3Smrg * license, and/or sell copies of the Software, and to permit persons to whom
97ec681f3Smrg * the Software is furnished to do so, subject to the following conditions:
107ec681f3Smrg *
117ec681f3Smrg * The above copyright notice and this permission notice (including the next
127ec681f3Smrg * paragraph) shall be included in all copies or substantial portions of the
137ec681f3Smrg * Software.
147ec681f3Smrg *
157ec681f3Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
167ec681f3Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
177ec681f3Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
187ec681f3Smrg * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
197ec681f3Smrg * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
207ec681f3Smrg * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
217ec681f3Smrg * USE OR OTHER DEALINGS IN THE SOFTWARE.
227ec681f3Smrg */
237ec681f3Smrg
247ec681f3Smrg#ifndef ZINK_STATE_H
257ec681f3Smrg#define ZINK_STATE_H
267ec681f3Smrg
277ec681f3Smrg#include <vulkan/vulkan.h>
287ec681f3Smrg
297ec681f3Smrg#include "pipe/p_state.h"
307ec681f3Smrg
317ec681f3Smrgstruct zink_vertex_elements_hw_state {
327ec681f3Smrg   uint32_t hash;
337ec681f3Smrg   union {
347ec681f3Smrg      VkVertexInputAttributeDescription attribs[PIPE_MAX_ATTRIBS];
357ec681f3Smrg      VkVertexInputAttributeDescription2EXT dynattribs[PIPE_MAX_ATTRIBS];
367ec681f3Smrg   };
377ec681f3Smrg   union {
387ec681f3Smrg      struct {
397ec681f3Smrg         VkVertexInputBindingDivisorDescriptionEXT divisors[PIPE_MAX_ATTRIBS];
407ec681f3Smrg         VkVertexInputBindingDescription bindings[PIPE_MAX_ATTRIBS]; // combination of element_state and stride
417ec681f3Smrg         uint8_t divisors_present;
427ec681f3Smrg      } b;
437ec681f3Smrg      VkVertexInputBindingDescription2EXT dynbindings[PIPE_MAX_ATTRIBS];
447ec681f3Smrg   };
457ec681f3Smrg   uint32_t num_bindings, num_attribs;
467ec681f3Smrg};
477ec681f3Smrg
487ec681f3Smrgstruct zink_vertex_elements_state {
497ec681f3Smrg   struct {
507ec681f3Smrg      uint32_t binding;
517ec681f3Smrg      VkVertexInputRate inputRate;
527ec681f3Smrg   } bindings[PIPE_MAX_ATTRIBS];
537ec681f3Smrg   uint32_t divisor[PIPE_MAX_ATTRIBS];
547ec681f3Smrg   uint8_t binding_map[PIPE_MAX_ATTRIBS];
557ec681f3Smrg   uint32_t decomposed_attrs;
567ec681f3Smrg   unsigned decomposed_attrs_size;
577ec681f3Smrg   uint32_t decomposed_attrs_without_w;
587ec681f3Smrg   unsigned decomposed_attrs_without_w_size;
597ec681f3Smrg   struct zink_vertex_elements_hw_state hw_state;
607ec681f3Smrg};
617ec681f3Smrg
627ec681f3Smrgstruct zink_rasterizer_hw_state {
637ec681f3Smrg   unsigned polygon_mode : 2; //VkPolygonMode
647ec681f3Smrg   unsigned cull_mode : 2; //VkCullModeFlags
657ec681f3Smrg   unsigned line_mode : 2; //VkLineRasterizationModeEXT
667ec681f3Smrg   unsigned depth_clamp:1;
677ec681f3Smrg   unsigned rasterizer_discard:1;
687ec681f3Smrg   unsigned pv_last:1;
697ec681f3Smrg   unsigned line_stipple_enable:1;
707ec681f3Smrg   unsigned force_persample_interp:1;
717ec681f3Smrg   unsigned clip_halfz:1;
727ec681f3Smrg};
737ec681f3Smrg#define ZINK_RAST_HW_STATE_SIZE 12
747ec681f3Smrg
757ec681f3Smrg
767ec681f3Smrgstruct zink_rasterizer_state {
777ec681f3Smrg   struct pipe_rasterizer_state base;
787ec681f3Smrg   bool offset_point, offset_line, offset_tri;
797ec681f3Smrg   float offset_units, offset_clamp, offset_scale;
807ec681f3Smrg   float line_width;
817ec681f3Smrg   VkFrontFace front_face;
827ec681f3Smrg   struct zink_rasterizer_hw_state hw_state;
837ec681f3Smrg};
847ec681f3Smrg
857ec681f3Smrgstruct zink_blend_state {
867ec681f3Smrg   uint32_t hash;
877ec681f3Smrg   VkPipelineColorBlendAttachmentState attachments[PIPE_MAX_COLOR_BUFS];
887ec681f3Smrg
897ec681f3Smrg   VkBool32 logicop_enable;
907ec681f3Smrg   VkLogicOp logicop_func;
917ec681f3Smrg
927ec681f3Smrg   VkBool32 alpha_to_coverage;
937ec681f3Smrg   VkBool32 alpha_to_one;
947ec681f3Smrg
957ec681f3Smrg   bool need_blend_constants;
967ec681f3Smrg   bool dual_src_blend;
977ec681f3Smrg};
987ec681f3Smrg
997ec681f3Smrgstruct zink_depth_stencil_alpha_hw_state {
1007ec681f3Smrg   VkBool32 depth_test;
1017ec681f3Smrg   VkCompareOp depth_compare_op;
1027ec681f3Smrg
1037ec681f3Smrg   VkBool32 depth_bounds_test;
1047ec681f3Smrg   float min_depth_bounds, max_depth_bounds;
1057ec681f3Smrg
1067ec681f3Smrg   VkBool32 stencil_test;
1077ec681f3Smrg   VkStencilOpState stencil_front;
1087ec681f3Smrg   VkStencilOpState stencil_back;
1097ec681f3Smrg
1107ec681f3Smrg   VkBool32 depth_write;
1117ec681f3Smrg};
1127ec681f3Smrg
1137ec681f3Smrgstruct zink_depth_stencil_alpha_state {
1147ec681f3Smrg   struct pipe_depth_stencil_alpha_state base;
1157ec681f3Smrg   struct zink_depth_stencil_alpha_hw_state hw_state;
1167ec681f3Smrg};
1177ec681f3Smrg
1187ec681f3Smrgvoid
1197ec681f3Smrgzink_context_state_init(struct pipe_context *pctx);
1207ec681f3Smrg
1217ec681f3Smrg#endif
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