1/* 2 * Copyright (c) 2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24#include <stdlib.h> 25#include <math.h> 26 27#include "util/macros.h" 28#include "main/macros.h" 29 30#include "intel_l3_config.h" 31 32struct intel_l3_list { 33 const struct intel_l3_config *configs; 34 int length; 35}; 36 37#define DECLARE_L3_LIST(hw) \ 38 struct intel_l3_list hw##_l3_list = \ 39 { .configs = hw##_l3_configs, .length = ARRAY_SIZE(hw##_l3_configs) } 40 41/** 42 * IVB/HSW validated L3 configurations. The first entry will be used as 43 * default by gfx7_restore_default_l3_config(), otherwise the ordering is 44 * unimportant. 45 */ 46static const struct intel_l3_config ivb_l3_configs[] = { 47 /* SLM URB ALL DC RO IS C T */ 48 {{ 0, 32, 0, 0, 32, 0, 0, 0 }}, 49 {{ 0, 32, 0, 16, 16, 0, 0, 0 }}, 50 {{ 0, 32, 0, 4, 0, 8, 4, 16 }}, 51 {{ 0, 28, 0, 8, 0, 8, 4, 16 }}, 52 {{ 0, 28, 0, 16, 0, 8, 4, 8 }}, 53 {{ 0, 28, 0, 8, 0, 16, 4, 8 }}, 54 {{ 0, 28, 0, 0, 0, 16, 4, 16 }}, 55 {{ 0, 32, 0, 0, 0, 16, 0, 16 }}, 56 {{ 0, 28, 0, 4, 32, 0, 0, 0 }}, 57 {{ 16, 16, 0, 16, 16, 0, 0, 0 }}, 58 {{ 16, 16, 0, 8, 0, 8, 8, 8 }}, 59 {{ 16, 16, 0, 4, 0, 8, 4, 16 }}, 60 {{ 16, 16, 0, 4, 0, 16, 4, 8 }}, 61 {{ 16, 16, 0, 0, 32, 0, 0, 0 }}, 62}; 63DECLARE_L3_LIST(ivb); 64 65/** 66 * VLV validated L3 configurations. \sa ivb_l3_configs. 67 */ 68static const struct intel_l3_config vlv_l3_configs[] = { 69 /* SLM URB ALL DC RO IS C T */ 70 {{ 0, 64, 0, 0, 32, 0, 0, 0 }}, 71 {{ 0, 80, 0, 0, 16, 0, 0, 0 }}, 72 {{ 0, 80, 0, 8, 8, 0, 0, 0 }}, 73 {{ 0, 64, 0, 16, 16, 0, 0, 0 }}, 74 {{ 0, 60, 0, 4, 32, 0, 0, 0 }}, 75 {{ 32, 32, 0, 16, 16, 0, 0, 0 }}, 76 {{ 32, 40, 0, 8, 16, 0, 0, 0 }}, 77 {{ 32, 40, 0, 16, 8, 0, 0, 0 }}, 78}; 79DECLARE_L3_LIST(vlv); 80 81/** 82 * BDW validated L3 configurations. \sa ivb_l3_configs. 83 */ 84static const struct intel_l3_config bdw_l3_configs[] = { 85 /* SLM URB ALL DC RO IS C T */ 86 {{ 0, 48, 48, 0, 0, 0, 0, 0 }}, 87 {{ 0, 48, 0, 16, 32, 0, 0, 0 }}, 88 {{ 0, 32, 0, 16, 48, 0, 0, 0 }}, 89 {{ 0, 32, 0, 0, 64, 0, 0, 0 }}, 90 {{ 0, 32, 64, 0, 0, 0, 0, 0 }}, 91 {{ 24, 16, 48, 0, 0, 0, 0, 0 }}, 92 {{ 24, 16, 0, 16, 32, 0, 0, 0 }}, 93 {{ 24, 16, 0, 32, 16, 0, 0, 0 }}, 94}; 95DECLARE_L3_LIST(bdw); 96 97/** 98 * CHV/SKL validated L3 configurations. \sa ivb_l3_configs. 99 */ 100static const struct intel_l3_config chv_l3_configs[] = { 101 /* SLM URB ALL DC RO IS C T */ 102 {{ 0, 48, 48, 0, 0, 0, 0, 0 }}, 103 {{ 0, 48, 0, 16, 32, 0, 0, 0 }}, 104 {{ 0, 32, 0, 16, 48, 0, 0, 0 }}, 105 {{ 0, 32, 0, 0, 64, 0, 0, 0 }}, 106 {{ 0, 32, 64, 0, 0, 0, 0, 0 }}, 107 {{ 32, 16, 48, 0, 0, 0, 0, 0 }}, 108 {{ 32, 16, 0, 16, 32, 0, 0, 0 }}, 109 {{ 32, 16, 0, 32, 16, 0, 0, 0 }}, 110}; 111DECLARE_L3_LIST(chv); 112 113/** 114 * BXT 2x6 validated L3 configurations. \sa ivb_l3_configs. 115 */ 116static const struct intel_l3_config bxt_2x6_l3_configs[] = { 117 /* SLM URB ALL DC RO IS C T */ 118 {{ 0, 32, 48, 0, 0, 0, 0, 0 }}, 119 {{ 0, 32, 0, 8, 40, 0, 0, 0 }}, 120 {{ 0, 32, 0, 32, 16, 0, 0, 0 }}, 121 {{ 16, 16, 48, 0, 0, 0, 0, 0 }}, 122 {{ 16, 16, 0, 40, 8, 0, 0, 0 }}, 123 {{ 16, 16, 0, 16, 32, 0, 0, 0 }}, 124}; 125DECLARE_L3_LIST(bxt_2x6); 126 127/** 128 * ICL validated L3 configurations. \sa icl_l3_configs. 129 * Zeroth entry in below table has been commented out intentionally 130 * due to known issues with this configuration. Many other entries 131 * suggested by h/w specification aren't added here because they 132 * do under allocation of L3 cache with below partitioning. 133 */ 134static const struct intel_l3_config icl_l3_configs[] = { 135 /* SLM URB ALL DC RO IS C T */ 136 /*{{ 0, 16, 80, 0, 0, 0, 0, 0 }},*/ 137 {{ 0, 32, 64, 0, 0, 0, 0, 0 }}, 138}; 139DECLARE_L3_LIST(icl); 140 141/** 142 * TGL validated L3 configurations. \sa tgl_l3_configs. 143 */ 144static const struct intel_l3_config tgl_l3_configs[] = { 145 /* SLM URB ALL DC RO IS C T */ 146 {{ 0, 32, 88, 0, 0, 0, 0, 0 }}, 147 {{ 0, 16, 104, 0, 0, 0, 0, 0 }}, 148}; 149DECLARE_L3_LIST(tgl); 150 151/** 152 * Empty L3 configurations. \sa empty_l3_configs. 153 */ 154static const struct intel_l3_config empty_l3_configs[] = { 155 /* No configurations. L3FullWayAllocationEnable is always set. */ 156}; 157DECLARE_L3_LIST(empty); 158 159/** 160 * Return a zero-terminated array of validated L3 configurations for the 161 * specified device. 162 */ 163static const struct intel_l3_list * 164get_l3_list(const struct intel_device_info *devinfo) 165{ 166 switch (devinfo->ver) { 167 case 7: 168 return (devinfo->is_baytrail ? &vlv_l3_list : &ivb_l3_list); 169 170 case 8: 171 return (devinfo->is_cherryview ? &chv_l3_list : &bdw_l3_list); 172 173 case 9: 174 if (devinfo->l3_banks == 1) 175 return &bxt_2x6_l3_list; 176 return &chv_l3_list; 177 178 case 11: 179 return &icl_l3_list; 180 181 case 12: 182 if (devinfo->is_dg1 || devinfo->is_dg2) 183 return &empty_l3_list; 184 else 185 return &tgl_l3_list; 186 187 default: 188 unreachable("Not implemented"); 189 } 190} 191 192/** 193 * L1-normalize a vector of L3 partition weights. 194 */ 195static struct intel_l3_weights 196norm_l3_weights(struct intel_l3_weights w) 197{ 198 float sz = 0; 199 200 for (unsigned i = 0; i < INTEL_NUM_L3P; i++) 201 sz += w.w[i]; 202 203 for (unsigned i = 0; i < INTEL_NUM_L3P; i++) 204 w.w[i] /= sz; 205 206 return w; 207} 208 209/** 210 * Get the relative partition weights of the specified L3 configuration. 211 */ 212struct intel_l3_weights 213intel_get_l3_config_weights(const struct intel_l3_config *cfg) 214{ 215 if (cfg) { 216 struct intel_l3_weights w; 217 218 for (unsigned i = 0; i < INTEL_NUM_L3P; i++) 219 w.w[i] = cfg->n[i]; 220 221 return norm_l3_weights(w); 222 } else { 223 const struct intel_l3_weights w = { { 0 } }; 224 return w; 225 } 226} 227 228/** 229 * Distance between two L3 configurations represented as vectors of weights. 230 * Usually just the L1 metric except when the two configurations are 231 * considered incompatible in which case the distance will be infinite. Note 232 * that the compatibility condition is asymmetric -- They will be considered 233 * incompatible whenever the reference configuration \p w0 requires SLM, DC, 234 * or URB but \p w1 doesn't provide it. 235 */ 236float 237intel_diff_l3_weights(struct intel_l3_weights w0, struct intel_l3_weights w1) 238{ 239 if ((w0.w[INTEL_L3P_SLM] && !w1.w[INTEL_L3P_SLM]) || 240 (w0.w[INTEL_L3P_DC] && !w1.w[INTEL_L3P_DC] && !w1.w[INTEL_L3P_ALL]) || 241 (w0.w[INTEL_L3P_URB] && !w1.w[INTEL_L3P_URB])) { 242 return HUGE_VALF; 243 244 } else { 245 float dw = 0; 246 247 for (unsigned i = 0; i < INTEL_NUM_L3P; i++) 248 dw += fabsf(w0.w[i] - w1.w[i]); 249 250 return dw; 251 } 252} 253 254/** 255 * Return a reasonable default L3 configuration for the specified device based 256 * on whether SLM and DC are required. In the non-SLM non-DC case the result 257 * is intended to approximately resemble the hardware defaults. 258 */ 259struct intel_l3_weights 260intel_get_default_l3_weights(const struct intel_device_info *devinfo, 261 bool needs_dc, bool needs_slm) 262{ 263 struct intel_l3_weights w = {{ 0 }}; 264 265 w.w[INTEL_L3P_SLM] = devinfo->ver < 11 && needs_slm; 266 w.w[INTEL_L3P_URB] = 1.0; 267 268 if (devinfo->ver >= 8) { 269 w.w[INTEL_L3P_ALL] = 1.0; 270 } else { 271 w.w[INTEL_L3P_DC] = needs_dc ? 0.1 : 0; 272 w.w[INTEL_L3P_RO] = devinfo->is_baytrail ? 0.5 : 1.0; 273 } 274 275 return norm_l3_weights(w); 276} 277 278/** 279 * Get the default L3 configuration 280 */ 281const struct intel_l3_config * 282intel_get_default_l3_config(const struct intel_device_info *devinfo) 283{ 284 /* For efficiency assume that the first entry of the array matches the 285 * default configuration. 286 */ 287 const struct intel_l3_list *const list = get_l3_list(devinfo); 288 assert(list->length > 0 || devinfo->ver >= 12); 289 if (list->length > 0) { 290 const struct intel_l3_config *const cfg = &list->configs[0]; 291 assert(cfg == intel_get_l3_config(devinfo, 292 intel_get_default_l3_weights(devinfo, false, false))); 293 return cfg; 294 } else { 295 return NULL; 296 } 297} 298 299/** 300 * Return the closest validated L3 configuration for the specified device and 301 * weight vector. 302 */ 303const struct intel_l3_config * 304intel_get_l3_config(const struct intel_device_info *devinfo, 305 struct intel_l3_weights w0) 306{ 307 const struct intel_l3_list *const list = get_l3_list(devinfo); 308 const struct intel_l3_config *const cfgs = list->configs; 309 const struct intel_l3_config *cfg_best = NULL; 310 float dw_best = HUGE_VALF; 311 312 for (int i = 0; i < list->length; i++) { 313 const struct intel_l3_config *cfg = &cfgs[i]; 314 const float dw = intel_diff_l3_weights(w0, intel_get_l3_config_weights(cfg)); 315 316 if (dw < dw_best) { 317 cfg_best = cfg; 318 dw_best = dw; 319 } 320 } 321 322 assert(cfg_best || devinfo->ver >= 12); 323 return cfg_best; 324} 325 326/** 327 * Return the size of an L3 way in KB. 328 */ 329static unsigned 330get_l3_way_size(const struct intel_device_info *devinfo) 331{ 332 const unsigned way_size_per_bank = 333 (devinfo->ver >= 9 && devinfo->l3_banks == 1) || devinfo->ver >= 11 ? 334 4 : 2; 335 336 assert(devinfo->l3_banks); 337 return way_size_per_bank * devinfo->l3_banks; 338} 339 340/** 341 * Return the unit brw_context::urb::size is expressed in, in KB. \sa 342 * intel_device_info::urb::size. 343 */ 344static unsigned 345get_urb_size_scale(const struct intel_device_info *devinfo) 346{ 347 return (devinfo->ver >= 8 ? devinfo->num_slices : 1); 348} 349 350unsigned 351intel_get_l3_config_urb_size(const struct intel_device_info *devinfo, 352 const struct intel_l3_config *cfg) 353{ 354 /* We don't have to program the URB size in DG1, it's a fixed value. */ 355 if (devinfo->is_dg1) 356 return devinfo->urb.size; 357 358 /* From the SKL "L3 Allocation and Programming" documentation: 359 * 360 * "URB is limited to 1008KB due to programming restrictions. This is not 361 * a restriction of the L3 implementation, but of the FF and other clients. 362 * Therefore, in a GT4 implementation it is possible for the programmed 363 * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but 364 * only 1008KB of this will be used." 365 */ 366 const unsigned max = (devinfo->ver == 9 ? 1008 : ~0); 367 return MIN2(max, cfg->n[INTEL_L3P_URB] * get_l3_way_size(devinfo)) / 368 get_urb_size_scale(devinfo); 369} 370 371/** 372 * Print out the specified L3 configuration. 373 */ 374void 375intel_dump_l3_config(const struct intel_l3_config *cfg, FILE *fp) 376{ 377 fprintf(stderr, "SLM=%d URB=%d ALL=%d DC=%d RO=%d IS=%d C=%d T=%d\n", 378 cfg->n[INTEL_L3P_SLM], cfg->n[INTEL_L3P_URB], cfg->n[INTEL_L3P_ALL], 379 cfg->n[INTEL_L3P_DC], cfg->n[INTEL_L3P_RO], 380 cfg->n[INTEL_L3P_IS], cfg->n[INTEL_L3P_C], cfg->n[INTEL_L3P_T]); 381} 382