1/* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24/** 25 * @file brw_inst.h 26 * 27 * A representation of i965 EU assembly instructions, with helper methods to 28 * get and set various fields. This is the actual hardware format. 29 */ 30 31#ifndef BRW_INST_H 32#define BRW_INST_H 33 34#include <assert.h> 35#include <stdint.h> 36 37#include "brw_eu_defines.h" 38#include "brw_reg_type.h" 39#include "dev/intel_device_info.h" 40 41#ifdef __cplusplus 42extern "C" { 43#endif 44 45/* brw_context.h has a forward declaration of brw_inst, so name the struct. */ 46typedef struct brw_inst { 47 uint64_t data[2]; 48} brw_inst; 49 50static inline uint64_t brw_inst_bits(const brw_inst *inst, 51 unsigned high, unsigned low); 52static inline void brw_inst_set_bits(brw_inst *inst, 53 unsigned high, unsigned low, 54 uint64_t value); 55 56#define FC(name, hi4, lo4, hi12, lo12, assertions) \ 57static inline void \ 58brw_inst_set_##name(const struct intel_device_info *devinfo, \ 59 brw_inst *inst, uint64_t v) \ 60{ \ 61 assert(assertions); \ 62 if (devinfo->ver >= 12) \ 63 brw_inst_set_bits(inst, hi12, lo12, v); \ 64 else \ 65 brw_inst_set_bits(inst, hi4, lo4, v); \ 66} \ 67static inline uint64_t \ 68brw_inst_##name(const struct intel_device_info *devinfo, \ 69 const brw_inst *inst) \ 70{ \ 71 assert(assertions); \ 72 if (devinfo->ver >= 12) \ 73 return brw_inst_bits(inst, hi12, lo12); \ 74 else \ 75 return brw_inst_bits(inst, hi4, lo4); \ 76} 77 78/* A simple macro for fields which stay in the same place on all generations, 79 * except for Gfx12! 80 */ 81#define F(name, hi4, lo4, hi12, lo12) FC(name, hi4, lo4, hi12, lo12, true) 82 83#define BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \ 84 hi7, lo7, hi8, lo8, hi12, lo12) \ 85 unsigned high, low; \ 86 if (devinfo->ver >= 12) { \ 87 high = hi12; low = lo12; \ 88 } else if (devinfo->ver >= 8) { \ 89 high = hi8; low = lo8; \ 90 } else if (devinfo->ver >= 7) { \ 91 high = hi7; low = lo7; \ 92 } else if (devinfo->ver >= 6) { \ 93 high = hi6; low = lo6; \ 94 } else if (devinfo->ver >= 5) { \ 95 high = hi5; low = lo5; \ 96 } else if (devinfo->is_g4x) { \ 97 high = hi45; low = lo45; \ 98 } else { \ 99 high = hi4; low = lo4; \ 100 } \ 101 assert(((int) high) != -1 && ((int) low) != -1); 102 103/* A general macro for cases where the field has moved to several different 104 * bit locations across generations. GCC appears to combine cases where the 105 * bits are identical, removing some of the inefficiency. 106 */ 107#define FF(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \ 108 hi7, lo7, hi8, lo8, hi12, lo12) \ 109static inline void \ 110brw_inst_set_##name(const struct intel_device_info *devinfo, \ 111 brw_inst *inst, uint64_t value) \ 112{ \ 113 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \ 114 hi7, lo7, hi8, lo8, hi12, lo12) \ 115 brw_inst_set_bits(inst, high, low, value); \ 116} \ 117static inline uint64_t \ 118brw_inst_##name(const struct intel_device_info *devinfo, const brw_inst *inst)\ 119{ \ 120 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \ 121 hi7, lo7, hi8, lo8, hi12, lo12) \ 122 return brw_inst_bits(inst, high, low); \ 123} 124 125/* A macro for fields which moved as of Gfx8+. */ 126#define F8(name, gfx4_high, gfx4_low, gfx8_high, gfx8_low, \ 127 gfx12_high, gfx12_low) \ 128FF(name, \ 129 /* 4: */ gfx4_high, gfx4_low, \ 130 /* 4.5: */ gfx4_high, gfx4_low, \ 131 /* 5: */ gfx4_high, gfx4_low, \ 132 /* 6: */ gfx4_high, gfx4_low, \ 133 /* 7: */ gfx4_high, gfx4_low, \ 134 /* 8: */ gfx8_high, gfx8_low, \ 135 /* 12: */ gfx12_high, gfx12_low); 136 137/* Macro for fields that gained extra discontiguous MSBs in Gfx12 (specified 138 * by hi12ex-lo12ex). 139 */ 140#define FFDC(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \ 141 hi7, lo7, hi8, lo8, hi12ex, lo12ex, hi12, lo12, assertions) \ 142static inline void \ 143brw_inst_set_##name(const struct intel_device_info *devinfo, \ 144 brw_inst *inst, uint64_t value) \ 145{ \ 146 assert(assertions); \ 147 if (devinfo->ver >= 12) { \ 148 const unsigned k = hi12 - lo12 + 1; \ 149 if (hi12ex != -1 && lo12ex != -1) \ 150 brw_inst_set_bits(inst, hi12ex, lo12ex, value >> k); \ 151 brw_inst_set_bits(inst, hi12, lo12, value & ((1ull << k) - 1)); \ 152 } else { \ 153 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \ 154 hi7, lo7, hi8, lo8, -1, -1); \ 155 brw_inst_set_bits(inst, high, low, value); \ 156 } \ 157} \ 158static inline uint64_t \ 159brw_inst_##name(const struct intel_device_info *devinfo, const brw_inst *inst)\ 160{ \ 161 assert(assertions); \ 162 if (devinfo->ver >= 12) { \ 163 const unsigned k = hi12 - lo12 + 1; \ 164 return (hi12ex == -1 || lo12ex == -1 ? 0 : \ 165 brw_inst_bits(inst, hi12ex, lo12ex) << k) | \ 166 brw_inst_bits(inst, hi12, lo12); \ 167 } else { \ 168 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \ 169 hi7, lo7, hi8, lo8, -1, -1); \ 170 return brw_inst_bits(inst, high, low); \ 171 } \ 172} 173 174#define FD(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \ 175 hi7, lo7, hi8, lo8, hi12ex, lo12ex, hi12, lo12) \ 176 FFDC(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, \ 177 hi7, lo7, hi8, lo8, hi12ex, lo12ex, hi12, lo12, true) 178 179/* Macro for fields that didn't move across generations until Gfx12, and then 180 * gained extra discontiguous bits. 181 */ 182#define FDC(name, hi4, lo4, hi12ex, lo12ex, hi12, lo12, assertions) \ 183 FFDC(name, hi4, lo4, hi4, lo4, hi4, lo4, hi4, lo4, \ 184 hi4, lo4, hi4, lo4, hi12ex, lo12ex, hi12, lo12, assertions) 185 186 187/* Macro for the 2-bit register file field, which on Gfx12+ is stored as the 188 * variable length combination of an IsImm (hi12) bit and an additional file 189 * (lo12) bit. 190 */ 191#define FI(name, hi4, lo4, hi8, lo8, hi12, lo12) \ 192static inline void \ 193brw_inst_set_##name(const struct intel_device_info *devinfo, \ 194 brw_inst *inst, uint64_t value) \ 195{ \ 196 if (devinfo->ver >= 12) { \ 197 brw_inst_set_bits(inst, hi12, hi12, value >> 1); \ 198 if ((value >> 1) == 0) \ 199 brw_inst_set_bits(inst, lo12, lo12, value & 1); \ 200 } else { \ 201 BOUNDS(hi4, lo4, hi4, lo4, hi4, lo4, hi4, lo4, \ 202 hi4, lo4, hi8, lo8, -1, -1); \ 203 brw_inst_set_bits(inst, high, low, value); \ 204 } \ 205} \ 206static inline uint64_t \ 207brw_inst_##name(const struct intel_device_info *devinfo, const brw_inst *inst)\ 208{ \ 209 if (devinfo->ver >= 12) { \ 210 return (brw_inst_bits(inst, hi12, hi12) << 1) | \ 211 (brw_inst_bits(inst, hi12, hi12) == 0 ? \ 212 brw_inst_bits(inst, lo12, lo12) : 1); \ 213 } else { \ 214 BOUNDS(hi4, lo4, hi4, lo4, hi4, lo4, hi4, lo4, \ 215 hi4, lo4, hi8, lo8, -1, -1); \ 216 return brw_inst_bits(inst, high, low); \ 217 } \ 218} 219 220/* Macro for fields that become a constant in Gfx12+ not actually represented 221 * in the instruction. 222 */ 223#define FK(name, hi4, lo4, const12) \ 224static inline void \ 225brw_inst_set_##name(const struct intel_device_info *devinfo, \ 226 brw_inst *inst, uint64_t v) \ 227{ \ 228 if (devinfo->ver >= 12) \ 229 assert(v == (const12)); \ 230 else \ 231 brw_inst_set_bits(inst, hi4, lo4, v); \ 232} \ 233static inline uint64_t \ 234brw_inst_##name(const struct intel_device_info *devinfo, \ 235 const brw_inst *inst) \ 236{ \ 237 if (devinfo->ver >= 12) \ 238 return (const12); \ 239 else \ 240 return brw_inst_bits(inst, hi4, lo4); \ 241} 242 243F(src1_vstride, /* 4+ */ 120, 117, /* 12+ */ 119, 116) 244F(src1_width, /* 4+ */ 116, 114, /* 12+ */ 115, 113) 245F(src1_da16_swiz_w, /* 4+ */ 115, 114, /* 12+ */ -1, -1) 246F(src1_da16_swiz_z, /* 4+ */ 113, 112, /* 12+ */ -1, -1) 247F(src1_hstride, /* 4+ */ 113, 112, /* 12+ */ 97, 96) 248F(src1_address_mode, /* 4+ */ 111, 111, /* 12+ */ 112, 112) 249/** Src1.SrcMod @{ */ 250F(src1_negate, /* 4+ */ 110, 110, /* 12+ */ 121, 121) 251F(src1_abs, /* 4+ */ 109, 109, /* 12+ */ 120, 120) 252/** @} */ 253F8(src1_ia_subreg_nr, /* 4+ */ 108, 106, /* 8+ */ 108, 105, /* 12+ */ 111, 108) 254F(src1_da_reg_nr, /* 4+ */ 108, 101, /* 12+ */ 111, 104) 255F(src1_da16_subreg_nr, /* 4+ */ 100, 100, /* 12+ */ -1, -1) 256F(src1_da1_subreg_nr, /* 4+ */ 100, 96, /* 12+ */ 103, 99) 257F(src1_da16_swiz_y, /* 4+ */ 99, 98, /* 12+ */ -1, -1) 258F(src1_da16_swiz_x, /* 4+ */ 97, 96, /* 12+ */ -1, -1) 259F8(src1_reg_hw_type, /* 4+ */ 46, 44, /* 8+ */ 94, 91, /* 12+ */ 91, 88) 260FI(src1_reg_file, /* 4+ */ 43, 42, /* 8+ */ 90, 89, /* 12+ */ 47, 98) 261F(src1_is_imm, /* 4+ */ -1, -1, /* 12+ */ 47, 47) 262F(src0_vstride, /* 4+ */ 88, 85, /* 12+ */ 87, 84) 263F(src0_width, /* 4+ */ 84, 82, /* 12+ */ 83, 81) 264F(src0_da16_swiz_w, /* 4+ */ 83, 82, /* 12+ */ -1, -1) 265F(src0_da16_swiz_z, /* 4+ */ 81, 80, /* 12+ */ -1, -1) 266F(src0_hstride, /* 4+ */ 81, 80, /* 12+ */ 65, 64) 267F(src0_address_mode, /* 4+ */ 79, 79, /* 12+ */ 80, 80) 268/** Src0.SrcMod @{ */ 269F(src0_negate, /* 4+ */ 78, 78, /* 12+ */ 45, 45) 270F(src0_abs, /* 4+ */ 77, 77, /* 12+ */ 44, 44) 271/** @} */ 272F8(src0_ia_subreg_nr, /* 4+ */ 76, 74, /* 8+ */ 76, 73, /* 12+ */ 79, 76) 273F(src0_da_reg_nr, /* 4+ */ 76, 69, /* 12+ */ 79, 72) 274F(src0_da16_subreg_nr, /* 4+ */ 68, 68, /* 12+ */ -1, -1) 275F(src0_da1_subreg_nr, /* 4+ */ 68, 64, /* 12+ */ 71, 67) 276F(src0_da16_swiz_y, /* 4+ */ 67, 66, /* 12+ */ -1, -1) 277F(src0_da16_swiz_x, /* 4+ */ 65, 64, /* 12+ */ -1, -1) 278F(dst_address_mode, /* 4+ */ 63, 63, /* 12+ */ 35, 35) 279F(dst_hstride, /* 4+ */ 62, 61, /* 12+ */ 49, 48) 280F8(dst_ia_subreg_nr, /* 4+ */ 60, 58, /* 8+ */ 60, 57, /* 12+ */ 63, 60) 281F(dst_da_reg_nr, /* 4+ */ 60, 53, /* 12+ */ 63, 56) 282F(dst_da16_subreg_nr, /* 4+ */ 52, 52, /* 12+ */ -1, -1) 283F(dst_da1_subreg_nr, /* 4+ */ 52, 48, /* 12+ */ 55, 51) 284F(da16_writemask, /* 4+ */ 51, 48, /* 12+ */ -1, -1) /* Dst.ChanEn */ 285F8(src0_reg_hw_type, /* 4+ */ 41, 39, /* 8+ */ 46, 43, /* 12+ */ 43, 40) 286FI(src0_reg_file, /* 4+ */ 38, 37, /* 8+ */ 42, 41, /* 12+ */ 46, 66) 287F(src0_is_imm, /* 4+ */ -1, -1, /* 12+ */ 46, 46) 288F8(dst_reg_hw_type, /* 4+ */ 36, 34, /* 8+ */ 40, 37, /* 12+ */ 39, 36) 289F8(dst_reg_file, /* 4+ */ 33, 32, /* 8+ */ 36, 35, /* 12+ */ 50, 50) 290F8(mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34, /* 12+ */ 31, 31) 291FF(flag_reg_nr, 292 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1, 293 /* 7: */ 90, 90, 294 /* 8: */ 33, 33, 295 /* 12: */ 23, 23) 296F8(flag_subreg_nr, /* 4+ */ 89, 89, /* 8+ */ 32, 32, /* 12+ */ 22, 22) 297F(saturate, /* 4+ */ 31, 31, /* 12+ */ 34, 34) 298F(debug_control, /* 4+ */ 30, 30, /* 12+ */ 30, 30) 299F(cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29) 300FC(branch_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33, devinfo->ver >= 8) 301FC(acc_wr_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33, devinfo->ver >= 6) 302FC(mask_control_ex, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo->is_g4x || devinfo->ver == 5) 303F(cond_modifier, /* 4+ */ 27, 24, /* 12+ */ 95, 92) 304FC(math_function, /* 4+ */ 27, 24, /* 12+ */ 95, 92, devinfo->ver >= 6) 305F(exec_size, /* 4+ */ 23, 21, /* 12+ */ 18, 16) 306F(pred_inv, /* 4+ */ 20, 20, /* 12+ */ 28, 28) 307F(pred_control, /* 4+ */ 19, 16, /* 12+ */ 27, 24) 308F(thread_control, /* 4+ */ 15, 14, /* 12+ */ -1, -1) 309F(atomic_control, /* 4+ */ -1, -1, /* 12+ */ 32, 32) 310F(qtr_control, /* 4+ */ 13, 12, /* 12+ */ 21, 20) 311FF(nib_control, 312 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1, 313 /* 7: */ 47, 47, 314 /* 8: */ 11, 11, 315 /* 12: */ 19, 19) 316F8(no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10, /* 12+ */ -1, -1) 317F8(no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9, /* 12+ */ -1, -1) 318F(swsb, /* 4+ */ -1, -1, /* 12+ */ 15, 8) 319FK(access_mode, /* 4+ */ 8, 8, /* 12+ */ BRW_ALIGN_1) 320/* Bit 7 is Reserved (for future Opcode expansion) */ 321F(hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0) 322 323/** 324 * Three-source instructions: 325 * @{ 326 */ 327F(3src_src2_reg_nr, /* 4+ */ 125, 118, /* 12+ */ 127, 120) /* same in align1 */ 328F(3src_a16_src2_subreg_nr, /* 4+ */ 117, 115, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */ 329F(3src_a16_src2_swizzle, /* 4+ */ 114, 107, /* 12+ */ -1, -1) 330F(3src_a16_src2_rep_ctrl, /* 4+ */ 106, 106, /* 12+ */ -1, -1) 331F(3src_src1_reg_nr, /* 4+ */ 104, 97, /* 12+ */ 111, 104) /* same in align1 */ 332F(3src_a16_src1_subreg_nr, /* 4+ */ 96, 94, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */ 333F(3src_a16_src1_swizzle, /* 4+ */ 93, 86, /* 12+ */ -1, -1) 334F(3src_a16_src1_rep_ctrl, /* 4+ */ 85, 85, /* 12+ */ -1, -1) 335F(3src_src0_reg_nr, /* 4+ */ 83, 76, /* 12+ */ 79, 72) /* same in align1 */ 336F(3src_a16_src0_subreg_nr, /* 4+ */ 75, 73, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */ 337F(3src_a16_src0_swizzle, /* 4+ */ 72, 65, /* 12+ */ -1, -1) 338F(3src_a16_src0_rep_ctrl, /* 4+ */ 64, 64, /* 12+ */ -1, -1) 339F(3src_dst_reg_nr, /* 4+ */ 63, 56, /* 12+ */ 63, 56) /* same in align1 */ 340F(3src_a16_dst_subreg_nr, /* 4+ */ 55, 53, /* 12+ */ -1, -1) 341F(3src_a16_dst_writemask, /* 4+ */ 52, 49, /* 12+ */ -1, -1) 342F8(3src_a16_nib_ctrl, /* 4+ */ 47, 47, /* 8+ */ 11, 11, /* 12+ */ -1, -1) /* only exists on IVB+ */ 343F8(3src_a16_dst_hw_type, /* 4+ */ 45, 44, /* 8+ */ 48, 46, /* 12+ */ -1, -1) /* only exists on IVB+ */ 344F8(3src_a16_src_hw_type, /* 4+ */ 43, 42, /* 8+ */ 45, 43, /* 12+ */ -1, -1) 345F8(3src_src2_negate, /* 4+ */ 41, 41, /* 8+ */ 42, 42, /* 12+ */ 85, 85) 346F8(3src_src2_abs, /* 4+ */ 40, 40, /* 8+ */ 41, 41, /* 12+ */ 84, 84) 347F8(3src_src1_negate, /* 4+ */ 39, 39, /* 8+ */ 40, 40, /* 12+ */ 87, 87) 348F8(3src_src1_abs, /* 4+ */ 38, 38, /* 8+ */ 39, 39, /* 12+ */ 86, 86) 349F8(3src_src0_negate, /* 4+ */ 37, 37, /* 8+ */ 38, 38, /* 12+ */ 45, 45) 350F8(3src_src0_abs, /* 4+ */ 36, 36, /* 8+ */ 37, 37, /* 12+ */ 44, 44) 351F8(3src_a16_src1_type, /* 4+ */ -1, -1, /* 8+ */ 36, 36, /* 12+ */ -1, -1) 352F8(3src_a16_src2_type, /* 4+ */ -1, -1, /* 8+ */ 35, 35, /* 12+ */ -1, -1) 353F8(3src_a16_flag_reg_nr, /* 4+ */ 34, 34, /* 8+ */ 33, 33, /* 12+ */ -1, -1) 354F8(3src_a16_flag_subreg_nr, /* 4+ */ 33, 33, /* 8+ */ 32, 32, /* 12+ */ -1, -1) 355FF(3src_a16_dst_reg_file, 356 /* 4-5: doesn't exist - no 3-source instructions */ -1, -1, -1, -1, -1, -1, 357 /* 6: */ 32, 32, 358 /* 7-8: doesn't exist - no MRFs */ -1, -1, -1, -1, 359 /* 12: */ -1, -1) 360F(3src_saturate, /* 4+ */ 31, 31, /* 12+ */ 34, 34) 361F(3src_debug_control, /* 4+ */ 30, 30, /* 12+ */ 30, 30) 362F(3src_cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29) 363F(3src_acc_wr_control, /* 4+ */ 28, 28, /* 12+ */ 33, 33) 364F(3src_cond_modifier, /* 4+ */ 27, 24, /* 12+ */ 95, 92) 365F(3src_exec_size, /* 4+ */ 23, 21, /* 12+ */ 18, 16) 366F(3src_pred_inv, /* 4+ */ 20, 20, /* 12+ */ 28, 28) 367F(3src_pred_control, /* 4+ */ 19, 16, /* 12+ */ 27, 24) 368F(3src_thread_control, /* 4+ */ 15, 14, /* 12+ */ -1, -1) 369F(3src_atomic_control, /* 4+ */ -1, -1, /* 12+ */ 32, 32) 370F(3src_qtr_control, /* 4+ */ 13, 12, /* 12+ */ 21, 20) 371F8(3src_no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10, /* 12+ */ -1, -1) 372F8(3src_no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9, /* 12+ */ -1, -1) 373F8(3src_mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34, /* 12+ */ 31, 31) 374FK(3src_access_mode, /* 4+ */ 8, 8, /* 12+ */ BRW_ALIGN_1) 375F(3src_swsb, /* 4+ */ -1, -1, /* 12+ */ 15, 8) 376/* Bit 7 is Reserved (for future Opcode expansion) */ 377F(3src_hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0) 378/** @} */ 379 380#define REG_TYPE(reg) \ 381static inline void \ 382brw_inst_set_3src_a16_##reg##_type(const struct intel_device_info *devinfo, \ 383 brw_inst *inst, enum brw_reg_type type) \ 384{ \ 385 unsigned hw_type = brw_reg_type_to_a16_hw_3src_type(devinfo, type); \ 386 brw_inst_set_3src_a16_##reg##_hw_type(devinfo, inst, hw_type); \ 387} \ 388 \ 389static inline enum brw_reg_type \ 390brw_inst_3src_a16_##reg##_type(const struct intel_device_info *devinfo, \ 391 const brw_inst *inst) \ 392{ \ 393 unsigned hw_type = brw_inst_3src_a16_##reg##_hw_type(devinfo, inst); \ 394 return brw_a16_hw_3src_type_to_reg_type(devinfo, hw_type); \ 395} 396 397REG_TYPE(dst) 398REG_TYPE(src) 399#undef REG_TYPE 400 401/** 402 * Three-source align1 instructions: 403 * @{ 404 */ 405/* Reserved 127:126 */ 406/* src2_reg_nr same in align16 */ 407FC(3src_a1_src2_subreg_nr, /* 4+ */ 117, 113, /* 12+ */ 119, 115, devinfo->ver >= 10) 408FC(3src_a1_src2_hstride, /* 4+ */ 112, 111, /* 12+ */ 113, 112, devinfo->ver >= 10) 409/* Reserved 110:109. src2 vstride is an implied parameter */ 410FC(3src_a1_src2_hw_type, /* 4+ */ 108, 106, /* 12+ */ 82, 80, devinfo->ver >= 10) 411/* Reserved 105 */ 412/* src1_reg_nr same in align16 */ 413FC(3src_a1_src1_subreg_nr, /* 4+ */ 96, 92, /* 12+ */ 103, 99, devinfo->ver >= 10) 414FC(3src_a1_src1_hstride, /* 4+ */ 91, 90, /* 12+ */ 97, 96, devinfo->ver >= 10) 415FDC(3src_a1_src1_vstride, /* 4+ */ 89, 88, /* 12+ */ 91, 91, 83, 83, devinfo->ver >= 10) 416FC(3src_a1_src1_hw_type, /* 4+ */ 87, 85, /* 12+ */ 90, 88, devinfo->ver >= 10) 417/* Reserved 84 */ 418/* src0_reg_nr same in align16 */ 419FC(3src_a1_src0_subreg_nr, /* 4+ */ 75, 71, /* 12+ */ 71, 67, devinfo->ver >= 10) 420FC(3src_a1_src0_hstride, /* 4+ */ 70, 69, /* 12+ */ 65, 64, devinfo->ver >= 10) 421FDC(3src_a1_src0_vstride, /* 4+ */ 68, 67, /* 12+ */ 43, 43, 35, 35, devinfo->ver >= 10) 422FC(3src_a1_src0_hw_type, /* 4+ */ 66, 64, /* 12+ */ 42, 40, devinfo->ver >= 10) 423/* dst_reg_nr same in align16 */ 424FC(3src_a1_dst_subreg_nr, /* 4+ */ 55, 54, /* 12+ */ 55, 54, devinfo->ver >= 10) 425FC(3src_a1_special_acc, /* 4+ */ 55, 52, /* 12+ */ 54, 51, devinfo->ver >= 10) /* aliases dst_subreg_nr */ 426/* Reserved 51:50 */ 427FC(3src_a1_dst_hstride, /* 4+ */ 49, 49, /* 12+ */ 48, 48, devinfo->ver >= 10) 428FC(3src_a1_dst_hw_type, /* 4+ */ 48, 46, /* 12+ */ 38, 36, devinfo->ver >= 10) 429FI(3src_a1_src2_reg_file, /* 4+ */ -1, -1, /* 8+ */ 45, 45, /* 12+ */ 47, 114) 430FC(3src_a1_src1_reg_file, /* 4+ */ 44, 44, /* 12+ */ 98, 98, devinfo->ver >= 10) 431FI(3src_a1_src0_reg_file, /* 4+ */ -1, -1, /* 8+ */ 43, 43, /* 12+ */ 46, 66) 432 433F(3src_a1_src2_is_imm, /* 4+ */ -1, -1, /* 12+ */ 47, 47) 434F(3src_a1_src0_is_imm, /* 4+ */ -1, -1, /* 12+ */ 46, 46) 435 436/* Source Modifier fields same in align16 */ 437FC(3src_a1_dst_reg_file, /* 4+ */ 36, 36, /* 12+ */ 50, 50, devinfo->ver >= 10) 438FC(3src_a1_exec_type, /* 4+ */ 35, 35, /* 12+ */ 39, 39, devinfo->ver >= 10) 439/* Fields below this same in align16 */ 440/** @} */ 441 442#define REG_TYPE(reg) \ 443static inline void \ 444brw_inst_set_3src_a1_##reg##_type(const struct intel_device_info *devinfo, \ 445 brw_inst *inst, enum brw_reg_type type) \ 446{ \ 447 UNUSED enum gfx10_align1_3src_exec_type exec_type = \ 448 (enum gfx10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \ 449 inst); \ 450 if (brw_reg_type_is_floating_point(type)) { \ 451 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT); \ 452 } else { \ 453 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_INT); \ 454 } \ 455 unsigned hw_type = brw_reg_type_to_a1_hw_3src_type(devinfo, type); \ 456 brw_inst_set_3src_a1_##reg##_hw_type(devinfo, inst, hw_type); \ 457} \ 458 \ 459static inline enum brw_reg_type \ 460brw_inst_3src_a1_##reg##_type(const struct intel_device_info *devinfo, \ 461 const brw_inst *inst) \ 462{ \ 463 enum gfx10_align1_3src_exec_type exec_type = \ 464 (enum gfx10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \ 465 inst); \ 466 unsigned hw_type = brw_inst_3src_a1_##reg##_hw_type(devinfo, inst); \ 467 return brw_a1_hw_3src_type_to_reg_type(devinfo, hw_type, exec_type); \ 468} 469 470REG_TYPE(dst) 471REG_TYPE(src0) 472REG_TYPE(src1) 473REG_TYPE(src2) 474#undef REG_TYPE 475 476/** 477 * Three-source align1 instruction immediates: 478 * @{ 479 */ 480static inline uint16_t 481brw_inst_3src_a1_src0_imm(ASSERTED const struct intel_device_info *devinfo, 482 const brw_inst *insn) 483{ 484 assert(devinfo->ver >= 10); 485 if (devinfo->ver >= 12) 486 return brw_inst_bits(insn, 79, 64); 487 else 488 return brw_inst_bits(insn, 82, 67); 489} 490 491static inline uint16_t 492brw_inst_3src_a1_src2_imm(ASSERTED const struct intel_device_info *devinfo, 493 const brw_inst *insn) 494{ 495 assert(devinfo->ver >= 10); 496 if (devinfo->ver >= 12) 497 return brw_inst_bits(insn, 127, 112); 498 else 499 return brw_inst_bits(insn, 124, 109); 500} 501 502static inline void 503brw_inst_set_3src_a1_src0_imm(ASSERTED const struct intel_device_info *devinfo, 504 brw_inst *insn, uint16_t value) 505{ 506 assert(devinfo->ver >= 10); 507 if (devinfo->ver >= 12) 508 brw_inst_set_bits(insn, 79, 64, value); 509 else 510 brw_inst_set_bits(insn, 82, 67, value); 511} 512 513static inline void 514brw_inst_set_3src_a1_src2_imm(ASSERTED const struct intel_device_info *devinfo, 515 brw_inst *insn, uint16_t value) 516{ 517 assert(devinfo->ver >= 10); 518 if (devinfo->ver >= 12) 519 brw_inst_set_bits(insn, 127, 112, value); 520 else 521 brw_inst_set_bits(insn, 124, 109, value); 522} 523/** @} */ 524 525/** 526 * Flow control instruction bits: 527 * @{ 528 */ 529static inline void 530brw_inst_set_uip(const struct intel_device_info *devinfo, 531 brw_inst *inst, int32_t value) 532{ 533 assert(devinfo->ver >= 6); 534 535 if (devinfo->ver >= 12) 536 brw_inst_set_src1_is_imm(devinfo, inst, 1); 537 538 if (devinfo->ver >= 8) { 539 brw_inst_set_bits(inst, 95, 64, (uint32_t)value); 540 } else { 541 assert(value <= (1 << 16) - 1); 542 assert(value > -(1 << 16)); 543 brw_inst_set_bits(inst, 127, 112, (uint16_t)value); 544 } 545} 546 547static inline int32_t 548brw_inst_uip(const struct intel_device_info *devinfo, const brw_inst *inst) 549{ 550 assert(devinfo->ver >= 6); 551 552 if (devinfo->ver >= 8) { 553 return brw_inst_bits(inst, 95, 64); 554 } else { 555 return (int16_t)brw_inst_bits(inst, 127, 112); 556 } 557} 558 559static inline void 560brw_inst_set_jip(const struct intel_device_info *devinfo, 561 brw_inst *inst, int32_t value) 562{ 563 assert(devinfo->ver >= 6); 564 565 if (devinfo->ver >= 12) 566 brw_inst_set_src0_is_imm(devinfo, inst, 1); 567 568 if (devinfo->ver >= 8) { 569 brw_inst_set_bits(inst, 127, 96, (uint32_t)value); 570 } else { 571 assert(value <= (1 << 15) - 1); 572 assert(value >= -(1 << 15)); 573 brw_inst_set_bits(inst, 111, 96, (uint16_t)value); 574 } 575} 576 577static inline int32_t 578brw_inst_jip(const struct intel_device_info *devinfo, const brw_inst *inst) 579{ 580 assert(devinfo->ver >= 6); 581 582 if (devinfo->ver >= 8) { 583 return brw_inst_bits(inst, 127, 96); 584 } else { 585 return (int16_t)brw_inst_bits(inst, 111, 96); 586 } 587} 588 589/** Like FC, but using int16_t to handle negative jump targets. */ 590#define FJ(name, high, low, assertions) \ 591static inline void \ 592brw_inst_set_##name(const struct intel_device_info *devinfo, brw_inst *inst, int16_t v) \ 593{ \ 594 assert(assertions); \ 595 (void) devinfo; \ 596 brw_inst_set_bits(inst, high, low, (uint16_t) v); \ 597} \ 598static inline int16_t \ 599brw_inst_##name(const struct intel_device_info *devinfo, const brw_inst *inst)\ 600{ \ 601 assert(assertions); \ 602 (void) devinfo; \ 603 return brw_inst_bits(inst, high, low); \ 604} 605 606FJ(gfx6_jump_count, 63, 48, devinfo->ver == 6) 607FJ(gfx4_jump_count, 111, 96, devinfo->ver < 6) 608FC(gfx4_pop_count, /* 4+ */ 115, 112, /* 12+ */ -1, -1, devinfo->ver < 6) 609/** @} */ 610 611/** 612 * SEND instructions: 613 * @{ 614 */ 615FC(send_ex_desc_ia_subreg_nr, /* 4+ */ 82, 80, /* 12+ */ 42, 40, devinfo->ver >= 9) 616FC(send_src0_address_mode, /* 4+ */ 79, 79, /* 12+ */ -1, -1, devinfo->ver >= 9) 617FC(send_sel_reg32_desc, /* 4+ */ 77, 77, /* 12+ */ 48, 48, devinfo->ver >= 9) 618FC(send_sel_reg32_ex_desc, /* 4+ */ 61, 61, /* 12+ */ 49, 49, devinfo->ver >= 9) 619F8(send_src0_reg_file, /* 4+ */ 38, 37, /* 8+ */ 42, 41, /* 12+ */ 66, 66) 620FC(send_src1_reg_nr, /* 4+ */ 51, 44, /* 12+ */ 111, 104, devinfo->ver >= 9) 621FC(send_src1_reg_file, /* 4+ */ 36, 36, /* 12+ */ 98, 98, devinfo->ver >= 9) 622FC(send_dst_reg_file, /* 4+ */ 35, 35, /* 12+ */ 50, 50, devinfo->ver >= 9) 623/** @} */ 624 625/* Message descriptor bits */ 626#define MD(x) ((x) + 96) 627#define MD12(x) ((x) >= 30 ? (x) - 30 + 122 : \ 628 (x) >= 25 ? (x) - 25 + 67 : \ 629 (x) >= 20 ? (x) - 20 + 51 : \ 630 (x) >= 11 ? (x) - 11 + 113 : \ 631 (x) - 0 + 81) 632 633/** 634 * Set the SEND(C) message descriptor immediate. 635 * 636 * This doesn't include the SFID nor the EOT field that were considered to be 637 * part of the message descriptor by ancient versions of the BSpec, because 638 * they are present in the instruction even if the message descriptor is 639 * provided indirectly in the address register, so we want to specify them 640 * separately. 641 */ 642static inline void 643brw_inst_set_send_desc(const struct intel_device_info *devinfo, 644 brw_inst *inst, uint32_t value) 645{ 646 if (devinfo->ver >= 12) { 647 brw_inst_set_bits(inst, 123, 122, GET_BITS(value, 31, 30)); 648 brw_inst_set_bits(inst, 71, 67, GET_BITS(value, 29, 25)); 649 brw_inst_set_bits(inst, 55, 51, GET_BITS(value, 24, 20)); 650 brw_inst_set_bits(inst, 121, 113, GET_BITS(value, 19, 11)); 651 brw_inst_set_bits(inst, 91, 81, GET_BITS(value, 10, 0)); 652 } else if (devinfo->ver >= 9) { 653 brw_inst_set_bits(inst, 126, 96, value); 654 assert(value >> 31 == 0); 655 } else if (devinfo->ver >= 5) { 656 brw_inst_set_bits(inst, 124, 96, value); 657 assert(value >> 29 == 0); 658 } else { 659 brw_inst_set_bits(inst, 119, 96, value); 660 assert(value >> 24 == 0); 661 } 662} 663 664/** 665 * Get the SEND(C) message descriptor immediate. 666 * 667 * \sa brw_inst_set_send_desc(). 668 */ 669static inline uint32_t 670brw_inst_send_desc(const struct intel_device_info *devinfo, 671 const brw_inst *inst) 672{ 673 if (devinfo->ver >= 12) { 674 return (brw_inst_bits(inst, 123, 122) << 30 | 675 brw_inst_bits(inst, 71, 67) << 25 | 676 brw_inst_bits(inst, 55, 51) << 20 | 677 brw_inst_bits(inst, 121, 113) << 11 | 678 brw_inst_bits(inst, 91, 81)); 679 } else if (devinfo->ver >= 9) { 680 return brw_inst_bits(inst, 126, 96); 681 } else if (devinfo->ver >= 5) { 682 return brw_inst_bits(inst, 124, 96); 683 } else { 684 return brw_inst_bits(inst, 119, 96); 685 } 686} 687 688/** 689 * Set the SEND(C) message extended descriptor immediate. 690 * 691 * This doesn't include the SFID nor the EOT field that were considered to be 692 * part of the extended message descriptor by some versions of the BSpec, 693 * because they are present in the instruction even if the extended message 694 * descriptor is provided indirectly in a register, so we want to specify them 695 * separately. 696 */ 697static inline void 698brw_inst_set_send_ex_desc(const struct intel_device_info *devinfo, 699 brw_inst *inst, uint32_t value) 700{ 701 if (devinfo->ver >= 12) { 702 brw_inst_set_bits(inst, 127, 124, GET_BITS(value, 31, 28)); 703 brw_inst_set_bits(inst, 97, 96, GET_BITS(value, 27, 26)); 704 brw_inst_set_bits(inst, 65, 64, GET_BITS(value, 25, 24)); 705 brw_inst_set_bits(inst, 47, 35, GET_BITS(value, 23, 11)); 706 brw_inst_set_bits(inst, 103, 99, GET_BITS(value, 10, 6)); 707 assert(GET_BITS(value, 5, 0) == 0); 708 } else { 709 assert(devinfo->ver >= 9); 710 brw_inst_set_bits(inst, 94, 91, GET_BITS(value, 31, 28)); 711 brw_inst_set_bits(inst, 88, 85, GET_BITS(value, 27, 24)); 712 brw_inst_set_bits(inst, 83, 80, GET_BITS(value, 23, 20)); 713 brw_inst_set_bits(inst, 67, 64, GET_BITS(value, 19, 16)); 714 assert(GET_BITS(value, 15, 0) == 0); 715 } 716} 717 718/** 719 * Set the SENDS(C) message extended descriptor immediate. 720 * 721 * This doesn't include the SFID nor the EOT field that were considered to be 722 * part of the extended message descriptor by some versions of the BSpec, 723 * because they are present in the instruction even if the extended message 724 * descriptor is provided indirectly in a register, so we want to specify them 725 * separately. 726 */ 727static inline void 728brw_inst_set_sends_ex_desc(const struct intel_device_info *devinfo, 729 brw_inst *inst, uint32_t value) 730{ 731 if (devinfo->ver >= 12) { 732 brw_inst_set_send_ex_desc(devinfo, inst, value); 733 } else { 734 brw_inst_set_bits(inst, 95, 80, GET_BITS(value, 31, 16)); 735 assert(GET_BITS(value, 15, 10) == 0); 736 brw_inst_set_bits(inst, 67, 64, GET_BITS(value, 9, 6)); 737 assert(GET_BITS(value, 5, 0) == 0); 738 } 739} 740 741/** 742 * Get the SEND(C) message extended descriptor immediate. 743 * 744 * \sa brw_inst_set_send_ex_desc(). 745 */ 746static inline uint32_t 747brw_inst_send_ex_desc(const struct intel_device_info *devinfo, 748 const brw_inst *inst) 749{ 750 if (devinfo->ver >= 12) { 751 return (brw_inst_bits(inst, 127, 124) << 28 | 752 brw_inst_bits(inst, 97, 96) << 26 | 753 brw_inst_bits(inst, 65, 64) << 24 | 754 brw_inst_bits(inst, 47, 35) << 11 | 755 brw_inst_bits(inst, 103, 99) << 6); 756 } else { 757 assert(devinfo->ver >= 9); 758 return (brw_inst_bits(inst, 94, 91) << 28 | 759 brw_inst_bits(inst, 88, 85) << 24 | 760 brw_inst_bits(inst, 83, 80) << 20 | 761 brw_inst_bits(inst, 67, 64) << 16); 762 } 763} 764 765/** 766 * Get the SENDS(C) message extended descriptor immediate. 767 * 768 * \sa brw_inst_set_send_ex_desc(). 769 */ 770static inline uint32_t 771brw_inst_sends_ex_desc(const struct intel_device_info *devinfo, 772 const brw_inst *inst) 773{ 774 if (devinfo->ver >= 12) { 775 return brw_inst_send_ex_desc(devinfo, inst); 776 } else { 777 return (brw_inst_bits(inst, 95, 80) << 16 | 778 brw_inst_bits(inst, 67, 64) << 6); 779 } 780} 781 782/** 783 * Fields for SEND messages: 784 * @{ 785 */ 786F(eot, /* 4+ */ 127, 127, /* 12+ */ 34, 34) 787FF(mlen, 788 /* 4: */ 119, 116, 789 /* 4.5: */ 119, 116, 790 /* 5: */ 124, 121, 791 /* 6: */ 124, 121, 792 /* 7: */ 124, 121, 793 /* 8: */ 124, 121, 794 /* 12: */ MD12(28), MD12(25)); 795FF(rlen, 796 /* 4: */ 115, 112, 797 /* 4.5: */ 115, 112, 798 /* 5: */ 120, 116, 799 /* 6: */ 120, 116, 800 /* 7: */ 120, 116, 801 /* 8: */ 120, 116, 802 /* 12: */ MD12(24), MD12(20)); 803FF(header_present, 804 /* 4: doesn't exist */ -1, -1, -1, -1, 805 /* 5: */ 115, 115, 806 /* 6: */ 115, 115, 807 /* 7: */ 115, 115, 808 /* 8: */ 115, 115, 809 /* 12: */ MD12(19), MD12(19)) 810F(gateway_notify, /* 4+ */ MD(16), MD(15), /* 12+ */ -1, -1) 811FD(function_control, 812 /* 4: */ 111, 96, 813 /* 4.5: */ 111, 96, 814 /* 5: */ 114, 96, 815 /* 6: */ 114, 96, 816 /* 7: */ 114, 96, 817 /* 8: */ 114, 96, 818 /* 12: */ MD12(18), MD12(11), MD12(10), MD12(0)) 819FF(gateway_subfuncid, 820 /* 4: */ MD(1), MD(0), 821 /* 4.5: */ MD(1), MD(0), 822 /* 5: */ MD(1), MD(0), /* 2:0, but bit 2 is reserved MBZ */ 823 /* 6: */ MD(2), MD(0), 824 /* 7: */ MD(2), MD(0), 825 /* 8: */ MD(2), MD(0), 826 /* 12: */ MD12(2), MD12(0)) 827FF(sfid, 828 /* 4: */ 123, 120, /* called msg_target */ 829 /* 4.5 */ 123, 120, 830 /* 5: */ 95, 92, 831 /* 6: */ 27, 24, 832 /* 7: */ 27, 24, 833 /* 8: */ 27, 24, 834 /* 12: */ 95, 92) 835FF(null_rt, 836 /* 4-7: */ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 837 /* 8: */ 80, 80, 838 /* 12: */ 44, 44) /* actually only Gfx11+ */ 839FC(base_mrf, /* 4+ */ 27, 24, /* 12+ */ -1, -1, devinfo->ver < 6); 840FF(send_rta_index, 841 /* 4: */ -1, -1, 842 /* 4.5 */ -1, -1, 843 /* 5: */ -1, -1, 844 /* 6: */ -1, -1, 845 /* 7: */ -1, -1, 846 /* 8: */ -1, -1, 847 /* 12: */ 38, 36) 848/** @} */ 849 850/** 851 * URB message function control bits: 852 * @{ 853 */ 854FF(urb_per_slot_offset, 855 /* 4-6: */ -1, -1, -1, -1, -1, -1, -1, -1, 856 /* 7: */ MD(16), MD(16), 857 /* 8: */ MD(17), MD(17), 858 /* 12: */ MD12(17), MD12(17)) 859FC(urb_channel_mask_present, /* 4+ */ MD(15), MD(15), /* 12+ */ MD12(15), MD12(15), devinfo->ver >= 8) 860FC(urb_complete, /* 4+ */ MD(15), MD(15), /* 12+ */ -1, -1, devinfo->ver < 8) 861FC(urb_used, /* 4+ */ MD(14), MD(14), /* 12+ */ -1, -1, devinfo->ver < 7) 862FC(urb_allocate, /* 4+ */ MD(13), MD(13), /* 12+ */ -1, -1, devinfo->ver < 7) 863FF(urb_swizzle_control, 864 /* 4: */ MD(11), MD(10), 865 /* 4.5: */ MD(11), MD(10), 866 /* 5: */ MD(11), MD(10), 867 /* 6: */ MD(11), MD(10), 868 /* 7: */ MD(14), MD(14), 869 /* 8: */ MD(15), MD(15), 870 /* 12: */ -1, -1) 871FD(urb_global_offset, 872 /* 4: */ MD( 9), MD(4), 873 /* 4.5: */ MD( 9), MD(4), 874 /* 5: */ MD( 9), MD(4), 875 /* 6: */ MD( 9), MD(4), 876 /* 7: */ MD(13), MD(3), 877 /* 8: */ MD(14), MD(4), 878 /* 12: */ MD12(14), MD12(11), MD12(10), MD12(4)) 879FF(urb_opcode, 880 /* 4: */ MD( 3), MD(0), 881 /* 4.5: */ MD( 3), MD(0), 882 /* 5: */ MD( 3), MD(0), 883 /* 6: */ MD( 3), MD(0), 884 /* 7: */ MD( 2), MD(0), 885 /* 8: */ MD( 3), MD(0), 886 /* 12: */ MD12(3), MD12(0)) 887/** @} */ 888 889/** 890 * Gfx4-5 math messages: 891 * @{ 892 */ 893FC(math_msg_data_type, /* 4+ */ MD(7), MD(7), /* 12+ */ -1, -1, devinfo->ver < 6) 894FC(math_msg_saturate, /* 4+ */ MD(6), MD(6), /* 12+ */ -1, -1, devinfo->ver < 6) 895FC(math_msg_precision, /* 4+ */ MD(5), MD(5), /* 12+ */ -1, -1, devinfo->ver < 6) 896FC(math_msg_signed_int, /* 4+ */ MD(4), MD(4), /* 12+ */ -1, -1, devinfo->ver < 6) 897FC(math_msg_function, /* 4+ */ MD(3), MD(0), /* 12+ */ -1, -1, devinfo->ver < 6) 898/** @} */ 899 900/** 901 * Sampler message function control bits: 902 * @{ 903 */ 904FF(sampler_simd_mode, 905 /* 4: doesn't exist */ -1, -1, -1, -1, 906 /* 5: */ MD(17), MD(16), 907 /* 6: */ MD(17), MD(16), 908 /* 7: */ MD(18), MD(17), 909 /* 8: */ MD(18), MD(17), 910 /* 12: */ MD12(18), MD12(17)) 911FF(sampler_msg_type, 912 /* 4: */ MD(15), MD(14), 913 /* 4.5: */ MD(15), MD(12), 914 /* 5: */ MD(15), MD(12), 915 /* 6: */ MD(15), MD(12), 916 /* 7: */ MD(16), MD(12), 917 /* 8: */ MD(16), MD(12), 918 /* 12: */ MD12(16), MD12(12)) 919FC(sampler_return_format, /* 4+ */ MD(13), MD(12), /* 12+ */ -1, -1, devinfo->ver == 4 && !devinfo->is_g4x) 920FD(sampler, 921 /* 4: */ MD(11), MD(8), 922 /* 4.5: */ MD(11), MD(8), 923 /* 5: */ MD(11), MD(8), 924 /* 6: */ MD(11), MD(8), 925 /* 7: */ MD(11), MD(8), 926 /* 8: */ MD(11), MD(8), 927 /* 12: */ MD12(11), MD12(11), MD12(10), MD12(8)) 928F(binding_table_index, /* 4+ */ MD(7), MD(0), /* 12+ */ MD12(7), MD12(0)) /* also used by other messages */ 929/** @} */ 930 931/** 932 * Data port message function control bits: 933 * @{ 934 */ 935FC(dp_category, /* 4+ */ MD(18), MD(18), /* 12+ */ MD12(18), MD12(18), devinfo->ver >= 7) 936 937/* Gfx4-5 store fields in different bits for read/write messages. */ 938FF(dp_read_msg_type, 939 /* 4: */ MD(13), MD(12), 940 /* 4.5: */ MD(13), MD(11), 941 /* 5: */ MD(13), MD(11), 942 /* 6: */ MD(16), MD(13), 943 /* 7: */ MD(17), MD(14), 944 /* 8: */ MD(17), MD(14), 945 /* 12: */ MD12(17), MD12(14)) 946FF(dp_write_msg_type, 947 /* 4: */ MD(14), MD(12), 948 /* 4.5: */ MD(14), MD(12), 949 /* 5: */ MD(14), MD(12), 950 /* 6: */ MD(16), MD(13), 951 /* 7: */ MD(17), MD(14), 952 /* 8: */ MD(17), MD(14), 953 /* 12: */ MD12(17), MD12(14)) 954FD(dp_read_msg_control, 955 /* 4: */ MD(11), MD( 8), 956 /* 4.5: */ MD(10), MD( 8), 957 /* 5: */ MD(10), MD( 8), 958 /* 6: */ MD(12), MD( 8), 959 /* 7: */ MD(13), MD( 8), 960 /* 8: */ MD(13), MD( 8), 961 /* 12: */ MD12(13), MD12(11), MD12(10), MD12(8)) 962FD(dp_write_msg_control, 963 /* 4: */ MD(11), MD( 8), 964 /* 4.5: */ MD(11), MD( 8), 965 /* 5: */ MD(11), MD( 8), 966 /* 6: */ MD(12), MD( 8), 967 /* 7: */ MD(13), MD( 8), 968 /* 8: */ MD(13), MD( 8), 969 /* 12: */ MD12(13), MD12(11), MD12(10), MD12(8)) 970FC(dp_read_target_cache, /* 4+ */ MD(15), MD(14), /* 12+ */ -1, -1, devinfo->ver < 6); 971 972FF(dp_write_commit, 973 /* 4: */ MD(15), MD(15), 974 /* 4.5: */ MD(15), MD(15), 975 /* 5: */ MD(15), MD(15), 976 /* 6: */ MD(17), MD(17), 977 /* 7+: does not exist */ -1, -1, -1, -1, 978 /* 12: */ -1, -1) 979 980/* Gfx6+ use the same bit locations for everything. */ 981FF(dp_msg_type, 982 /* 4-5: use dp_read_msg_type or dp_write_msg_type instead */ 983 -1, -1, -1, -1, -1, -1, 984 /* 6: */ MD(16), MD(13), 985 /* 7: */ MD(17), MD(14), 986 /* 8: */ MD(18), MD(14), 987 /* 12: */ MD12(18), MD12(14)) 988FD(dp_msg_control, 989 /* 4: */ MD(11), MD( 8), 990 /* 4.5-5: use dp_read_msg_control or dp_write_msg_control */ -1, -1, -1, -1, 991 /* 6: */ MD(12), MD( 8), 992 /* 7: */ MD(13), MD( 8), 993 /* 8: */ MD(13), MD( 8), 994 /* 12: */ MD12(13), MD12(11), MD12(10), MD12(8)) 995/** @} */ 996 997/** 998 * Scratch message bits (Gfx7+): 999 * @{ 1000 */ 1001FC(scratch_read_write, /* 4+ */ MD(17), MD(17), /* 12+ */ MD12(17), MD12(17), devinfo->ver >= 7) /* 0 = read, 1 = write */ 1002FC(scratch_type, /* 4+ */ MD(16), MD(16), /* 12+ */ -1, -1, devinfo->ver >= 7) /* 0 = OWord, 1 = DWord */ 1003FC(scratch_invalidate_after_read, /* 4+ */ MD(15), MD(15), /* 12+ */ MD12(15), MD12(15), devinfo->ver >= 7) 1004FC(scratch_block_size, /* 4+ */ MD(13), MD(12), /* 12+ */ MD12(13), MD12(12), devinfo->ver >= 7) 1005FD(scratch_addr_offset, 1006 /* 4: */ -1, -1, 1007 /* 4.5: */ -1, -1, 1008 /* 5: */ -1, -1, 1009 /* 6: */ -1, -1, 1010 /* 7: */ MD(11), MD(0), 1011 /* 8: */ MD(11), MD(0), 1012 /* 12: */ MD12(11), MD12(11), MD12(10), MD12(0)) 1013/** @} */ 1014 1015/** 1016 * Render Target message function control bits: 1017 * @{ 1018 */ 1019FF(rt_last, 1020 /* 4: */ MD(11), MD(11), 1021 /* 4.5: */ MD(11), MD(11), 1022 /* 5: */ MD(11), MD(11), 1023 /* 6: */ MD(12), MD(12), 1024 /* 7: */ MD(12), MD(12), 1025 /* 8: */ MD(12), MD(12), 1026 /* 12: */ MD12(12), MD12(12)) 1027FC(rt_slot_group, /* 4+ */ MD(11), MD(11), /* 12+ */ MD12(11), MD12(11), devinfo->ver >= 6) 1028F(rt_message_type, /* 4+ */ MD(10), MD( 8), /* 12+ */ MD12(10), MD12(8)) 1029/** @} */ 1030 1031/** 1032 * Thread Spawn message function control bits: 1033 * @{ 1034 */ 1035FC(ts_resource_select, /* 4+ */ MD( 4), MD( 4), /* 12+ */ -1, -1, devinfo->ver < 11) 1036FC(ts_request_type, /* 4+ */ MD( 1), MD( 1), /* 12+ */ -1, -1, devinfo->ver < 11) 1037F(ts_opcode, /* 4+ */ MD( 0), MD( 0), /* 12+ */ MD12(0), MD12(0)) 1038/** @} */ 1039 1040/** 1041 * Pixel Interpolator message function control bits: 1042 * @{ 1043 */ 1044F(pi_simd_mode, /* 4+ */ MD(16), MD(16), /* 12+ */ MD12(16), MD12(16)) 1045F(pi_nopersp, /* 4+ */ MD(14), MD(14), /* 12+ */ MD12(14), MD12(14)) 1046F(pi_message_type, /* 4+ */ MD(13), MD(12), /* 12+ */ MD12(13), MD12(12)) 1047F(pi_slot_group, /* 4+ */ MD(11), MD(11), /* 12+ */ MD12(11), MD12(11)) 1048F(pi_message_data, /* 4+ */ MD(7), MD(0), /* 12+ */ MD12(7), MD12(0)) 1049/** @} */ 1050 1051/** 1052 * Immediates: 1053 * @{ 1054 */ 1055static inline int 1056brw_inst_imm_d(const struct intel_device_info *devinfo, const brw_inst *insn) 1057{ 1058 (void) devinfo; 1059 return brw_inst_bits(insn, 127, 96); 1060} 1061 1062static inline unsigned 1063brw_inst_imm_ud(const struct intel_device_info *devinfo, const brw_inst *insn) 1064{ 1065 (void) devinfo; 1066 return brw_inst_bits(insn, 127, 96); 1067} 1068 1069static inline uint64_t 1070brw_inst_imm_uq(ASSERTED const struct intel_device_info *devinfo, 1071 const brw_inst *insn) 1072{ 1073 assert(devinfo->ver >= 8); 1074 return brw_inst_bits(insn, 127, 64); 1075} 1076 1077static inline float 1078brw_inst_imm_f(const struct intel_device_info *devinfo, const brw_inst *insn) 1079{ 1080 union { 1081 float f; 1082 uint32_t u; 1083 } ft; 1084 (void) devinfo; 1085 ft.u = brw_inst_bits(insn, 127, 96); 1086 return ft.f; 1087} 1088 1089static inline double 1090brw_inst_imm_df(const struct intel_device_info *devinfo, const brw_inst *insn) 1091{ 1092 union { 1093 double d; 1094 uint64_t u; 1095 } dt; 1096 (void) devinfo; 1097 dt.u = brw_inst_bits(insn, 127, 64); 1098 return dt.d; 1099} 1100 1101static inline void 1102brw_inst_set_imm_d(const struct intel_device_info *devinfo, 1103 brw_inst *insn, int value) 1104{ 1105 (void) devinfo; 1106 return brw_inst_set_bits(insn, 127, 96, value); 1107} 1108 1109static inline void 1110brw_inst_set_imm_ud(const struct intel_device_info *devinfo, 1111 brw_inst *insn, unsigned value) 1112{ 1113 (void) devinfo; 1114 return brw_inst_set_bits(insn, 127, 96, value); 1115} 1116 1117static inline void 1118brw_inst_set_imm_f(const struct intel_device_info *devinfo, 1119 brw_inst *insn, float value) 1120{ 1121 union { 1122 float f; 1123 uint32_t u; 1124 } ft; 1125 (void) devinfo; 1126 ft.f = value; 1127 brw_inst_set_bits(insn, 127, 96, ft.u); 1128} 1129 1130static inline void 1131brw_inst_set_imm_df(const struct intel_device_info *devinfo, 1132 brw_inst *insn, double value) 1133{ 1134 union { 1135 double d; 1136 uint64_t u; 1137 } dt; 1138 (void) devinfo; 1139 dt.d = value; 1140 1141 if (devinfo->ver >= 12) { 1142 brw_inst_set_bits(insn, 95, 64, dt.u >> 32); 1143 brw_inst_set_bits(insn, 127, 96, dt.u & 0xFFFFFFFF); 1144 } else { 1145 brw_inst_set_bits(insn, 127, 64, dt.u); 1146 } 1147} 1148 1149static inline void 1150brw_inst_set_imm_uq(const struct intel_device_info *devinfo, 1151 brw_inst *insn, uint64_t value) 1152{ 1153 (void) devinfo; 1154 if (devinfo->ver >= 12) { 1155 brw_inst_set_bits(insn, 95, 64, value >> 32); 1156 brw_inst_set_bits(insn, 127, 96, value & 0xFFFFFFFF); 1157 } else { 1158 brw_inst_set_bits(insn, 127, 64, value); 1159 } 1160} 1161 1162/** @} */ 1163 1164#define REG_TYPE(reg) \ 1165static inline void \ 1166brw_inst_set_##reg##_file_type(const struct intel_device_info *devinfo, \ 1167 brw_inst *inst, enum brw_reg_file file, \ 1168 enum brw_reg_type type) \ 1169{ \ 1170 assert(file <= BRW_IMMEDIATE_VALUE); \ 1171 unsigned hw_type = brw_reg_type_to_hw_type(devinfo, file, type); \ 1172 brw_inst_set_##reg##_reg_file(devinfo, inst, file); \ 1173 brw_inst_set_##reg##_reg_hw_type(devinfo, inst, hw_type); \ 1174} \ 1175 \ 1176static inline enum brw_reg_type \ 1177brw_inst_##reg##_type(const struct intel_device_info *devinfo, \ 1178 const brw_inst *inst) \ 1179{ \ 1180 unsigned file = __builtin_strcmp("dst", #reg) == 0 ? \ 1181 (unsigned) BRW_GENERAL_REGISTER_FILE : \ 1182 brw_inst_##reg##_reg_file(devinfo, inst); \ 1183 unsigned hw_type = brw_inst_##reg##_reg_hw_type(devinfo, inst); \ 1184 return brw_hw_type_to_reg_type(devinfo, (enum brw_reg_file)file, hw_type); \ 1185} 1186 1187REG_TYPE(dst) 1188REG_TYPE(src0) 1189REG_TYPE(src1) 1190#undef REG_TYPE 1191 1192 1193/* The AddrImm fields are split into two discontiguous sections on Gfx8+ */ 1194#define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low, \ 1195 g12_high, g12_low) \ 1196static inline void \ 1197brw_inst_set_##reg##_ia1_addr_imm(const struct \ 1198 intel_device_info *devinfo, \ 1199 brw_inst *inst, \ 1200 unsigned value) \ 1201{ \ 1202 assert((value & ~0x3ff) == 0); \ 1203 if (devinfo->ver >= 12) { \ 1204 brw_inst_set_bits(inst, g12_high, g12_low, value); \ 1205 } else if (devinfo->ver >= 8) { \ 1206 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \ 1207 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \ 1208 } else { \ 1209 brw_inst_set_bits(inst, g4_high, g4_low, value); \ 1210 } \ 1211} \ 1212static inline unsigned \ 1213brw_inst_##reg##_ia1_addr_imm(const struct intel_device_info *devinfo, \ 1214 const brw_inst *inst) \ 1215{ \ 1216 if (devinfo->ver >= 12) { \ 1217 return brw_inst_bits(inst, g12_high, g12_low); \ 1218 } else if (devinfo->ver >= 8) { \ 1219 return brw_inst_bits(inst, g8_high, g8_low) | \ 1220 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \ 1221 } else { \ 1222 return brw_inst_bits(inst, g4_high, g4_low); \ 1223 } \ 1224} 1225 1226/* AddrImm[9:0] for Align1 Indirect Addressing */ 1227/* -Gen 4- ----Gfx8---- -Gfx12- */ 1228BRW_IA1_ADDR_IMM(src1, 105, 96, 121, 104, 96, 107, 98) 1229BRW_IA1_ADDR_IMM(src0, 73, 64, 95, 72, 64, 75, 66) 1230BRW_IA1_ADDR_IMM(dst, 57, 48, 47, 56, 48, 59, 50) 1231 1232#define BRW_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \ 1233static inline void \ 1234brw_inst_set_##reg##_ia16_addr_imm(const struct \ 1235 intel_device_info *devinfo, \ 1236 brw_inst *inst, unsigned value) \ 1237{ \ 1238 assert(devinfo->ver < 12); \ 1239 assert((value & ~0x3ff) == 0); \ 1240 if (devinfo->ver >= 8) { \ 1241 assert(GET_BITS(value, 3, 0) == 0); \ 1242 brw_inst_set_bits(inst, g8_high, g8_low, GET_BITS(value, 8, 4)); \ 1243 brw_inst_set_bits(inst, g8_nine, g8_nine, GET_BITS(value, 9, 9)); \ 1244 } else { \ 1245 brw_inst_set_bits(inst, g4_high, g4_low, value); \ 1246 } \ 1247} \ 1248static inline unsigned \ 1249brw_inst_##reg##_ia16_addr_imm(const struct intel_device_info *devinfo, \ 1250 const brw_inst *inst) \ 1251{ \ 1252 assert(devinfo->ver < 12); \ 1253 if (devinfo->ver >= 8) { \ 1254 return (brw_inst_bits(inst, g8_high, g8_low) << 4) | \ 1255 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \ 1256 } else { \ 1257 return brw_inst_bits(inst, g4_high, g4_low); \ 1258 } \ 1259} 1260 1261/* AddrImm[9:0] for Align16 Indirect Addressing: 1262 * Compared to Align1, these are missing the low 4 bits. 1263 * -Gen 4- ----Gfx8---- 1264 */ 1265BRW_IA16_ADDR_IMM(src1, 105, 96, 121, 104, 100) 1266BRW_IA16_ADDR_IMM(src0, 73, 64, 95, 72, 68) 1267BRW_IA16_ADDR_IMM(dst, 57, 52, 47, 56, 52) 1268BRW_IA16_ADDR_IMM(send_src0, -1, -1, 78, 72, 68) 1269BRW_IA16_ADDR_IMM(send_dst, -1, -1, 62, 56, 52) 1270 1271/** 1272 * Fetch a set of contiguous bits from the instruction. 1273 * 1274 * Bits indices range from 0..127; fields may not cross 64-bit boundaries. 1275 */ 1276static inline uint64_t 1277brw_inst_bits(const brw_inst *inst, unsigned high, unsigned low) 1278{ 1279 assume(high < 128); 1280 assume(high >= low); 1281 /* We assume the field doesn't cross 64-bit boundaries. */ 1282 const unsigned word = high / 64; 1283 assert(word == low / 64); 1284 1285 high %= 64; 1286 low %= 64; 1287 1288 const uint64_t mask = (~0ull >> (64 - (high - low + 1))); 1289 1290 return (inst->data[word] >> low) & mask; 1291} 1292 1293/** 1294 * Set bits in the instruction, with proper shifting and masking. 1295 * 1296 * Bits indices range from 0..127; fields may not cross 64-bit boundaries. 1297 */ 1298static inline void 1299brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned low, uint64_t value) 1300{ 1301 assume(high < 128); 1302 assume(high >= low); 1303 const unsigned word = high / 64; 1304 assert(word == low / 64); 1305 1306 high %= 64; 1307 low %= 64; 1308 1309 const uint64_t mask = (~0ull >> (64 - (high - low + 1))) << low; 1310 1311 /* Make sure the supplied value actually fits in the given bitfield. */ 1312 assert((value & (mask >> low)) == value); 1313 1314 inst->data[word] = (inst->data[word] & ~mask) | (value << low); 1315} 1316 1317#undef BRW_IA16_ADDR_IMM 1318#undef BRW_IA1_ADDR_IMM 1319#undef MD 1320#undef F8 1321#undef FF 1322#undef BOUNDS 1323#undef F 1324#undef FC 1325 1326typedef struct { 1327 uint64_t data; 1328} brw_compact_inst; 1329 1330/** 1331 * Fetch a set of contiguous bits from the compacted instruction. 1332 * 1333 * Bits indices range from 0..63. 1334 */ 1335static inline unsigned 1336brw_compact_inst_bits(const brw_compact_inst *inst, unsigned high, unsigned low) 1337{ 1338 const uint64_t mask = (1ull << (high - low + 1)) - 1; 1339 1340 return (inst->data >> low) & mask; 1341} 1342 1343/** 1344 * Set bits in the compacted instruction. 1345 * 1346 * Bits indices range from 0..63. 1347 */ 1348static inline void 1349brw_compact_inst_set_bits(brw_compact_inst *inst, unsigned high, unsigned low, 1350 uint64_t value) 1351{ 1352 const uint64_t mask = ((1ull << (high - low + 1)) - 1) << low; 1353 1354 /* Make sure the supplied value actually fits in the given bitfield. */ 1355 assert((value & (mask >> low)) == value); 1356 1357 inst->data = (inst->data & ~mask) | (value << low); 1358} 1359 1360#define FC(name, high, low, gfx12_high, gfx12_low, assertions) \ 1361static inline void \ 1362brw_compact_inst_set_##name(const struct \ 1363 intel_device_info *devinfo, \ 1364 brw_compact_inst *inst, unsigned v) \ 1365{ \ 1366 assert(assertions); \ 1367 if (devinfo->ver >= 12) \ 1368 brw_compact_inst_set_bits(inst, gfx12_high, gfx12_low, v); \ 1369 else \ 1370 brw_compact_inst_set_bits(inst, high, low, v); \ 1371} \ 1372static inline unsigned \ 1373brw_compact_inst_##name(const struct intel_device_info *devinfo, \ 1374 const brw_compact_inst *inst) \ 1375{ \ 1376 assert(assertions); \ 1377 if (devinfo->ver >= 12) \ 1378 return brw_compact_inst_bits(inst, gfx12_high, gfx12_low); \ 1379 else \ 1380 return brw_compact_inst_bits(inst, high, low); \ 1381} 1382 1383/* A simple macro for fields which stay in the same place on all generations 1384 * except for Gfx12. 1385 */ 1386#define F(name, high, low, gfx12_high, gfx12_low) \ 1387 FC(name, high, low, gfx12_high, gfx12_low, true) 1388 1389F(src1_reg_nr, /* 4+ */ 63, 56, /* 12+ */ 63, 56) 1390F(src0_reg_nr, /* 4+ */ 55, 48, /* 12+ */ 47, 40) 1391F(dst_reg_nr, /* 4+ */ 47, 40, /* 12+ */ 23, 16) 1392F(src1_index, /* 4+ */ 39, 35, /* 12+ */ 55, 52) 1393F(src0_index, /* 4+ */ 34, 30, /* 12+ */ 51, 48) 1394F(cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29) /* Same location as brw_inst */ 1395FC(flag_subreg_nr, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo->ver <= 6) 1396F(cond_modifier, /* 4+ */ 27, 24, /* 12+ */ -1, -1) /* Same location as brw_inst */ 1397FC(acc_wr_control, /* 4+ */ 23, 23, /* 12+ */ -1, -1, devinfo->ver >= 6) 1398FC(mask_control_ex, /* 4+ */ 23, 23, /* 12+ */ -1, -1, devinfo->is_g4x || devinfo->ver == 5) 1399F(subreg_index, /* 4+ */ 22, 18, /* 12+ */ 39, 35) 1400F(datatype_index, /* 4+ */ 17, 13, /* 12+ */ 34, 30) 1401F(control_index, /* 4+ */ 12, 8, /* 12+ */ 28, 24) 1402FC(swsb, /* 4+ */ -1, -1, /* 12+ */ 15, 8, devinfo->ver >= 12) 1403F(debug_control, /* 4+ */ 7, 7, /* 12+ */ 7, 7) 1404F(hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0) /* Same location as brw_inst */ 1405 1406static inline unsigned 1407brw_compact_inst_imm(const struct intel_device_info *devinfo, 1408 const brw_compact_inst *inst) 1409{ 1410 if (devinfo->ver >= 12) { 1411 return brw_compact_inst_bits(inst, 63, 52); 1412 } else { 1413 return (brw_compact_inst_bits(inst, 39, 35) << 8) | 1414 (brw_compact_inst_bits(inst, 63, 56)); 1415 } 1416} 1417 1418/** 1419 * (Gfx8+) Compacted three-source instructions: 1420 * @{ 1421 */ 1422FC(3src_src2_reg_nr, /* 4+ */ 63, 57, /* 12+ */ 55, 48, devinfo->ver >= 8) 1423FC(3src_src1_reg_nr, /* 4+ */ 56, 50, /* 12+ */ 63, 56, devinfo->ver >= 8) 1424FC(3src_src0_reg_nr, /* 4+ */ 49, 43, /* 12+ */ 47, 40, devinfo->ver >= 8) 1425FC(3src_src2_subreg_nr, /* 4+ */ 42, 40, /* 12+ */ -1, -1, devinfo->ver >= 8) 1426FC(3src_src1_subreg_nr, /* 4+ */ 39, 37, /* 12+ */ -1, -1, devinfo->ver >= 8) 1427FC(3src_src0_subreg_nr, /* 4+ */ 36, 34, /* 12+ */ -1, -1, devinfo->ver >= 8) 1428FC(3src_src2_rep_ctrl, /* 4+ */ 33, 33, /* 12+ */ -1, -1, devinfo->ver >= 8) 1429FC(3src_src1_rep_ctrl, /* 4+ */ 32, 32, /* 12+ */ -1, -1, devinfo->ver >= 8) 1430FC(3src_saturate, /* 4+ */ 31, 31, /* 12+ */ -1, -1, devinfo->ver >= 8) 1431FC(3src_debug_control, /* 4+ */ 30, 30, /* 12+ */ 7, 7, devinfo->ver >= 8) 1432FC(3src_cmpt_control, /* 4+ */ 29, 29, /* 12+ */ 29, 29, devinfo->ver >= 8) 1433FC(3src_src0_rep_ctrl, /* 4+ */ 28, 28, /* 12+ */ -1, -1, devinfo->ver >= 8) 1434/* Reserved */ 1435FC(3src_dst_reg_nr, /* 4+ */ 18, 12, /* 12+ */ 23, 16, devinfo->ver >= 8) 1436FC(3src_source_index, /* 4+ */ 11, 10, /* 12+ */ 34, 30, devinfo->ver >= 8) 1437FC(3src_subreg_index, /* 4+ */ -1, -1, /* 12+ */ 39, 35, devinfo->ver >= 12) 1438FC(3src_control_index, /* 4+ */ 9, 8, /* 12+ */ 28, 24, devinfo->ver >= 8) 1439FC(3src_swsb, /* 4+ */ -1, -1, /* 12+ */ 15, 8, devinfo->ver >= 8) 1440/* Bit 7 is Reserved (for future Opcode expansion) */ 1441FC(3src_hw_opcode, /* 4+ */ 6, 0, /* 12+ */ 6, 0, devinfo->ver >= 8) 1442/** @} */ 1443 1444#undef F 1445 1446#ifdef __cplusplus 1447} 1448#endif 1449 1450#endif 1451