1/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24
25#include "brw_vec4_vs.h"
26#include "dev/intel_debug.h"
27
28namespace brw {
29
30void
31vec4_vs_visitor::emit_prolog()
32{
33}
34
35
36void
37vec4_vs_visitor::emit_urb_write_header(int mrf)
38{
39   /* No need to do anything for VS; an implied write to this MRF will be
40    * performed by VS_OPCODE_URB_WRITE.
41    */
42   (void) mrf;
43}
44
45
46vec4_instruction *
47vec4_vs_visitor::emit_urb_write_opcode(bool complete)
48{
49   /* For VS, the URB writes end the thread. */
50   if (complete) {
51      if (INTEL_DEBUG(DEBUG_SHADER_TIME))
52         emit_shader_time_end();
53   }
54
55   vec4_instruction *inst = emit(VS_OPCODE_URB_WRITE);
56   inst->urb_write_flags = complete ?
57      BRW_URB_WRITE_EOT_COMPLETE : BRW_URB_WRITE_NO_FLAGS;
58
59   return inst;
60}
61
62
63void
64vec4_vs_visitor::emit_urb_slot(dst_reg reg, int varying)
65{
66   reg.type = BRW_REGISTER_TYPE_F;
67   output_reg[varying][0].type = reg.type;
68
69   switch (varying) {
70   case VARYING_SLOT_COL0:
71   case VARYING_SLOT_COL1:
72   case VARYING_SLOT_BFC0:
73   case VARYING_SLOT_BFC1: {
74      /* These built-in varyings are only supported in compatibility mode,
75       * and we only support GS in core profile.  So, this must be a vertex
76       * shader.
77       */
78      vec4_instruction *inst = emit_generic_urb_slot(reg, varying, 0);
79      if (inst && key->clamp_vertex_color)
80         inst->saturate = true;
81      break;
82   }
83   default:
84      return vec4_visitor::emit_urb_slot(reg, varying);
85   }
86}
87
88
89void
90vec4_vs_visitor::emit_thread_end()
91{
92   /* For VS, we always end the thread by emitting a single vertex.
93    * emit_urb_write_opcode() will take care of setting the eot flag on the
94    * SEND instruction.
95    */
96   emit_vertex();
97}
98
99
100vec4_vs_visitor::vec4_vs_visitor(const struct brw_compiler *compiler,
101                                 void *log_data,
102                                 const struct brw_vs_prog_key *key,
103                                 struct brw_vs_prog_data *vs_prog_data,
104                                 const nir_shader *shader,
105                                 void *mem_ctx,
106                                 int shader_time_index,
107                                 bool debug_enabled)
108   : vec4_visitor(compiler, log_data, &key->base.tex, &vs_prog_data->base,
109                  shader, mem_ctx, false /* no_spills */, shader_time_index,
110                  debug_enabled),
111     key(key),
112     vs_prog_data(vs_prog_data)
113{
114}
115
116
117} /* namespace brw */
118