101e04c3fSmrg/*
201e04c3fSmrg * Copyright 2017 Intel Corporation
301e04c3fSmrg *
401e04c3fSmrg *  Permission is hereby granted, free of charge, to any person obtaining a
501e04c3fSmrg *  copy of this software and associated documentation files (the "Software"),
601e04c3fSmrg *  to deal in the Software without restriction, including without limitation
701e04c3fSmrg *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
801e04c3fSmrg *  and/or sell copies of the Software, and to permit persons to whom the
901e04c3fSmrg *  Software is furnished to do so, subject to the following conditions:
1001e04c3fSmrg *
1101e04c3fSmrg *  The above copyright notice and this permission notice (including the next
1201e04c3fSmrg *  paragraph) shall be included in all copies or substantial portions of the
1301e04c3fSmrg *  Software.
1401e04c3fSmrg *
1501e04c3fSmrg *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1601e04c3fSmrg *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1701e04c3fSmrg *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
1801e04c3fSmrg *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
1901e04c3fSmrg *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2001e04c3fSmrg *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
2101e04c3fSmrg *  IN THE SOFTWARE.
2201e04c3fSmrg */
2301e04c3fSmrg
2401e04c3fSmrg#include <assert.h>
2501e04c3fSmrg#include <stdlib.h>
2601e04c3fSmrg
279f464c52Smaya#include "drm-uapi/drm_fourcc.h"
289f464c52Smaya#include "drm-uapi/i915_drm.h"
2901e04c3fSmrg
3001e04c3fSmrg#include "isl.h"
317ec681f3Smrg#include "dev/intel_device_info.h"
327ec681f3Smrg#include "dev/intel_debug.h"
3301e04c3fSmrg
3401e04c3fSmrguint32_t
3501e04c3fSmrgisl_tiling_to_i915_tiling(enum isl_tiling tiling)
3601e04c3fSmrg{
3701e04c3fSmrg   switch (tiling) {
3801e04c3fSmrg   case ISL_TILING_LINEAR:
3901e04c3fSmrg      return I915_TILING_NONE;
4001e04c3fSmrg
4101e04c3fSmrg   case ISL_TILING_X:
4201e04c3fSmrg      return I915_TILING_X;
4301e04c3fSmrg
4401e04c3fSmrg   case ISL_TILING_Y0:
457ec681f3Smrg   case ISL_TILING_HIZ:
467ec681f3Smrg   case ISL_TILING_CCS:
4701e04c3fSmrg      return I915_TILING_Y;
4801e04c3fSmrg
4901e04c3fSmrg   case ISL_TILING_W:
5001e04c3fSmrg   case ISL_TILING_Yf:
5101e04c3fSmrg   case ISL_TILING_Ys:
527ec681f3Smrg   case ISL_TILING_4:
537ec681f3Smrg   case ISL_TILING_64:
547ec681f3Smrg   case ISL_TILING_GFX12_CCS:
5501e04c3fSmrg      return I915_TILING_NONE;
5601e04c3fSmrg   }
5701e04c3fSmrg
5801e04c3fSmrg   unreachable("Invalid ISL tiling");
5901e04c3fSmrg}
6001e04c3fSmrg
6101e04c3fSmrgenum isl_tiling
6201e04c3fSmrgisl_tiling_from_i915_tiling(uint32_t tiling)
6301e04c3fSmrg{
6401e04c3fSmrg   switch (tiling) {
6501e04c3fSmrg   case I915_TILING_NONE:
6601e04c3fSmrg      return ISL_TILING_LINEAR;
6701e04c3fSmrg
6801e04c3fSmrg   case I915_TILING_X:
6901e04c3fSmrg      return ISL_TILING_X;
7001e04c3fSmrg
7101e04c3fSmrg   case I915_TILING_Y:
7201e04c3fSmrg      return ISL_TILING_Y0;
7301e04c3fSmrg   }
7401e04c3fSmrg
7501e04c3fSmrg   unreachable("Invalid i915 tiling");
7601e04c3fSmrg}
7701e04c3fSmrg
787ec681f3Smrg/** Sentinel is DRM_FORMAT_MOD_INVALID. */
797ec681f3Smrgconst struct isl_drm_modifier_info
807ec681f3Smrgisl_drm_modifier_info_list[] = {
8101e04c3fSmrg   {
8201e04c3fSmrg      .modifier = DRM_FORMAT_MOD_NONE,
8301e04c3fSmrg      .name = "DRM_FORMAT_MOD_NONE",
8401e04c3fSmrg      .tiling = ISL_TILING_LINEAR,
8501e04c3fSmrg   },
8601e04c3fSmrg   {
8701e04c3fSmrg      .modifier = I915_FORMAT_MOD_X_TILED,
8801e04c3fSmrg      .name = "I915_FORMAT_MOD_X_TILED",
8901e04c3fSmrg      .tiling = ISL_TILING_X,
9001e04c3fSmrg   },
9101e04c3fSmrg   {
9201e04c3fSmrg      .modifier = I915_FORMAT_MOD_Y_TILED,
9301e04c3fSmrg      .name = "I915_FORMAT_MOD_Y_TILED",
9401e04c3fSmrg      .tiling = ISL_TILING_Y0,
9501e04c3fSmrg   },
9601e04c3fSmrg   {
9701e04c3fSmrg      .modifier = I915_FORMAT_MOD_Y_TILED_CCS,
9801e04c3fSmrg      .name = "I915_FORMAT_MOD_Y_TILED_CCS",
9901e04c3fSmrg      .tiling = ISL_TILING_Y0,
10001e04c3fSmrg      .aux_usage = ISL_AUX_USAGE_CCS_E,
10101e04c3fSmrg      .supports_clear_color = false,
10201e04c3fSmrg   },
1037ec681f3Smrg   {
1047ec681f3Smrg      .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
1057ec681f3Smrg      .name = "I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS",
1067ec681f3Smrg      .tiling = ISL_TILING_Y0,
1077ec681f3Smrg      .aux_usage = ISL_AUX_USAGE_GFX12_CCS_E,
1087ec681f3Smrg      .supports_clear_color = false,
1097ec681f3Smrg   },
1107ec681f3Smrg   {
1117ec681f3Smrg      .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
1127ec681f3Smrg      .name = "I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS",
1137ec681f3Smrg      .tiling = ISL_TILING_Y0,
1147ec681f3Smrg      .aux_usage = ISL_AUX_USAGE_MC,
1157ec681f3Smrg      .supports_clear_color = false,
1167ec681f3Smrg   },
1177ec681f3Smrg   {
1187ec681f3Smrg      .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
1197ec681f3Smrg      .name = "I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC",
1207ec681f3Smrg      .tiling = ISL_TILING_Y0,
1217ec681f3Smrg      .aux_usage = ISL_AUX_USAGE_GFX12_CCS_E,
1227ec681f3Smrg      .supports_clear_color = true,
1237ec681f3Smrg   },
1247ec681f3Smrg   {
1257ec681f3Smrg      .modifier = DRM_FORMAT_MOD_INVALID,
1267ec681f3Smrg   },
12701e04c3fSmrg};
12801e04c3fSmrg
12901e04c3fSmrgconst struct isl_drm_modifier_info *
13001e04c3fSmrgisl_drm_modifier_get_info(uint64_t modifier)
13101e04c3fSmrg{
1327ec681f3Smrg   isl_drm_modifier_info_for_each(info) {
1337ec681f3Smrg      if (info->modifier == modifier)
1347ec681f3Smrg         return info;
13501e04c3fSmrg   }
13601e04c3fSmrg
13701e04c3fSmrg   return NULL;
13801e04c3fSmrg}
1397ec681f3Smrg
1407ec681f3Smrguint32_t
1417ec681f3Smrgisl_drm_modifier_get_score(const struct intel_device_info *devinfo,
1427ec681f3Smrg                           uint64_t modifier)
1437ec681f3Smrg{
1447ec681f3Smrg   /* FINISHME: Add gfx12 modifiers */
1457ec681f3Smrg   switch (modifier) {
1467ec681f3Smrg   default:
1477ec681f3Smrg      return 0;
1487ec681f3Smrg   case DRM_FORMAT_MOD_LINEAR:
1497ec681f3Smrg      return 1;
1507ec681f3Smrg   case I915_FORMAT_MOD_X_TILED:
1517ec681f3Smrg      return 2;
1527ec681f3Smrg   case I915_FORMAT_MOD_Y_TILED:
1537ec681f3Smrg      /* Gfx12.5 doesn't have Y-tiling. */
1547ec681f3Smrg      if (devinfo->verx10 >= 125)
1557ec681f3Smrg         return 0;
1567ec681f3Smrg
1577ec681f3Smrg      return 3;
1587ec681f3Smrg   case I915_FORMAT_MOD_Y_TILED_CCS:
1597ec681f3Smrg      /* Gfx12's CCS layout differs from Gfx9-11. */
1607ec681f3Smrg      if (devinfo->ver >= 12)
1617ec681f3Smrg         return 0;
1627ec681f3Smrg
1637ec681f3Smrg      if (INTEL_DEBUG(DEBUG_NO_RBC))
1647ec681f3Smrg         return 0;
1657ec681f3Smrg
1667ec681f3Smrg      return 4;
1677ec681f3Smrg   }
1687ec681f3Smrg}
169