101e04c3fSmrg/* 201e04c3fSmrg * Copyright © 2018 Intel Corporation 301e04c3fSmrg * 401e04c3fSmrg * Permission is hereby granted, free of charge, to any person obtaining a 501e04c3fSmrg * copy of this software and associated documentation files (the "Software"), 601e04c3fSmrg * to deal in the Software without restriction, including without limitation 701e04c3fSmrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 801e04c3fSmrg * and/or sell copies of the Software, and to permit persons to whom the 901e04c3fSmrg * Software is furnished to do so, subject to the following conditions: 1001e04c3fSmrg * 1101e04c3fSmrg * The above copyright notice and this permission notice (including the next 1201e04c3fSmrg * paragraph) shall be included in all copies or substantial portions of the 1301e04c3fSmrg * Software. 1401e04c3fSmrg * 1501e04c3fSmrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1601e04c3fSmrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1701e04c3fSmrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1801e04c3fSmrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 1901e04c3fSmrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 2001e04c3fSmrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 2101e04c3fSmrg * IN THE SOFTWARE. 2201e04c3fSmrg * 2301e04c3fSmrg */ 2401e04c3fSmrg 2501e04c3fSmrg#ifndef INTEL_AUB_MEM 2601e04c3fSmrg#define INTEL_AUB_MEM 2701e04c3fSmrg 2801e04c3fSmrg#include <stdint.h> 2901e04c3fSmrg 3001e04c3fSmrg#include "util/list.h" 3101e04c3fSmrg#include "util/rb_tree.h" 3201e04c3fSmrg 337ec681f3Smrg#include "dev/intel_device_info.h" 347ec681f3Smrg#include "common/intel_decoder.h" 3501e04c3fSmrg 3601e04c3fSmrg#ifdef __cplusplus 3701e04c3fSmrgextern "C" { 3801e04c3fSmrg#endif 3901e04c3fSmrg 4001e04c3fSmrgstruct aub_mem { 4101e04c3fSmrg uint64_t pml4; 4201e04c3fSmrg 4301e04c3fSmrg int mem_fd; 4401e04c3fSmrg off_t mem_fd_len; 4501e04c3fSmrg 4601e04c3fSmrg struct list_head maps; 4701e04c3fSmrg struct rb_tree ggtt; 4801e04c3fSmrg struct rb_tree mem; 4901e04c3fSmrg}; 5001e04c3fSmrg 5101e04c3fSmrgbool aub_mem_init(struct aub_mem *mem); 5201e04c3fSmrgvoid aub_mem_fini(struct aub_mem *mem); 5301e04c3fSmrg 5401e04c3fSmrgvoid aub_mem_clear_bo_maps(struct aub_mem *mem); 5501e04c3fSmrg 5601e04c3fSmrgvoid aub_mem_phys_write(void *mem, uint64_t virt_address, 5701e04c3fSmrg const void *data, uint32_t size); 5801e04c3fSmrgvoid aub_mem_ggtt_write(void *mem, uint64_t virt_address, 5901e04c3fSmrg const void *data, uint32_t size); 6001e04c3fSmrgvoid aub_mem_ggtt_entry_write(void *mem, uint64_t virt_address, 6101e04c3fSmrg const void *data, uint32_t size); 6201e04c3fSmrgvoid aub_mem_local_write(void *mem, uint64_t virt_address, 6301e04c3fSmrg const void *data, uint32_t size); 6401e04c3fSmrg 657ec681f3Smrgstruct intel_batch_decode_bo aub_mem_get_ggtt_bo(void *mem, uint64_t address); 667ec681f3Smrgstruct intel_batch_decode_bo aub_mem_get_ppgtt_bo(void *mem, uint64_t address); 6701e04c3fSmrg 687ec681f3Smrgstruct intel_batch_decode_bo aub_mem_get_phys_addr_data(struct aub_mem *mem, uint64_t phys_addr); 697ec681f3Smrgstruct intel_batch_decode_bo aub_mem_get_ppgtt_addr_data(struct aub_mem *mem, uint64_t virt_addr); 7001e04c3fSmrg 717ec681f3Smrgstruct intel_batch_decode_bo aub_mem_get_ppgtt_addr_aub_data(struct aub_mem *mem, uint64_t virt_addr); 7201e04c3fSmrg 7301e04c3fSmrg 7401e04c3fSmrg#ifdef __cplusplus 7501e04c3fSmrg} 7601e04c3fSmrg#endif 7701e04c3fSmrg 7801e04c3fSmrg#endif /* INTEL_AUB_MEM */ 79