1/* 2 * Copyright © 2018 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24#ifndef GFX10_CONTEXT_H 25#define GFX10_CONTEXT_H 26 27static inline void gfx10_render_context_init(const struct intel_context_parameters *params, 28 uint32_t *data, uint32_t *size) 29{ 30 *size = CONTEXT_RENDER_SIZE; 31 if (!data) 32 return; 33 34 *data++ = 0; /* MI_NOOP */ 35 MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED, 36 0x2244 /* CONTEXT_CONTROL */, 0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */, 37 0x2034 /* RING_HEAD */, 0, 38 0x2030 /* RING_TAIL */, 0, 39 0x2038 /* RING_BUFFER_START */, params->ring_addr, 40 0x203C /* RING_BUFFER_CONTROL */, (params->ring_size - 4096) | 1 /* Buffer Length | Ring Buffer Enable */, 41 0x2168 /* BB_HEAD_U */, 0, 42 0x2140 /* BB_HEAD_L */, 0, 43 0x2110 /* BB_STATE */, 0, 44 0x211C /* SECOND_BB_HEAD_U */, 0, 45 0x2114 /* SECOND_BB_HEAD_L */, 0, 46 0x2118 /* SECOND_BB_STATE */, 0, 47 0x21C0 /* BB_PER_CTX_PTR */, 0, 48 0x21C4 /* RCS_INDIRECT_CTX */, 0, 49 0x21C8 /* RCS_INDIRECT_CTX_OFFSET */, 0, 50 0x2180 /* CCID */, 0); 51 *data++ = 0; /* MI_NOOP */ 52 53 MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED, 54 0x23A8 /* CTX_TIMESTAMP */, 0, 55 0x228C /* PDP3_UDW */, 0, 56 0x2288 /* PDP3_LDW */, 0, 57 0x2284 /* PDP2_UDW */, 0, 58 0x2280 /* PDP2_LDW */, 0, 59 0x227C /* PDP1_UDW */, 0, 60 0x2278 /* PDP1_LDW */, 0, 61 0x2274 /* PDP0_UDW */, params->pml4_addr >> 32, 62 0x2270 /* PDP0_LDW */, params->pml4_addr & 0xffffffff); 63 for (int i = 0; i < 12; i++) 64 *data++ = 0; /* MI_NOOP */ 65 66 *data++ = 0; /* MI_NOOP */ 67 MI_LOAD_REGISTER_IMM_vals(data, 0, 68 0x20C8 /* R_PWR_CLK_STATE */, 0x7FFFFFFF, 69 0, /* GPGPU_CSR_BASE_ADDRESS ? */ 0); 70 *data++ = 0; /* MI_NOOP */ 71 72 for (int i = 0; i < 9; i++) 73 *data++ = 0; 74 75 *data++ = MI_BATCH_BUFFER_END | 1 /* End Context */; 76} 77 78static inline void gfx10_blitter_context_init(const struct intel_context_parameters *params, 79 uint32_t *data, uint32_t *size) 80{ 81 *size = CONTEXT_OTHER_SIZE; 82 if (!data) 83 return; 84 85 *data++ = 0 /* MI_NOOP */; 86 MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED, 87 0x22244 /* CONTEXT_CONTROL */, 0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */, 88 0x22034 /* RING_HEAD */, 0, 89 0x22030 /* RING_TAIL */, 0, 90 0x22038 /* RING_BUFFER_START */, params->ring_addr, 91 0x2203C /* RING_BUFFER_CONTROL */, (params->ring_size - 4096) | 1 /* Buffer Length | Ring Buffer Enable */, 92 0x22168 /* BB_HEAD_U */, 0, 93 0x22140 /* BB_HEAD_L */, 0, 94 0x22110 /* BB_STATE */, 0, 95 0x2211C /* SECOND_BB_HEAD_U */, 0, 96 0x22114 /* SECOND_BB_HEAD_L */, 0, 97 0x22118 /* SECOND_BB_STATE */, 0, 98 0x221C0 /* BB_PER_CTX_PTR */, 0, 99 0x221C4 /* INDIRECT_CTX */, 0, 100 0x221C8 /* INDIRECT_CTX_OFFSET */, 0); 101 *data++ = 0 /* MI_NOOP */; 102 *data++ = 0 /* MI_NOOP */; 103 104 *data++ = 0 /* MI_NOOP */; 105 MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED, 106 0x223A8 /* CTX_TIMESTAMP */, 0, 107 0x2228C /* PDP3_UDW */, 0, 108 0x22288 /* PDP3_LDW */, 0, 109 0x22284 /* PDP2_UDW */, 0, 110 0x22280 /* PDP2_LDW */, 0, 111 0x2227C /* PDP1_UDW */, 0, 112 0x22278 /* PDP1_LDW */, 0, 113 0x22274 /* PDP0_UDW */, params->pml4_addr >> 32, 114 0x22270 /* PDP0_LDW */, params->pml4_addr & 0xffffffff); 115 for (int i = 0; i < 13; i++) 116 *data++ = 0 /* MI_NOOP */; 117 118 MI_LOAD_REGISTER_IMM_vals(data, 0, 119 0x22200 /* BCS_SWCTRL */, 0); 120 121 for (int i = 0; i < 12; i++) 122 *data++ = 0 /* MI_NOOP */; 123 124 125 *data++ = MI_BATCH_BUFFER_END | 1 /* End Context */; 126} 127 128static inline void gfx10_video_context_init(const struct intel_context_parameters *params, 129 uint32_t *data, uint32_t *size) 130{ 131 *size = CONTEXT_OTHER_SIZE; 132 if (!data) 133 return; 134 135 *data++ = 0 /* MI_NOOP */; 136 MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED, 137 0x1C244 /* CONTEXT_CONTROL */, 0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */, 138 0x1C034 /* RING_HEAD */, 0, 139 0x1C030 /* RING_TAIL */, 0, 140 0x1C038 /* RING_BUFFER_START */, params->ring_addr, 141 0x1C03C /* RING_BUFFER_CONTROL */, (params->ring_size - 4096) | 1 /* Buffer Length | Ring Buffer Enable */, 142 0x1C168 /* BB_HEAD_U */, 0, 143 0x1C140 /* BB_HEAD_L */, 0, 144 0x1C110 /* BB_STATE */, 0, 145 0x1C11C /* SECOND_BB_HEAD_U */, 0, 146 0x1C114 /* SECOND_BB_HEAD_L */, 0, 147 0x1C118 /* SECOND_BB_STATE */, 0); 148 for (int i = 0; i < 8; i++) 149 *data++ = 0 /* MI_NOOP */; 150 151 *data++ = 0 /* MI_NOOP */; 152 MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED, 153 0x1C3A8 /* CTX_TIMESTAMP */, 0, 154 0x1C28C /* PDP3_UDW */, 0, 155 0x1C288 /* PDP3_LDW */, 0, 156 0x1C284 /* PDP2_UDW */, 0, 157 0x1C280 /* PDP2_LDW */, 0, 158 0x1C27C /* PDP1_UDW */, 0, 159 0x1C278 /* PDP1_LDW */, 0, 160 0x1C274 /* PDP0_UDW */, params->pml4_addr >> 32, 161 0x1C270 /* PDP0_LDW */, params->pml4_addr & 0xffffffff); 162 for (int i = 0; i < 12; i++) 163 *data++ = 0 /* MI_NOOP */; 164 165 *data++ = MI_BATCH_BUFFER_END | 1 /* End Context */; 166} 167 168#endif /* GFX10_CONTEXT_H */ 169