1/*
2 * Copyright 2003 VMware, Inc.
3 * Copyright 2009, 2012 Intel Corporation.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 */
26
27#include "main/mtypes.h"
28#include "main/condrender.h"
29#include "swrast/swrast.h"
30#include "drivers/common/meta.h"
31
32#include "brw_batch.h"
33#include "brw_fbo.h"
34#include "brw_mipmap_tree.h"
35
36#include "brw_context.h"
37#include "brw_blorp.h"
38#include "brw_defines.h"
39
40#define FILE_DEBUG_FLAG DEBUG_BLIT
41
42static const char *buffer_names[] = {
43   [BUFFER_FRONT_LEFT] = "front",
44   [BUFFER_BACK_LEFT] = "back",
45   [BUFFER_FRONT_RIGHT] = "front right",
46   [BUFFER_BACK_RIGHT] = "back right",
47   [BUFFER_DEPTH] = "depth",
48   [BUFFER_STENCIL] = "stencil",
49   [BUFFER_ACCUM] = "accum",
50   [BUFFER_COLOR0] = "color0",
51   [BUFFER_COLOR1] = "color1",
52   [BUFFER_COLOR2] = "color2",
53   [BUFFER_COLOR3] = "color3",
54   [BUFFER_COLOR4] = "color4",
55   [BUFFER_COLOR5] = "color5",
56   [BUFFER_COLOR6] = "color6",
57   [BUFFER_COLOR7] = "color7",
58};
59
60static void
61debug_mask(const char *name, GLbitfield mask)
62{
63   GLuint i;
64
65   if (INTEL_DEBUG(DEBUG_BLIT)) {
66      DBG("%s clear:", name);
67      for (i = 0; i < BUFFER_COUNT; i++) {
68         if (mask & (1 << i))
69            DBG(" %s", buffer_names[i]);
70      }
71      DBG("\n");
72   }
73}
74
75/**
76 * Returns true if the scissor is a noop (cuts out nothing).
77 */
78static bool
79noop_scissor(struct gl_framebuffer *fb)
80{
81   return fb->_Xmin <= 0 &&
82          fb->_Ymin <= 0 &&
83          fb->_Xmax >= fb->Width &&
84          fb->_Ymax >= fb->Height;
85}
86
87/**
88 * Implements fast depth clears on gfx6+.
89 *
90 * Fast clears basically work by setting a flag in each of the subspans
91 * represented in the HiZ buffer that says "When you need the depth values for
92 * this subspan, it's the hardware's current clear value."  Then later rendering
93 * can just use the static clear value instead of referencing memory.
94 *
95 * The tricky part of the implementation is that you have to have the clear
96 * value that was used on the depth buffer in place for all further rendering,
97 * at least until a resolve to the real depth buffer happens.
98 */
99static bool
100brw_fast_clear_depth(struct gl_context *ctx)
101{
102   struct brw_context *brw = brw_context(ctx);
103   struct gl_framebuffer *fb = ctx->DrawBuffer;
104   struct brw_renderbuffer *depth_irb =
105      brw_get_renderbuffer(fb, BUFFER_DEPTH);
106   struct brw_mipmap_tree *mt = depth_irb->mt;
107   struct gl_renderbuffer_attachment *depth_att = &fb->Attachment[BUFFER_DEPTH];
108   const struct intel_device_info *devinfo = &brw->screen->devinfo;
109
110   if (INTEL_DEBUG(DEBUG_NO_FAST_CLEAR))
111      return false;
112
113   if (devinfo->ver < 6)
114      return false;
115
116   if (!brw_renderbuffer_has_hiz(depth_irb))
117      return false;
118
119   /* We only handle full buffer clears -- otherwise you'd have to track whether
120    * a previous clear had happened at a different clear value and resolve it
121    * first.
122    */
123   if ((ctx->Scissor.EnableFlags & 1) && !noop_scissor(fb)) {
124      perf_debug("Failed to fast clear %dx%d depth because of scissors.  "
125                 "Possible 5%% performance win if avoided.\n",
126                 mt->surf.logical_level0_px.width,
127                 mt->surf.logical_level0_px.height);
128      return false;
129   }
130
131   switch (mt->format) {
132   case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
133   case MESA_FORMAT_Z24_UNORM_S8_UINT:
134      /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
135       *
136       *     "[DevSNB+]: Several cases exist where Depth Buffer Clear cannot be
137       *      enabled (the legacy method of clearing must be performed):
138       *
139       *      - If the depth buffer format is D32_FLOAT_S8X24_UINT or
140       *        D24_UNORM_S8_UINT.
141       */
142      return false;
143
144   case MESA_FORMAT_Z_UNORM16:
145      /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
146       *
147       *     "[DevSNB+]: Several cases exist where Depth Buffer Clear cannot be
148       *      enabled (the legacy method of clearing must be performed):
149       *
150       *      - DevSNB{W/A}]: When depth buffer format is D16_UNORM and the
151       *        width of the map (LOD0) is not multiple of 16, fast clear
152       *        optimization must be disabled.
153       */
154      if (devinfo->ver == 6 &&
155          (minify(mt->surf.phys_level0_sa.width,
156                  depth_irb->mt_level - mt->first_level) % 16) != 0)
157         return false;
158      break;
159
160   default:
161      break;
162   }
163
164   /* Quantize the clear value to what can be stored in the actual depth
165    * buffer.  This makes the following check more accurate because it now
166    * checks if the actual depth bits will match.  It also prevents us from
167    * getting a too-accurate depth value during depth testing or when sampling
168    * with HiZ enabled.
169    */
170   float clear_value =
171      mt->format == MESA_FORMAT_Z_FLOAT32 ? ctx->Depth.Clear :
172      _mesa_lroundeven(ctx->Depth.Clear * fb->_DepthMax) / (float)(fb->_DepthMax);
173
174   const uint32_t num_layers = depth_att->Layered ? depth_irb->layer_count : 1;
175
176   /* If we're clearing to a new clear value, then we need to resolve any clear
177    * flags out of the HiZ buffer into the real depth buffer.
178    */
179   if (mt->fast_clear_color.f32[0] != clear_value) {
180      for (uint32_t level = mt->first_level; level <= mt->last_level; level++) {
181         if (!brw_miptree_level_has_hiz(mt, level))
182            continue;
183
184         const unsigned level_layers = brw_get_num_logical_layers(mt, level);
185
186         for (uint32_t layer = 0; layer < level_layers; layer++) {
187            if (level == depth_irb->mt_level &&
188                layer >= depth_irb->mt_layer &&
189                layer < depth_irb->mt_layer + num_layers) {
190               /* We're going to clear this layer anyway.  Leave it alone. */
191               continue;
192            }
193
194            enum isl_aux_state aux_state =
195               brw_miptree_get_aux_state(mt, level, layer);
196
197            if (aux_state != ISL_AUX_STATE_CLEAR &&
198                aux_state != ISL_AUX_STATE_COMPRESSED_CLEAR) {
199               /* This slice doesn't have any fast-cleared bits. */
200               continue;
201            }
202
203            /* If we got here, then the level may have fast-clear bits that
204             * use the old clear value.  We need to do a depth resolve to get
205             * rid of their use of the clear value before we can change it.
206             * Fortunately, few applications ever change their depth clear
207             * value so this shouldn't happen often.
208             */
209            brw_hiz_exec(brw, mt, level, layer, 1, ISL_AUX_OP_FULL_RESOLVE);
210            brw_miptree_set_aux_state(brw, mt, level, layer, 1,
211                                        ISL_AUX_STATE_RESOLVED);
212         }
213      }
214
215      const union isl_color_value clear_color = { .f32 = {clear_value, } };
216      brw_miptree_set_clear_color(brw, mt, clear_color);
217   }
218
219   for (unsigned a = 0; a < num_layers; a++) {
220      enum isl_aux_state aux_state =
221         brw_miptree_get_aux_state(mt, depth_irb->mt_level,
222                                     depth_irb->mt_layer + a);
223
224      if (aux_state != ISL_AUX_STATE_CLEAR) {
225         brw_hiz_exec(brw, mt, depth_irb->mt_level,
226                      depth_irb->mt_layer + a, 1,
227                      ISL_AUX_OP_FAST_CLEAR);
228      }
229   }
230
231   brw_miptree_set_aux_state(brw, mt, depth_irb->mt_level,
232                               depth_irb->mt_layer, num_layers,
233                               ISL_AUX_STATE_CLEAR);
234   return true;
235}
236
237/**
238 * Called by ctx->Driver.Clear.
239 */
240static void
241brw_clear(struct gl_context *ctx, GLbitfield mask)
242{
243   struct brw_context *brw = brw_context(ctx);
244   struct gl_framebuffer *fb = ctx->DrawBuffer;
245   const struct intel_device_info *devinfo = &brw->screen->devinfo;
246   bool partial_clear = ctx->Scissor.EnableFlags && !noop_scissor(fb);
247
248   if (!_mesa_check_conditional_render(ctx))
249      return;
250
251   if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_FRONT_RIGHT)) {
252      brw->front_buffer_dirty = true;
253   }
254
255   brw_prepare_render(brw);
256   brw_workaround_depthstencil_alignment(brw, partial_clear ? 0 : mask);
257
258   if (mask & BUFFER_BIT_DEPTH) {
259      if (brw_fast_clear_depth(ctx)) {
260         DBG("fast clear: depth\n");
261         mask &= ~BUFFER_BIT_DEPTH;
262      }
263   }
264
265   if (mask & BUFFER_BITS_COLOR) {
266      brw_blorp_clear_color(brw, fb, mask, partial_clear,
267                            ctx->Color.sRGBEnabled);
268      debug_mask("blorp color", mask & BUFFER_BITS_COLOR);
269      mask &= ~BUFFER_BITS_COLOR;
270   }
271
272   if (devinfo->ver >= 6 && (mask & BUFFER_BITS_DEPTH_STENCIL)) {
273      brw_blorp_clear_depth_stencil(brw, fb, mask, partial_clear);
274      debug_mask("blorp depth/stencil", mask & BUFFER_BITS_DEPTH_STENCIL);
275      mask &= ~BUFFER_BITS_DEPTH_STENCIL;
276   }
277
278   GLbitfield tri_mask = mask & (BUFFER_BIT_STENCIL |
279                                 BUFFER_BIT_DEPTH);
280
281   if (tri_mask) {
282      debug_mask("tri", tri_mask);
283      mask &= ~tri_mask;
284      _mesa_meta_glsl_Clear(&brw->ctx, tri_mask);
285   }
286
287   /* Any strange buffers get passed off to swrast.  The only thing that
288    * should be left at this point is the accumulation buffer.
289    */
290   assert((mask & ~BUFFER_BIT_ACCUM) == 0);
291   if (mask) {
292      debug_mask("swrast", mask);
293      _swrast_Clear(ctx, mask);
294   }
295}
296
297
298void
299brw_init_clear_functions(struct dd_function_table *functions)
300{
301   functions->Clear = brw_clear;
302}
303