1<!-- 2 Copyright (C) 2021 Collabora Ltd. 3 4 Permission is hereby granted, free of charge, to any person obtaining a 5 copy of this software and associated documentation files (the "Software"), 6 to deal in the Software without restriction, including without limitation 7 the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 and/or sell copies of the Software, and to permit persons to whom the 9 Software is furnished to do so, subject to the following conditions: 10 11 The above copyright notice and this permission notice (including the next 12 paragraph) shall be included in all copies or substantial portions of the 13 Software. 14 15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 SOFTWARE. 22--> 23 24<valhall> 25 <lut name="Immediates"> 26 <desc> 27 This immediates are accessible in (almost) any instruction, provided the 28 immediate mode is kept to the default. They optimize for the most common 29 immediate values; any immediate listed here may be used without taking up 30 a uniform slot or a register. Most integer instructions can access 31 separate half-words and individual bytes via swizzles on the source. 32 </desc> 33 <constant desc="Zero">0x00000000</constant> 34 <constant desc="All ones; integer $-1$">0xFFFFFFFF</constant> 35 <constant desc="Maximum integer; floating-point NaN">0x7FFFFFFF</constant> 36 <constant desc="Integers $(-2, -3, -4, -5)$">0xFAFCFDFE</constant> 37 <constant desc="16-bit integer $2^8$">0x01000000</constant> 38 <constant desc="Multiples of 16 $(0, 32, 0, 128)$">0x80002000</constant> 39 <constant desc="Multiples of 16 $(48, 80, 96, 112)$">0x70605030</constant> 40 <constant desc="Multiples of 16 $(144, 160, 176, 192)$">0xC0B0A090</constant> 41 <constant desc="Integers $(0, 1, 2, 3)$">0x03020100</constant> 42 <constant desc="Integers $(4, 5, 6, 7)$">0x07060504</constant> 43 <constant desc="Integers $(8, 9, 10, 11)$">0x0B0A0908</constant> 44 <constant desc="Integers $(12, 13, 14, 15)$">0x0F0E0D0C</constant> 45 <constant desc="Integers $(16, 17, 18, 19)$">0x13121110</constant> 46 <constant desc="Integers $(20, 21, 22, 23)$">0x17161514</constant> 47 <constant desc="Integers $(24, 25, 26, 27)$">0x1B1A1918</constant> 48 <constant desc="Integers $(28, 29, 30, 31)$">0x1F1E1D1C</constant> 49 <constant desc="Float $1.0$">0x3F800000</constant> 50 <constant desc="Float $0.1$">0x3DCCCCCD</constant> 51 <constant desc="Float $1 / \pi$">0x3EA2F983</constant> 52 <constant desc="Float $\log(2)$">0x3F317218</constant> 53 <constant desc="Float $\pi$">0x40490FDB</constant> 54 <constant desc="Float $0.0$">0x00000000</constant> 55 <constant desc="Float $65535.0 = 2^{16} - 1$">0x477FFF00</constant> 56 <constant desc="Half-float $(255.0, 256.0) = (2^8 - 1, 2^8)$">0x5C005BF8</constant> 57 <constant desc="Half-float $0.1 = 1 / 10$">0x2E660000</constant> 58 <constant desc="Half-float $0.25 = 2^{-2}$">0x34000000</constant> 59 <constant desc="Half-float $0.5 = 2^{-1}$">0x38000000</constant> 60 <constant desc="Half-float $1.0 = 2^0$">0x3C000000</constant> 61 <constant desc="Half-float $2.0 = 2^1$">0x40000000</constant> 62 <constant desc="Half-float $4.0 = 2^2$">0x44000000</constant> 63 <constant desc="Half-float $8.0 = 2^3$">0x48000000</constant> 64 <constant desc="Half-float $\pi$">0x42480000</constant> 65 </lut> 66 67 <enum name="Action"> 68 <desc> 69 Every Valhall instruction can perform an action, like wait on dependency 70 slots. A few special actions are available, specified in the instruction 71 metadata from this enum. The `wait0126` action is required to wait on 72 dependency slot #6 and should be set on the instruction immediately 73 preceding `ATEST`. The `barrier` action may be set on any instruction for 74 subgroup barriers, and should particularly be set with the `BARRIER` 75 instruction for global barriers. The `td` action only applies to fragment 76 shaders and is used to terminate helper invocations, it should be set as 77 early as possible after helper invocations are no longer needed as 78 determined by data flow analysis. The `return` action is used to terminate 79 the shader, although it may be overloaded by the `BLEND` instruction. 80 81 The `reconverge` action is required on any instruction immediately 82 preceding a possible change to the mask of active threads in a subgroup. 83 This includes all divergent branches, but it also includes the final 84 instruction at the end of any basic block where the immediate successor 85 (fallthrough) is the target of a divergent branch. 86 </desc> 87 <value name="Wait on all dependency slots">wait0126</value> 88 <value name="Subgroup barrier">barrier</value> 89 <value name="Perform branch reconverge">reconverge</value> 90 <reserved/> 91 <reserved/> 92 <value name="Terminate discarded threads">td</value> 93 <reserved/> 94 <value name="Return from shader">return</value> 95 </enum> 96 97 <enum name="Immediate mode"> 98 <desc>Selects how immediates sources are interpreted.</desc> 99 <value desc="No special immediates" default="true">none</value> 100 <value desc="Thread storage pointers">ts</value> 101 <reserved/> 102 <value desc="Thread identification">id</value> 103 </enum> 104 105 <enum name="Thread storage pointers"> 106 <desc> 107 Situated between the immediates hard-coded in the hardware and the 108 uniforms defined purely in software, Valhall has a some special 109 "constants" passing through data structures. These are encoded like the 110 table of immediates, as if special constant $i$ were lookup table entry 111 $32 + i$. These special values are selected with the `.ts` modifier. 112 </desc> 113 <reserved/> 114 <reserved/> 115 <value desc="Thread local storage base pointer (low word)">tls_ptr</value> 116 <value desc="Thread local storage base pointer (high word)">tls_ptr_hi</value> 117 <reserved/> 118 <reserved/> 119 <value desc="Workgroup local storage base pointer (low word)">wls_ptr</value> 120 <value desc="Workgroup local storage base pointer (high word)">wls_ptr_hi</value> 121 </enum> 122 123 <enum name="Thread identification"> 124 <desc> 125 Situated between the immediates hard-coded in the hardware and the 126 uniforms defined purely in software, Valhall has a some special 127 "constants" passing through data structures. These are encoded like the 128 table of immediates, as if special constant $i$ were lookup table entry 129 $32 + i$. These special values are selected with the `.id` modifier. 130 </desc> 131 <reserved/> 132 <reserved/> 133 <value desc="Lane ID">lane_id</value> 134 <reserved/> 135 <reserved/> 136 <reserved/> 137 <value desc="Core ID">core_id</value> 138 <reserved/> 139 <reserved/> 140 <reserved/> 141 <reserved/> 142 <reserved/> 143 <reserved/> 144 <reserved/> 145 <reserved/> 146 <reserved/> 147 <reserved/> 148 <reserved/> 149 <reserved/> 150 <reserved/> 151 <reserved/> 152 <reserved/> 153 <reserved/> 154 <reserved/> 155 <reserved/> 156 <reserved/> 157 <reserved/> 158 <reserved/> 159 <reserved/> 160 <reserved/> 161 <value desc="Program counter">program_counter</value> 162 <reserved/> 163 </enum> 164 165 <enum name="Swizzles (8-bit)"> 166 <value default="true">b0123</value> 167 <value>b3210</value> 168 <value>b0101</value> 169 <value>b2323</value> 170 <value>b0000</value> 171 <value>b1111</value> 172 <value>b2222</value> 173 <value>b3333</value> 174 <value>b2301</value> 175 <value>b1032</value> 176 <value>b0011</value> 177 <value>b2233</value> 178 <reserved/> 179 <reserved/> 180 <reserved/> 181 <reserved/> 182 </enum> 183 184 <enum name="Lanes (8-bit)"> 185 <desc>Used to select the 2 bytes for shifts of 16-bit vectors</desc> 186 <value>b02</value> 187 <reserved/> 188 <reserved/> 189 <reserved/> 190 <value>b00</value> 191 <value>b11</value> 192 <value>b22</value> 193 <value>b33</value> 194 <reserved/> 195 <reserved/> 196 <value>b01</value> 197 <value>b23</value> 198 <reserved/> 199 <reserved/> 200 <reserved/> 201 <reserved/> 202 </enum> 203 204 <enum name="Swizzles (16-bit)"> 205 <value>h00</value> <!-- 0,2 --> 206 <value>h10</value> 207 <value default="true">h01</value> 208 <value>h11</value> 209 <value>b00</value> <!-- 0,0 --> 210 <value>b20</value> <!-- 1,1 --> 211 <value>b02</value> <!-- 2,2 --> 212 <value>b22</value> <!-- 3,3 --> 213 <value>b11</value> 214 <value>b31</value> 215 <value>b13</value> <!-- 0,1 --> 216 <value>b33</value> <!-- 2,3 --> 217 <value>b01</value> 218 <value>b23</value> 219 <reserved/> 220 <reserved/> 221 </enum> 222 223 <enum name="Swizzles (32-bit)"> 224 <value default="true">none</value> 225 <reserved/> 226 <value>h0</value> 227 <value>h1</value> 228 <value>b0</value> 229 <value>b1</value> 230 <value>b2</value> 231 <value>b3</value> 232 </enum> 233 234 <enum name="Swizzles (64-bit)"> 235 <value default="true">none</value> 236 <reserved/> 237 <value>h0</value> 238 <value>h1</value> 239 <value>b0</value> 240 <value>b1</value> 241 <value>b2</value> 242 <value>b3</value> 243 <value>w0</value> 244 <reserved/> 245 <reserved/> 246 <reserved/> 247 <reserved/> 248 <reserved/> 249 <reserved/> 250 <reserved/> 251 </enum> 252 253 <enum name="Lane (8-bit)" implied="true"> 254 <value>b0</value> 255 <value>b1</value> 256 <value>b2</value> 257 <value>b3</value> 258 </enum> 259 260 <enum name="Lane (32-bit)"> 261 <desc> 262 Used for the lane select of `BRANCHZ`. To use an 8-bit condition, a 263 separate `ICMP` is required to cast to 16-bit. 264 </desc> 265 <value default="true">none</value> 266 <value>h0</value> 267 <value>h1</value> 268 <reserved/> 269 </enum> 270 271 <enum name="Lane (16-bit)" implied="true"> 272 <value>h0</value> 273 <value>h1</value> 274 </enum> 275 276 <enum name="Load lane (8-bit)"> 277 <value default="true">b0</value> 278 <value>b1</value> 279 <value>b2</value> 280 <value>b3</value> 281 <value desc="Zero-extend to 16-bit, low-half">h0</value> 282 <value desc="Zero-extend to 16-bit, high-half">h1</value> 283 <value desc="Zero-extend to 32-bit">w0</value> 284 <value desc="Zero-extend to 32-bit">d0</value> 285 </enum> 286 287 <enum name="Load lane (16-bit)"> 288 <value desc="Low half" default="true">h0</value> 289 <value desc="High half">h1</value> 290 <value desc="Zero-extend to 32-bit">w0</value> 291 <value desc="Zero-extend to 64-bit">d0</value> 292 <reserved/> 293 <reserved/> 294 <reserved/> 295 <reserved/> 296 </enum> 297 298 <enum name="Load lane (24-bit)" implied="true"> 299 <value default="true">identity</value> 300 <reserved/> 301 <reserved/> 302 <reserved/> 303 <reserved/> 304 <reserved/> 305 <reserved/> 306 </enum> 307 308 <enum name="Load lane (32-bit)"> 309 <value default="true">w0</value> 310 <value desc="Zero-extend to 64-bit">d0</value> 311 <reserved/> 312 <reserved/> 313 <reserved/> 314 <reserved/> 315 <reserved/> 316 <reserved/> 317 </enum> 318 319 <enum name="Load lane (48-bit)"> 320 <reserved/> 321 <reserved/> 322 <reserved/> 323 <reserved/> 324 <value default="true">identity</value> 325 <reserved/> 326 <reserved/> 327 <reserved/> 328 </enum> 329 330 <enum name="Load lane (64-bit)"> 331 <reserved/> 332 <reserved/> 333 <reserved/> 334 <reserved/> 335 <reserved/> 336 <reserved/> 337 <reserved/> 338 <value default="true">identity</value> 339 </enum> 340 341 <enum name="Load lane (96-bit)"> 342 <reserved/> 343 <reserved/> 344 <reserved/> 345 <reserved/> 346 <reserved/> 347 <reserved/> 348 <value default="true">identity</value> 349 <reserved/> 350 </enum> 351 352 <enum name="Load lane (128-bit)"> 353 <reserved/> 354 <reserved/> 355 <reserved/> 356 <reserved/> 357 <reserved/> 358 <reserved/> 359 <reserved/> 360 <value default="true">identity</value> 361 </enum> 362 363 <enum name="Round mode"> 364 <desc>Corresponds to IEEE 754 rounding modes</desc> 365 <value desc="Round to nearest even" default="true">rte</value> 366 <value desc="Round to positive infinity">rtp</value> 367 <value desc="Round to negative infinity">rtn</value> 368 <value desc="Round to zero">rtz</value> 369 </enum> 370 371 <enum name="Result type"> 372 <desc> 373 Comparison instructions like `FCMP` return a boolean but may encode this 374 boolean in a variety of ways. `i1` gives a OpenGL style `0/1` boolean. 375 `m1` gives a Direct3D style `0/~0` boolean. `f1` gives a floating-point 376 `0.0f / 1.0f` boolean. Switching between these modes is useful to fold a 377 boolean type convert into a comparison. `u1` is used internally to 378 implement 64-bit comparisons. 379 </desc> 380 <value desc="Integer 1">i1</value> 381 <value desc="Float 1">f1</value> 382 <value desc="Minus 1">m1</value> 383 <value desc="Low half of 64-bit compare">u1</value> 384 </enum> 385 386 <enum name="Widen"> 387 <value default="true">none</value> 388 <value>h0</value> 389 <value>h1</value> 390 <reserved/> 391 <reserved/> 392 <reserved/> 393 <reserved/> 394 <reserved/> 395 </enum> 396 397 <enum name="Clamp"> 398 <desc> 399 Clamp applied to the destination of a floating-point instruction. Note the 400 clamps may be decomposed as two independent bits for `clamp_0_inf` and 401 `clamp_m1_1`, with `clamp_0_1` arising as the composition of `clamp_0_inf` 402 and `clamp_m1_1` in either order. 403 404 Clamps are implemented per the SPIR-V specification: 405 406 $$\text{clamp} \; (x, \ell, h) = \min( \max( x, \ell ), h)$$ 407 408 The min/max functions return the other operand if one operand is NaN, and 409 compare $-0 < +0$. That means the following identities hold for Valhall 410 clamps: 411 412 \begin{align*} 413 \text{clamp}(-0.0, 0.0, 1.0) & = +0.0 \\ 414 \text{clamp}(-\text{NaN}, 0.0, 1.0) & = +0.0 \\ 415 \text{clamp}(\text{NaN}, 0.0, 1.0) & = +0.0 \\ 416 & \\ 417 \text{clamp}(-0.0, -1.0, 1.0) & = -0.0 \\ 418 \text{clamp}(\text{NaN}, -1.0, 1.0) & = -1.0 \\ 419 \text{clamp}(-\text{NaN}, -1.0, 1.0) & = -1.0 \\ 420 & \\ 421 \max(\text{NaN}, 0.0) & = +0.0 \\ 422 \max(-\text{NaN}, 0.0) & = +0.0 \\ 423 \max(-0.0, 0.0) & = +0.0 \\ 424 \end{align*} 425 426 This behaviour is consistent with the FMin/FMax/FClamp and 427 NMin/NMax/NClamp rules prescribed by SPIR-V and governed by IEEE-754. As 428 a consequence, substituting these clamps for equivalent minimum/maximum 429 exprssions is legal even with strict floating point rules. 430 </desc> 431 <value default="true" desc="Identity">none</value> 432 <value desc="Clamp positive">clamp_0_inf</value> 433 <value desc="Clamp to $[-1, 1]$">clamp_m1_1</value> 434 <value desc="Clamp to $[0, 1]$">clamp_0_1</value> 435 </enum> 436 437 <enum name="Condition"> 438 <desc> 439 Condition code. Type must be inferred from the instruction. IEEE 754 total 440 ordering only applies to floating point compares. "Not equal" and "greater 441 than or less than" are distinguished by NaN behaviour conforming to 442 the IEEE 754 specification. 443 </desc> 444 <value desc="Equal">eq</value> 445 <value desc="Greater than">gt</value> 446 <value desc="Greater than or equal">ge</value> 447 <value desc="Not equal">ne</value> 448 <value desc="Less than">lt</value> 449 <value desc="Less than or equal">le</value> 450 <value desc="Greater than or less than">gtlt</value> 451 <value desc="Totally ordered">total</value> 452 </enum> 453 454 <enum name="Dimension"> 455 <desc>Texture dimension.</desc> 456 <value desc="1D or buffer">1d</value> 457 <value desc="2D or 2D array">2d</value> 458 <value desc="3D or 3D array">3d</value> 459 <value desc="Cube map or cube map array">cube</value> 460 </enum> 461 462 <enum name="LOD mode"> 463 <desc>Level-of-detail selection mode in a texture instruction.</desc> 464 <value desc="Set to zero">zero</value> 465 <value desc="Computed based on neighboring fragments">computed</value> 466 <reserved/> 467 <reserved/> 468 <value desc="Explicitly specified in a register">explicit</value> 469 <value desc="Computed based on neighboring fragments added with bias in a register">computed_bias</value> 470 <value desc="Derived from a gradient descriptor in registers">grdesc</value> 471 <reserved/> 472 </enum> 473 474 <enum name="Register format"> 475 <desc>Format of data loaded to / stored from registers for general memory access.</desc> 476 <reserved/> 477 <reserved/> 478 <value desc="32-bit floats">f32</value> 479 <value desc="16-bit floats">f16</value> 480 <value desc="32-bit unsigned integers">u32</value> 481 <reserved/> 482 <reserved/> 483 <reserved/> 484 </enum> 485 486 <enum name="Staging register count" implied="true"> 487 <value>sr0</value> 488 <value>sr1</value> 489 <value>sr2</value> 490 <value>sr3</value> 491 <value>sr4</value> 492 <value>sr5</value> 493 <value>sr6</value> 494 <value>sr7</value> 495 </enum> 496 497 <enum name="Vector size"> 498 <desc>Number of channels loaded/stored for general memory access.</desc> 499 <value default="true" desc="Scalar">none</value> 500 <value desc="2 channels">v2</value> 501 <value desc="3 channels">v3</value> 502 <value desc="4 channels">v4</value> 503 </enum> 504 505 <enum name="Slot"> 506 <desc> 507 Dependency slot set on a message-passing instruction that writes to 508 registers. Before reading the destination, a future instruction must wait 509 on the specified slot. Slot #7 is for `BARRIER` instructions only. 510 </desc> 511 <value desc="Slot #0">slot0</value> 512 <value desc="Slot #1">slot1</value> 513 <value desc="Slot #2">slot2</value> 514 <reserved/> 515 <reserved/> 516 <reserved/> 517 <reserved/> 518 <value desc="Slot #7">slot7</value> 519 </enum> 520 521 <enum name="Store segment"> 522 <desc>Memory segment written to by a `STORE` instruction.</desc> 523 <value desc="Global or workgroup local memory" default="none">global</value> 524 <value desc="Position output (in a position shader)">pos</value> 525 <value desc="Varyings with LEA_ATTR computed addresses">vary</value> 526 <value desc="Thread local storage">tl</value> 527 </enum> 528 529 <enum name="Subgroup size"> 530 <desc> 531 Selects the effective subgroup size from subgroup operations. The hardware 532 warps are sixteen threads on Valhall, but subdividing a warp may be useful 533 for API requirements. In particular, derivatives may be calculated with 534 quads (four threads). 535 </desc> 536 <value desc="Two threads">subgroup2</value> 537 <value desc="Four threads">subgroup4</value> 538 <value desc="Eight threads">subgroup8</value> 539 <value desc="Sixteen threads" default="true">subgroup16</value> 540 </enum> 541 542 <enum name="Lane operation"> 543 <desc> 544 Acts as a modifier on the lane specificier for a `CLPER` instruction. The 545 `accumulate` mode is required for efficient subgroup reductions. 546 </desc> 547 <value name="No operation" default="true">none</value> 548 <value name="Exclusive-or">xor</value> 549 <value name="Accumulate">accumulate</value> 550 <value name="Shift">shift</value> 551 </enum> 552 553 <enum name="Inactive result"> 554 <desc> 555 Accesses to inactive lanes (due to divergence) in a subgroup is generally 556 undefined in APIs. However, the results of permuting with an inactive lane 557 with `CLPER.i32` are well-defined in Valhall: they return one of the 558 following values, as specified in the `CLPER.i32` instructions. Sometimes 559 certain values enable small optimizations. 560 </desc> 561 <value name="0x00000000" default="true">zero</value> 562 <value name="0xFFFFFFFF">umax</value> 563 <value name="0x00000001">i1</value> 564 <value name="0x00010001">v2i1</value> 565 <value name="0x80000000">smin</value> 566 <value name="0x7FFFFFFF">smax</value> 567 <value name="0x80008000">v2smin</value> 568 <value name="0x7FFF7FFF">v2smax</value> 569 <value name="0x80808080">v4smin</value> 570 <value name="0x7F7F7F7F">v4smax</value> 571 <value name="0x3F800000">f1</value> 572 <value name="0x3C003C00">v2f1</value> 573 <value name="0xFF800000">infn</value> 574 <value name="0x7F800000">inf</value> 575 <value name="0xFC00FC00">v2infn</value> 576 <value name="0x7C007C00">v2inf</value> 577 </enum> 578 579 <ins name="NOP" title="No operation" dests="0" opcode="0x00"> 580 <desc> 581 Do nothing. Useful at the start of a block for waiting on slots required 582 by the first actual instruction of the block, to reconcile dependencies 583 after a branch. Also useful as the sole instruction of an empty shader. 584 </desc> 585 </ins> 586 587 <ins name="BRANCHZ" title="Compare to zero and branch" dests="0" opcode="0x1F"> 588 <desc> 589 Branches to a specified relative offset if its source is nonzero (default) 590 or if its source is zero (if `.eq` is set). The offset is 27-bits and 591 sign-extended, giving an effective range of ±26-bits. The offset is 592 specified in units of instructions, relative to the *next* instruction. 593 Positive offsets may be interpreted as "number of instructions to skip". 594 Since Valhall instructions are 8 bytes, this operates as: 595 596 $$PC := \begin{cases} PC + 8 \cdot (\text{offset} \; + 1) & \text{if} \; 597 \text{src} \stackrel{?}{=} 0 \\ PC + 8 & \text{otherwise} \end{cases}$$ 598 599 Used with comparison instructions to implement control flow. Tie the 600 source to a nonzero constant to implement a jump. May introduce 601 divergence, so generally requires `.reconverge` flow control. 602 </desc> 603 <src lane="37">Value to compare against zero</src> 604 <imm name="offset" start="8" size="27" signed="true"/> 605 <mod name="eq" start="36" size="1"/> 606 </ins> 607 608 <ins name="DISCARD.f32" title="Discard fragment" opcode="0x20"> 609 <desc> 610 Evaluates the given condition, and if it passes, discards the current 611 fragment and terminates the thread. The destination should be set to R60. 612 Only valid in a **fragment** shader. 613 </desc> 614 <cmp/> 615 <dest>Updated coverage mask (set to R60)</dest> 616 <src absneg="true" swizzle="true">Left value to compare</src> 617 <src absneg="true" swizzle="true">Right value to compare</src> 618 </ins> 619 620 <ins name="BRANCHZI" title="Compare to zero and branch indirect" opcode="0x2F"> 621 <desc> 622 Jump to an indirectly specified address. Used to jump to blend shaders at 623 the end of a fragment shader. 624 </desc> 625 <src>Value to compare against zero</src> 626 <src>Branch target</src> 627 <mod name="eq" start="36" size="1"/> 628 </ins> 629 630 <ins name="BARRIER" title="Execution and memory barrier" opcode="0x45"> 631 <desc> 632 General-purpose barrier. Must use slot #7. Must be paired with a 633 `.barrier` action on the instruction. 634 </desc> 635 <slot/> 636 </ins> 637 638 <group name="CSEL" title="Floating-point conditional select" dests="1"> 639 <ins name="CSEL.f32" opcode="0x154"/> 640 <ins name="CSEL.v2f16" opcode="0x155"/> 641 <desc> 642 Evaluates the given condition and outputs either the true source or the 643 false source. 644 </desc> 645 <cmp/> 646 <src float="true">Left value to compare</src> 647 <src float="true">Right value to compare</src> 648 <src float="true">Return value if true</src> 649 <src float="true">Return value if false</src> 650 </group> 651 652 <group name="CSEL" title="Integer conditional select" dests="1"> 653 <ins name="CSEL.u32" opcode="0x150"/> 654 <ins name="CSEL.v2u16" opcode="0x151"/> 655 <ins name="CSEL.i32" opcode="0x158"/> 656 <ins name="CSEL.v2i16" opcode="0x159"/> 657 <desc> 658 Evaluates the given condition and outputs either the true source or the 659 false source. 660 661 Valhall lacks integer minimum/maximum instructions. `CSEL` instructions 662 with tied operands form the canonical implementations of these 663 instructions. Similarly, the integer $\text{sign}$ function is canonically 664 implemented with a pair of `CSEL` instructions. 665 </desc> 666 <cmp/> 667 <src>Left value to compare</src> 668 <src>Right value to compare</src> 669 <src>Return value if true</src> 670 <src>Return value if false</src> 671 </group> 672 673 <ins name="LD_VAR_SPECIAL" title="Load special varying" opcode="0x56"> 674 <sr write="true"/> 675 <sr_count/> 676 <vecsize/> 677 <regfmt/> 678 <slot/> 679 <src/> 680 <imm name="index" start="12" size="4"/> <!-- 0 for pointx, 1 for pointy, 2 for fragw, 3 for fragz --> 681 </ins> 682 683 <group name="LD_VAR_IMM_F32" title="Load immediate varying"> 684 <desc>Interpolates a given varying</desc> 685 <ins name="LD_VAR_IMM_F32" opcode="0x5C"/> 686 <ins name="LD_VAR_IMM_F16" opcode="0x5D"/> 687 <sr write="true"/> 688 <vecsize/> 689 <sr_count/> 690 <regfmt/> 691 <slot/> 692 <src/> 693 <src/> 694 <imm name="index" start="20" size="4"/> 695 </group> 696 697 <ins name="LD_ATTR_IMM" title="Load immediate attribute" opcode="0x66"> 698 <sr_count/> 699 <vecsize/> 700 <regfmt/> 701 <slot/> 702 <sr write="true"/> 703 <src>Vertex ID</src> 704 <src>Instance ID</src> 705 <imm name="index" start="20" size="4"/> 706 </ins> 707 708 <ins name="LD_ATTR" title="Load indirect attribute" opcode="0x67"> 709 <desc>The index must not diverge within a warp.</desc> 710 <vecsize/> 711 <regfmt/> 712 <slot/> 713 <sr_count/> 714 <sr write="true"/> 715 <src>Vertex ID</src> 716 <src>Instance ID</src> 717 <src>Index</src> 718 </ins> 719 720 <ins name="LEA_ATTR" title="Load effective address" opcode="0x5E"> 721 <desc> 722 Loads the effective address of the position buffer (in a position shader) 723 or the varying buffer (in a varying shader). That is, the base pointer 724 plus the vertex's linear ID (the first source) times the buffer's 725 per-vertex stride. `LEA_ATTR` should be executed once in a 726 position/varying shader, with the linear ID preloaded as `r59`. Each 727 position/varying store can then be constructed as `STORE` with the base 728 address sourced from the 64-bit destination of `LEA_ATTR` and an 729 appropriately computed offset. Varying stores bypass the usual conversion 730 hardware for attributes; this diverges from earlier Mali hardware. 731 </desc> 732 <sr write="true"/> 733 <sr_count/> 734 <slot/> 735 <imm name="unk" start="8" size="4"/> 736 <src>Linear ID</src> 737 </ins> 738 739 <ins name="LOAD.i8" title="Global memory load" opcode="0x60" opcode2="0"> 740 <desc>Loads from main memory</desc> 741 <sr write="true"/> 742 <sr_count/> 743 <mod name="load_lane_8_bit" start="36" size="3"/> 744 <mod name="unsigned" start="39" size="1"/> 745 <slot/> 746 <src>Address to load from after adding offset</src> 747 <imm name="offset" start="8" size="16" signed="true"/> 748 </ins> 749 750 <ins name="LOAD.i16" title="Global memory load" opcode="0x60" opcode2="1"> 751 <desc>Loads from main memory</desc> 752 <sr write="true"/> 753 <sr_count/> 754 <mod name="load_lane_16_bit" start="36" size="3"/> 755 <mod name="unsigned" start="39" size="1"/> 756 <slot/> 757 <src>Address to load from after adding offset</src> 758 <imm name="offset" start="8" size="16" signed="true"/> 759 </ins> 760 761 <ins name="LOAD.i24" title="Global memory load" opcode="0x60" opcode2="2"> 762 <desc>Loads from main memory</desc> 763 <sr write="true"/> 764 <sr_count/> 765 <mod name="load_lane_24_bit" start="36" size="3"/> 766 <mod name="unsigned" start="39" size="1"/> 767 <slot/> 768 <src>Address to load from after adding offset</src> 769 <imm name="offset" start="8" size="16" signed="true"/> 770 </ins> 771 772 <ins name="LOAD.i32" title="Global memory load" opcode="0x60" opcode2="3"> 773 <desc>Loads from main memory</desc> 774 <sr write="true"/> 775 <sr_count/> 776 <mod name="load_lane_32_bit" start="36" size="3"/> 777 <mod name="unsigned" start="39" size="1"/> 778 <slot/> 779 <src>Address to load from after adding offset</src> 780 <imm name="offset" start="8" size="16" signed="true"/> 781 </ins> 782 783 <ins name="LOAD.i48" title="Global memory load" opcode="0x60" opcode2="4"> 784 <desc>Loads from main memory</desc> 785 <sr write="true"/> 786 <sr_count/> 787 <mod name="load_lane_48_bit" start="36" size="3"/> 788 <mod name="unsigned" start="39" size="1"/> 789 <slot/> 790 <src>Address to load from after adding offset</src> 791 <imm name="offset" start="8" size="16" signed="true"/> 792 </ins> 793 794 <ins name="LOAD.i64" title="Global memory load" opcode="0x60" opcode2="5"> 795 <desc>Loads from main memory</desc> 796 <sr write="true"/> 797 <sr_count/> 798 <mod name="load_lane_64_bit" start="36" size="3"/> 799 <mod name="unsigned" start="39" size="1"/> 800 <slot/> 801 <src>Address to load from after adding offset</src> 802 <imm name="offset" start="8" size="16" signed="true"/> 803 </ins> 804 805 <ins name="LOAD.i96" title="Global memory load" opcode="0x60" opcode2="6"> 806 <desc>Loads from main memory</desc> 807 <sr write="true"/> 808 <sr_count/> 809 <mod name="load_lane_96_bit" start="36" size="3"/> 810 <mod name="unsigned" start="39" size="1"/> 811 <slot/> 812 <src>Address to load from after adding offset</src> 813 <imm name="offset" start="8" size="16" signed="true"/> 814 </ins> 815 816 <ins name="LOAD.i128" title="Global memory load" opcode="0x60" opcode2="7"> 817 <desc>Loads from main memory</desc> 818 <sr write="true"/> 819 <sr_count/> 820 <mod name="load_lane_128_bit" start="36" size="3"/> 821 <mod name="unsigned" start="39" size="1"/> 822 <slot/> 823 <src>Address to load from after adding offset</src> 824 <imm name="offset" start="8" size="16" signed="true"/> 825 </ins> 826 827 <group name="STORE" title="Global memory store" opcode="0x61"> 828 <desc>Stores to main memory</desc> 829 <sr read="true"/> 830 <ins name="STORE.i8" opcode2="0x0"/> 831 <ins name="STORE.i16" opcode2="0x1"/> 832 <ins name="STORE.i24" opcode2="0x2"/> 833 <ins name="STORE.i32" opcode2="0x3"/> 834 <ins name="STORE.i48" opcode2="0x4"/> 835 <ins name="STORE.i64" opcode2="0x5"/> 836 <ins name="STORE.i96" opcode2="0x6"/> 837 <ins name="STORE.i128" opcode2="0x7"/> 838 <sr_count/> 839 <store_segment/> 840 <slot/> 841 <src>Address to store to after adding offset</src> 842 <imm name="offset" start="8" size="16" signed="true"/> 843 </group> 844 845 <ins name="ST_IMAGE" title="Image store" opcode="0x71"> 846 <desc>Stores to images</desc> 847 <sr read="true"/> 848 <sr_count/> 849 <slot/> 850 <src>Address to store to after adding offset</src> 851 </ins> 852 853 <ins name="LD_TILE" title="Load from tilebuffer" opcode="0x78"> 854 <desc> 855 Loads a given render target, specified in the pixel indices descriptor, at 856 a given location and sample, and convert to the format specified in the 857 internal conversion descriptor. Used to implement EXT_framebuffer_fetch 858 and internally in blend shaders. 859 </desc> 860 <sr write="true"/> 861 <sr_count/> 862 <slot/> 863 <src>Pixel indices descriptor</src> 864 <src>Coverage mask</src> 865 <src>Conversion descriptor</src> 866 </ins> 867 868 <ins name="BLEND" title="Blend render target" opcode="0x7F"> 869 <desc> 870 Blends a given render target. This loads the API-specified blend state for 871 the render target from the first source. Blend descriptors are available 872 as special immediates. It then reads the colour to be blended from the 873 first staging register, with the specified vector size and register format 874 as desired. The resulting coverage mask is stored to the second set of 875 staging registers. 876 877 In the fixed-function path, `BLEND` sends the colour to the blender to be 878 written to the tilebuffer. Then, if the instruction's flow control 879 specifies termination, the fragment program is ended. If it does not 880 specify termination, `BLEND` acts as a relative branch, branching with the 881 offset specified as `target`. This allows the subsequent instructions to 882 be skipped when fixed-function blending is used. Note this implicit branch 883 can never introduce divergence, so `.reconverge` is not required. 884 885 In the blend shader path, `BLEND` ignores the specified flow control and 886 does not branch to the specified offset. Instead, execution considers 887 normally with the next instruction. The compiler should insert code for 888 calling a blend shader after the `BLEND` instruction unless it is known 889 that a blend shader will never be required. 890 891 The indirection is required to support both fixed-function and blend 892 shaders efficiently and without shader variants. 893 </desc> 894 <sr read="true"/> 895 <sr write="true" count="1" flags="false"/> 896 <src>Blend descriptor</src> 897 <imm name="target" start="8" size="8"/> 898 <slot/> 899 <sr_count/> 900 <vecsize/> 901 <regfmt/> 902 </ins> 903 904 <ins name="ATEST" title="Alpha test" opcode="0x7D"> 905 <desc> 906 Does alpha-to-coverage testing, updating the sample coverage mask. ATEST 907 does not do an implicit discard. It should be executed before the first 908 ZS_EMIT or BLEND instruction. 909 </desc> 910 <sr write="true">Updated coverage mask</sr> 911 <src>Input coverage mask</src> 912 <src swizzle="true">Alpha value (render target 0)</src> 913 <src/> 914 <sr_count/> 915 </ins> 916 917 <ins name="ZS_EMIT" title="Depth/stencil write" opcode="0x7E"> 918 <desc> 919 Programatically writes out depth, stencil, or both, depending on which 920 modifiers are set. Used to implement gl_FragDepth and gl_FragStencil. 921 </desc> 922 <mod name="z" start="25" size="1"/> 923 <mod name="stencil" start="24" size="1"/> 924 <dest>Updated coverage mask</dest> 925 <src>Depth value</src> 926 <src>Stencil value</src> 927 <src>Input coverage mask</src> 928 </ins> 929 930 <group name="CONVERT" title="Data conversions" dests="1" opcode="0x90"> 931 <desc> 932 Performs the given data conversion. Note that floating-point rounding is 933 handled via the same hardware and therefore shares an encoding. Round mode 934 is specified where it makes sense. 935 </desc> 936 937 <ins name="S16_TO_S32" opcode2="0x4"/> 938 <ins name="S16_TO_F32" opcode2="0x5"/> 939 <ins name="V2S16_TO_V2F16" opcode2="0x7"/> 940 941 <ins name="S32_TO_F32" opcode2="0x9"/> 942 943 <ins name="U16_TO_U32" opcode2="0x14"/> 944 <ins name="U16_TO_F32" opcode2="0x15"/> 945 <ins name="V2U16_TO_V2F16" opcode2="0x17"/> 946 947 <ins name="U32_TO_F32" opcode2="0x19"/> 948 949 <roundmode/> 950 <src widen="true">Value to convert</src> 951 </group> 952 953 <group name="CONVERT" title="Float-to-int data conversions" dests="1" opcode="0x90"> 954 <desc>Performs the given data conversion.</desc> 955 <ins name="F32_TO_S32" opcode2="0xC"/> 956 <ins name="F32_TO_U32" opcode2="0x1C"/> 957 <roundmode/> 958 <src absneg="true">Value to convert</src> 959 </group> 960 961 <group name="CONVERT" title="Float-to-int data conversions" dests="1" opcode="0x90"> 962 <desc>Performs the given data conversion.</desc> 963 <ins name="V2F16_TO_V2S16" opcode2="0xE"/> 964 <ins name="V2F16_TO_V2U16" opcode2="0x1E"/> 965 <ins name="F16_TO_S32" opcode2="0xA"/> 966 <ins name="F16_TO_U32" opcode2="0x1A"/> 967 <roundmode/> 968 <src swizzle="true" absneg="true" size="16">Value to convert</src> 969 </group> 970 971 <ins name="F16_TO_F32" title="16-bit float to 32-bit float conversion" dests="1" opcode="0x90" opcode2="0xB"> 972 <desc>Converts up with the specified round mode.</desc> 973 <roundmode/> 974 <src lane="28" size="16" absneg="true">Value to convert</src> 975 </ins> 976 977 <group name="CONVERT" title="8-bit data conversions" dests="1" opcode="0x90"> 978 <desc> 979 Performs the given data conversion. 980 </desc> 981 982 <ins name="S8_TO_S32" opcode2="0x0"/> 983 <ins name="S8_TO_F32" opcode2="0x1"/> 984 <ins name="S8_TO_S16" opcode2="0x2"/> 985 <ins name="S8_TO_F16" opcode2="0x3"/> 986 987 <ins name="U8_TO_U32" opcode2="0x10"/> 988 <ins name="U8_TO_F32" opcode2="0x11"/> 989 <ins name="U8_TO_U16" opcode2="0x12"/> 990 <ins name="U8_TO_F16" opcode2="0x13"/> 991 992 <src lane="28" size="8">Value to convert</src> 993 </group> 994 995 <group name="FROUND" title="Floating-point rounding" dests="1" opcode="0x90"> 996 <desc> 997 Performs the given rounding, using the convert unit. 998 </desc> 999 1000 <ins name="FROUND.f32" opcode2="0xD"/> 1001 <ins name="FROUND.v2f16" opcode2="0xF"/> 1002 1003 <roundmode/> 1004 <src swizzle="true" absneg="true">Value to convert</src> 1005 </group> 1006 1007 <ins name="MOV.i32" title="Register move" dests="1" opcode="0x91" opcode2="0x0"> 1008 <desc>Canonical register-to-register move.</desc> 1009 <src/> 1010 </ins> 1011 1012 <ins name="CLZ.u32" title="Count leading zeroes" dests="1" opcode="0x91" opcode2="0x4"> 1013 <desc> 1014 Used as a primitive for various bitwise operations. 1015 </desc> 1016 <src/> 1017 </ins> 1018 1019 <ins name="CLZ.v2u16" title="Count leading zeroes" dests="1" opcode="0x91" opcode2="0x5"> 1020 <desc> 1021 Used as a primitive for various bitwise operations. 1022 </desc> 1023 <src/> 1024 </ins> 1025 1026 <ins name="CLZ.v4u8" title="Count leading zeroes" dests="1" opcode="0x91" opcode2="0x6"> 1027 <desc> 1028 Used as a primitive for various bitwise operations. 1029 </desc> 1030 <src/> 1031 </ins> 1032 1033 <ins name="IABS.s32" title="Absolute value" dests="1" opcode="0x91" opcode2="0x8"> 1034 <desc> 1035 64-bit abs may be constructed in 4 instructions (5 clocks) by checking the 1036 sign with `ICMP.s32.lt.m1 hi, 0` and negating based on the result with 1037 `IADD.s64` and `LSHIFT_XOR.i32` on each half. 1038 </desc> 1039 <src widen="true"/> 1040 </ins> 1041 1042 <ins name="IABS.v2s16" title="Absolute value" dests="1" opcode="0x91" opcode2="0x9"> 1043 <src widen="true"/> 1044 </ins> 1045 1046 <ins name="IABS.v4s8" title="Absolute value" dests="1" opcode="0x91" opcode2="0xa"> 1047 <src/> 1048 </ins> 1049 1050 <ins name="POPCOUNT.i32" title="Population count" dests="1" opcode="0x91" opcode2="0xC"> 1051 <desc> 1052 Only available as 32-bit. Smaller bitsizes require explicit conversions. 1053 64-bit popcount may be constructed in 3 clocks by separate 32-bit 1054 popcounts of each half and a 32-bit add, which is guaranteed not to 1055 overflow. 1056 </desc> 1057 <src/> 1058 </ins> 1059 1060 <ins name="BITREV.i32" title="Bitwise reverse" dests="1" opcode="0x91" opcode2="0xD"> 1061 <desc> 1062 Only available as 32-bit. Other bitsizes may be derived with swizzles. 1063 </desc> 1064 <src/> 1065 </ins> 1066 1067 <ins name="NOT.i32" title="Bitwise complement" dests="1" opcode="0x91" opcode2="0xE"> 1068 <desc> 1069 For fully featured bitwise operation, see the shift opcodes. 1070 </desc> 1071 <src/> 1072 </ins> 1073 1074 <ins name="NOT.i64" title="Bitwise complement" dests="1" opcode="0x191" opcode2="0xE"> 1075 <desc> 1076 For fully featured bitwise operation, see the shift opcodes. 1077 </desc> 1078 <src/> 1079 </ins> 1080 1081 <ins name="WMASK" title="Warp mask" dests="1" opcode="0x95"> 1082 <desc> 1083 Returns the mask of lanes ever active within the warp (subgroup), such 1084 that the source is nonzero. The number of work-items in a subgroup is 1085 given as the popcount of this value with a nonzero input. 1086 1087 An `all()` subgroup operation may be constructed as `WMASK` of the input 1088 compared for equality with `WMASK` of an nonzero value. 1089 1090 An `any()` subgroup operation may be constructed as `WMASK` of the input 1091 compared against zero. 1092 </desc> 1093 <src/> 1094 <subgroup/> 1095 </ins> 1096 1097 <group name="FREXP" title="Fraction/exponent extract" dests="1" opcode="0x99"> 1098 <ins name="FREXPM.f32" opcode2="0"/> 1099 <ins name="FREXPM.v2f16" opcode2="1"/> 1100 <ins name="FREXPE.f32" opcode2="2"/> 1101 <ins name="FREXPE.v2f16" opcode2="3"/> 1102 <desc> 1103 Breaks up the floating-point input into its fractional (mantissa) and 1104 exponent parts. By default, this is compatible with the `frexp()` function 1105 in APIs. With the log modifier, the floating point format is adjusted to 1106 be compatible with Valhall's argument reduction for logarithm computation. 1107 </desc> 1108 <mod name="log" start="25" size="1"/> 1109 <src float="true" swizzle="true"/> 1110 </group> 1111 1112 <group name="SFU" title="Special function unit" dests="1" opcode="0x9C"> 1113 <ins name="FRCP.f32" opcode2="0"/> 1114 <ins name="FRCP.f16" opcode2="1"/> 1115 <ins name="FRSQ.f32" opcode2="2"/> 1116 <ins name="FRSQ.f16" opcode2="3"/> 1117 <ins name="FLOGD.f32" opcode2="8"/> 1118 <desc> 1119 Performs a given special function. The floating-point reciprocal (`FRCP`) 1120 and reciprocal square root (`FRSQ`) instructions may be freely used as-is. 1121 The logarithm instruction (`FLOGD.f32`) requires an argument reduction. See the 1122 transcendentals section for more information. 1123 </desc> 1124 <src float="true" swizzle="true"/> 1125 </group> 1126 1127 <group name="SFU" title="Special function unit" dests="1" opcode="0x9C"> 1128 <ins name="FSIN_TABLE.u6" opcode2="4"/> 1129 <ins name="FCOS_TABLE.u6" opcode2="5"/> 1130 <desc> 1131 Performs a given special function.The trigonometric tables (`FSIN_TABLE.u6` and `FCOS_TABLE.u6`) are crude, 1132 requiring both an argument reduction and postprocessing. 1133 </desc> 1134 <src/> 1135 </group> 1136 1137 <group name="FADD" title="Floating-point add" dests="1" opcode2="0"> 1138 <ins name="FADD.f32" opcode="0xA4"/> 1139 <ins name="FADD.v2f16" opcode="0xA5"/> 1140 <desc>$A + B$</desc> 1141 <clamp/> 1142 <src absneg="true" swizzle="true">A</src> 1143 <src absneg="true" swizzle="true">B</src> 1144 </group> 1145 1146 <group name="FMIN" title="Floating-point minimum" dests="1" opcode2="2"> 1147 <ins name="FMIN.f32" opcode="0xA4"/> 1148 <ins name="FMIN.v2f16" opcode="0xA5"/> 1149 <desc>$\min \{ A, B \}$</desc> 1150 <clamp/> 1151 <src absneg="true" swizzle="true">A</src> 1152 <src absneg="true" swizzle="true">B</src> 1153 </group> 1154 1155 <group name="FMAX" title="Floating-point maximum" dests="1" opcode2="3"> 1156 <ins name="FMAX.f32" opcode="0xA4"/> 1157 <ins name="FMAX.v2f16" opcode="0xA5"/> 1158 <desc>$\max \{ A, B \}$</desc> 1159 <clamp/> 1160 <src absneg="true" swizzle="true">A</src> 1161 <src absneg="true" swizzle="true">B</src> 1162 </group> 1163 1164 <group name="V2F32_TO_V2F16" title="Vectorized floating-point conversion" dests="1" opcode2="4"> 1165 <ins name="V2F32_TO_V2F16" opcode="0xA5"/> 1166 <desc> 1167 Given a pair of 32-bit floats, output a pair of 16-bit floats packed into 1168 a 32-bit destination. 1169 </desc> 1170 <src>A</src> 1171 <src>B</src> 1172 </group> 1173 1174 <group name="FRSCALE" title="Floating-point rescaling" dests="1" opcode2="6"> 1175 <ins name="FRSCALE.f32" opcode="0xA4"/> 1176 <ins name="FRSCALE.v2f16" opcode="0xA5"/> 1177 <desc> 1178 Computes $A \cdot 2^B$ by adding B to the exponent of A. Used to calculate 1179 various special functions, particularly base-2 exponents. Special case 1180 handling differs from an actual floating-point multiply, so this should 1181 not be used outside fixed instruction sequences. 1182 </desc> 1183 <clamp/> 1184 <src absneg="true" swizzle="true">A</src> 1185 <src absneg="true" swizzle="true">B</src> 1186 </group> 1187 1188 <ins name="FEXP.f32" title="Floating-point exponent" dests="1" opcode="0xA4" opcode2="8"> 1189 <desc> 1190 Calculates the base-2 exponent of an argument specified as a 8:24 1191 fixed-point. The original argument is passed as well for correct handling 1192 of special cases. 1193 </desc> 1194 <clamp/> 1195 <src>Input as 8:24 fixed-point</src> 1196 <src absneg="true">Input as 32-bit float</src> 1197 </ins> 1198 1199 <ins name="FADD_LSCALE.f32" title="Floating-point add with logarithm scale" dests="1" opcode="0xA4" opcode2="9"> 1200 <desc> 1201 Performs a floating-point addition specialized for logarithm computation. 1202 </desc> 1203 <clamp/> 1204 <src absneg="true">A</src> 1205 <src absneg="true">B</src> 1206 </ins> 1207 1208 <group name="IADD" title="Integer addition" dests="1" opcode2="0"> 1209 <desc> 1210 $A + B$ with optional saturation. 1211 1212 As Valhall lacks swizzle instructions, `IADD.v2i16` with zero is the 1213 canonical lowering for swizzles. 1214 </desc> 1215 <ins name="IADD.u32" opcode="0xA0"/> 1216 <ins name="IADD.v2u16" opcode="0xA1"/> 1217 <ins name="IADD.v4u8" opcode="0xA2"/> 1218 <ins name="IADD.s32" opcode="0xA8"/> 1219 <ins name="IADD.v2s16" opcode="0xA9"/> 1220 <ins name="IADD.v4s8" opcode="0x1A2"/> 1221 <ins name="IADD.u64" opcode="0x1A3"/> 1222 <ins name="IADD.s64" opcode="0x1AB"/> 1223 <!-- <ins name="IADD.s32" opcode="0x1A0"/> --> 1224 <src widen="true">A</src> 1225 <src widen="true">B</src> 1226 <saturate/> 1227 </group> 1228 1229 <ins name="MKVEC.v2i16" title="Make 16-bit vector" dests="1" opcode="0xA1" opcode2="0x5"> 1230 <desc>Calculates $A | (B \ll 16)$. Used to implement `(ushort2)(A, B)`</desc> 1231 <src widen="true">A</src> 1232 <src widen="true">B</src> 1233 </ins> 1234 1235 <group name="ISUB" title="Integer subtract" dests="1" opcode2="1"> 1236 <ins name="ISUB.u32" opcode="0xA0"/> 1237 <ins name="ISUB.v2u16" opcode="0xA1"/> 1238 <ins name="ISUB.v4u8" opcode="0xA2"/> 1239 <ins name="ISUB.s32" opcode="0xA8"/> 1240 <ins name="ISUB.v2s16" opcode="0xA9"/> 1241 <ins name="ISUB.v4s8" opcode="0x1A2"/> 1242 <ins name="ISUB.u64" opcode="0x1A3"/> 1243 <ins name="ISUB.s64" opcode="0x1AB"/> 1244 <desc>$A - B$ with optional saturation</desc> 1245 <src widen="true">A</src> 1246 <src widen="true">B</src> 1247 <saturate/> 1248 </group> 1249 1250 <group name="SHADDX" title="Shift, extend, and 64-bit add" dests="1" opcode2="7"> 1251 <desc> 1252 Sign or zero extend B to 64-bits, left-shift by `shift`, and add the 1253 64-bit value A. These instructions accelerate address arithmetic, but may 1254 be used in full generality for 64-bit integer arithmetic. 1255 </desc> 1256 <ins name="SHADDX.u64" opcode="0x1A3"/> 1257 <ins name="SHADDX.s64" opcode="0x1AB"/> 1258 <imm name="shift" start="20" size="3"/> 1259 <src>A</src> 1260 <src widen="true">B</src> 1261 </group> 1262 1263 <group name="IMUL" title="Integer multiply" dests="1" opcode2="0x0A"> 1264 <ins name="IMUL.i32" opcode="0xA0"/> 1265 <ins name="IMUL.v2i16" opcode="0xA1"/> 1266 <ins name="IMUL.v4i8" opcode="0xA2"/> 1267 <ins name="IMUL.s32" opcode="0xA8"/> 1268 <ins name="IMUL.v2s16" opcode="0xA9"/> 1269 <ins name="IMUL.v4s8" opcode="0x1A2"/> 1270 <ins name="IMULD.u64" opcode="0x1A3"/> 1271 <!-- <ins name="IMUL.s32" opcode="0x1A0"/> --> 1272 <desc> 1273 $A \cdot B$ with optional saturation. Note the multipliers can only handle up to 1274 32-bit by 32-bit multiplies. The 64-bit "multiply" acts like IMUL.u32 but 1275 additionally writes the high half of the product to the high half of the 1276 64-bit destination. Along with IADD.u32 and IADD.u64, this allows the 1277 construction of a 64-bit multiply in 5 instructions (6 clocks). 1278 </desc> 1279 <src widen="true">A</src> 1280 <src widen="true">B</src> 1281 <saturate/> 1282 </group> 1283 1284 <group name="HADD" title="Integer half-add" dests="1" opcode2="0x0B"> 1285 <ins name="HADD.u32" opcode="0xA0"/> 1286 <ins name="HADD.v2u16" opcode="0xA1"/> 1287 <ins name="HADD.v4u8" opcode="0xA2"/> 1288 <ins name="HADD.s32" opcode="0xA8"/> 1289 <ins name="HADD.v2s16" opcode="0xA9"/> 1290 <ins name="HADD.v4s8" opcode="0x1A2"/> 1291 <mod name="rhadd" start="30" size="1"/> 1292 <src widen="true">A</src> 1293 <src widen="true">B</src> 1294 <desc> 1295 $(A + B) \gg 1$ without intermediate overflow, corresponding to `hadd()` in 1296 OpenCL. With the `.rhadd` modifier set, it instead calculates 1297 $(A + B + 1) \gg 1$ corresponding to `rhadd()` in OpenCL. 1298 </desc> 1299 </group> 1300 1301 <group name="CLPER" title="Cross-lane permute" dests="1" opcode2="0xF"> 1302 <ins name="CLPER.i32" opcode="0xA0"/> 1303 <ins name="CLPER.v2u16" opcode="0xA1"/> 1304 <ins name="CLPER.v4u8" opcode="0xA2"/> 1305 <ins name="CLPER.s32" opcode="0xA8"/> 1306 <ins name="CLPER.v2s16" opcode="0xA9"/> 1307 <ins name="CLPER.v4s8" opcode="0x1A2"/> 1308 <ins name="CLPER.u64" opcode="0x1A3"/> 1309 <ins name="CLPER.s64" opcode="0x1AB"/> 1310 <!-- <ins name="CLPER.s32" opcode="0x1A0"/> --> 1311 <desc> 1312 Selects the value of A in the subgroup lane given by B. This implements 1313 subgroup broadcasts. It may be used as a primitive for screen space 1314 derivatives in fragment shaders. 1315 </desc> 1316 <src>A</src> 1317 <src widen="true">B</src> 1318 <subgroup/> 1319 <lane_op/> 1320 <inactive_result/> 1321 </group> 1322 1323 <group name="FMA" title="Fused floating-point multiply add" dests="1"> 1324 <ins name="FMA.f32" opcode="0xB2"/> 1325 <ins name="FMA.v2f16" opcode="0xB3"/> 1326 <desc>$A \cdot B + C$</desc> 1327 <clamp/> 1328 <src absneg="true" swizzle="true">A</src> 1329 <src absneg="true" swizzle="true">B</src> 1330 <src absneg="true" swizzle="true">C</src> 1331 </group> 1332 1333 <group name="LSHIFT_AND" title="Left shift and bitwise AND" dests="1" opcode2="0x100"> 1334 <ins name="LSHIFT_AND.i32" opcode="0xB4"/> 1335 <ins name="LSHIFT_AND.v2i16" opcode="0xB5"/> 1336 <ins name="LSHIFT_AND.v4i8" opcode="0xB6"/> 1337 <ins name="LSHIFT_AND.i64" opcode="0x1B7"/> 1338 <mod name="left" start="128" size="1" implied="true"/> 1339 <desc> 1340 Left shifts its first source by a specified amount and bitwise ANDs it with the 1341 second source, optionally inverting the second source or the result. 1342 </desc> 1343 <not_result/> 1344 <src widen="true">A</src> 1345 <src lanes="true" size="8">shift</src> 1346 <src not="true">B</src> 1347 </group> 1348 1349 <group name="RSHIFT_AND" title="Right shift and bitwise AND" dests="1" opcode2="0x000"> 1350 <ins name="RSHIFT_AND.i32" opcode="0xB4"/> 1351 <ins name="RSHIFT_AND.v2i16" opcode="0xB5"/> 1352 <ins name="RSHIFT_AND.v4i8" opcode="0xB6"/> 1353 <ins name="RSHIFT_AND.i64" opcode="0x1B7"/> 1354 <mod name="left" start="128" size="1" implied="true"/> 1355 <desc> 1356 Right shifts its first source by a specified amount and bitwise ANDs it with the 1357 second source, optionally inverting the second source or the result. 1358 </desc> 1359 <not_result/> 1360 <src widen="true">A</src> 1361 <src lanes="true" size="8">shift</src> 1362 <src not="true">B</src> 1363 </group> 1364 1365 <group name="LSHIFT_OR" title="Left shift and bitwise OR" dests="1" opcode2="0x101"> 1366 <ins name="LSHIFT_OR.i32" opcode="0xB4"/> 1367 <ins name="LSHIFT_OR.v2i16" opcode="0xB5"/> 1368 <ins name="LSHIFT_OR.v4i8" opcode="0xB6"/> 1369 <ins name="LSHIFT_OR.i64" opcode="0x1B7"/> 1370 <mod name="left" start="128" size="1" implied="true"/> 1371 <desc> 1372 Left shifts its first source by a specified amount and bitwise ORs it with the 1373 second source, optionally inverting the second source or the result. 1374 </desc> 1375 <not_result/> 1376 <src widen="true">A</src> 1377 <src lanes="true" size="8">shift</src> 1378 <src not="true">B</src> 1379 </group> 1380 1381 <group name="RSHIFT_OR" title="Right shift and bitwise OR" dests="1" opcode2="0x001"> 1382 <ins name="RSHIFT_OR.i32" opcode="0xB4"/> 1383 <ins name="RSHIFT_OR.v2i16" opcode="0xB5"/> 1384 <ins name="RSHIFT_OR.v4i8" opcode="0xB6"/> 1385 <ins name="RSHIFT_OR.i64" opcode="0x1B7"/> 1386 <mod name="left" start="128" size="1" implied="true"/> 1387 <desc> 1388 Right shifts its first source by a specified amount and bitwise ORs it with the 1389 second source, optionally inverting the second source or the result. 1390 </desc> 1391 <not_result/> 1392 <src widen="true">A</src> 1393 <src lanes="true" size="8">shift</src> 1394 <src not="true">B</src> 1395 </group> 1396 1397 <group name="LSHIFT_XOR" title="Left shift and bitwise XOR" dests="1" opcode2="0x102"> 1398 <ins name="LSHIFT_XOR.i32" opcode="0xB4"/> 1399 <ins name="LSHIFT_XOR.v2i16" opcode="0xB5"/> 1400 <ins name="LSHIFT_XOR.v4i8" opcode="0xB6"/> 1401 <ins name="LSHIFT_XOR.i64" opcode="0x1B7"/> 1402 <mod name="left" start="128" size="1" implied="true"/> 1403 <desc> 1404 Left shifts its first source by a specified amount and bitwise XORs it with the 1405 second source, optionally inverting the second source or the result. 1406 </desc> 1407 <not_result/> 1408 <src widen="true">A</src> 1409 <src lanes="true" size="8">shift</src> 1410 <src not="true">B</src> 1411 </group> 1412 1413 <group name="RSHIFT_XOR" title="Right shift and bitwise XOR" dests="1" opcode2="0x002"> 1414 <ins name="RSHIFT_XOR.i32" opcode="0xB4"/> 1415 <ins name="RSHIFT_XOR.v2i16" opcode="0xB5"/> 1416 <ins name="RSHIFT_XOR.v4i8" opcode="0xB6"/> 1417 <ins name="RSHIFT_XOR.i64" opcode="0x1B7"/> 1418 <mod name="left" start="128" size="1" implied="true"/> 1419 <desc> 1420 Right shifts its first source by a specified amount and bitwise XORs it with the 1421 second source, optionally inverting the second source or the result. 1422 </desc> 1423 <not_result/> 1424 <src widen="true">A</src> 1425 <src lanes="true" size="8">shift</src> 1426 <src not="true">B</src> 1427 </group> 1428 1429 <ins name="MUX.i32" title="Mux" dests="1" opcode="0xB8"> 1430 <desc> 1431 Mux between A and B based on the provided mask. Equivalent to 1432 `bitselect()` in OpenCL. `(A & mask) | (A & ~mask)` 1433 </desc> 1434 <src>A</src> 1435 <src>B</src> 1436 <src>Mask</src> 1437 </ins> 1438 1439 <ins name="CUBE_SSEL" title="Cube S-coordinate select" dests="1" opcode="0xBC" opcode2="0"> 1440 <desc>During a cube map transform, select the S coordinate given a selected face.</desc> 1441 <src absneg="true">Z coordinate as 32-bit floating point</src> 1442 <src absneg="true">X coordinate as 32-bit floating point</src> 1443 <src>Cube face index</src> 1444 </ins> 1445 1446 <ins name="CUBE_TSEL" title="Cube T-coordinate select" dests="1" opcode="0xBC" opcode2="1"> 1447 <desc>During a cube map transform, select the T coordinate given a selected face.</desc> 1448 <src absneg="true">Y coordinate as 32-bit floating point</src> 1449 <src absneg="true">Z coordinate as 32-bit floating point</src> 1450 <src>Cube face index</src> 1451 </ins> 1452 1453 <ins name="MKVEC.v4i8" title="Make 8-bit vector" dests="1" opcode="0xBD"> 1454 <desc> 1455 Calculates $A | (B \ll 8) | (CD \ll 16)$ for 8-bit A and B and 16-bit CD. 1456 1457 To implement `(uchar4) (A, B, C, D)` in full generality, use the sequence 1458 `MKVEC.v4i8 CD, C, D, #0; MKVEC.v4i8 out, A, B, CD` 1459 1460 `MKVEC.v4i8` also allows zero extending arbitrary 8-bit lanes. For 1461 example, to extend `r0.b3` to `r1`, use `MKVEC.v4i8 r1, r0.b3, 0x0.b0, 0x0`. 1462 </desc> 1463 <src lane="true">A</src> 1464 <src lane="true">B</src> 1465 <src>CD</src> 1466 </ins> 1467 1468 <ins name="CUBEFACE1" title="Cube map transform step 1" dests="1" opcode="0xC0"> 1469 <desc>Select the maximum absolute value of its arguments.</desc> 1470 <src absneg="true">X coordinate as 32-bit floating point</src> 1471 <src absneg="true">Y coordinate as 32-bit floating point</src> 1472 <src absneg="true">Z coordinate as 32-bit floating point</src> 1473 </ins> 1474 1475 <ins name="CUBEFACE2" title="Cube map transform step 2" dests="1" opcode="0xC1"> 1476 <desc>Select the cube face index corresponding to the arguments.</desc> 1477 <src absneg="true">X coordinate as 32-bit floating point</src> 1478 <src absneg="true">Y coordinate as 32-bit floating point</src> 1479 <src absneg="true">Z coordinate as 32-bit floating point</src> 1480 </ins> 1481 1482 <group name="IDP" title="8-bit dot product" dests="1" opcode="0xC2"> 1483 <desc> 1484 8-bit integer dot product between 4 channel vectors, intended for machine 1485 learning. Available in both unsigned and signed variants, controlling 1486 sign-extension/zero-extension behaviour to the final 32-bit destination. 1487 Saturation is available. Corresponds to the `cl_arm_integer_dot_product_*` 1488 family of OpenCL extensions. Not for actual use, just for completeness. 1489 Instead, use your platform's neural accelerator. 1490 1491 For $A, B \in \{ 0, \ldots, 255 \}^4$ and $\text{Accumulator} \in 1492 \mathbb{Z}$, calculates $(A \cdot B) + \text{Accumulator}$ and optionally 1493 saturates. 1494 </desc> 1495 <ins name="IDP.v4s8" opcode2="0"/> 1496 <ins name="IDP.v4u8" opcode2="1"/> 1497 <src>A</src> 1498 <src>B</src> 1499 <src>Accumulator</src> 1500 <saturate/> 1501 </group> 1502 1503 <group name="ICMP" title="Unsigned integer compare" dests="1"> 1504 <desc> 1505 Evaluates the given condition, do a logical and/or with the condition in 1506 the result source, and return in the given result type (integer 1507 one, integer minus one, or floating-point one). The third source is useful 1508 for chaining together conditions without intermediate bitwise arithmetic; 1509 when this is not desired, tie it to zero and use the OR combine mode (do 1510 not set the `.and` modifier). 1511 1512 The sequence modifier `.seq` is used to construct 64-bit compares in 2 1513 `ICMP.u32` instructions, in conjunction with the `u1` result type on the 1514 low half, the `m1` result type on the high half, and the result of the low 1515 half comparison passed as the third source. For comparisons other than 1516 64-bit, do not set the `.seq` modifier and do not use the `u1` result 1517 type. 1518 </desc> 1519 <ins name="ICMP.u32" opcode="0xF0"/> 1520 <ins name="ICMP.v2u16" opcode="0xF1"/> 1521 <ins name="ICMP.v4u8" opcode="0xF2"/> 1522 <cmp/> 1523 <result_type/> 1524 <mod name="and" start="24" size="1"/> 1525 <mod name="seq" start="25" size="1"/> 1526 <src widen="true">A</src> 1527 <src widen="true">B</src> 1528 <src>C</src> 1529 </group> 1530 1531 <group name="FCMP" title="Floating-point compare" dests="1"> 1532 <desc> 1533 Evaluates the given condition, do a logical and/or with the condition in 1534 the result source, and return in the given result type (integer 1535 one, integer minus one, or floating-point one). The third source is useful 1536 for chaining together conditions without intermediate bitwise arithmetic; 1537 when this is not desired, tie it to zero and use the OR combine mode (do 1538 not set the `.and` modifier). 1539 </desc> 1540 <ins name="FCMP.f32" opcode="0xF4"/> 1541 <ins name="FCMP.v2f16" opcode="0xF5"/> 1542 <cmp/> 1543 <result_type/> 1544 <mod name="and" start="24" size="1"/> 1545 <src absneg="true" swizzle="true">A</src> 1546 <src absneg="true" swizzle="true">B</src> 1547 <src>C</src> 1548 </group> 1549 1550 <group name="ICMP" title="Signed integer compare" dests="1"> 1551 <desc> 1552 Evaluates the given condition, do a logical and/or with the condition in 1553 the result source, and return in the given result type (integer 1554 one, integer minus one, or floating-point one). The third source is useful 1555 for chaining together conditions without intermediate bitwise arithmetic; 1556 when this is not desired, tie it to zero and use the OR combine mode (do 1557 not set the `.and` modifier). 1558 1559 The sequence modifier `.seq` is used to construct signed 64-bit compares 1560 in 1 `ICMP.u32` and 1 `ICMP.s32` instruction, in conjunction with the `u1` 1561 result type on the low half, the `m1` result type on the high half, and 1562 the result of the low half comparison passed as the third source. For 1563 comparisons other than 64-bit, do not set the `.seq` modifier and do not 1564 use the `u1` result type. 1565 </desc> 1566 <ins name="ICMP.s32" opcode="0xF8"/> 1567 <ins name="ICMP.v2s16" opcode="0xF9"/> 1568 <ins name="ICMP.v4s8" opcode="0xFA"/> 1569 <cmp/> 1570 <result_type/> 1571 <mod name="and" start="24" size="1"/> 1572 <mod name="seq" start="25" size="1"/> 1573 <src widen="true">A</src> 1574 <src widen="true">B</src> 1575 <src>C</src> 1576 </group> 1577 1578 <ins name="IADD_IMM.i32" title="Integer addition with immediate" dests="1" opcode="0x110"> 1579 <desc> 1580 Adds an arbitrary 32-bit immediate embedded within the instruction stream. 1581 If no modifiers are required, this is preferred to `IADD.i32` with a 1582 constant accessed as a uniform. However, if the constant is available 1583 inline, `IADD.f32` is preferred. 1584 1585 `IADD_IMM.i32` with the source tied to zero is the canonical immediate move. 1586 </desc> 1587 <src>A</src> 1588 <imm name="constant" start="8" size="32"/> 1589 </ins> 1590 1591 <ins name="IADD_IMM.v2i16" title="Integer addition with immediate" dests="1" opcode="0x111"> 1592 <desc> 1593 Adds an arbitrary pair of 16-bit immediates embedded within the 1594 instruction stream. If no modifiers are required, this is preferred to 1595 `IADD.v2i16` with a constant accessed as a uniform. However, if the 1596 constant is available inline, `IADD.v2i16` is preferred. Adding only a 1597 single 16-bit constant requires replication of the constant. 1598 </desc> 1599 <src>A</src> 1600 <imm name="constant" start="8" size="32"/> 1601 </ins> 1602 1603 <ins name="IADD_IMM.v4i8" title="Integer addition with immediate" dests="1" opcode="0x112"> 1604 <desc> 1605 Adds an arbitrary quad of 8-bit immediates embedded within the 1606 instruction stream. If no modifiers are required, this is preferred to 1607 `IADD.v4i8` with a constant accessed as a uniform. However, if the 1608 constant is available inline, `IADD.v4i8` is preferred. Adding only a 1609 single 8-bit constant requires replication of the constant. 1610 </desc> 1611 <src>A</src> 1612 <imm name="constant" start="8" size="32"/> 1613 </ins> 1614 1615 <ins name="FADD_IMM.f32" title="Floating-point addition with immediate" dests="1" opcode="0x114"> 1616 <desc> 1617 Adds an arbitrary 32-bit immediate embedded within the instruction stream. 1618 If no modifiers are required, this is preferred to `FADD.f32` with a 1619 constant accessed as a uniform. However, if the constant is available 1620 inline, `FADD.f32` is preferred. 1621 </desc> 1622 <src>A</src> 1623 <imm name="constant" start="8" size="32"/> 1624 </ins> 1625 1626 <ins name="FADD_IMM.v2f16" title="Floating-point addition with immediate" dests="1" opcode="0x115"> 1627 <desc> 1628 Adds an arbitrary pair of 16-bit immediates embedded within the 1629 instruction stream. If no modifiers are required, this is preferred to 1630 `FADD.v2f16` with a constant accessed as a uniform. However, if the 1631 constant is available inline, `FADD.v2f16` is preferred. Adding only a 1632 single 16-bit constant requires replication of the constant. 1633 </desc> 1634 <src float="true">A</src> 1635 <imm name="constant" start="8" size="32"/> 1636 </ins> 1637 1638 <ins name="TODO.ATOM_C1" title="Atomic operations on memory with 1" opcode="0x69"> 1639 <!-- TODO --> 1640 <mod name="i32" start="17" size="1"/> 1641 <mod name="unk" start="23" size="1"/> 1642 <sr write="true"/> 1643 <src/> 1644 <imm name="operation" start="24" size="6"/> 1645 <sr_count/> 1646 <slot/> 1647 </ins> 1648 1649 <ins name="TODO.ATOM_C" title="Atomic operations on memory" opcode="0x120"> 1650 <!-- TODO --> 1651 <mod name="i32" start="17" size="1"/> 1652 <mod name="unk" start="23" size="1"/> 1653 <sr read="true" write="true"/> 1654 <src/> 1655 <imm name="operation" start="24" size="6"/> 1656 <sr_count/> 1657 <slot/> 1658 </ins> 1659 1660 <ins name="TEX_FETCH" title="Texel fetch" opcode="0x125"> 1661 <desc>Unfiltered textured instruction.</desc> 1662 <sr read="true"/> 1663 <sr write="true" count="4"/> 1664 <mod name="explicit_offset" start="11" size="1"/> 1665 <mod name="dimension" start="28" size="2"/> 1666 <mod name="skip" start="39" size="1"/> 1667 <sr_count/> 1668 <slot/> 1669 <src>Image to read from</src> 1670 </ins> 1671 1672 <ins name="TEX" title="Texture load" opcode="0x128"> 1673 <desc>Ordinary texturing instruction using a sampler.</desc> 1674 <sr read="true"/> 1675 <sr write="true" count="4"/> 1676 <src>Image to read from</src> 1677 <mod name="explicit_offset" start="11" size="1"/> 1678 <mod name="shadow" start="12" size="1"/> 1679 <mod name="lod_mode" start="13" size="3"/> 1680 <mod name="dimension" start="28" size="2"/> 1681 <mod name="skip" start="39" size="1"/> 1682 <sr_count/> 1683 <slot/> 1684 </ins> 1685 1686 <ins name="TODO.VAR_TEX" title="Fused varying-texturing" opcode="0x130"> 1687 <desc>Only works for FP32 varyings.</desc> 1688 <sr write="true" count="4"/> 1689 <mod name="dimension" start="28" size="2"/> 1690 <mod name="skip" start="39" size="1"/> 1691 <slot/> 1692 <src>Image to read from</src> 1693 </ins> 1694 1695 <ins name="FMA_RSCALE.f32" title="Fused floating-point multiply add with exponent bias" dests="1" opcode="0x160"> 1696 <desc> 1697 First calculates $A \cdot B + C$ and then biases the exponent by D. Used in 1698 special transcendental function sequences. It should not be used for 1699 general code as its special case handling differs from two back-to-back 1700 `FMA.f32` operations. Equivalent to `FMA.f32` back-to-back with 1701 `RSCALE.f32` 1702 </desc> 1703 <clamp/> 1704 <src absneg="true">A</src> 1705 <src absneg="true">B</src> 1706 <src absneg="true">C</src> 1707 <src>D</src> 1708 </ins> 1709 1710</valhall> 1711