1/*
2 * Copyright (C) 2019 Collabora, Ltd.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24#ifndef __MDG_QUIRKS_H
25#define __MDG_QUIRKS_H
26
27/* Model-specific quirks requiring compiler workarounds/etc. Quirks
28 * may be errata requiring a workaround, or features. We're trying to be
29 * quirk-positive here; quirky is the best! */
30
31/* bit 0 unused */
32
33/* Whether output texture registers (normally r28/r29) overlap with work
34 * registers r0/r1 and input texture registers (also normally r28/r29) overlap
35 * with load/store registers r26/r27. This constrains register allocation
36 * considerably but is a space-saving measure on small Midgards. It's worth
37 * noting if you try to access r28/r29, it may still work, but you'll mess up
38 * the interference. Corresponds to BASE_HW_FEATURE_INTERPIPE_REG_ALIASING in
39 * kbase. */
40
41#define MIDGARD_INTERPIPE_REG_ALIASING (1 << 1)
42
43/* Whether we should use old-style blend opcodes */
44
45#define MIDGARD_OLD_BLEND (1 << 2)
46
47/* Errata causing the LOD clamps and bias in the sampler descriptor to be
48 * ignored. This errata affects the command stream but uses a compiler
49 * workaround (applying the clamps/bias manually in the shader. Corresponds in
50 * BASE_HW_ISSUE_10471 in kbase, described as "TEXGRD doesn't honor Sampler
51 * Descriptor LOD clamps nor bias". (I'm assuming TEXGRD is what we call
52 * textureLod) */
53
54#define MIDGARD_BROKEN_LOD (1 << 3)
55
56/* Don't use upper ALU tags for writeout (if you do, you'll get a
57 * INSTR_INVALID_ENC). It's not clear to me what these tags are for. */
58
59#define MIDGARD_NO_UPPER_ALU (1 << 4)
60
61/* Whether (texture) out-of-order execution support is missing on early
62 * Midgards. For these just set the OoO bits to 0. */
63
64#define MIDGARD_NO_OOO (1 << 5)
65
66static inline unsigned
67midgard_get_quirks(unsigned gpu_id)
68{
69        switch (gpu_id) {
70        case 0x600:
71        case 0x620:
72                return MIDGARD_OLD_BLEND |
73                        MIDGARD_BROKEN_LOD |
74                        MIDGARD_NO_UPPER_ALU |
75                        MIDGARD_NO_OOO;
76
77        case 0x720:
78                return MIDGARD_INTERPIPE_REG_ALIASING |
79                        MIDGARD_OLD_BLEND |
80                        MIDGARD_BROKEN_LOD |
81                        MIDGARD_NO_UPPER_ALU |
82                        MIDGARD_NO_OOO;
83
84        case 0x820:
85        case 0x830:
86                return MIDGARD_INTERPIPE_REG_ALIASING;
87
88        case 0x750:
89                return MIDGARD_NO_UPPER_ALU;
90
91        case 0x860:
92        case 0x880:
93                return 0;
94
95        default:
96                unreachable("Invalid Midgard GPU ID");
97        }
98}
99
100#endif
101