1/*
2 * Copyright © 2021 Collabora, Ltd.
3 * Author: Antonio Caggiano <antonio.caggiano@collabora.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a copy
6 * of this software and associated documentation files (the "Software"), to deal
7 * in the Software without restriction, including without limitation the rights
8 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9 * copies of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21 * THE SOFTWARE.
22 */
23
24#include "pan_perf.h"
25
26#include <pan_perf_metrics.h>
27#include <lib/pan_device.h>
28#include <drm-uapi/panfrost_drm.h>
29
30#define PAN_COUNTERS_PER_CATEGORY 64
31#define PAN_SHADER_CORE_INDEX 2
32
33uint32_t
34panfrost_perf_counter_read(const struct panfrost_perf_counter *counter,
35                           const struct panfrost_perf *perf)
36{
37   assert(counter->offset < perf->n_counter_values);
38   uint32_t ret = perf->counter_values[counter->offset];
39
40   // If counter belongs to shader core, accumulate values for all other cores
41   if (counter->category == &perf->cfg->categories[PAN_SHADER_CORE_INDEX]) {
42      for (uint32_t core = 1; core < perf->dev->core_count; ++core) {
43         ret += perf->counter_values[counter->offset + PAN_COUNTERS_PER_CATEGORY * core];
44      }
45   }
46
47   return ret;
48}
49
50static const struct panfrost_perf_config*
51get_perf_config(unsigned int gpu_id)
52{
53   switch (gpu_id) {
54   case 0x720:
55      return &panfrost_perf_config_t72x;
56   case 0x750:
57      return &panfrost_perf_config_t76x;
58   case 0x820:
59      return &panfrost_perf_config_t82x;
60   case 0x830:
61      return &panfrost_perf_config_t83x;
62   case 0x860:
63      return &panfrost_perf_config_t86x;
64   case 0x880:
65      return &panfrost_perf_config_t88x;
66   case 0x6221:
67      return &panfrost_perf_config_thex;
68   case 0x7093:
69      return &panfrost_perf_config_tdvx;
70   case 0x7212:
71   case 0x7402:
72      return &panfrost_perf_config_tgox;
73   default:
74      unreachable("Invalid GPU ID");
75   }
76}
77
78void
79panfrost_perf_init(struct panfrost_perf *perf, struct panfrost_device *dev)
80{
81   perf->dev = dev;
82   perf->cfg = get_perf_config(dev->gpu_id);
83
84   // Generally counter blocks are laid out in the following order:
85   // Job manager, tiler, L2 cache, and one or more shader cores.
86   uint32_t n_blocks = 3 + dev->core_count;
87   perf->n_counter_values = PAN_COUNTERS_PER_CATEGORY * n_blocks;
88   perf->counter_values = ralloc_array(perf, uint32_t, perf->n_counter_values);
89}
90
91static int
92panfrost_perf_query(struct panfrost_perf *perf, uint32_t enable)
93{
94   struct drm_panfrost_perfcnt_enable perfcnt_enable = {enable, 0};
95   return drmIoctl(perf->dev->fd, DRM_IOCTL_PANFROST_PERFCNT_ENABLE, &perfcnt_enable);
96}
97
98int
99panfrost_perf_enable(struct panfrost_perf *perf)
100{
101   return panfrost_perf_query(perf, 1 /* enable */);
102}
103
104int
105panfrost_perf_disable(struct panfrost_perf *perf)
106{
107   return panfrost_perf_query(perf, 0 /* disable */);
108}
109
110int
111panfrost_perf_dump(struct panfrost_perf *perf)
112{
113   // Dump performance counter values to the memory buffer pointed to by counter_values
114   struct drm_panfrost_perfcnt_dump perfcnt_dump = {(uint64_t)(uintptr_t)perf->counter_values};
115   return drmIoctl(perf->dev->fd, DRM_IOCTL_PANFROST_PERFCNT_DUMP, &perfcnt_dump);
116}
117