101e04c3fSmrg/**************************************************************************
201e04c3fSmrg *
301e04c3fSmrg * Copyright 2008 VMware, Inc.
401e04c3fSmrg * All Rights Reserved.
501e04c3fSmrg *
601e04c3fSmrg * Permission is hereby granted, free of charge, to any person obtaining a
701e04c3fSmrg * copy of this software and associated documentation files (the
801e04c3fSmrg * "Software"), to deal in the Software without restriction, including
901e04c3fSmrg * without limitation the rights to use, copy, modify, merge, publish,
1001e04c3fSmrg * distribute, sub license, and/or sell copies of the Software, and to
1101e04c3fSmrg * permit persons to whom the Software is furnished to do so, subject to
1201e04c3fSmrg * the following conditions:
1301e04c3fSmrg *
1401e04c3fSmrg * The above copyright notice and this permission notice (including the
1501e04c3fSmrg * next paragraph) shall be included in all copies or substantial portions
1601e04c3fSmrg * of the Software.
1701e04c3fSmrg *
1801e04c3fSmrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
1901e04c3fSmrg * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
2001e04c3fSmrg * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
2101e04c3fSmrg * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
2201e04c3fSmrg * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
2301e04c3fSmrg * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
2401e04c3fSmrg * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
2501e04c3fSmrg *
2601e04c3fSmrg **************************************************************************/
2701e04c3fSmrg
2801e04c3fSmrg
2901e04c3fSmrg#include "bitscan.h"
3001e04c3fSmrg
3101e04c3fSmrg#ifdef HAVE___BUILTIN_FFS
3201e04c3fSmrg#elif defined(_MSC_VER) && (_M_IX86 || _M_ARM || _M_AMD64 || _M_IA64)
3301e04c3fSmrg#else
3401e04c3fSmrgint
3501e04c3fSmrgffs(int i)
3601e04c3fSmrg{
3701e04c3fSmrg   int bit = 0;
3801e04c3fSmrg   if (!i)
3901e04c3fSmrg      return bit;
4001e04c3fSmrg   if (!(i & 0xffff)) {
4101e04c3fSmrg      bit += 16;
4201e04c3fSmrg      i >>= 16;
4301e04c3fSmrg   }
4401e04c3fSmrg   if (!(i & 0xff)) {
4501e04c3fSmrg      bit += 8;
4601e04c3fSmrg      i >>= 8;
4701e04c3fSmrg   }
4801e04c3fSmrg   if (!(i & 0xf)) {
4901e04c3fSmrg      bit += 4;
5001e04c3fSmrg      i >>= 4;
5101e04c3fSmrg   }
5201e04c3fSmrg   if (!(i & 0x3)) {
5301e04c3fSmrg      bit += 2;
5401e04c3fSmrg      i >>= 2;
5501e04c3fSmrg   }
5601e04c3fSmrg   if (!(i & 0x1))
5701e04c3fSmrg      bit += 1;
5801e04c3fSmrg   return bit + 1;
5901e04c3fSmrg}
6001e04c3fSmrg#endif
6101e04c3fSmrg
6201e04c3fSmrg#ifdef HAVE___BUILTIN_FFSLL
637ec681f3Smrg#elif defined(_MSC_VER) && (_M_AMD64 || _M_ARM64 || _M_IA64)
6401e04c3fSmrg#else
6501e04c3fSmrgint
6601e04c3fSmrgffsll(long long int val)
6701e04c3fSmrg{
6801e04c3fSmrg   int bit;
6901e04c3fSmrg
7001e04c3fSmrg   bit = ffs((unsigned) (val & 0xffffffff));
7101e04c3fSmrg   if (bit != 0)
7201e04c3fSmrg      return bit;
7301e04c3fSmrg
7401e04c3fSmrg   bit = ffs((unsigned) (val >> 32));
7501e04c3fSmrg   if (bit != 0)
7601e04c3fSmrg      return 32 + bit;
7701e04c3fSmrg
7801e04c3fSmrg   return 0;
7901e04c3fSmrg}
8001e04c3fSmrg#endif
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