etnaviv_drm.h revision d8807b2f 
1/*
2 * Copyright (C) 2015 Etnaviv Project
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published by
6 * the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program.  If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __ETNAVIV_DRM_H__
18#define __ETNAVIV_DRM_H__
19
20#include "drm.h"
21
22#if defined(__cplusplus)
23extern "C" {
24#endif
25
26/* Please note that modifications to all structs defined here are
27 * subject to backwards-compatibility constraints:
28 *  1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
29 *     user/kernel compatibility
30 *  2) Keep fields aligned to their size
31 *  3) Because of how drm_ioctl() works, we can add new fields at
32 *     the end of an ioctl if some care is taken: drm_ioctl() will
33 *     zero out the new fields at the tail of the ioctl, so a zero
34 *     value should have a backwards compatible meaning.  And for
35 *     output params, userspace won't see the newly added output
36 *     fields.. so that has to be somehow ok.
37 */
38
39/* timeouts are specified in clock-monotonic absolute times (to simplify
40 * restarting interrupted ioctls).  The following struct is logically the
41 * same as 'struct timespec' but 32/64b ABI safe.
42 */
43struct drm_etnaviv_timespec {
44	__s64 tv_sec;          /* seconds */
45	__s64 tv_nsec;         /* nanoseconds */
46};
47
48#define ETNAVIV_PARAM_GPU_MODEL                     0x01
49#define ETNAVIV_PARAM_GPU_REVISION                  0x02
50#define ETNAVIV_PARAM_GPU_FEATURES_0                0x03
51#define ETNAVIV_PARAM_GPU_FEATURES_1                0x04
52#define ETNAVIV_PARAM_GPU_FEATURES_2                0x05
53#define ETNAVIV_PARAM_GPU_FEATURES_3                0x06
54#define ETNAVIV_PARAM_GPU_FEATURES_4                0x07
55#define ETNAVIV_PARAM_GPU_FEATURES_5                0x08
56#define ETNAVIV_PARAM_GPU_FEATURES_6                0x09
57
58#define ETNAVIV_PARAM_GPU_STREAM_COUNT              0x10
59#define ETNAVIV_PARAM_GPU_REGISTER_MAX              0x11
60#define ETNAVIV_PARAM_GPU_THREAD_COUNT              0x12
61#define ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE         0x13
62#define ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT         0x14
63#define ETNAVIV_PARAM_GPU_PIXEL_PIPES               0x15
64#define ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE 0x16
65#define ETNAVIV_PARAM_GPU_BUFFER_SIZE               0x17
66#define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT         0x18
67#define ETNAVIV_PARAM_GPU_NUM_CONSTANTS             0x19
68#define ETNAVIV_PARAM_GPU_NUM_VARYINGS              0x1a
69
70#define ETNA_MAX_PIPES 4
71
72struct drm_etnaviv_param {
73	__u32 pipe;           /* in */
74	__u32 param;          /* in, ETNAVIV_PARAM_x */
75	__u64 value;          /* out (get_param) or in (set_param) */
76};
77
78/*
79 * GEM buffers:
80 */
81
82#define ETNA_BO_CACHE_MASK   0x000f0000
83/* cache modes */
84#define ETNA_BO_CACHED       0x00010000
85#define ETNA_BO_WC           0x00020000
86#define ETNA_BO_UNCACHED     0x00040000
87/* map flags */
88#define ETNA_BO_FORCE_MMU    0x00100000
89
90struct drm_etnaviv_gem_new {
91	__u64 size;           /* in */
92	__u32 flags;          /* in, mask of ETNA_BO_x */
93	__u32 handle;         /* out */
94};
95
96struct drm_etnaviv_gem_info {
97	__u32 handle;         /* in */
98	__u32 pad;
99	__u64 offset;         /* out, offset to pass to mmap() */
100};
101
102#define ETNA_PREP_READ        0x01
103#define ETNA_PREP_WRITE       0x02
104#define ETNA_PREP_NOSYNC      0x04
105
106struct drm_etnaviv_gem_cpu_prep {
107	__u32 handle;         /* in */
108	__u32 op;             /* in, mask of ETNA_PREP_x */
109	struct drm_etnaviv_timespec timeout;   /* in */
110};
111
112struct drm_etnaviv_gem_cpu_fini {
113	__u32 handle;         /* in */
114	__u32 flags;          /* in, placeholder for now, no defined values */
115};
116
117/*
118 * Cmdstream Submission:
119 */
120
121/* The value written into the cmdstream is logically:
122 * relocbuf->gpuaddr + reloc_offset
123 *
124 * NOTE that reloc's must be sorted by order of increasing submit_offset,
125 * otherwise EINVAL.
126 */
127struct drm_etnaviv_gem_submit_reloc {
128	__u32 submit_offset;  /* in, offset from submit_bo */
129	__u32 reloc_idx;      /* in, index of reloc_bo buffer */
130	__u64 reloc_offset;   /* in, offset from start of reloc_bo */
131	__u32 flags;          /* in, placeholder for now, no defined values */
132};
133
134/* Each buffer referenced elsewhere in the cmdstream submit (ie. the
135 * cmdstream buffer(s) themselves or reloc entries) has one (and only
136 * one) entry in the submit->bos[] table.
137 *
138 * As a optimization, the current buffer (gpu virtual address) can be
139 * passed back through the 'presumed' field.  If on a subsequent reloc,
140 * userspace passes back a 'presumed' address that is still valid,
141 * then patching the cmdstream for this entry is skipped.  This can
142 * avoid kernel needing to map/access the cmdstream bo in the common
143 * case.
144 */
145#define ETNA_SUBMIT_BO_READ             0x0001
146#define ETNA_SUBMIT_BO_WRITE            0x0002
147struct drm_etnaviv_gem_submit_bo {
148	__u32 flags;          /* in, mask of ETNA_SUBMIT_BO_x */
149	__u32 handle;         /* in, GEM handle */
150	__u64 presumed;       /* in/out, presumed buffer address */
151};
152
153/* Each cmdstream submit consists of a table of buffers involved, and
154 * one or more cmdstream buffers.  This allows for conditional execution
155 * (context-restore), and IB buffers needed for per tile/bin draw cmds.
156 */
157#define ETNA_SUBMIT_NO_IMPLICIT         0x0001
158#define ETNA_SUBMIT_FENCE_FD_IN         0x0002
159#define ETNA_SUBMIT_FENCE_FD_OUT        0x0004
160#define ETNA_SUBMIT_FLAGS		(ETNA_SUBMIT_NO_IMPLICIT | \
161					 ETNA_SUBMIT_FENCE_FD_IN | \
162					 ETNA_SUBMIT_FENCE_FD_OUT)
163#define ETNA_PIPE_3D      0x00
164#define ETNA_PIPE_2D      0x01
165#define ETNA_PIPE_VG      0x02
166struct drm_etnaviv_gem_submit {
167	__u32 fence;          /* out */
168	__u32 pipe;           /* in */
169	__u32 exec_state;     /* in, initial execution state (ETNA_PIPE_x) */
170	__u32 nr_bos;         /* in, number of submit_bo's */
171	__u32 nr_relocs;      /* in, number of submit_reloc's */
172	__u32 stream_size;    /* in, cmdstream size */
173	__u64 bos;            /* in, ptr to array of submit_bo's */
174	__u64 relocs;         /* in, ptr to array of submit_reloc's */
175	__u64 stream;         /* in, ptr to cmdstream */
176	__u32 flags;          /* in, mask of ETNA_SUBMIT_x */
177	__s32 fence_fd;       /* in/out, fence fd (see ETNA_SUBMIT_FENCE_FD_x) */
178};
179
180/* The normal way to synchronize with the GPU is just to CPU_PREP on
181 * a buffer if you need to access it from the CPU (other cmdstream
182 * submission from same or other contexts, PAGE_FLIP ioctl, etc, all
183 * handle the required synchronization under the hood).  This ioctl
184 * mainly just exists as a way to implement the gallium pipe_fence
185 * APIs without requiring a dummy bo to synchronize on.
186 */
187#define ETNA_WAIT_NONBLOCK      0x01
188struct drm_etnaviv_wait_fence {
189	__u32 pipe;           /* in */
190	__u32 fence;          /* in */
191	__u32 flags;          /* in, mask of ETNA_WAIT_x */
192	__u32 pad;
193	struct drm_etnaviv_timespec timeout;   /* in */
194};
195
196#define ETNA_USERPTR_READ	0x01
197#define ETNA_USERPTR_WRITE	0x02
198struct drm_etnaviv_gem_userptr {
199	__u64 user_ptr;	/* in, page aligned user pointer */
200	__u64 user_size;	/* in, page aligned user size */
201	__u32 flags;		/* in, flags */
202	__u32 handle;	/* out, non-zero handle */
203};
204
205struct drm_etnaviv_gem_wait {
206	__u32 pipe;				/* in */
207	__u32 handle;				/* in, bo to be waited for */
208	__u32 flags;				/* in, mask of ETNA_WAIT_x  */
209	__u32 pad;
210	struct drm_etnaviv_timespec timeout;	/* in */
211};
212
213#define DRM_ETNAVIV_GET_PARAM          0x00
214/* placeholder:
215#define DRM_ETNAVIV_SET_PARAM          0x01
216 */
217#define DRM_ETNAVIV_GEM_NEW            0x02
218#define DRM_ETNAVIV_GEM_INFO           0x03
219#define DRM_ETNAVIV_GEM_CPU_PREP       0x04
220#define DRM_ETNAVIV_GEM_CPU_FINI       0x05
221#define DRM_ETNAVIV_GEM_SUBMIT         0x06
222#define DRM_ETNAVIV_WAIT_FENCE         0x07
223#define DRM_ETNAVIV_GEM_USERPTR        0x08
224#define DRM_ETNAVIV_GEM_WAIT           0x09
225#define DRM_ETNAVIV_NUM_IOCTLS         0x0a
226
227#define DRM_IOCTL_ETNAVIV_GET_PARAM    DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param)
228#define DRM_IOCTL_ETNAVIV_GEM_NEW      DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new)
229#define DRM_IOCTL_ETNAVIV_GEM_INFO     DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, struct drm_etnaviv_gem_info)
230#define DRM_IOCTL_ETNAVIV_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep)
231#define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini)
232#define DRM_IOCTL_ETNAVIV_GEM_SUBMIT   DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, struct drm_etnaviv_gem_submit)
233#define DRM_IOCTL_ETNAVIV_WAIT_FENCE   DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence)
234#define DRM_IOCTL_ETNAVIV_GEM_USERPTR  DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr)
235#define DRM_IOCTL_ETNAVIV_GEM_WAIT     DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait)
236
237#if defined(__cplusplus)
238}
239#endif
240
241#endif /* __ETNAVIV_DRM_H__ */
242