drm.h revision 6260e5d5
1/** 2 * \file drm.h 3 * Header for the Direct Rendering Manager 4 * 5 * \author Rickard E. (Rik) Faith <faith@valinux.com> 6 * 7 * \par Acknowledgments: 8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg. 9 */ 10 11/* 12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 14 * All rights reserved. 15 * 16 * Permission is hereby granted, free of charge, to any person obtaining a 17 * copy of this software and associated documentation files (the "Software"), 18 * to deal in the Software without restriction, including without limitation 19 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 20 * and/or sell copies of the Software, and to permit persons to whom the 21 * Software is furnished to do so, subject to the following conditions: 22 * 23 * The above copyright notice and this permission notice (including the next 24 * paragraph) shall be included in all copies or substantial portions of the 25 * Software. 26 * 27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 33 * OTHER DEALINGS IN THE SOFTWARE. 34 */ 35 36#ifndef _DRM_H_ 37#define _DRM_H_ 38 39#if defined(__linux__) 40 41#include <linux/types.h> 42#include <asm/ioctl.h> 43typedef unsigned int drm_handle_t; 44 45#else /* One of the BSDs */ 46 47#include <sys/ioccom.h> 48#include <sys/types.h> 49#ifndef __linux_sized_types__ 50#define __linux_sized_types__ 51typedef int8_t __s8; 52typedef uint8_t __u8; 53typedef int16_t __s16; 54typedef uint16_t __u16; 55typedef int32_t __s32; 56typedef uint32_t __u32; 57typedef int64_t __s64; 58typedef uint64_t __u64; 59#endif /* __linux_sized_types__ */ 60typedef size_t __kernel_size_t; 61typedef unsigned long drm_handle_t; 62 63#endif 64 65#if defined(__cplusplus) 66extern "C" { 67#endif 68 69#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ 70#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ 71#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ 72#define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ 73 74#define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ 75#define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ 76#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) 77#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) 78#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) 79 80typedef unsigned int drm_context_t; 81typedef unsigned int drm_drawable_t; 82typedef unsigned int drm_magic_t; 83 84/** 85 * Cliprect. 86 * 87 * \warning: If you change this structure, make sure you change 88 * XF86DRIClipRectRec in the server as well 89 * 90 * \note KW: Actually it's illegal to change either for 91 * backwards-compatibility reasons. 92 */ 93struct drm_clip_rect { 94 unsigned short x1; 95 unsigned short y1; 96 unsigned short x2; 97 unsigned short y2; 98}; 99 100/** 101 * Drawable information. 102 */ 103struct drm_drawable_info { 104 unsigned int num_rects; 105 struct drm_clip_rect *rects; 106}; 107 108/** 109 * Texture region, 110 */ 111struct drm_tex_region { 112 unsigned char next; 113 unsigned char prev; 114 unsigned char in_use; 115 unsigned char padding; 116 unsigned int age; 117}; 118 119/** 120 * Hardware lock. 121 * 122 * The lock structure is a simple cache-line aligned integer. To avoid 123 * processor bus contention on a multiprocessor system, there should not be any 124 * other data stored in the same cache line. 125 */ 126struct drm_hw_lock { 127 __volatile__ unsigned int lock; /**< lock variable */ 128 char padding[60]; /**< Pad to cache line */ 129}; 130 131/** 132 * DRM_IOCTL_VERSION ioctl argument type. 133 * 134 * \sa drmGetVersion(). 135 */ 136struct drm_version { 137 int version_major; /**< Major version */ 138 int version_minor; /**< Minor version */ 139 int version_patchlevel; /**< Patch level */ 140 __kernel_size_t name_len; /**< Length of name buffer */ 141 char *name; /**< Name of driver */ 142 __kernel_size_t date_len; /**< Length of date buffer */ 143 char *date; /**< User-space buffer to hold date */ 144 __kernel_size_t desc_len; /**< Length of desc buffer */ 145 char *desc; /**< User-space buffer to hold desc */ 146}; 147 148/** 149 * DRM_IOCTL_GET_UNIQUE ioctl argument type. 150 * 151 * \sa drmGetBusid() and drmSetBusId(). 152 */ 153struct drm_unique { 154 __kernel_size_t unique_len; /**< Length of unique */ 155 char *unique; /**< Unique name for driver instantiation */ 156}; 157 158struct drm_list { 159 int count; /**< Length of user-space structures */ 160 struct drm_version *version; 161}; 162 163struct drm_block { 164 int unused; 165}; 166 167/** 168 * DRM_IOCTL_CONTROL ioctl argument type. 169 * 170 * \sa drmCtlInstHandler() and drmCtlUninstHandler(). 171 */ 172struct drm_control { 173 enum { 174 DRM_ADD_COMMAND, 175 DRM_RM_COMMAND, 176 DRM_INST_HANDLER, 177 DRM_UNINST_HANDLER 178 } func; 179 int irq; 180}; 181 182/** 183 * Type of memory to map. 184 */ 185enum drm_map_type { 186 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ 187 _DRM_REGISTERS = 1, /**< no caching, no core dump */ 188 _DRM_SHM = 2, /**< shared, cached */ 189 _DRM_AGP = 3, /**< AGP/GART */ 190 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ 191 _DRM_CONSISTENT = 5 /**< Consistent memory for PCI DMA */ 192}; 193 194/** 195 * Memory mapping flags. 196 */ 197enum drm_map_flags { 198 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ 199 _DRM_READ_ONLY = 0x02, 200 _DRM_LOCKED = 0x04, /**< shared, cached, locked */ 201 _DRM_KERNEL = 0x08, /**< kernel requires access */ 202 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ 203 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ 204 _DRM_REMOVABLE = 0x40, /**< Removable mapping */ 205 _DRM_DRIVER = 0x80 /**< Managed by driver */ 206}; 207 208struct drm_ctx_priv_map { 209 unsigned int ctx_id; /**< Context requesting private mapping */ 210 void *handle; /**< Handle of map */ 211}; 212 213/** 214 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls 215 * argument type. 216 * 217 * \sa drmAddMap(). 218 */ 219struct drm_map { 220 unsigned long offset; /**< Requested physical address (0 for SAREA)*/ 221 unsigned long size; /**< Requested physical size (bytes) */ 222 enum drm_map_type type; /**< Type of memory to map */ 223 enum drm_map_flags flags; /**< Flags */ 224 void *handle; /**< User-space: "Handle" to pass to mmap() */ 225 /**< Kernel-space: kernel-virtual address */ 226 int mtrr; /**< MTRR slot used */ 227 /* Private data */ 228}; 229 230/** 231 * DRM_IOCTL_GET_CLIENT ioctl argument type. 232 */ 233struct drm_client { 234 int idx; /**< Which client desired? */ 235 int auth; /**< Is client authenticated? */ 236 unsigned long pid; /**< Process ID */ 237 unsigned long uid; /**< User ID */ 238 unsigned long magic; /**< Magic */ 239 unsigned long iocs; /**< Ioctl count */ 240}; 241 242enum drm_stat_type { 243 _DRM_STAT_LOCK, 244 _DRM_STAT_OPENS, 245 _DRM_STAT_CLOSES, 246 _DRM_STAT_IOCTLS, 247 _DRM_STAT_LOCKS, 248 _DRM_STAT_UNLOCKS, 249 _DRM_STAT_VALUE, /**< Generic value */ 250 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ 251 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ 252 253 _DRM_STAT_IRQ, /**< IRQ */ 254 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ 255 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ 256 _DRM_STAT_DMA, /**< DMA */ 257 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ 258 _DRM_STAT_MISSED /**< Missed DMA opportunity */ 259 /* Add to the *END* of the list */ 260}; 261 262/** 263 * DRM_IOCTL_GET_STATS ioctl argument type. 264 */ 265struct drm_stats { 266 unsigned long count; 267 struct { 268 unsigned long value; 269 enum drm_stat_type type; 270 } data[15]; 271}; 272 273/** 274 * Hardware locking flags. 275 */ 276enum drm_lock_flags { 277 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ 278 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ 279 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ 280 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ 281 /* These *HALT* flags aren't supported yet 282 -- they will be used to support the 283 full-screen DGA-like mode. */ 284 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ 285 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ 286}; 287 288/** 289 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. 290 * 291 * \sa drmGetLock() and drmUnlock(). 292 */ 293struct drm_lock { 294 int context; 295 enum drm_lock_flags flags; 296}; 297 298/** 299 * DMA flags 300 * 301 * \warning 302 * These values \e must match xf86drm.h. 303 * 304 * \sa drm_dma. 305 */ 306enum drm_dma_flags { 307 /* Flags for DMA buffer dispatch */ 308 _DRM_DMA_BLOCK = 0x01, /**< 309 * Block until buffer dispatched. 310 * 311 * \note The buffer may not yet have 312 * been processed by the hardware -- 313 * getting a hardware lock with the 314 * hardware quiescent will ensure 315 * that the buffer has been 316 * processed. 317 */ 318 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ 319 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ 320 321 /* Flags for DMA buffer request */ 322 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ 323 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ 324 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ 325}; 326 327/** 328 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. 329 * 330 * \sa drmAddBufs(). 331 */ 332struct drm_buf_desc { 333 int count; /**< Number of buffers of this size */ 334 int size; /**< Size in bytes */ 335 int low_mark; /**< Low water mark */ 336 int high_mark; /**< High water mark */ 337 enum { 338 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ 339 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ 340 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ 341 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */ 342 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */ 343 } flags; 344 unsigned long agp_start; /**< 345 * Start address of where the AGP buffers are 346 * in the AGP aperture 347 */ 348}; 349 350/** 351 * DRM_IOCTL_INFO_BUFS ioctl argument type. 352 */ 353struct drm_buf_info { 354 int count; /**< Entries in list */ 355 struct drm_buf_desc *list; 356}; 357 358/** 359 * DRM_IOCTL_FREE_BUFS ioctl argument type. 360 */ 361struct drm_buf_free { 362 int count; 363 int *list; 364}; 365 366/** 367 * Buffer information 368 * 369 * \sa drm_buf_map. 370 */ 371struct drm_buf_pub { 372 int idx; /**< Index into the master buffer list */ 373 int total; /**< Buffer size */ 374 int used; /**< Amount of buffer in use (for DMA) */ 375 void *address; /**< Address of buffer */ 376}; 377 378/** 379 * DRM_IOCTL_MAP_BUFS ioctl argument type. 380 */ 381struct drm_buf_map { 382 int count; /**< Length of the buffer list */ 383#ifdef __cplusplus 384 void *virt; 385#else 386 void *virtual; /**< Mmap'd area in user-virtual */ 387#endif 388 struct drm_buf_pub *list; /**< Buffer information */ 389}; 390 391/** 392 * DRM_IOCTL_DMA ioctl argument type. 393 * 394 * Indices here refer to the offset into the buffer list in drm_buf_get. 395 * 396 * \sa drmDMA(). 397 */ 398struct drm_dma { 399 int context; /**< Context handle */ 400 int send_count; /**< Number of buffers to send */ 401 int *send_indices; /**< List of handles to buffers */ 402 int *send_sizes; /**< Lengths of data to send */ 403 enum drm_dma_flags flags; /**< Flags */ 404 int request_count; /**< Number of buffers requested */ 405 int request_size; /**< Desired size for buffers */ 406 int *request_indices; /**< Buffer information */ 407 int *request_sizes; 408 int granted_count; /**< Number of buffers granted */ 409}; 410 411enum drm_ctx_flags { 412 _DRM_CONTEXT_PRESERVED = 0x01, 413 _DRM_CONTEXT_2DONLY = 0x02 414}; 415 416/** 417 * DRM_IOCTL_ADD_CTX ioctl argument type. 418 * 419 * \sa drmCreateContext() and drmDestroyContext(). 420 */ 421struct drm_ctx { 422 drm_context_t handle; 423 enum drm_ctx_flags flags; 424}; 425 426/** 427 * DRM_IOCTL_RES_CTX ioctl argument type. 428 */ 429struct drm_ctx_res { 430 int count; 431 struct drm_ctx *contexts; 432}; 433 434/** 435 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. 436 */ 437struct drm_draw { 438 drm_drawable_t handle; 439}; 440 441/** 442 * DRM_IOCTL_UPDATE_DRAW ioctl argument type. 443 */ 444typedef enum { 445 DRM_DRAWABLE_CLIPRECTS 446} drm_drawable_info_type_t; 447 448struct drm_update_draw { 449 drm_drawable_t handle; 450 unsigned int type; 451 unsigned int num; 452 unsigned long long data; 453}; 454 455/** 456 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. 457 */ 458struct drm_auth { 459 drm_magic_t magic; 460}; 461 462/** 463 * DRM_IOCTL_IRQ_BUSID ioctl argument type. 464 * 465 * \sa drmGetInterruptFromBusID(). 466 */ 467struct drm_irq_busid { 468 int irq; /**< IRQ number */ 469 int busnum; /**< bus number */ 470 int devnum; /**< device number */ 471 int funcnum; /**< function number */ 472}; 473 474enum drm_vblank_seq_type { 475 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ 476 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ 477 /* bits 1-6 are reserved for high crtcs */ 478 _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e, 479 _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */ 480 _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ 481 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ 482 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ 483 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */ 484}; 485#define _DRM_VBLANK_HIGH_CRTC_SHIFT 1 486 487#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) 488#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \ 489 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS) 490 491struct drm_wait_vblank_request { 492 enum drm_vblank_seq_type type; 493 unsigned int sequence; 494 unsigned long signal; 495}; 496 497struct drm_wait_vblank_reply { 498 enum drm_vblank_seq_type type; 499 unsigned int sequence; 500 long tval_sec; 501 long tval_usec; 502}; 503 504/** 505 * DRM_IOCTL_WAIT_VBLANK ioctl argument type. 506 * 507 * \sa drmWaitVBlank(). 508 */ 509union drm_wait_vblank { 510 struct drm_wait_vblank_request request; 511 struct drm_wait_vblank_reply reply; 512}; 513 514#define _DRM_PRE_MODESET 1 515#define _DRM_POST_MODESET 2 516 517/** 518 * DRM_IOCTL_MODESET_CTL ioctl argument type 519 * 520 * \sa drmModesetCtl(). 521 */ 522struct drm_modeset_ctl { 523 __u32 crtc; 524 __u32 cmd; 525}; 526 527/** 528 * DRM_IOCTL_AGP_ENABLE ioctl argument type. 529 * 530 * \sa drmAgpEnable(). 531 */ 532struct drm_agp_mode { 533 unsigned long mode; /**< AGP mode */ 534}; 535 536/** 537 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. 538 * 539 * \sa drmAgpAlloc() and drmAgpFree(). 540 */ 541struct drm_agp_buffer { 542 unsigned long size; /**< In bytes -- will round to page boundary */ 543 unsigned long handle; /**< Used for binding / unbinding */ 544 unsigned long type; /**< Type of memory to allocate */ 545 unsigned long physical; /**< Physical used by i810 */ 546}; 547 548/** 549 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. 550 * 551 * \sa drmAgpBind() and drmAgpUnbind(). 552 */ 553struct drm_agp_binding { 554 unsigned long handle; /**< From drm_agp_buffer */ 555 unsigned long offset; /**< In bytes -- will round to page boundary */ 556}; 557 558/** 559 * DRM_IOCTL_AGP_INFO ioctl argument type. 560 * 561 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), 562 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), 563 * drmAgpVendorId() and drmAgpDeviceId(). 564 */ 565struct drm_agp_info { 566 int agp_version_major; 567 int agp_version_minor; 568 unsigned long mode; 569 unsigned long aperture_base; /* physical address */ 570 unsigned long aperture_size; /* bytes */ 571 unsigned long memory_allowed; /* bytes */ 572 unsigned long memory_used; 573 574 /* PCI information */ 575 unsigned short id_vendor; 576 unsigned short id_device; 577}; 578 579/** 580 * DRM_IOCTL_SG_ALLOC ioctl argument type. 581 */ 582struct drm_scatter_gather { 583 unsigned long size; /**< In bytes -- will round to page boundary */ 584 unsigned long handle; /**< Used for mapping / unmapping */ 585}; 586 587/** 588 * DRM_IOCTL_SET_VERSION ioctl argument type. 589 */ 590struct drm_set_version { 591 int drm_di_major; 592 int drm_di_minor; 593 int drm_dd_major; 594 int drm_dd_minor; 595}; 596 597/** DRM_IOCTL_GEM_CLOSE ioctl argument type */ 598struct drm_gem_close { 599 /** Handle of the object to be closed. */ 600 __u32 handle; 601 __u32 pad; 602}; 603 604/** DRM_IOCTL_GEM_FLINK ioctl argument type */ 605struct drm_gem_flink { 606 /** Handle for the object being named */ 607 __u32 handle; 608 609 /** Returned global name */ 610 __u32 name; 611}; 612 613/** DRM_IOCTL_GEM_OPEN ioctl argument type */ 614struct drm_gem_open { 615 /** Name of object being opened */ 616 __u32 name; 617 618 /** Returned handle for the object */ 619 __u32 handle; 620 621 /** Returned size of the object */ 622 __u64 size; 623}; 624 625#define DRM_CAP_DUMB_BUFFER 0x1 626#define DRM_CAP_VBLANK_HIGH_CRTC 0x2 627#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3 628#define DRM_CAP_DUMB_PREFER_SHADOW 0x4 629#define DRM_CAP_PRIME 0x5 630#define DRM_PRIME_CAP_IMPORT 0x1 631#define DRM_PRIME_CAP_EXPORT 0x2 632#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6 633#define DRM_CAP_ASYNC_PAGE_FLIP 0x7 634/* 635 * The CURSOR_WIDTH and CURSOR_HEIGHT capabilities return a valid widthxheight 636 * combination for the hardware cursor. The intention is that a hardware 637 * agnostic userspace can query a cursor plane size to use. 638 * 639 * Note that the cross-driver contract is to merely return a valid size; 640 * drivers are free to attach another meaning on top, eg. i915 returns the 641 * maximum plane size. 642 */ 643#define DRM_CAP_CURSOR_WIDTH 0x8 644#define DRM_CAP_CURSOR_HEIGHT 0x9 645#define DRM_CAP_ADDFB2_MODIFIERS 0x10 646#define DRM_CAP_PAGE_FLIP_TARGET 0x11 647#define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12 648#define DRM_CAP_SYNCOBJ 0x13 649 650/** DRM_IOCTL_GET_CAP ioctl argument type */ 651struct drm_get_cap { 652 __u64 capability; 653 __u64 value; 654}; 655 656/** 657 * DRM_CLIENT_CAP_STEREO_3D 658 * 659 * if set to 1, the DRM core will expose the stereo 3D capabilities of the 660 * monitor by advertising the supported 3D layouts in the flags of struct 661 * drm_mode_modeinfo. 662 */ 663#define DRM_CLIENT_CAP_STEREO_3D 1 664 665/** 666 * DRM_CLIENT_CAP_UNIVERSAL_PLANES 667 * 668 * If set to 1, the DRM core will expose all planes (overlay, primary, and 669 * cursor) to userspace. 670 */ 671#define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2 672 673/** 674 * DRM_CLIENT_CAP_ATOMIC 675 * 676 * If set to 1, the DRM core will expose atomic properties to userspace 677 */ 678#define DRM_CLIENT_CAP_ATOMIC 3 679 680/** 681 * DRM_CLIENT_CAP_ASPECT_RATIO 682 * 683 * If set to 1, the DRM core will provide aspect ratio information in modes. 684 */ 685#define DRM_CLIENT_CAP_ASPECT_RATIO 4 686 687/** 688 * DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 689 * 690 * If set to 1, the DRM core will expose special connectors to be used for 691 * writing back to memory the scene setup in the commit. Depends on client 692 * also supporting DRM_CLIENT_CAP_ATOMIC 693 */ 694#define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5 695 696/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */ 697struct drm_set_client_cap { 698 __u64 capability; 699 __u64 value; 700}; 701 702#define DRM_RDWR O_RDWR 703#define DRM_CLOEXEC O_CLOEXEC 704struct drm_prime_handle { 705 __u32 handle; 706 707 /** Flags.. only applicable for handle->fd */ 708 __u32 flags; 709 710 /** Returned dmabuf file descriptor */ 711 __s32 fd; 712}; 713 714struct drm_syncobj_create { 715 __u32 handle; 716#define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0) 717 __u32 flags; 718}; 719 720struct drm_syncobj_destroy { 721 __u32 handle; 722 __u32 pad; 723}; 724 725#define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0) 726#define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0) 727struct drm_syncobj_handle { 728 __u32 handle; 729 __u32 flags; 730 731 __s32 fd; 732 __u32 pad; 733}; 734 735#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0) 736#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1) 737struct drm_syncobj_wait { 738 __u64 handles; 739 /* absolute timeout */ 740 __s64 timeout_nsec; 741 __u32 count_handles; 742 __u32 flags; 743 __u32 first_signaled; /* only valid when not waiting all */ 744 __u32 pad; 745}; 746 747struct drm_syncobj_array { 748 __u64 handles; 749 __u32 count_handles; 750 __u32 pad; 751}; 752 753/* Query current scanout sequence number */ 754struct drm_crtc_get_sequence { 755 __u32 crtc_id; /* requested crtc_id */ 756 __u32 active; /* return: crtc output is active */ 757 __u64 sequence; /* return: most recent vblank sequence */ 758 __s64 sequence_ns; /* return: most recent time of first pixel out */ 759}; 760 761/* Queue event to be delivered at specified sequence. Time stamp marks 762 * when the first pixel of the refresh cycle leaves the display engine 763 * for the display 764 */ 765#define DRM_CRTC_SEQUENCE_RELATIVE 0x00000001 /* sequence is relative to current */ 766#define DRM_CRTC_SEQUENCE_NEXT_ON_MISS 0x00000002 /* Use next sequence if we've missed */ 767 768struct drm_crtc_queue_sequence { 769 __u32 crtc_id; 770 __u32 flags; 771 __u64 sequence; /* on input, target sequence. on output, actual sequence */ 772 __u64 user_data; /* user data passed to event */ 773}; 774 775#if defined(__cplusplus) 776} 777#endif 778 779#include "drm_mode.h" 780 781#if defined(__cplusplus) 782extern "C" { 783#endif 784 785#define DRM_IOCTL_BASE 'd' 786#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) 787#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) 788#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) 789#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) 790 791#define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version) 792#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique) 793#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth) 794#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid) 795#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map) 796#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client) 797#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats) 798#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version) 799#define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl) 800#define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close) 801#define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink) 802#define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open) 803#define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap) 804#define DRM_IOCTL_SET_CLIENT_CAP DRM_IOW( 0x0d, struct drm_set_client_cap) 805 806#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique) 807#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth) 808#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block) 809#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block) 810#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control) 811#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map) 812#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc) 813#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc) 814#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info) 815#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map) 816#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free) 817 818#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map) 819 820#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map) 821#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map) 822 823#define DRM_IOCTL_SET_MASTER DRM_IO(0x1e) 824#define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f) 825 826#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx) 827#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx) 828#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx) 829#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx) 830#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx) 831#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx) 832#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res) 833#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw) 834#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw) 835#define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma) 836#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock) 837#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock) 838#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock) 839 840#define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle) 841#define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle) 842 843#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) 844#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) 845#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode) 846#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info) 847#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer) 848#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer) 849#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) 850#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) 851 852#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather) 853#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) 854 855#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) 856 857#define DRM_IOCTL_CRTC_GET_SEQUENCE DRM_IOWR(0x3b, struct drm_crtc_get_sequence) 858#define DRM_IOCTL_CRTC_QUEUE_SEQUENCE DRM_IOWR(0x3c, struct drm_crtc_queue_sequence) 859 860#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) 861 862#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res) 863#define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc) 864#define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc) 865#define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor) 866#define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut) 867#define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut) 868#define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder) 869#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector) 870#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) /* deprecated (never worked) */ 871#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) /* deprecated (never worked) */ 872 873#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property) 874#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property) 875#define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob) 876#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd) 877#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd) 878#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int) 879#define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip) 880#define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd) 881 882#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb) 883#define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb) 884#define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb) 885#define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res) 886#define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane) 887#define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane) 888#define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2) 889#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties) 890#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property) 891#define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2) 892#define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic) 893#define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob) 894#define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob) 895 896#define DRM_IOCTL_SYNCOBJ_CREATE DRM_IOWR(0xBF, struct drm_syncobj_create) 897#define DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct drm_syncobj_destroy) 898#define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD DRM_IOWR(0xC1, struct drm_syncobj_handle) 899#define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE DRM_IOWR(0xC2, struct drm_syncobj_handle) 900#define DRM_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct drm_syncobj_wait) 901#define DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct drm_syncobj_array) 902#define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array) 903 904#define DRM_IOCTL_MODE_CREATE_LEASE DRM_IOWR(0xC6, struct drm_mode_create_lease) 905#define DRM_IOCTL_MODE_LIST_LESSEES DRM_IOWR(0xC7, struct drm_mode_list_lessees) 906#define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease) 907#define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease) 908 909/** 910 * Device specific ioctls should only be in their respective headers 911 * The device specific ioctl range is from 0x40 to 0x9f. 912 * Generic IOCTLS restart at 0xA0. 913 * 914 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and 915 * drmCommandReadWrite(). 916 */ 917#define DRM_COMMAND_BASE 0x40 918#define DRM_COMMAND_END 0xA0 919 920/** 921 * Header for events written back to userspace on the drm fd. The 922 * type defines the type of event, the length specifies the total 923 * length of the event (including the header), and user_data is 924 * typically a 64 bit value passed with the ioctl that triggered the 925 * event. A read on the drm fd will always only return complete 926 * events, that is, if for example the read buffer is 100 bytes, and 927 * there are two 64 byte events pending, only one will be returned. 928 * 929 * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and 930 * up are chipset specific. 931 */ 932struct drm_event { 933 __u32 type; 934 __u32 length; 935}; 936 937#define DRM_EVENT_VBLANK 0x01 938#define DRM_EVENT_FLIP_COMPLETE 0x02 939#define DRM_EVENT_CRTC_SEQUENCE 0x03 940 941struct drm_event_vblank { 942 struct drm_event base; 943 __u64 user_data; 944 __u32 tv_sec; 945 __u32 tv_usec; 946 __u32 sequence; 947 __u32 crtc_id; /* 0 on older kernels that do not support this */ 948}; 949 950/* Event delivered at sequence. Time stamp marks when the first pixel 951 * of the refresh cycle leaves the display engine for the display 952 */ 953struct drm_event_crtc_sequence { 954 struct drm_event base; 955 __u64 user_data; 956 __s64 time_ns; 957 __u64 sequence; 958}; 959 960/* typedef area */ 961typedef struct drm_clip_rect drm_clip_rect_t; 962typedef struct drm_drawable_info drm_drawable_info_t; 963typedef struct drm_tex_region drm_tex_region_t; 964typedef struct drm_hw_lock drm_hw_lock_t; 965typedef struct drm_version drm_version_t; 966typedef struct drm_unique drm_unique_t; 967typedef struct drm_list drm_list_t; 968typedef struct drm_block drm_block_t; 969typedef struct drm_control drm_control_t; 970typedef enum drm_map_type drm_map_type_t; 971typedef enum drm_map_flags drm_map_flags_t; 972typedef struct drm_ctx_priv_map drm_ctx_priv_map_t; 973typedef struct drm_map drm_map_t; 974typedef struct drm_client drm_client_t; 975typedef enum drm_stat_type drm_stat_type_t; 976typedef struct drm_stats drm_stats_t; 977typedef enum drm_lock_flags drm_lock_flags_t; 978typedef struct drm_lock drm_lock_t; 979typedef enum drm_dma_flags drm_dma_flags_t; 980typedef struct drm_buf_desc drm_buf_desc_t; 981typedef struct drm_buf_info drm_buf_info_t; 982typedef struct drm_buf_free drm_buf_free_t; 983typedef struct drm_buf_pub drm_buf_pub_t; 984typedef struct drm_buf_map drm_buf_map_t; 985typedef struct drm_dma drm_dma_t; 986typedef union drm_wait_vblank drm_wait_vblank_t; 987typedef struct drm_agp_mode drm_agp_mode_t; 988typedef enum drm_ctx_flags drm_ctx_flags_t; 989typedef struct drm_ctx drm_ctx_t; 990typedef struct drm_ctx_res drm_ctx_res_t; 991typedef struct drm_draw drm_draw_t; 992typedef struct drm_update_draw drm_update_draw_t; 993typedef struct drm_auth drm_auth_t; 994typedef struct drm_irq_busid drm_irq_busid_t; 995typedef enum drm_vblank_seq_type drm_vblank_seq_type_t; 996 997typedef struct drm_agp_buffer drm_agp_buffer_t; 998typedef struct drm_agp_binding drm_agp_binding_t; 999typedef struct drm_agp_info drm_agp_info_t; 1000typedef struct drm_scatter_gather drm_scatter_gather_t; 1001typedef struct drm_set_version drm_set_version_t; 1002 1003#if defined(__cplusplus) 1004} 1005#endif 1006 1007#endif 1008