drm_mode.h revision 13d1d17d
122944501Smrg/*
222944501Smrg * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
322944501Smrg * Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com>
422944501Smrg * Copyright (c) 2008 Red Hat Inc.
522944501Smrg * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
622944501Smrg * Copyright (c) 2007-2008 Intel Corporation
722944501Smrg *
822944501Smrg * Permission is hereby granted, free of charge, to any person obtaining a
922944501Smrg * copy of this software and associated documentation files (the "Software"),
1022944501Smrg * to deal in the Software without restriction, including without limitation
1122944501Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
1222944501Smrg * and/or sell copies of the Software, and to permit persons to whom the
1322944501Smrg * Software is furnished to do so, subject to the following conditions:
1422944501Smrg *
1522944501Smrg * The above copyright notice and this permission notice shall be included in
1622944501Smrg * all copies or substantial portions of the Software.
1722944501Smrg *
1822944501Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1922944501Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
2022944501Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
2122944501Smrg * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
2222944501Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2322944501Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
2422944501Smrg * IN THE SOFTWARE.
2522944501Smrg */
2622944501Smrg
2722944501Smrg#ifndef _DRM_MODE_H
2822944501Smrg#define _DRM_MODE_H
2922944501Smrg
3022944501Smrg#define DRM_DISPLAY_INFO_LEN	32
3122944501Smrg#define DRM_CONNECTOR_NAME_LEN	32
3222944501Smrg#define DRM_DISPLAY_MODE_LEN	32
3322944501Smrg#define DRM_PROP_NAME_LEN	32
3422944501Smrg
3522944501Smrg#define DRM_MODE_TYPE_BUILTIN	(1<<0)
3622944501Smrg#define DRM_MODE_TYPE_CLOCK_C	((1<<1) | DRM_MODE_TYPE_BUILTIN)
3722944501Smrg#define DRM_MODE_TYPE_CRTC_C	((1<<2) | DRM_MODE_TYPE_BUILTIN)
3822944501Smrg#define DRM_MODE_TYPE_PREFERRED	(1<<3)
3922944501Smrg#define DRM_MODE_TYPE_DEFAULT	(1<<4)
4022944501Smrg#define DRM_MODE_TYPE_USERDEF	(1<<5)
4122944501Smrg#define DRM_MODE_TYPE_DRIVER	(1<<6)
4222944501Smrg
4322944501Smrg/* Video mode flags */
4422944501Smrg/* bit compatible with the xorg definitions. */
4522944501Smrg#define DRM_MODE_FLAG_PHSYNC	(1<<0)
4622944501Smrg#define DRM_MODE_FLAG_NHSYNC	(1<<1)
4722944501Smrg#define DRM_MODE_FLAG_PVSYNC	(1<<2)
4822944501Smrg#define DRM_MODE_FLAG_NVSYNC	(1<<3)
4922944501Smrg#define DRM_MODE_FLAG_INTERLACE	(1<<4)
5022944501Smrg#define DRM_MODE_FLAG_DBLSCAN	(1<<5)
5122944501Smrg#define DRM_MODE_FLAG_CSYNC	(1<<6)
5222944501Smrg#define DRM_MODE_FLAG_PCSYNC	(1<<7)
5322944501Smrg#define DRM_MODE_FLAG_NCSYNC	(1<<8)
5422944501Smrg#define DRM_MODE_FLAG_HSKEW	(1<<9) /* hskew provided */
5522944501Smrg#define DRM_MODE_FLAG_BCAST	(1<<10)
5622944501Smrg#define DRM_MODE_FLAG_PIXMUX	(1<<11)
5722944501Smrg#define DRM_MODE_FLAG_DBLCLK	(1<<12)
5822944501Smrg#define DRM_MODE_FLAG_CLKDIV2	(1<<13)
5922944501Smrg
6022944501Smrg/* DPMS flags */
6122944501Smrg/* bit compatible with the xorg definitions. */
6222944501Smrg#define DRM_MODE_DPMS_ON	0
6322944501Smrg#define DRM_MODE_DPMS_STANDBY	1
6422944501Smrg#define DRM_MODE_DPMS_SUSPEND	2
6522944501Smrg#define DRM_MODE_DPMS_OFF	3
6622944501Smrg
6722944501Smrg/* Scaling mode options */
6822944501Smrg#define DRM_MODE_SCALE_NONE		0 /* Unmodified timing (display or
6922944501Smrg					     software can still scale) */
7022944501Smrg#define DRM_MODE_SCALE_FULLSCREEN	1 /* Full screen, ignore aspect */
7122944501Smrg#define DRM_MODE_SCALE_CENTER		2 /* Centered, no scaling */
7222944501Smrg#define DRM_MODE_SCALE_ASPECT		3 /* Full screen, preserve aspect */
7322944501Smrg
7422944501Smrg/* Dithering mode options */
7522944501Smrg#define DRM_MODE_DITHERING_OFF	0
7622944501Smrg#define DRM_MODE_DITHERING_ON	1
7722944501Smrg
7813d1d17dSmrg/* Dirty info options */
7913d1d17dSmrg#define DRM_MODE_DIRTY_OFF      0
8013d1d17dSmrg#define DRM_MODE_DIRTY_ON       1
8113d1d17dSmrg#define DRM_MODE_DIRTY_ANNOTATE 2
8213d1d17dSmrg
8322944501Smrgstruct drm_mode_modeinfo {
8422944501Smrg	__u32 clock;
8522944501Smrg	__u16 hdisplay, hsync_start, hsync_end, htotal, hskew;
8622944501Smrg	__u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;
8722944501Smrg
8822944501Smrg	__u32 vrefresh; /* vertical refresh * 1000 */
8922944501Smrg
9022944501Smrg	__u32 flags;
9122944501Smrg	__u32 type;
9222944501Smrg	char name[DRM_DISPLAY_MODE_LEN];
9322944501Smrg};
9422944501Smrg
9522944501Smrgstruct drm_mode_card_res {
9622944501Smrg	__u64 fb_id_ptr;
9722944501Smrg	__u64 crtc_id_ptr;
9822944501Smrg	__u64 connector_id_ptr;
9922944501Smrg	__u64 encoder_id_ptr;
10022944501Smrg	__u32 count_fbs;
10122944501Smrg	__u32 count_crtcs;
10222944501Smrg	__u32 count_connectors;
10322944501Smrg	__u32 count_encoders;
10422944501Smrg	__u32 min_width, max_width;
10522944501Smrg	__u32 min_height, max_height;
10622944501Smrg};
10722944501Smrg
10822944501Smrgstruct drm_mode_crtc {
10922944501Smrg	__u64 set_connectors_ptr;
11022944501Smrg	__u32 count_connectors;
11122944501Smrg
11222944501Smrg	__u32 crtc_id; /**< Id */
11322944501Smrg	__u32 fb_id; /**< Id of framebuffer */
11422944501Smrg
11522944501Smrg	__u32 x, y; /**< Position on the frameuffer */
11622944501Smrg
11722944501Smrg	__u32 gamma_size;
11822944501Smrg	__u32 mode_valid;
11922944501Smrg	struct drm_mode_modeinfo mode;
12022944501Smrg};
12122944501Smrg
12222944501Smrg#define DRM_MODE_ENCODER_NONE	0
12322944501Smrg#define DRM_MODE_ENCODER_DAC	1
12422944501Smrg#define DRM_MODE_ENCODER_TMDS	2
12522944501Smrg#define DRM_MODE_ENCODER_LVDS	3
12622944501Smrg#define DRM_MODE_ENCODER_TVDAC	4
12722944501Smrg
12822944501Smrgstruct drm_mode_get_encoder {
12922944501Smrg	__u32 encoder_id;
13022944501Smrg	__u32 encoder_type;
13122944501Smrg
13222944501Smrg	__u32 crtc_id; /**< Id of crtc */
13322944501Smrg
13422944501Smrg	__u32 possible_crtcs;
13522944501Smrg	__u32 possible_clones;
13622944501Smrg};
13722944501Smrg
13822944501Smrg/* This is for connectors with multiple signal types. */
13922944501Smrg/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
14022944501Smrg#define DRM_MODE_SUBCONNECTOR_Automatic	0
14122944501Smrg#define DRM_MODE_SUBCONNECTOR_Unknown	0
14222944501Smrg#define DRM_MODE_SUBCONNECTOR_DVID	3
14322944501Smrg#define DRM_MODE_SUBCONNECTOR_DVIA	4
14422944501Smrg#define DRM_MODE_SUBCONNECTOR_Composite	5
14522944501Smrg#define DRM_MODE_SUBCONNECTOR_SVIDEO	6
14622944501Smrg#define DRM_MODE_SUBCONNECTOR_Component	8
14722944501Smrg#define DRM_MODE_SUBCONNECTOR_SCART	9
14822944501Smrg
14922944501Smrg#define DRM_MODE_CONNECTOR_Unknown	0
15022944501Smrg#define DRM_MODE_CONNECTOR_VGA		1
15122944501Smrg#define DRM_MODE_CONNECTOR_DVII		2
15222944501Smrg#define DRM_MODE_CONNECTOR_DVID		3
15322944501Smrg#define DRM_MODE_CONNECTOR_DVIA		4
15422944501Smrg#define DRM_MODE_CONNECTOR_Composite	5
15522944501Smrg#define DRM_MODE_CONNECTOR_SVIDEO	6
15622944501Smrg#define DRM_MODE_CONNECTOR_LVDS		7
15722944501Smrg#define DRM_MODE_CONNECTOR_Component	8
15822944501Smrg#define DRM_MODE_CONNECTOR_9PinDIN	9
15922944501Smrg#define DRM_MODE_CONNECTOR_DisplayPort	10
16022944501Smrg#define DRM_MODE_CONNECTOR_HDMIA	11
16122944501Smrg#define DRM_MODE_CONNECTOR_HDMIB	12
16222944501Smrg#define DRM_MODE_CONNECTOR_TV		13
16322944501Smrg
16422944501Smrgstruct drm_mode_get_connector {
16522944501Smrg
16622944501Smrg	__u64 encoders_ptr;
16722944501Smrg	__u64 modes_ptr;
16822944501Smrg	__u64 props_ptr;
16922944501Smrg	__u64 prop_values_ptr;
17022944501Smrg
17122944501Smrg	__u32 count_modes;
17222944501Smrg	__u32 count_props;
17322944501Smrg	__u32 count_encoders;
17422944501Smrg
17522944501Smrg	__u32 encoder_id; /**< Current Encoder */
17622944501Smrg	__u32 connector_id; /**< Id */
17722944501Smrg	__u32 connector_type;
17822944501Smrg	__u32 connector_type_id;
17922944501Smrg
18022944501Smrg	__u32 connection;
18122944501Smrg	__u32 mm_width, mm_height; /**< HxW in millimeters */
18222944501Smrg	__u32 subpixel;
18322944501Smrg};
18422944501Smrg
18522944501Smrg#define DRM_MODE_PROP_PENDING	(1<<0)
18622944501Smrg#define DRM_MODE_PROP_RANGE	(1<<1)
18722944501Smrg#define DRM_MODE_PROP_IMMUTABLE	(1<<2)
18822944501Smrg#define DRM_MODE_PROP_ENUM	(1<<3) /* enumerated type with text strings */
18922944501Smrg#define DRM_MODE_PROP_BLOB	(1<<4)
19022944501Smrg
19122944501Smrgstruct drm_mode_property_enum {
19222944501Smrg	__u64 value;
19322944501Smrg	char name[DRM_PROP_NAME_LEN];
19422944501Smrg};
19522944501Smrg
19622944501Smrgstruct drm_mode_get_property {
19722944501Smrg	__u64 values_ptr; /* values and blob lengths */
19822944501Smrg	__u64 enum_blob_ptr; /* enum and blob id ptrs */
19922944501Smrg
20022944501Smrg	__u32 prop_id;
20122944501Smrg	__u32 flags;
20222944501Smrg	char name[DRM_PROP_NAME_LEN];
20322944501Smrg
20422944501Smrg	__u32 count_values;
20522944501Smrg	__u32 count_enum_blobs;
20622944501Smrg};
20722944501Smrg
20822944501Smrgstruct drm_mode_connector_set_property {
20922944501Smrg	__u64 value;
21022944501Smrg	__u32 prop_id;
21122944501Smrg	__u32 connector_id;
21222944501Smrg};
21322944501Smrg
21422944501Smrgstruct drm_mode_get_blob {
21522944501Smrg	__u32 blob_id;
21622944501Smrg	__u32 length;
21722944501Smrg	__u64 data;
21822944501Smrg};
21922944501Smrg
22022944501Smrgstruct drm_mode_fb_cmd {
22122944501Smrg	__u32 fb_id;
22222944501Smrg	__u32 width, height;
22322944501Smrg	__u32 pitch;
22422944501Smrg	__u32 bpp;
22522944501Smrg	__u32 depth;
22622944501Smrg	/* driver specific handle */
22722944501Smrg	__u32 handle;
22822944501Smrg};
22922944501Smrg
23022944501Smrg#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
23122944501Smrg#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
23222944501Smrg#define DRM_MODE_FB_DIRTY_FLAGS         0x03
23322944501Smrg
23422944501Smrg/*
23522944501Smrg * Mark a region of a framebuffer as dirty.
23622944501Smrg *
23722944501Smrg * Some hardware does not automatically update display contents
23822944501Smrg * as a hardware or software draw to a framebuffer. This ioctl
23922944501Smrg * allows userspace to tell the kernel and the hardware what
24022944501Smrg * regions of the framebuffer have changed.
24122944501Smrg *
24222944501Smrg * The kernel or hardware is free to update more then just the
24322944501Smrg * region specified by the clip rects. The kernel or hardware
24422944501Smrg * may also delay and/or coalesce several calls to dirty into a
24522944501Smrg * single update.
24622944501Smrg *
24722944501Smrg * Userspace may annotate the updates, the annotates are a
24822944501Smrg * promise made by the caller that the change is either a copy
24922944501Smrg * of pixels or a fill of a single color in the region specified.
25022944501Smrg *
25122944501Smrg * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then
25222944501Smrg * the number of updated regions are half of num_clips given,
25322944501Smrg * where the clip rects are paired in src and dst. The width and
25422944501Smrg * height of each one of the pairs must match.
25522944501Smrg *
25622944501Smrg * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller
25722944501Smrg * promises that the region specified of the clip rects is filled
25822944501Smrg * completely with a single color as given in the color argument.
25922944501Smrg */
26022944501Smrg
26122944501Smrgstruct drm_mode_fb_dirty_cmd {
26222944501Smrg	__u32 fb_id;
26322944501Smrg	__u32 flags;
26422944501Smrg	__u32 color;
26522944501Smrg	__u32 num_clips;
26622944501Smrg	__u64 clips_ptr;
26722944501Smrg};
26822944501Smrg
26922944501Smrgstruct drm_mode_mode_cmd {
27022944501Smrg	__u32 connector_id;
27122944501Smrg	struct drm_mode_modeinfo mode;
27222944501Smrg};
27322944501Smrg
27422944501Smrg#define DRM_MODE_CURSOR_BO	(1<<0)
27522944501Smrg#define DRM_MODE_CURSOR_MOVE	(1<<1)
27622944501Smrg
27722944501Smrg/*
27822944501Smrg * depending on the value in flags diffrent members are used.
27922944501Smrg *
28022944501Smrg * CURSOR_BO uses
28122944501Smrg *    crtc
28222944501Smrg *    width
28322944501Smrg *    height
28422944501Smrg *    handle - if 0 turns the cursor of
28522944501Smrg *
28622944501Smrg * CURSOR_MOVE uses
28722944501Smrg *    crtc
28822944501Smrg *    x
28922944501Smrg *    y
29022944501Smrg */
29122944501Smrgstruct drm_mode_cursor {
29222944501Smrg	__u32 flags;
29322944501Smrg	__u32 crtc_id;
29422944501Smrg	__s32 x;
29522944501Smrg	__s32 y;
29622944501Smrg	__u32 width;
29722944501Smrg	__u32 height;
29822944501Smrg	/* driver specific handle */
29922944501Smrg	__u32 handle;
30022944501Smrg};
30122944501Smrg
30222944501Smrgstruct drm_mode_crtc_lut {
30322944501Smrg	__u32 crtc_id;
30422944501Smrg	__u32 gamma_size;
30522944501Smrg
30622944501Smrg	/* pointers to arrays */
30722944501Smrg	__u64 red;
30822944501Smrg	__u64 green;
30922944501Smrg	__u64 blue;
31022944501Smrg};
31122944501Smrg
31222944501Smrg#define DRM_MODE_PAGE_FLIP_EVENT 0x01
31322944501Smrg#define DRM_MODE_PAGE_FLIP_FLAGS DRM_MODE_PAGE_FLIP_EVENT
31422944501Smrg
31513d1d17dSmrg/*
31613d1d17dSmrg * Request a page flip on the specified crtc.
31713d1d17dSmrg *
31813d1d17dSmrg * This ioctl will ask KMS to schedule a page flip for the specified
31913d1d17dSmrg * crtc.  Once any pending rendering targeting the specified fb (as of
32013d1d17dSmrg * ioctl time) has completed, the crtc will be reprogrammed to display
32113d1d17dSmrg * that fb after the next vertical refresh.  The ioctl returns
32213d1d17dSmrg * immediately, but subsequent rendering to the current fb will block
32313d1d17dSmrg * in the execbuffer ioctl until the page flip happens.  If a page
32413d1d17dSmrg * flip is already pending as the ioctl is called, EBUSY will be
32513d1d17dSmrg * returned.
32613d1d17dSmrg *
32713d1d17dSmrg * The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will
32813d1d17dSmrg * request that drm sends back a vblank event (see drm.h: struct
32913d1d17dSmrg * drm_event_vblank) when the page flip is done.  The user_data field
33013d1d17dSmrg * passed in with this ioctl will be returned as the user_data field
33113d1d17dSmrg * in the vblank event struct.
33213d1d17dSmrg *
33313d1d17dSmrg * The reserved field must be zero until we figure out something
33413d1d17dSmrg * clever to use it for.
33513d1d17dSmrg */
33613d1d17dSmrg
33722944501Smrgstruct drm_mode_crtc_page_flip {
33813d1d17dSmrg	__u32 crtc_id;
33913d1d17dSmrg	__u32 fb_id;
34013d1d17dSmrg	__u32 flags;
34113d1d17dSmrg	__u32 reserved;
34213d1d17dSmrg	__u64 user_data;
34322944501Smrg};
34422944501Smrg
34522944501Smrg#endif
346