122944501Smrg/* r128_drm.h -- Public header for the r128 driver -*- linux-c -*- 222944501Smrg * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com 322944501Smrg */ 422944501Smrg/* 522944501Smrg * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 622944501Smrg * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 722944501Smrg * All rights reserved. 822944501Smrg * 922944501Smrg * Permission is hereby granted, free of charge, to any person obtaining a 1022944501Smrg * copy of this software and associated documentation files (the "Software"), 1122944501Smrg * to deal in the Software without restriction, including without limitation 1222944501Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1322944501Smrg * and/or sell copies of the Software, and to permit persons to whom the 1422944501Smrg * Software is furnished to do so, subject to the following conditions: 1522944501Smrg * 1622944501Smrg * The above copyright notice and this permission notice (including the next 1722944501Smrg * paragraph) shall be included in all copies or substantial portions of the 1822944501Smrg * Software. 1922944501Smrg * 2022944501Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 2122944501Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 2222944501Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 2322944501Smrg * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 2422944501Smrg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2522944501Smrg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 2622944501Smrg * DEALINGS IN THE SOFTWARE. 2722944501Smrg * 2822944501Smrg * Authors: 2922944501Smrg * Gareth Hughes <gareth@valinux.com> 3022944501Smrg * Kevin E. Martin <martin@valinux.com> 3122944501Smrg */ 3222944501Smrg 3322944501Smrg#ifndef __R128_DRM_H__ 3422944501Smrg#define __R128_DRM_H__ 3522944501Smrg 3600a23bdaSmrg#include "drm.h" 3700a23bdaSmrg 3800a23bdaSmrg#if defined(__cplusplus) 3900a23bdaSmrgextern "C" { 4000a23bdaSmrg#endif 4100a23bdaSmrg 4222944501Smrg/* WARNING: If you change any of these defines, make sure to change the 4322944501Smrg * defines in the X server file (r128_sarea.h) 4422944501Smrg */ 4522944501Smrg#ifndef __R128_SAREA_DEFINES__ 4622944501Smrg#define __R128_SAREA_DEFINES__ 4722944501Smrg 4822944501Smrg/* What needs to be changed for the current vertex buffer? 4922944501Smrg */ 5022944501Smrg#define R128_UPLOAD_CONTEXT 0x001 5122944501Smrg#define R128_UPLOAD_SETUP 0x002 5222944501Smrg#define R128_UPLOAD_TEX0 0x004 5322944501Smrg#define R128_UPLOAD_TEX1 0x008 5422944501Smrg#define R128_UPLOAD_TEX0IMAGES 0x010 5522944501Smrg#define R128_UPLOAD_TEX1IMAGES 0x020 5622944501Smrg#define R128_UPLOAD_CORE 0x040 5722944501Smrg#define R128_UPLOAD_MASKS 0x080 5822944501Smrg#define R128_UPLOAD_WINDOW 0x100 5922944501Smrg#define R128_UPLOAD_CLIPRECTS 0x200 /* handled client-side */ 6022944501Smrg#define R128_REQUIRE_QUIESCENCE 0x400 6122944501Smrg#define R128_UPLOAD_ALL 0x7ff 6222944501Smrg 6322944501Smrg#define R128_FRONT 0x1 6422944501Smrg#define R128_BACK 0x2 6522944501Smrg#define R128_DEPTH 0x4 6622944501Smrg 6722944501Smrg/* Primitive types 6822944501Smrg */ 6922944501Smrg#define R128_POINTS 0x1 7022944501Smrg#define R128_LINES 0x2 7122944501Smrg#define R128_LINE_STRIP 0x3 7222944501Smrg#define R128_TRIANGLES 0x4 7322944501Smrg#define R128_TRIANGLE_FAN 0x5 7422944501Smrg#define R128_TRIANGLE_STRIP 0x6 7522944501Smrg 7622944501Smrg/* Vertex/indirect buffer size 7722944501Smrg */ 7822944501Smrg#define R128_BUFFER_SIZE 16384 7922944501Smrg 8022944501Smrg/* Byte offsets for indirect buffer data 8122944501Smrg */ 8222944501Smrg#define R128_INDEX_PRIM_OFFSET 20 8322944501Smrg#define R128_HOSTDATA_BLIT_OFFSET 32 8422944501Smrg 8522944501Smrg/* Keep these small for testing. 8622944501Smrg */ 8722944501Smrg#define R128_NR_SAREA_CLIPRECTS 12 8822944501Smrg 8922944501Smrg/* There are 2 heaps (local/AGP). Each region within a heap is a 9022944501Smrg * minimum of 64k, and there are at most 64 of them per heap. 9122944501Smrg */ 9222944501Smrg#define R128_LOCAL_TEX_HEAP 0 9322944501Smrg#define R128_AGP_TEX_HEAP 1 9422944501Smrg#define R128_NR_TEX_HEAPS 2 9522944501Smrg#define R128_NR_TEX_REGIONS 64 9622944501Smrg#define R128_LOG_TEX_GRANULARITY 16 9722944501Smrg 9822944501Smrg#define R128_NR_CONTEXT_REGS 12 9922944501Smrg 10022944501Smrg#define R128_MAX_TEXTURE_LEVELS 11 10122944501Smrg#define R128_MAX_TEXTURE_UNITS 2 10222944501Smrg 10322944501Smrg#endif /* __R128_SAREA_DEFINES__ */ 10422944501Smrg 10522944501Smrgtypedef struct { 10622944501Smrg /* Context state - can be written in one large chunk */ 10722944501Smrg unsigned int dst_pitch_offset_c; 10822944501Smrg unsigned int dp_gui_master_cntl_c; 10922944501Smrg unsigned int sc_top_left_c; 11022944501Smrg unsigned int sc_bottom_right_c; 11122944501Smrg unsigned int z_offset_c; 11222944501Smrg unsigned int z_pitch_c; 11322944501Smrg unsigned int z_sten_cntl_c; 11422944501Smrg unsigned int tex_cntl_c; 11522944501Smrg unsigned int misc_3d_state_cntl_reg; 11622944501Smrg unsigned int texture_clr_cmp_clr_c; 11722944501Smrg unsigned int texture_clr_cmp_msk_c; 11822944501Smrg unsigned int fog_color_c; 11922944501Smrg 12022944501Smrg /* Texture state */ 12122944501Smrg unsigned int tex_size_pitch_c; 12222944501Smrg unsigned int constant_color_c; 12322944501Smrg 12422944501Smrg /* Setup state */ 12522944501Smrg unsigned int pm4_vc_fpu_setup; 12622944501Smrg unsigned int setup_cntl; 12722944501Smrg 12822944501Smrg /* Mask state */ 12922944501Smrg unsigned int dp_write_mask; 13022944501Smrg unsigned int sten_ref_mask_c; 13122944501Smrg unsigned int plane_3d_mask_c; 13222944501Smrg 13322944501Smrg /* Window state */ 13422944501Smrg unsigned int window_xy_offset; 13522944501Smrg 13622944501Smrg /* Core state */ 13722944501Smrg unsigned int scale_3d_cntl; 13822944501Smrg} drm_r128_context_regs_t; 13922944501Smrg 14022944501Smrg/* Setup registers for each texture unit 14122944501Smrg */ 14222944501Smrgtypedef struct { 14322944501Smrg unsigned int tex_cntl; 14422944501Smrg unsigned int tex_combine_cntl; 14522944501Smrg unsigned int tex_size_pitch; 14622944501Smrg unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS]; 14722944501Smrg unsigned int tex_border_color; 14822944501Smrg} drm_r128_texture_regs_t; 14922944501Smrg 15022944501Smrgtypedef struct drm_r128_sarea { 15122944501Smrg /* The channel for communication of state information to the kernel 15222944501Smrg * on firing a vertex buffer. 15322944501Smrg */ 15422944501Smrg drm_r128_context_regs_t context_state; 15522944501Smrg drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS]; 15622944501Smrg unsigned int dirty; 15722944501Smrg unsigned int vertsize; 15822944501Smrg unsigned int vc_format; 15922944501Smrg 16022944501Smrg /* The current cliprects, or a subset thereof. 16122944501Smrg */ 16222944501Smrg struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS]; 16322944501Smrg unsigned int nbox; 16422944501Smrg 16522944501Smrg /* Counters for client-side throttling of rendering clients. 16622944501Smrg */ 16722944501Smrg unsigned int last_frame; 16822944501Smrg unsigned int last_dispatch; 16922944501Smrg 17022944501Smrg struct drm_tex_region tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1]; 17122944501Smrg unsigned int tex_age[R128_NR_TEX_HEAPS]; 17222944501Smrg int ctx_owner; 17322944501Smrg int pfAllowPageFlip; /* number of 3d windows (0,1,2 or more) */ 17422944501Smrg int pfCurrentPage; /* which buffer is being displayed? */ 17522944501Smrg} drm_r128_sarea_t; 17622944501Smrg 17722944501Smrg/* WARNING: If you change any of these defines, make sure to change the 17822944501Smrg * defines in the Xserver file (xf86drmR128.h) 17922944501Smrg */ 18022944501Smrg 18122944501Smrg/* Rage 128 specific ioctls 18222944501Smrg * The device specific ioctl range is 0x40 to 0x79. 18322944501Smrg */ 18422944501Smrg#define DRM_R128_INIT 0x00 18522944501Smrg#define DRM_R128_CCE_START 0x01 18622944501Smrg#define DRM_R128_CCE_STOP 0x02 18722944501Smrg#define DRM_R128_CCE_RESET 0x03 18822944501Smrg#define DRM_R128_CCE_IDLE 0x04 18922944501Smrg/* 0x05 not used */ 19022944501Smrg#define DRM_R128_RESET 0x06 19122944501Smrg#define DRM_R128_SWAP 0x07 19222944501Smrg#define DRM_R128_CLEAR 0x08 19322944501Smrg#define DRM_R128_VERTEX 0x09 19422944501Smrg#define DRM_R128_INDICES 0x0a 19522944501Smrg#define DRM_R128_BLIT 0x0b 19622944501Smrg#define DRM_R128_DEPTH 0x0c 19722944501Smrg#define DRM_R128_STIPPLE 0x0d 19822944501Smrg/* 0x0e not used */ 19922944501Smrg#define DRM_R128_INDIRECT 0x0f 20022944501Smrg#define DRM_R128_FULLSCREEN 0x10 20122944501Smrg#define DRM_R128_CLEAR2 0x11 20222944501Smrg#define DRM_R128_GETPARAM 0x12 20322944501Smrg#define DRM_R128_FLIP 0x13 20422944501Smrg 20522944501Smrg#define DRM_IOCTL_R128_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t) 20622944501Smrg#define DRM_IOCTL_R128_CCE_START DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_START) 20722944501Smrg#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t) 20822944501Smrg#define DRM_IOCTL_R128_CCE_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_RESET) 20922944501Smrg#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_IDLE) 21022944501Smrg/* 0x05 not used */ 21122944501Smrg#define DRM_IOCTL_R128_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_RESET) 21222944501Smrg#define DRM_IOCTL_R128_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_R128_SWAP) 21322944501Smrg#define DRM_IOCTL_R128_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t) 21422944501Smrg#define DRM_IOCTL_R128_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t) 21522944501Smrg#define DRM_IOCTL_R128_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t) 21622944501Smrg#define DRM_IOCTL_R128_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t) 21722944501Smrg#define DRM_IOCTL_R128_DEPTH DRM_IOW( DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t) 21822944501Smrg#define DRM_IOCTL_R128_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t) 21922944501Smrg/* 0x0e not used */ 22022944501Smrg#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t) 22122944501Smrg#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t) 22222944501Smrg#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t) 22322944501Smrg#define DRM_IOCTL_R128_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t) 22422944501Smrg#define DRM_IOCTL_R128_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_R128_FLIP) 22522944501Smrg 22622944501Smrgtypedef struct drm_r128_init { 22722944501Smrg enum { 22822944501Smrg R128_INIT_CCE = 0x01, 22922944501Smrg R128_CLEANUP_CCE = 0x02 23022944501Smrg } func; 23122944501Smrg unsigned long sarea_priv_offset; 23222944501Smrg int is_pci; 23322944501Smrg int cce_mode; 23422944501Smrg int cce_secure; 23522944501Smrg int ring_size; 23622944501Smrg int usec_timeout; 23722944501Smrg 23822944501Smrg unsigned int fb_bpp; 23922944501Smrg unsigned int front_offset, front_pitch; 24022944501Smrg unsigned int back_offset, back_pitch; 24122944501Smrg unsigned int depth_bpp; 24222944501Smrg unsigned int depth_offset, depth_pitch; 24322944501Smrg unsigned int span_offset; 24422944501Smrg 24522944501Smrg unsigned long fb_offset; 24622944501Smrg unsigned long mmio_offset; 24722944501Smrg unsigned long ring_offset; 24822944501Smrg unsigned long ring_rptr_offset; 24922944501Smrg unsigned long buffers_offset; 25022944501Smrg unsigned long agp_textures_offset; 25122944501Smrg} drm_r128_init_t; 25222944501Smrg 25322944501Smrgtypedef struct drm_r128_cce_stop { 25422944501Smrg int flush; 25522944501Smrg int idle; 25622944501Smrg} drm_r128_cce_stop_t; 25722944501Smrg 25822944501Smrgtypedef struct drm_r128_clear { 25922944501Smrg unsigned int flags; 26022944501Smrg unsigned int clear_color; 26122944501Smrg unsigned int clear_depth; 26222944501Smrg unsigned int color_mask; 26322944501Smrg unsigned int depth_mask; 26422944501Smrg} drm_r128_clear_t; 26522944501Smrg 26622944501Smrgtypedef struct drm_r128_vertex { 26722944501Smrg int prim; 26822944501Smrg int idx; /* Index of vertex buffer */ 26922944501Smrg int count; /* Number of vertices in buffer */ 27022944501Smrg int discard; /* Client finished with buffer? */ 27122944501Smrg} drm_r128_vertex_t; 27222944501Smrg 27322944501Smrgtypedef struct drm_r128_indices { 27422944501Smrg int prim; 27522944501Smrg int idx; 27622944501Smrg int start; 27722944501Smrg int end; 27822944501Smrg int discard; /* Client finished with buffer? */ 27922944501Smrg} drm_r128_indices_t; 28022944501Smrg 28122944501Smrgtypedef struct drm_r128_blit { 28222944501Smrg int idx; 28322944501Smrg int pitch; 28422944501Smrg int offset; 28522944501Smrg int format; 28622944501Smrg unsigned short x, y; 28722944501Smrg unsigned short width, height; 28822944501Smrg} drm_r128_blit_t; 28922944501Smrg 29022944501Smrgtypedef struct drm_r128_depth { 29122944501Smrg enum { 29222944501Smrg R128_WRITE_SPAN = 0x01, 29322944501Smrg R128_WRITE_PIXELS = 0x02, 29422944501Smrg R128_READ_SPAN = 0x03, 29522944501Smrg R128_READ_PIXELS = 0x04 29622944501Smrg } func; 29722944501Smrg int n; 29822944501Smrg int *x; 29922944501Smrg int *y; 30022944501Smrg unsigned int *buffer; 30122944501Smrg unsigned char *mask; 30222944501Smrg} drm_r128_depth_t; 30322944501Smrg 30422944501Smrgtypedef struct drm_r128_stipple { 30522944501Smrg unsigned int *mask; 30622944501Smrg} drm_r128_stipple_t; 30722944501Smrg 30822944501Smrgtypedef struct drm_r128_indirect { 30922944501Smrg int idx; 31022944501Smrg int start; 31122944501Smrg int end; 31222944501Smrg int discard; 31322944501Smrg} drm_r128_indirect_t; 31422944501Smrg 31522944501Smrgtypedef struct drm_r128_fullscreen { 31622944501Smrg enum { 31722944501Smrg R128_INIT_FULLSCREEN = 0x01, 31822944501Smrg R128_CLEANUP_FULLSCREEN = 0x02 31922944501Smrg } func; 32022944501Smrg} drm_r128_fullscreen_t; 32122944501Smrg 32222944501Smrg/* 2.3: An ioctl to get parameters that aren't available to the 3d 32322944501Smrg * client any other way. 32422944501Smrg */ 32522944501Smrg#define R128_PARAM_IRQ_NR 1 32622944501Smrg 32722944501Smrgtypedef struct drm_r128_getparam { 32822944501Smrg int param; 32922944501Smrg void *value; 33022944501Smrg} drm_r128_getparam_t; 33122944501Smrg 33200a23bdaSmrg#if defined(__cplusplus) 33300a23bdaSmrg} 33400a23bdaSmrg#endif 33500a23bdaSmrg 33622944501Smrg#endif 337