tegra_drm.h revision 00a23bda
108d7334dSsnj/*
208d7334dSsnj * Copyright (c) 2012-2013, NVIDIA CORPORATION.  All rights reserved.
308d7334dSsnj *
408d7334dSsnj * Permission is hereby granted, free of charge, to any person obtaining a
508d7334dSsnj * copy of this software and associated documentation files (the "Software"),
608d7334dSsnj * to deal in the Software without restriction, including without limitation
708d7334dSsnj * the rights to use, copy, modify, merge, publish, distribute, sublicense,
808d7334dSsnj * and/or sell copies of the Software, and to permit persons to whom the
908d7334dSsnj * Software is furnished to do so, subject to the following conditions:
1008d7334dSsnj *
1108d7334dSsnj * The above copyright notice and this permission notice shall be included in
1208d7334dSsnj * all copies or substantial portions of the Software.
1308d7334dSsnj *
1408d7334dSsnj * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1508d7334dSsnj * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1608d7334dSsnj * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
1708d7334dSsnj * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
1808d7334dSsnj * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
1908d7334dSsnj * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2008d7334dSsnj * OTHER DEALINGS IN THE SOFTWARE.
2108d7334dSsnj */
2208d7334dSsnj
2300a23bdaSmrg#ifndef _TEGRA_DRM_H_
2400a23bdaSmrg#define _TEGRA_DRM_H_
2508d7334dSsnj
2600a23bdaSmrg#include "drm.h"
2700a23bdaSmrg
2800a23bdaSmrg#if defined(__cplusplus)
2900a23bdaSmrgextern "C" {
3000a23bdaSmrg#endif
3108d7334dSsnj
3208d7334dSsnj#define DRM_TEGRA_GEM_CREATE_TILED     (1 << 0)
3308d7334dSsnj#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
3408d7334dSsnj
3508d7334dSsnjstruct drm_tegra_gem_create {
3608d7334dSsnj	__u64 size;
3708d7334dSsnj	__u32 flags;
3808d7334dSsnj	__u32 handle;
3908d7334dSsnj};
4008d7334dSsnj
4108d7334dSsnjstruct drm_tegra_gem_mmap {
4208d7334dSsnj	__u32 handle;
433f012e29Smrg	__u32 pad;
443f012e29Smrg	__u64 offset;
4508d7334dSsnj};
4608d7334dSsnj
4708d7334dSsnjstruct drm_tegra_syncpt_read {
4808d7334dSsnj	__u32 id;
4908d7334dSsnj	__u32 value;
5008d7334dSsnj};
5108d7334dSsnj
5208d7334dSsnjstruct drm_tegra_syncpt_incr {
5308d7334dSsnj	__u32 id;
5408d7334dSsnj	__u32 pad;
5508d7334dSsnj};
5608d7334dSsnj
5708d7334dSsnjstruct drm_tegra_syncpt_wait {
5808d7334dSsnj	__u32 id;
5908d7334dSsnj	__u32 thresh;
6008d7334dSsnj	__u32 timeout;
6108d7334dSsnj	__u32 value;
6208d7334dSsnj};
6308d7334dSsnj
6408d7334dSsnj#define DRM_TEGRA_NO_TIMEOUT	(0xffffffff)
6508d7334dSsnj
6608d7334dSsnjstruct drm_tegra_open_channel {
6708d7334dSsnj	__u32 client;
6808d7334dSsnj	__u32 pad;
6908d7334dSsnj	__u64 context;
7008d7334dSsnj};
7108d7334dSsnj
7208d7334dSsnjstruct drm_tegra_close_channel {
7308d7334dSsnj	__u64 context;
7408d7334dSsnj};
7508d7334dSsnj
7608d7334dSsnjstruct drm_tegra_get_syncpt {
7708d7334dSsnj	__u64 context;
7808d7334dSsnj	__u32 index;
7908d7334dSsnj	__u32 id;
8008d7334dSsnj};
8108d7334dSsnj
8208d7334dSsnjstruct drm_tegra_get_syncpt_base {
8308d7334dSsnj	__u64 context;
8408d7334dSsnj	__u32 syncpt;
8508d7334dSsnj	__u32 id;
8608d7334dSsnj};
8708d7334dSsnj
8808d7334dSsnjstruct drm_tegra_syncpt {
8908d7334dSsnj	__u32 id;
9008d7334dSsnj	__u32 incrs;
9108d7334dSsnj};
9208d7334dSsnj
9308d7334dSsnjstruct drm_tegra_cmdbuf {
9408d7334dSsnj	__u32 handle;
9508d7334dSsnj	__u32 offset;
9608d7334dSsnj	__u32 words;
9708d7334dSsnj	__u32 pad;
9808d7334dSsnj};
9908d7334dSsnj
10008d7334dSsnjstruct drm_tegra_reloc {
10108d7334dSsnj	struct {
10208d7334dSsnj		__u32 handle;
10308d7334dSsnj		__u32 offset;
10408d7334dSsnj	} cmdbuf;
10508d7334dSsnj	struct {
10608d7334dSsnj		__u32 handle;
10708d7334dSsnj		__u32 offset;
10808d7334dSsnj	} target;
10908d7334dSsnj	__u32 shift;
11008d7334dSsnj	__u32 pad;
11108d7334dSsnj};
11208d7334dSsnj
11308d7334dSsnjstruct drm_tegra_waitchk {
11408d7334dSsnj	__u32 handle;
11508d7334dSsnj	__u32 offset;
11608d7334dSsnj	__u32 syncpt;
11708d7334dSsnj	__u32 thresh;
11808d7334dSsnj};
11908d7334dSsnj
12008d7334dSsnjstruct drm_tegra_submit {
12108d7334dSsnj	__u64 context;
12208d7334dSsnj	__u32 num_syncpts;
12308d7334dSsnj	__u32 num_cmdbufs;
12408d7334dSsnj	__u32 num_relocs;
12508d7334dSsnj	__u32 num_waitchks;
12608d7334dSsnj	__u32 waitchk_mask;
12708d7334dSsnj	__u32 timeout;
12808d7334dSsnj	__u64 syncpts;
12908d7334dSsnj	__u64 cmdbufs;
13008d7334dSsnj	__u64 relocs;
13108d7334dSsnj	__u64 waitchks;
13208d7334dSsnj	__u32 fence;		/* Return value */
13308d7334dSsnj
13408d7334dSsnj	__u32 reserved[5];	/* future expansion */
13508d7334dSsnj};
13608d7334dSsnj
13708d7334dSsnj#define DRM_TEGRA_GEM_TILING_MODE_PITCH 0
13808d7334dSsnj#define DRM_TEGRA_GEM_TILING_MODE_TILED 1
13908d7334dSsnj#define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2
14008d7334dSsnj
14108d7334dSsnjstruct drm_tegra_gem_set_tiling {
14208d7334dSsnj	/* input */
14308d7334dSsnj	__u32 handle;
14408d7334dSsnj	__u32 mode;
14508d7334dSsnj	__u32 value;
14608d7334dSsnj	__u32 pad;
14708d7334dSsnj};
14808d7334dSsnj
14908d7334dSsnjstruct drm_tegra_gem_get_tiling {
15008d7334dSsnj	/* input */
15108d7334dSsnj	__u32 handle;
15208d7334dSsnj	/* output */
15308d7334dSsnj	__u32 mode;
15408d7334dSsnj	__u32 value;
15508d7334dSsnj	__u32 pad;
15608d7334dSsnj};
15708d7334dSsnj
15808d7334dSsnj#define DRM_TEGRA_GEM_BOTTOM_UP		(1 << 0)
15908d7334dSsnj#define DRM_TEGRA_GEM_FLAGS		(DRM_TEGRA_GEM_BOTTOM_UP)
16008d7334dSsnj
16108d7334dSsnjstruct drm_tegra_gem_set_flags {
16208d7334dSsnj	/* input */
16308d7334dSsnj	__u32 handle;
16408d7334dSsnj	/* output */
16508d7334dSsnj	__u32 flags;
16608d7334dSsnj};
16708d7334dSsnj
16808d7334dSsnjstruct drm_tegra_gem_get_flags {
16908d7334dSsnj	/* input */
17008d7334dSsnj	__u32 handle;
17108d7334dSsnj	/* output */
17208d7334dSsnj	__u32 flags;
17308d7334dSsnj};
17408d7334dSsnj
17508d7334dSsnj#define DRM_TEGRA_GEM_CREATE		0x00
17608d7334dSsnj#define DRM_TEGRA_GEM_MMAP		0x01
17708d7334dSsnj#define DRM_TEGRA_SYNCPT_READ		0x02
17808d7334dSsnj#define DRM_TEGRA_SYNCPT_INCR		0x03
17908d7334dSsnj#define DRM_TEGRA_SYNCPT_WAIT		0x04
18008d7334dSsnj#define DRM_TEGRA_OPEN_CHANNEL		0x05
18108d7334dSsnj#define DRM_TEGRA_CLOSE_CHANNEL		0x06
18208d7334dSsnj#define DRM_TEGRA_GET_SYNCPT		0x07
18308d7334dSsnj#define DRM_TEGRA_SUBMIT		0x08
18408d7334dSsnj#define DRM_TEGRA_GET_SYNCPT_BASE	0x09
18508d7334dSsnj#define DRM_TEGRA_GEM_SET_TILING	0x0a
18608d7334dSsnj#define DRM_TEGRA_GEM_GET_TILING	0x0b
18708d7334dSsnj#define DRM_TEGRA_GEM_SET_FLAGS		0x0c
18808d7334dSsnj#define DRM_TEGRA_GEM_GET_FLAGS		0x0d
18908d7334dSsnj
19008d7334dSsnj#define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create)
19108d7334dSsnj#define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap)
19208d7334dSsnj#define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read)
19308d7334dSsnj#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
19408d7334dSsnj#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
19508d7334dSsnj#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
19608d7334dSsnj#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel)
19708d7334dSsnj#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
19808d7334dSsnj#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
19908d7334dSsnj#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base)
20008d7334dSsnj#define DRM_IOCTL_TEGRA_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_TILING, struct drm_tegra_gem_set_tiling)
20108d7334dSsnj#define DRM_IOCTL_TEGRA_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling)
20208d7334dSsnj#define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags)
20308d7334dSsnj#define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags)
20408d7334dSsnj
20500a23bdaSmrg#if defined(__cplusplus)
20600a23bdaSmrg}
20700a23bdaSmrg#endif
20800a23bdaSmrg
20908d7334dSsnj#endif
210