122944501Smrg/*
2e88f27b3Smrg * Copyright © 2008-2012 Intel Corporation
322944501Smrg *
422944501Smrg * Permission is hereby granted, free of charge, to any person obtaining a
522944501Smrg * copy of this software and associated documentation files (the "Software"),
622944501Smrg * to deal in the Software without restriction, including without limitation
722944501Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
822944501Smrg * and/or sell copies of the Software, and to permit persons to whom the
922944501Smrg * Software is furnished to do so, subject to the following conditions:
1022944501Smrg *
1122944501Smrg * The above copyright notice and this permission notice (including the next
1222944501Smrg * paragraph) shall be included in all copies or substantial portions of the
1322944501Smrg * Software.
1422944501Smrg *
1522944501Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1622944501Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1722944501Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
1822944501Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
1922944501Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2022944501Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
2122944501Smrg * IN THE SOFTWARE.
2222944501Smrg *
2322944501Smrg * Authors:
2422944501Smrg *    Eric Anholt <eric@anholt.net>
2522944501Smrg *
2622944501Smrg */
2722944501Smrg
2822944501Smrg/**
2922944501Smrg * @file intel_bufmgr.h
3022944501Smrg *
3122944501Smrg * Public definitions of Intel-specific bufmgr functions.
3222944501Smrg */
3322944501Smrg
3422944501Smrg#ifndef INTEL_BUFMGR_H
3522944501Smrg#define INTEL_BUFMGR_H
3622944501Smrg
37e88f27b3Smrg#include <stdio.h>
3822944501Smrg#include <stdint.h>
39e88f27b3Smrg#include <stdio.h>
4022944501Smrg
413f012e29Smrg#if defined(__cplusplus)
423f012e29Smrgextern "C" {
433f012e29Smrg#endif
443f012e29Smrg
4569dda199Smrgstruct drm_clip_rect;
4669dda199Smrg
4722944501Smrgtypedef struct _drm_intel_bufmgr drm_intel_bufmgr;
48e88f27b3Smrgtypedef struct _drm_intel_context drm_intel_context;
4922944501Smrgtypedef struct _drm_intel_bo drm_intel_bo;
5022944501Smrg
5122944501Smrgstruct _drm_intel_bo {
5222944501Smrg	/**
5322944501Smrg	 * Size in bytes of the buffer object.
5422944501Smrg	 *
5522944501Smrg	 * The size may be larger than the size originally requested for the
5622944501Smrg	 * allocation, such as being aligned to page size.
5722944501Smrg	 */
5822944501Smrg	unsigned long size;
5922944501Smrg
6022944501Smrg	/**
6122944501Smrg	 * Alignment requirement for object
6222944501Smrg	 *
6322944501Smrg	 * Used for GTT mapping & pinning the object.
6422944501Smrg	 */
6522944501Smrg	unsigned long align;
6622944501Smrg
6722944501Smrg	/**
68e88f27b3Smrg	 * Deprecated field containing (possibly the low 32-bits of) the last
69e88f27b3Smrg	 * seen virtual card address.  Use offset64 instead.
7022944501Smrg	 */
7122944501Smrg	unsigned long offset;
7222944501Smrg
7322944501Smrg	/**
7422944501Smrg	 * Virtual address for accessing the buffer data.  Only valid while
7522944501Smrg	 * mapped.
7622944501Smrg	 */
77d049871aSmrg#ifdef __cplusplus
78d049871aSmrg	void *virt;
79d049871aSmrg#else
8022944501Smrg	void *virtual;
81d049871aSmrg#endif
8222944501Smrg
8322944501Smrg	/** Buffer manager context associated with this buffer object */
8422944501Smrg	drm_intel_bufmgr *bufmgr;
8522944501Smrg
8622944501Smrg	/**
8722944501Smrg	 * MM-specific handle for accessing object
8822944501Smrg	 */
8922944501Smrg	int handle;
90e88f27b3Smrg
91e88f27b3Smrg	/**
92e88f27b3Smrg	 * Last seen card virtual address (offset from the beginning of the
93e88f27b3Smrg	 * aperture) for the object.  This should be used to fill relocation
94e88f27b3Smrg	 * entries when calling drm_intel_bo_emit_reloc()
95e88f27b3Smrg	 */
96e88f27b3Smrg	uint64_t offset64;
97e88f27b3Smrg};
98e88f27b3Smrg
99e88f27b3Smrgenum aub_dump_bmp_format {
100e88f27b3Smrg	AUB_DUMP_BMP_FORMAT_8BIT = 1,
101e88f27b3Smrg	AUB_DUMP_BMP_FORMAT_ARGB_4444 = 4,
102e88f27b3Smrg	AUB_DUMP_BMP_FORMAT_ARGB_0888 = 6,
103e88f27b3Smrg	AUB_DUMP_BMP_FORMAT_ARGB_8888 = 7,
10422944501Smrg};
10522944501Smrg
106e88f27b3Smrgtypedef struct _drm_intel_aub_annotation {
107e88f27b3Smrg	uint32_t type;
108e88f27b3Smrg	uint32_t subtype;
109e88f27b3Smrg	uint32_t ending_offset;
110e88f27b3Smrg} drm_intel_aub_annotation;
111e88f27b3Smrg
11222944501Smrg#define BO_ALLOC_FOR_RENDER (1<<0)
11322944501Smrg
11422944501Smrgdrm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
11522944501Smrg				 unsigned long size, unsigned int alignment);
11622944501Smrgdrm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
11722944501Smrg					    const char *name,
11822944501Smrg					    unsigned long size,
11922944501Smrg					    unsigned int alignment);
120baaff307Smrgdrm_intel_bo *drm_intel_bo_alloc_userptr(drm_intel_bufmgr *bufmgr,
121baaff307Smrg					const char *name,
122baaff307Smrg					void *addr, uint32_t tiling_mode,
123baaff307Smrg					uint32_t stride, unsigned long size,
124baaff307Smrg					unsigned long flags);
12522944501Smrgdrm_intel_bo *drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr,
12622944501Smrg				       const char *name,
12722944501Smrg				       int x, int y, int cpp,
12822944501Smrg				       uint32_t *tiling_mode,
12922944501Smrg				       unsigned long *pitch,
13022944501Smrg				       unsigned long flags);
13122944501Smrgvoid drm_intel_bo_reference(drm_intel_bo *bo);
13222944501Smrgvoid drm_intel_bo_unreference(drm_intel_bo *bo);
13322944501Smrgint drm_intel_bo_map(drm_intel_bo *bo, int write_enable);
13422944501Smrgint drm_intel_bo_unmap(drm_intel_bo *bo);
13522944501Smrg
13622944501Smrgint drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
13722944501Smrg			 unsigned long size, const void *data);
13822944501Smrgint drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
13922944501Smrg			     unsigned long size, void *data);
14022944501Smrgvoid drm_intel_bo_wait_rendering(drm_intel_bo *bo);
14122944501Smrg
14222944501Smrgvoid drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug);
14322944501Smrgvoid drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr);
14422944501Smrgint drm_intel_bo_exec(drm_intel_bo *bo, int used,
14569dda199Smrg		      struct drm_clip_rect *cliprects, int num_cliprects, int DR4);
14613d1d17dSmrgint drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
14769dda199Smrg			struct drm_clip_rect *cliprects, int num_cliprects, int DR4,
148e88f27b3Smrg			unsigned int flags);
14922944501Smrgint drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count);
15022944501Smrg
15122944501Smrgint drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
15222944501Smrg			    drm_intel_bo *target_bo, uint32_t target_offset,
15322944501Smrg			    uint32_t read_domains, uint32_t write_domain);
15422944501Smrgint drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
15522944501Smrg				  drm_intel_bo *target_bo,
15622944501Smrg				  uint32_t target_offset,
15722944501Smrg				  uint32_t read_domains, uint32_t write_domain);
15822944501Smrgint drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment);
15922944501Smrgint drm_intel_bo_unpin(drm_intel_bo *bo);
16022944501Smrgint drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
16122944501Smrg			    uint32_t stride);
16222944501Smrgint drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
16322944501Smrg			    uint32_t * swizzle_mode);
16422944501Smrgint drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name);
16522944501Smrgint drm_intel_bo_busy(drm_intel_bo *bo);
16622944501Smrgint drm_intel_bo_madvise(drm_intel_bo *bo, int madv);
1673f012e29Smrgint drm_intel_bo_use_48b_address_range(drm_intel_bo *bo, uint32_t enable);
1683f012e29Smrgint drm_intel_bo_set_softpin_offset(drm_intel_bo *bo, uint64_t offset);
16922944501Smrg
17022944501Smrgint drm_intel_bo_disable_reuse(drm_intel_bo *bo);
17113d1d17dSmrgint drm_intel_bo_is_reusable(drm_intel_bo *bo);
17222944501Smrgint drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo);
17322944501Smrg
17422944501Smrg/* drm_intel_bufmgr_gem.c */
17522944501Smrgdrm_intel_bufmgr *drm_intel_bufmgr_gem_init(int fd, int batch_size);
17622944501Smrgdrm_intel_bo *drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
17722944501Smrg						const char *name,
17822944501Smrg						unsigned int handle);
17922944501Smrgvoid drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr);
18022944501Smrgvoid drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr);
181e88f27b3Smrgvoid drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr,
182e88f27b3Smrg					     int limit);
183e88f27b3Smrgint drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo);
18422944501Smrgint drm_intel_gem_bo_map_gtt(drm_intel_bo *bo);
18522944501Smrgint drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo);
186e88f27b3Smrg
187037b3c26Smrg#define HAVE_DRM_INTEL_GEM_BO_DISABLE_IMPLICIT_SYNC 1
188037b3c26Smrgint drm_intel_bufmgr_gem_can_disable_implicit_sync(drm_intel_bufmgr *bufmgr);
189037b3c26Smrgvoid drm_intel_gem_bo_disable_implicit_sync(drm_intel_bo *bo);
190037b3c26Smrgvoid drm_intel_gem_bo_enable_implicit_sync(drm_intel_bo *bo);
191037b3c26Smrg
192037b3c26Smrgvoid *drm_intel_gem_bo_map__cpu(drm_intel_bo *bo);
193037b3c26Smrgvoid *drm_intel_gem_bo_map__gtt(drm_intel_bo *bo);
194037b3c26Smrgvoid *drm_intel_gem_bo_map__wc(drm_intel_bo *bo);
195037b3c26Smrg
196e88f27b3Smrgint drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo);
197e88f27b3Smrgvoid drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start);
19822944501Smrgvoid drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable);
19922944501Smrg
200e88f27b3Smrgvoid
201e88f27b3Smrgdrm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
202e88f27b3Smrg				      const char *filename);
203e88f27b3Smrgvoid drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable);
204e88f27b3Smrgvoid drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
205e88f27b3Smrg				   int x1, int y1, int width, int height,
206e88f27b3Smrg				   enum aub_dump_bmp_format format,
207e88f27b3Smrg				   int pitch, int offset);
208e88f27b3Smrgvoid
209e88f27b3Smrgdrm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
210e88f27b3Smrg					 drm_intel_aub_annotation *annotations,
211e88f27b3Smrg					 unsigned count);
212e88f27b3Smrg
21322944501Smrgint drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id);
21422944501Smrg
215e88f27b3Smrgint drm_intel_get_aperture_sizes(int fd, size_t *mappable, size_t *total);
216e88f27b3Smrgint drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr);
217e88f27b3Smrgint drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns);
218e88f27b3Smrg
219e88f27b3Smrgdrm_intel_context *drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr);
220037b3c26Smrgint drm_intel_gem_context_get_id(drm_intel_context *ctx,
221037b3c26Smrg                                 uint32_t *ctx_id);
222e88f27b3Smrgvoid drm_intel_gem_context_destroy(drm_intel_context *ctx);
223e88f27b3Smrgint drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
224e88f27b3Smrg				  int used, unsigned int flags);
225037b3c26Smrgint drm_intel_gem_bo_fence_exec(drm_intel_bo *bo,
226037b3c26Smrg				drm_intel_context *ctx,
227037b3c26Smrg				int used,
228037b3c26Smrg				int in_fence,
229037b3c26Smrg				int *out_fence,
230037b3c26Smrg				unsigned int flags);
231e88f27b3Smrg
232e88f27b3Smrgint drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd);
233e88f27b3Smrgdrm_intel_bo *drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr,
234e88f27b3Smrg						int prime_fd, int size);
235e88f27b3Smrg
23622944501Smrg/* drm_intel_bufmgr_fake.c */
23722944501Smrgdrm_intel_bufmgr *drm_intel_bufmgr_fake_init(int fd,
23822944501Smrg					     unsigned long low_offset,
23922944501Smrg					     void *low_virtual,
24022944501Smrg					     unsigned long size,
24122944501Smrg					     volatile unsigned int
24222944501Smrg					     *last_dispatch);
24322944501Smrgvoid drm_intel_bufmgr_fake_set_last_dispatch(drm_intel_bufmgr *bufmgr,
24422944501Smrg					     volatile unsigned int
24522944501Smrg					     *last_dispatch);
24622944501Smrgvoid drm_intel_bufmgr_fake_set_exec_callback(drm_intel_bufmgr *bufmgr,
24722944501Smrg					     int (*exec) (drm_intel_bo *bo,
24822944501Smrg							  unsigned int used,
24922944501Smrg							  void *priv),
25022944501Smrg					     void *priv);
25122944501Smrgvoid drm_intel_bufmgr_fake_set_fence_callback(drm_intel_bufmgr *bufmgr,
25222944501Smrg					      unsigned int (*emit) (void *priv),
25322944501Smrg					      void (*wait) (unsigned int fence,
25422944501Smrg							    void *priv),
25522944501Smrg					      void *priv);
25622944501Smrgdrm_intel_bo *drm_intel_bo_fake_alloc_static(drm_intel_bufmgr *bufmgr,
25722944501Smrg					     const char *name,
25822944501Smrg					     unsigned long offset,
259d049871aSmrg					     unsigned long size, void *virt);
26022944501Smrgvoid drm_intel_bo_fake_disable_backing_store(drm_intel_bo *bo,
26122944501Smrg					     void (*invalidate_cb) (drm_intel_bo
26222944501Smrg								    * bo,
26322944501Smrg								    void *ptr),
26422944501Smrg					     void *ptr);
26522944501Smrg
26622944501Smrgvoid drm_intel_bufmgr_fake_contended_lock_take(drm_intel_bufmgr *bufmgr);
26722944501Smrgvoid drm_intel_bufmgr_fake_evict_all(drm_intel_bufmgr *bufmgr);
26822944501Smrg
269e88f27b3Smrgstruct drm_intel_decode *drm_intel_decode_context_alloc(uint32_t devid);
270e88f27b3Smrgvoid drm_intel_decode_context_free(struct drm_intel_decode *ctx);
271e88f27b3Smrgvoid drm_intel_decode_set_batch_pointer(struct drm_intel_decode *ctx,
272e88f27b3Smrg					void *data, uint32_t hw_offset,
273e88f27b3Smrg					int count);
274e88f27b3Smrgvoid drm_intel_decode_set_dump_past_end(struct drm_intel_decode *ctx,
275e88f27b3Smrg					int dump_past_end);
276e88f27b3Smrgvoid drm_intel_decode_set_head_tail(struct drm_intel_decode *ctx,
277e88f27b3Smrg				    uint32_t head, uint32_t tail);
278e88f27b3Smrgvoid drm_intel_decode_set_output_file(struct drm_intel_decode *ctx, FILE *out);
279e88f27b3Smrgvoid drm_intel_decode(struct drm_intel_decode *ctx);
280e88f27b3Smrg
281e88f27b3Smrgint drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
282e88f27b3Smrg		       uint32_t offset,
283e88f27b3Smrg		       uint64_t *result);
284e88f27b3Smrg
285e88f27b3Smrgint drm_intel_get_reset_stats(drm_intel_context *ctx,
286e88f27b3Smrg			      uint32_t *reset_count,
287e88f27b3Smrg			      uint32_t *active,
288e88f27b3Smrg			      uint32_t *pending);
289e88f27b3Smrg
290e6188e58Smrgint drm_intel_get_subslice_total(int fd, unsigned int *subslice_total);
291e6188e58Smrgint drm_intel_get_eu_total(int fd, unsigned int *eu_total);
292e6188e58Smrg
293037b3c26Smrgint drm_intel_get_pooled_eu(int fd);
294037b3c26Smrgint drm_intel_get_min_eu_in_pool(int fd);
295037b3c26Smrg
29622944501Smrg/** @{ Compatibility defines to keep old code building despite the symbol rename
29722944501Smrg * from dri_* to drm_intel_*
29822944501Smrg */
29922944501Smrg#define dri_bo drm_intel_bo
30022944501Smrg#define dri_bufmgr drm_intel_bufmgr
30122944501Smrg#define dri_bo_alloc drm_intel_bo_alloc
30222944501Smrg#define dri_bo_reference drm_intel_bo_reference
30322944501Smrg#define dri_bo_unreference drm_intel_bo_unreference
30422944501Smrg#define dri_bo_map drm_intel_bo_map
30522944501Smrg#define dri_bo_unmap drm_intel_bo_unmap
30622944501Smrg#define dri_bo_subdata drm_intel_bo_subdata
30722944501Smrg#define dri_bo_get_subdata drm_intel_bo_get_subdata
30822944501Smrg#define dri_bo_wait_rendering drm_intel_bo_wait_rendering
30922944501Smrg#define dri_bufmgr_set_debug drm_intel_bufmgr_set_debug
31022944501Smrg#define dri_bufmgr_destroy drm_intel_bufmgr_destroy
31122944501Smrg#define dri_bo_exec drm_intel_bo_exec
31222944501Smrg#define dri_bufmgr_check_aperture_space drm_intel_bufmgr_check_aperture_space
31322944501Smrg#define dri_bo_emit_reloc(reloc_bo, read, write, target_offset,		\
31422944501Smrg			  reloc_offset, target_bo)			\
31522944501Smrg	drm_intel_bo_emit_reloc(reloc_bo, reloc_offset,			\
31622944501Smrg				target_bo, target_offset,		\
31722944501Smrg				read, write);
31822944501Smrg#define dri_bo_pin drm_intel_bo_pin
31922944501Smrg#define dri_bo_unpin drm_intel_bo_unpin
32022944501Smrg#define dri_bo_get_tiling drm_intel_bo_get_tiling
32122944501Smrg#define dri_bo_set_tiling(bo, mode) drm_intel_bo_set_tiling(bo, mode, 0)
32222944501Smrg#define dri_bo_flink drm_intel_bo_flink
32322944501Smrg#define intel_bufmgr_gem_init drm_intel_bufmgr_gem_init
32422944501Smrg#define intel_bo_gem_create_from_name drm_intel_bo_gem_create_from_name
32522944501Smrg#define intel_bufmgr_gem_enable_reuse drm_intel_bufmgr_gem_enable_reuse
32622944501Smrg#define intel_bufmgr_fake_init drm_intel_bufmgr_fake_init
32722944501Smrg#define intel_bufmgr_fake_set_last_dispatch drm_intel_bufmgr_fake_set_last_dispatch
32822944501Smrg#define intel_bufmgr_fake_set_exec_callback drm_intel_bufmgr_fake_set_exec_callback
32922944501Smrg#define intel_bufmgr_fake_set_fence_callback drm_intel_bufmgr_fake_set_fence_callback
33022944501Smrg#define intel_bo_fake_alloc_static drm_intel_bo_fake_alloc_static
33122944501Smrg#define intel_bo_fake_disable_backing_store drm_intel_bo_fake_disable_backing_store
33222944501Smrg#define intel_bufmgr_fake_contended_lock_take drm_intel_bufmgr_fake_contended_lock_take
33322944501Smrg#define intel_bufmgr_fake_evict_all drm_intel_bufmgr_fake_evict_all
33422944501Smrg
33522944501Smrg/** @{ */
33622944501Smrg
3373f012e29Smrg#if defined(__cplusplus)
3383f012e29Smrg}
3393f012e29Smrg#endif
3403f012e29Smrg
34122944501Smrg#endif /* INTEL_BUFMGR_H */
342