intel_bufmgr.h revision e88f27b3
122944501Smrg/* 2e88f27b3Smrg * Copyright © 2008-2012 Intel Corporation 322944501Smrg * 422944501Smrg * Permission is hereby granted, free of charge, to any person obtaining a 522944501Smrg * copy of this software and associated documentation files (the "Software"), 622944501Smrg * to deal in the Software without restriction, including without limitation 722944501Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 822944501Smrg * and/or sell copies of the Software, and to permit persons to whom the 922944501Smrg * Software is furnished to do so, subject to the following conditions: 1022944501Smrg * 1122944501Smrg * The above copyright notice and this permission notice (including the next 1222944501Smrg * paragraph) shall be included in all copies or substantial portions of the 1322944501Smrg * Software. 1422944501Smrg * 1522944501Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1622944501Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1722944501Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1822944501Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 1922944501Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 2022944501Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 2122944501Smrg * IN THE SOFTWARE. 2222944501Smrg * 2322944501Smrg * Authors: 2422944501Smrg * Eric Anholt <eric@anholt.net> 2522944501Smrg * 2622944501Smrg */ 2722944501Smrg 2822944501Smrg/** 2922944501Smrg * @file intel_bufmgr.h 3022944501Smrg * 3122944501Smrg * Public definitions of Intel-specific bufmgr functions. 3222944501Smrg */ 3322944501Smrg 3422944501Smrg#ifndef INTEL_BUFMGR_H 3522944501Smrg#define INTEL_BUFMGR_H 3622944501Smrg 37e88f27b3Smrg#include <stdio.h> 3822944501Smrg#include <stdint.h> 39e88f27b3Smrg#include <stdio.h> 4022944501Smrg 4169dda199Smrgstruct drm_clip_rect; 4269dda199Smrg 4322944501Smrgtypedef struct _drm_intel_bufmgr drm_intel_bufmgr; 44e88f27b3Smrgtypedef struct _drm_intel_context drm_intel_context; 4522944501Smrgtypedef struct _drm_intel_bo drm_intel_bo; 4622944501Smrg 4722944501Smrgstruct _drm_intel_bo { 4822944501Smrg /** 4922944501Smrg * Size in bytes of the buffer object. 5022944501Smrg * 5122944501Smrg * The size may be larger than the size originally requested for the 5222944501Smrg * allocation, such as being aligned to page size. 5322944501Smrg */ 5422944501Smrg unsigned long size; 5522944501Smrg 5622944501Smrg /** 5722944501Smrg * Alignment requirement for object 5822944501Smrg * 5922944501Smrg * Used for GTT mapping & pinning the object. 6022944501Smrg */ 6122944501Smrg unsigned long align; 6222944501Smrg 6322944501Smrg /** 64e88f27b3Smrg * Deprecated field containing (possibly the low 32-bits of) the last 65e88f27b3Smrg * seen virtual card address. Use offset64 instead. 6622944501Smrg */ 6722944501Smrg unsigned long offset; 6822944501Smrg 6922944501Smrg /** 7022944501Smrg * Virtual address for accessing the buffer data. Only valid while 7122944501Smrg * mapped. 7222944501Smrg */ 73d049871aSmrg#ifdef __cplusplus 74d049871aSmrg void *virt; 75d049871aSmrg#else 7622944501Smrg void *virtual; 77d049871aSmrg#endif 7822944501Smrg 7922944501Smrg /** Buffer manager context associated with this buffer object */ 8022944501Smrg drm_intel_bufmgr *bufmgr; 8122944501Smrg 8222944501Smrg /** 8322944501Smrg * MM-specific handle for accessing object 8422944501Smrg */ 8522944501Smrg int handle; 86e88f27b3Smrg 87e88f27b3Smrg /** 88e88f27b3Smrg * Last seen card virtual address (offset from the beginning of the 89e88f27b3Smrg * aperture) for the object. This should be used to fill relocation 90e88f27b3Smrg * entries when calling drm_intel_bo_emit_reloc() 91e88f27b3Smrg */ 92e88f27b3Smrg uint64_t offset64; 93e88f27b3Smrg}; 94e88f27b3Smrg 95e88f27b3Smrgenum aub_dump_bmp_format { 96e88f27b3Smrg AUB_DUMP_BMP_FORMAT_8BIT = 1, 97e88f27b3Smrg AUB_DUMP_BMP_FORMAT_ARGB_4444 = 4, 98e88f27b3Smrg AUB_DUMP_BMP_FORMAT_ARGB_0888 = 6, 99e88f27b3Smrg AUB_DUMP_BMP_FORMAT_ARGB_8888 = 7, 10022944501Smrg}; 10122944501Smrg 102e88f27b3Smrgtypedef struct _drm_intel_aub_annotation { 103e88f27b3Smrg uint32_t type; 104e88f27b3Smrg uint32_t subtype; 105e88f27b3Smrg uint32_t ending_offset; 106e88f27b3Smrg} drm_intel_aub_annotation; 107e88f27b3Smrg 10822944501Smrg#define BO_ALLOC_FOR_RENDER (1<<0) 10922944501Smrg 11022944501Smrgdrm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name, 11122944501Smrg unsigned long size, unsigned int alignment); 11222944501Smrgdrm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, 11322944501Smrg const char *name, 11422944501Smrg unsigned long size, 11522944501Smrg unsigned int alignment); 11622944501Smrgdrm_intel_bo *drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, 11722944501Smrg const char *name, 11822944501Smrg int x, int y, int cpp, 11922944501Smrg uint32_t *tiling_mode, 12022944501Smrg unsigned long *pitch, 12122944501Smrg unsigned long flags); 12222944501Smrgvoid drm_intel_bo_reference(drm_intel_bo *bo); 12322944501Smrgvoid drm_intel_bo_unreference(drm_intel_bo *bo); 12422944501Smrgint drm_intel_bo_map(drm_intel_bo *bo, int write_enable); 12522944501Smrgint drm_intel_bo_unmap(drm_intel_bo *bo); 12622944501Smrg 12722944501Smrgint drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset, 12822944501Smrg unsigned long size, const void *data); 12922944501Smrgint drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset, 13022944501Smrg unsigned long size, void *data); 13122944501Smrgvoid drm_intel_bo_wait_rendering(drm_intel_bo *bo); 13222944501Smrg 13322944501Smrgvoid drm_intel_bufmgr_set_debug(drm_intel_bufmgr *bufmgr, int enable_debug); 13422944501Smrgvoid drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr); 13522944501Smrgint drm_intel_bo_exec(drm_intel_bo *bo, int used, 13669dda199Smrg struct drm_clip_rect *cliprects, int num_cliprects, int DR4); 13713d1d17dSmrgint drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used, 13869dda199Smrg struct drm_clip_rect *cliprects, int num_cliprects, int DR4, 139e88f27b3Smrg unsigned int flags); 14022944501Smrgint drm_intel_bufmgr_check_aperture_space(drm_intel_bo ** bo_array, int count); 14122944501Smrg 14222944501Smrgint drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset, 14322944501Smrg drm_intel_bo *target_bo, uint32_t target_offset, 14422944501Smrg uint32_t read_domains, uint32_t write_domain); 14522944501Smrgint drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset, 14622944501Smrg drm_intel_bo *target_bo, 14722944501Smrg uint32_t target_offset, 14822944501Smrg uint32_t read_domains, uint32_t write_domain); 14922944501Smrgint drm_intel_bo_pin(drm_intel_bo *bo, uint32_t alignment); 15022944501Smrgint drm_intel_bo_unpin(drm_intel_bo *bo); 15122944501Smrgint drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, 15222944501Smrg uint32_t stride); 15322944501Smrgint drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, 15422944501Smrg uint32_t * swizzle_mode); 15522944501Smrgint drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name); 15622944501Smrgint drm_intel_bo_busy(drm_intel_bo *bo); 15722944501Smrgint drm_intel_bo_madvise(drm_intel_bo *bo, int madv); 15822944501Smrg 15922944501Smrgint drm_intel_bo_disable_reuse(drm_intel_bo *bo); 16013d1d17dSmrgint drm_intel_bo_is_reusable(drm_intel_bo *bo); 16122944501Smrgint drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo); 16222944501Smrg 16322944501Smrg/* drm_intel_bufmgr_gem.c */ 16422944501Smrgdrm_intel_bufmgr *drm_intel_bufmgr_gem_init(int fd, int batch_size); 16522944501Smrgdrm_intel_bo *drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr, 16622944501Smrg const char *name, 16722944501Smrg unsigned int handle); 16822944501Smrgvoid drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr); 16922944501Smrgvoid drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr); 170e88f27b3Smrgvoid drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr, 171e88f27b3Smrg int limit); 172e88f27b3Smrgint drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo); 17322944501Smrgint drm_intel_gem_bo_map_gtt(drm_intel_bo *bo); 17422944501Smrgint drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo); 175e88f27b3Smrg 176e88f27b3Smrgint drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo); 177e88f27b3Smrgvoid drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start); 17822944501Smrgvoid drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable); 17922944501Smrg 180e88f27b3Smrgvoid 181e88f27b3Smrgdrm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr, 182e88f27b3Smrg const char *filename); 183e88f27b3Smrgvoid drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable); 184e88f27b3Smrgvoid drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo, 185e88f27b3Smrg int x1, int y1, int width, int height, 186e88f27b3Smrg enum aub_dump_bmp_format format, 187e88f27b3Smrg int pitch, int offset); 188e88f27b3Smrgvoid 189e88f27b3Smrgdrm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo, 190e88f27b3Smrg drm_intel_aub_annotation *annotations, 191e88f27b3Smrg unsigned count); 192e88f27b3Smrg 19322944501Smrgint drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id); 19422944501Smrg 195e88f27b3Smrgint drm_intel_get_aperture_sizes(int fd, size_t *mappable, size_t *total); 196e88f27b3Smrgint drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr); 197e88f27b3Smrgint drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns); 198e88f27b3Smrg 199e88f27b3Smrgdrm_intel_context *drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr); 200e88f27b3Smrgvoid drm_intel_gem_context_destroy(drm_intel_context *ctx); 201e88f27b3Smrgint drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx, 202e88f27b3Smrg int used, unsigned int flags); 203e88f27b3Smrg 204e88f27b3Smrgint drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd); 205e88f27b3Smrgdrm_intel_bo *drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr, 206e88f27b3Smrg int prime_fd, int size); 207e88f27b3Smrg 20822944501Smrg/* drm_intel_bufmgr_fake.c */ 20922944501Smrgdrm_intel_bufmgr *drm_intel_bufmgr_fake_init(int fd, 21022944501Smrg unsigned long low_offset, 21122944501Smrg void *low_virtual, 21222944501Smrg unsigned long size, 21322944501Smrg volatile unsigned int 21422944501Smrg *last_dispatch); 21522944501Smrgvoid drm_intel_bufmgr_fake_set_last_dispatch(drm_intel_bufmgr *bufmgr, 21622944501Smrg volatile unsigned int 21722944501Smrg *last_dispatch); 21822944501Smrgvoid drm_intel_bufmgr_fake_set_exec_callback(drm_intel_bufmgr *bufmgr, 21922944501Smrg int (*exec) (drm_intel_bo *bo, 22022944501Smrg unsigned int used, 22122944501Smrg void *priv), 22222944501Smrg void *priv); 22322944501Smrgvoid drm_intel_bufmgr_fake_set_fence_callback(drm_intel_bufmgr *bufmgr, 22422944501Smrg unsigned int (*emit) (void *priv), 22522944501Smrg void (*wait) (unsigned int fence, 22622944501Smrg void *priv), 22722944501Smrg void *priv); 22822944501Smrgdrm_intel_bo *drm_intel_bo_fake_alloc_static(drm_intel_bufmgr *bufmgr, 22922944501Smrg const char *name, 23022944501Smrg unsigned long offset, 231d049871aSmrg unsigned long size, void *virt); 23222944501Smrgvoid drm_intel_bo_fake_disable_backing_store(drm_intel_bo *bo, 23322944501Smrg void (*invalidate_cb) (drm_intel_bo 23422944501Smrg * bo, 23522944501Smrg void *ptr), 23622944501Smrg void *ptr); 23722944501Smrg 23822944501Smrgvoid drm_intel_bufmgr_fake_contended_lock_take(drm_intel_bufmgr *bufmgr); 23922944501Smrgvoid drm_intel_bufmgr_fake_evict_all(drm_intel_bufmgr *bufmgr); 24022944501Smrg 241e88f27b3Smrgstruct drm_intel_decode *drm_intel_decode_context_alloc(uint32_t devid); 242e88f27b3Smrgvoid drm_intel_decode_context_free(struct drm_intel_decode *ctx); 243e88f27b3Smrgvoid drm_intel_decode_set_batch_pointer(struct drm_intel_decode *ctx, 244e88f27b3Smrg void *data, uint32_t hw_offset, 245e88f27b3Smrg int count); 246e88f27b3Smrgvoid drm_intel_decode_set_dump_past_end(struct drm_intel_decode *ctx, 247e88f27b3Smrg int dump_past_end); 248e88f27b3Smrgvoid drm_intel_decode_set_head_tail(struct drm_intel_decode *ctx, 249e88f27b3Smrg uint32_t head, uint32_t tail); 250e88f27b3Smrgvoid drm_intel_decode_set_output_file(struct drm_intel_decode *ctx, FILE *out); 251e88f27b3Smrgvoid drm_intel_decode(struct drm_intel_decode *ctx); 252e88f27b3Smrg 253e88f27b3Smrgint drm_intel_reg_read(drm_intel_bufmgr *bufmgr, 254e88f27b3Smrg uint32_t offset, 255e88f27b3Smrg uint64_t *result); 256e88f27b3Smrg 257e88f27b3Smrgint drm_intel_get_reset_stats(drm_intel_context *ctx, 258e88f27b3Smrg uint32_t *reset_count, 259e88f27b3Smrg uint32_t *active, 260e88f27b3Smrg uint32_t *pending); 261e88f27b3Smrg 26222944501Smrg/** @{ Compatibility defines to keep old code building despite the symbol rename 26322944501Smrg * from dri_* to drm_intel_* 26422944501Smrg */ 26522944501Smrg#define dri_bo drm_intel_bo 26622944501Smrg#define dri_bufmgr drm_intel_bufmgr 26722944501Smrg#define dri_bo_alloc drm_intel_bo_alloc 26822944501Smrg#define dri_bo_reference drm_intel_bo_reference 26922944501Smrg#define dri_bo_unreference drm_intel_bo_unreference 27022944501Smrg#define dri_bo_map drm_intel_bo_map 27122944501Smrg#define dri_bo_unmap drm_intel_bo_unmap 27222944501Smrg#define dri_bo_subdata drm_intel_bo_subdata 27322944501Smrg#define dri_bo_get_subdata drm_intel_bo_get_subdata 27422944501Smrg#define dri_bo_wait_rendering drm_intel_bo_wait_rendering 27522944501Smrg#define dri_bufmgr_set_debug drm_intel_bufmgr_set_debug 27622944501Smrg#define dri_bufmgr_destroy drm_intel_bufmgr_destroy 27722944501Smrg#define dri_bo_exec drm_intel_bo_exec 27822944501Smrg#define dri_bufmgr_check_aperture_space drm_intel_bufmgr_check_aperture_space 27922944501Smrg#define dri_bo_emit_reloc(reloc_bo, read, write, target_offset, \ 28022944501Smrg reloc_offset, target_bo) \ 28122944501Smrg drm_intel_bo_emit_reloc(reloc_bo, reloc_offset, \ 28222944501Smrg target_bo, target_offset, \ 28322944501Smrg read, write); 28422944501Smrg#define dri_bo_pin drm_intel_bo_pin 28522944501Smrg#define dri_bo_unpin drm_intel_bo_unpin 28622944501Smrg#define dri_bo_get_tiling drm_intel_bo_get_tiling 28722944501Smrg#define dri_bo_set_tiling(bo, mode) drm_intel_bo_set_tiling(bo, mode, 0) 28822944501Smrg#define dri_bo_flink drm_intel_bo_flink 28922944501Smrg#define intel_bufmgr_gem_init drm_intel_bufmgr_gem_init 29022944501Smrg#define intel_bo_gem_create_from_name drm_intel_bo_gem_create_from_name 29122944501Smrg#define intel_bufmgr_gem_enable_reuse drm_intel_bufmgr_gem_enable_reuse 29222944501Smrg#define intel_bufmgr_fake_init drm_intel_bufmgr_fake_init 29322944501Smrg#define intel_bufmgr_fake_set_last_dispatch drm_intel_bufmgr_fake_set_last_dispatch 29422944501Smrg#define intel_bufmgr_fake_set_exec_callback drm_intel_bufmgr_fake_set_exec_callback 29522944501Smrg#define intel_bufmgr_fake_set_fence_callback drm_intel_bufmgr_fake_set_fence_callback 29622944501Smrg#define intel_bo_fake_alloc_static drm_intel_bo_fake_alloc_static 29722944501Smrg#define intel_bo_fake_disable_backing_store drm_intel_bo_fake_disable_backing_store 29822944501Smrg#define intel_bufmgr_fake_contended_lock_take drm_intel_bufmgr_fake_contended_lock_take 29922944501Smrg#define intel_bufmgr_fake_evict_all drm_intel_bufmgr_fake_evict_all 30022944501Smrg 30122944501Smrg/** @{ */ 30222944501Smrg 30322944501Smrg#endif /* INTEL_BUFMGR_H */ 304