intel_bufmgr_priv.h revision 22944501
122944501Smrg/* 222944501Smrg * Copyright © 2008 Intel Corporation 322944501Smrg * 422944501Smrg * Permission is hereby granted, free of charge, to any person obtaining a 522944501Smrg * copy of this software and associated documentation files (the "Software"), 622944501Smrg * to deal in the Software without restriction, including without limitation 722944501Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 822944501Smrg * and/or sell copies of the Software, and to permit persons to whom the 922944501Smrg * Software is furnished to do so, subject to the following conditions: 1022944501Smrg * 1122944501Smrg * The above copyright notice and this permission notice (including the next 1222944501Smrg * paragraph) shall be included in all copies or substantial portions of the 1322944501Smrg * Software. 1422944501Smrg * 1522944501Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1622944501Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1722944501Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1822944501Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 1922944501Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 2022944501Smrg * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 2122944501Smrg * IN THE SOFTWARE. 2222944501Smrg * 2322944501Smrg * Authors: 2422944501Smrg * Eric Anholt <eric@anholt.net> 2522944501Smrg * 2622944501Smrg */ 2722944501Smrg 2822944501Smrg/** 2922944501Smrg * @file intel_bufmgr_priv.h 3022944501Smrg * 3122944501Smrg * Private definitions of Intel-specific bufmgr functions and structures. 3222944501Smrg */ 3322944501Smrg 3422944501Smrg#ifndef INTEL_BUFMGR_PRIV_H 3522944501Smrg#define INTEL_BUFMGR_PRIV_H 3622944501Smrg 3722944501Smrg/** 3822944501Smrg * Context for a buffer manager instance. 3922944501Smrg * 4022944501Smrg * Contains public methods followed by private storage for the buffer manager. 4122944501Smrg */ 4222944501Smrgstruct _drm_intel_bufmgr { 4322944501Smrg /** 4422944501Smrg * Allocate a buffer object. 4522944501Smrg * 4622944501Smrg * Buffer objects are not necessarily initially mapped into CPU virtual 4722944501Smrg * address space or graphics device aperture. They must be mapped 4822944501Smrg * using bo_map() or drm_intel_gem_bo_map_gtt() to be used by the CPU. 4922944501Smrg */ 5022944501Smrg drm_intel_bo *(*bo_alloc) (drm_intel_bufmgr *bufmgr, const char *name, 5122944501Smrg unsigned long size, unsigned int alignment); 5222944501Smrg 5322944501Smrg /** 5422944501Smrg * Allocate a buffer object, hinting that it will be used as a 5522944501Smrg * render target. 5622944501Smrg * 5722944501Smrg * This is otherwise the same as bo_alloc. 5822944501Smrg */ 5922944501Smrg drm_intel_bo *(*bo_alloc_for_render) (drm_intel_bufmgr *bufmgr, 6022944501Smrg const char *name, 6122944501Smrg unsigned long size, 6222944501Smrg unsigned int alignment); 6322944501Smrg 6422944501Smrg /** 6522944501Smrg * Allocate a tiled buffer object. 6622944501Smrg * 6722944501Smrg * Alignment for tiled objects is set automatically; the 'flags' 6822944501Smrg * argument provides a hint about how the object will be used initially. 6922944501Smrg * 7022944501Smrg * Valid tiling formats are: 7122944501Smrg * I915_TILING_NONE 7222944501Smrg * I915_TILING_X 7322944501Smrg * I915_TILING_Y 7422944501Smrg * 7522944501Smrg * Note the tiling format may be rejected; callers should check the 7622944501Smrg * 'tiling_mode' field on return, as well as the pitch value, which 7722944501Smrg * may have been rounded up to accommodate for tiling restrictions. 7822944501Smrg */ 7922944501Smrg drm_intel_bo *(*bo_alloc_tiled) (drm_intel_bufmgr *bufmgr, 8022944501Smrg const char *name, 8122944501Smrg int x, int y, int cpp, 8222944501Smrg uint32_t *tiling_mode, 8322944501Smrg unsigned long *pitch, 8422944501Smrg unsigned long flags); 8522944501Smrg 8622944501Smrg /** Takes a reference on a buffer object */ 8722944501Smrg void (*bo_reference) (drm_intel_bo *bo); 8822944501Smrg 8922944501Smrg /** 9022944501Smrg * Releases a reference on a buffer object, freeing the data if 9122944501Smrg * no references remain. 9222944501Smrg */ 9322944501Smrg void (*bo_unreference) (drm_intel_bo *bo); 9422944501Smrg 9522944501Smrg /** 9622944501Smrg * Maps the buffer into userspace. 9722944501Smrg * 9822944501Smrg * This function will block waiting for any existing execution on the 9922944501Smrg * buffer to complete, first. The resulting mapping is available at 10022944501Smrg * buf->virtual. 10122944501Smrg */ 10222944501Smrg int (*bo_map) (drm_intel_bo *bo, int write_enable); 10322944501Smrg 10422944501Smrg /** 10522944501Smrg * Reduces the refcount on the userspace mapping of the buffer 10622944501Smrg * object. 10722944501Smrg */ 10822944501Smrg int (*bo_unmap) (drm_intel_bo *bo); 10922944501Smrg 11022944501Smrg /** 11122944501Smrg * Write data into an object. 11222944501Smrg * 11322944501Smrg * This is an optional function, if missing, 11422944501Smrg * drm_intel_bo will map/memcpy/unmap. 11522944501Smrg */ 11622944501Smrg int (*bo_subdata) (drm_intel_bo *bo, unsigned long offset, 11722944501Smrg unsigned long size, const void *data); 11822944501Smrg 11922944501Smrg /** 12022944501Smrg * Read data from an object 12122944501Smrg * 12222944501Smrg * This is an optional function, if missing, 12322944501Smrg * drm_intel_bo will map/memcpy/unmap. 12422944501Smrg */ 12522944501Smrg int (*bo_get_subdata) (drm_intel_bo *bo, unsigned long offset, 12622944501Smrg unsigned long size, void *data); 12722944501Smrg 12822944501Smrg /** 12922944501Smrg * Waits for rendering to an object by the GPU to have completed. 13022944501Smrg * 13122944501Smrg * This is not required for any access to the BO by bo_map, 13222944501Smrg * bo_subdata, etc. It is merely a way for the driver to implement 13322944501Smrg * glFinish. 13422944501Smrg */ 13522944501Smrg void (*bo_wait_rendering) (drm_intel_bo *bo); 13622944501Smrg 13722944501Smrg /** 13822944501Smrg * Tears down the buffer manager instance. 13922944501Smrg */ 14022944501Smrg void (*destroy) (drm_intel_bufmgr *bufmgr); 14122944501Smrg 14222944501Smrg /** 14322944501Smrg * Add relocation entry in reloc_buf, which will be updated with the 14422944501Smrg * target buffer's real offset on on command submission. 14522944501Smrg * 14622944501Smrg * Relocations remain in place for the lifetime of the buffer object. 14722944501Smrg * 14822944501Smrg * \param bo Buffer to write the relocation into. 14922944501Smrg * \param offset Byte offset within reloc_bo of the pointer to 15022944501Smrg * target_bo. 15122944501Smrg * \param target_bo Buffer whose offset should be written into the 15222944501Smrg * relocation entry. 15322944501Smrg * \param target_offset Constant value to be added to target_bo's 15422944501Smrg * offset in relocation entry. 15522944501Smrg * \param read_domains GEM read domains which the buffer will be 15622944501Smrg * read into by the command that this relocation 15722944501Smrg * is part of. 15822944501Smrg * \param write_domains GEM read domains which the buffer will be 15922944501Smrg * dirtied in by the command that this 16022944501Smrg * relocation is part of. 16122944501Smrg */ 16222944501Smrg int (*bo_emit_reloc) (drm_intel_bo *bo, uint32_t offset, 16322944501Smrg drm_intel_bo *target_bo, uint32_t target_offset, 16422944501Smrg uint32_t read_domains, uint32_t write_domain); 16522944501Smrg int (*bo_emit_reloc_fence)(drm_intel_bo *bo, uint32_t offset, 16622944501Smrg drm_intel_bo *target_bo, 16722944501Smrg uint32_t target_offset, 16822944501Smrg uint32_t read_domains, 16922944501Smrg uint32_t write_domain); 17022944501Smrg 17122944501Smrg /** Executes the command buffer pointed to by bo. */ 17222944501Smrg int (*bo_exec) (drm_intel_bo *bo, int used, 17322944501Smrg drm_clip_rect_t *cliprects, int num_cliprects, 17422944501Smrg int DR4); 17522944501Smrg 17622944501Smrg /** 17722944501Smrg * Pin a buffer to the aperture and fix the offset until unpinned 17822944501Smrg * 17922944501Smrg * \param buf Buffer to pin 18022944501Smrg * \param alignment Required alignment for aperture, in bytes 18122944501Smrg */ 18222944501Smrg int (*bo_pin) (drm_intel_bo *bo, uint32_t alignment); 18322944501Smrg 18422944501Smrg /** 18522944501Smrg * Unpin a buffer from the aperture, allowing it to be removed 18622944501Smrg * 18722944501Smrg * \param buf Buffer to unpin 18822944501Smrg */ 18922944501Smrg int (*bo_unpin) (drm_intel_bo *bo); 19022944501Smrg 19122944501Smrg /** 19222944501Smrg * Ask that the buffer be placed in tiling mode 19322944501Smrg * 19422944501Smrg * \param buf Buffer to set tiling mode for 19522944501Smrg * \param tiling_mode desired, and returned tiling mode 19622944501Smrg */ 19722944501Smrg int (*bo_set_tiling) (drm_intel_bo *bo, uint32_t * tiling_mode, 19822944501Smrg uint32_t stride); 19922944501Smrg 20022944501Smrg /** 20122944501Smrg * Get the current tiling (and resulting swizzling) mode for the bo. 20222944501Smrg * 20322944501Smrg * \param buf Buffer to get tiling mode for 20422944501Smrg * \param tiling_mode returned tiling mode 20522944501Smrg * \param swizzle_mode returned swizzling mode 20622944501Smrg */ 20722944501Smrg int (*bo_get_tiling) (drm_intel_bo *bo, uint32_t * tiling_mode, 20822944501Smrg uint32_t * swizzle_mode); 20922944501Smrg 21022944501Smrg /** 21122944501Smrg * Create a visible name for a buffer which can be used by other apps 21222944501Smrg * 21322944501Smrg * \param buf Buffer to create a name for 21422944501Smrg * \param name Returned name 21522944501Smrg */ 21622944501Smrg int (*bo_flink) (drm_intel_bo *bo, uint32_t * name); 21722944501Smrg 21822944501Smrg /** 21922944501Smrg * Returns 1 if mapping the buffer for write could cause the process 22022944501Smrg * to block, due to the object being active in the GPU. 22122944501Smrg */ 22222944501Smrg int (*bo_busy) (drm_intel_bo *bo); 22322944501Smrg 22422944501Smrg /** 22522944501Smrg * Specify the volatility of the buffer. 22622944501Smrg * \param bo Buffer to create a name for 22722944501Smrg * \param madv The purgeable status 22822944501Smrg * 22922944501Smrg * Use I915_MADV_DONTNEED to mark the buffer as purgeable, and it will be 23022944501Smrg * reclaimed under memory pressure. If you subsequently require the buffer, 23122944501Smrg * then you must pass I915_MADV_WILLNEED to mark the buffer as required. 23222944501Smrg * 23322944501Smrg * Returns 1 if the buffer was retained, or 0 if it was discarded whilst 23422944501Smrg * marked as I915_MADV_DONTNEED. 23522944501Smrg */ 23622944501Smrg int (*bo_madvise) (drm_intel_bo *bo, int madv); 23722944501Smrg 23822944501Smrg int (*check_aperture_space) (drm_intel_bo ** bo_array, int count); 23922944501Smrg 24022944501Smrg /** 24122944501Smrg * Disable buffer reuse for buffers which will be shared in some way, 24222944501Smrg * as with scanout buffers. When the buffer reference count goes to 24322944501Smrg * zero, it will be freed and not placed in the reuse list. 24422944501Smrg * 24522944501Smrg * \param bo Buffer to disable reuse for 24622944501Smrg */ 24722944501Smrg int (*bo_disable_reuse) (drm_intel_bo *bo); 24822944501Smrg 24922944501Smrg /** 25022944501Smrg * 25122944501Smrg * Return the pipe associated with a crtc_id so that vblank 25222944501Smrg * synchronization can use the correct data in the request. 25322944501Smrg * This is only supported for KMS and gem at this point, when 25422944501Smrg * unsupported, this function returns -1 and leaves the decision 25522944501Smrg * of what to do in that case to the caller 25622944501Smrg * 25722944501Smrg * \param bufmgr the associated buffer manager 25822944501Smrg * \param crtc_id the crtc identifier 25922944501Smrg */ 26022944501Smrg int (*get_pipe_from_crtc_id) (drm_intel_bufmgr *bufmgr, int crtc_id); 26122944501Smrg 26222944501Smrg /** Returns true if target_bo is in the relocation tree rooted at bo. */ 26322944501Smrg int (*bo_references) (drm_intel_bo *bo, drm_intel_bo *target_bo); 26422944501Smrg 26522944501Smrg /**< Enables verbose debugging printouts */ 26622944501Smrg int debug; 26722944501Smrg}; 26822944501Smrg 26922944501Smrg#define ALIGN(value, alignment) ((value + alignment - 1) & ~(alignment - 1)) 27022944501Smrg#define ROUND_UP_TO(x, y) (((x) + (y) - 1) / (y) * (y)) 27122944501Smrg#define ROUND_UP_TO_MB(x) ROUND_UP_TO((x), 1024*1024) 27222944501Smrg 27322944501Smrg#endif /* INTEL_BUFMGR_PRIV_H */ 274