class.h revision 3f012e29
13f012e29Smrg#ifndef __NVIF_CLASS_H__ 23f012e29Smrg#define __NVIF_CLASS_H__ 33f012e29Smrg 43f012e29Smrg/* these class numbers are made up by us, and not nvidia-assigned */ 53f012e29Smrg#define NVIF_CLASS_CONTROL /* if0001.h */ -1 63f012e29Smrg#define NVIF_CLASS_PERFMON /* if0002.h */ -2 73f012e29Smrg#define NVIF_CLASS_PERFDOM /* if0003.h */ -3 83f012e29Smrg#define NVIF_CLASS_SW_NV04 /* if0004.h */ -4 93f012e29Smrg#define NVIF_CLASS_SW_NV10 /* if0005.h */ -5 103f012e29Smrg#define NVIF_CLASS_SW_NV50 /* if0005.h */ -6 113f012e29Smrg#define NVIF_CLASS_SW_GF100 /* if0005.h */ -7 123f012e29Smrg 133f012e29Smrg/* the below match nvidia-assigned (either in hw, or sw) class numbers */ 143f012e29Smrg#define NV_DEVICE /* cl0080.h */ 0x00000080 153f012e29Smrg 163f012e29Smrg#define NV_DMA_FROM_MEMORY /* cl0002.h */ 0x00000002 173f012e29Smrg#define NV_DMA_TO_MEMORY /* cl0002.h */ 0x00000003 183f012e29Smrg#define NV_DMA_IN_MEMORY /* cl0002.h */ 0x0000003d 193f012e29Smrg 203f012e29Smrg#define FERMI_TWOD_A 0x0000902d 213f012e29Smrg 223f012e29Smrg#define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x00009039 233f012e29Smrg 243f012e29Smrg#define KEPLER_INLINE_TO_MEMORY_A 0x0000a040 253f012e29Smrg#define KEPLER_INLINE_TO_MEMORY_B 0x0000a140 263f012e29Smrg 273f012e29Smrg#define NV04_DISP /* cl0046.h */ 0x00000046 283f012e29Smrg 293f012e29Smrg#define NV03_CHANNEL_DMA /* cl506b.h */ 0x0000006b 303f012e29Smrg#define NV10_CHANNEL_DMA /* cl506b.h */ 0x0000006e 313f012e29Smrg#define NV17_CHANNEL_DMA /* cl506b.h */ 0x0000176e 323f012e29Smrg#define NV40_CHANNEL_DMA /* cl506b.h */ 0x0000406e 333f012e29Smrg#define NV50_CHANNEL_DMA /* cl506e.h */ 0x0000506e 343f012e29Smrg#define G82_CHANNEL_DMA /* cl826e.h */ 0x0000826e 353f012e29Smrg 363f012e29Smrg#define NV50_CHANNEL_GPFIFO /* cl506f.h */ 0x0000506f 373f012e29Smrg#define G82_CHANNEL_GPFIFO /* cl826f.h */ 0x0000826f 383f012e29Smrg#define FERMI_CHANNEL_GPFIFO /* cl906f.h */ 0x0000906f 393f012e29Smrg#define KEPLER_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000a06f 403f012e29Smrg#define MAXWELL_CHANNEL_GPFIFO_A /* cla06f.h */ 0x0000b06f 413f012e29Smrg 423f012e29Smrg#define NV50_DISP /* cl5070.h */ 0x00005070 433f012e29Smrg#define G82_DISP /* cl5070.h */ 0x00008270 443f012e29Smrg#define GT200_DISP /* cl5070.h */ 0x00008370 453f012e29Smrg#define GT214_DISP /* cl5070.h */ 0x00008570 463f012e29Smrg#define GT206_DISP /* cl5070.h */ 0x00008870 473f012e29Smrg#define GF110_DISP /* cl5070.h */ 0x00009070 483f012e29Smrg#define GK104_DISP /* cl5070.h */ 0x00009170 493f012e29Smrg#define GK110_DISP /* cl5070.h */ 0x00009270 503f012e29Smrg#define GM107_DISP /* cl5070.h */ 0x00009470 513f012e29Smrg#define GM204_DISP /* cl5070.h */ 0x00009570 523f012e29Smrg 533f012e29Smrg#define NV31_MPEG 0x00003174 543f012e29Smrg#define G82_MPEG 0x00008274 553f012e29Smrg 563f012e29Smrg#define NV74_VP2 0x00007476 573f012e29Smrg 583f012e29Smrg#define NV50_DISP_CURSOR /* cl507a.h */ 0x0000507a 593f012e29Smrg#define G82_DISP_CURSOR /* cl507a.h */ 0x0000827a 603f012e29Smrg#define GT214_DISP_CURSOR /* cl507a.h */ 0x0000857a 613f012e29Smrg#define GF110_DISP_CURSOR /* cl507a.h */ 0x0000907a 623f012e29Smrg#define GK104_DISP_CURSOR /* cl507a.h */ 0x0000917a 633f012e29Smrg 643f012e29Smrg#define NV50_DISP_OVERLAY /* cl507b.h */ 0x0000507b 653f012e29Smrg#define G82_DISP_OVERLAY /* cl507b.h */ 0x0000827b 663f012e29Smrg#define GT214_DISP_OVERLAY /* cl507b.h */ 0x0000857b 673f012e29Smrg#define GF110_DISP_OVERLAY /* cl507b.h */ 0x0000907b 683f012e29Smrg#define GK104_DISP_OVERLAY /* cl507b.h */ 0x0000917b 693f012e29Smrg 703f012e29Smrg#define NV50_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000507c 713f012e29Smrg#define G82_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000827c 723f012e29Smrg#define GT200_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000837c 733f012e29Smrg#define GT214_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000857c 743f012e29Smrg#define GF110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000907c 753f012e29Smrg#define GK104_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000917c 763f012e29Smrg#define GK110_DISP_BASE_CHANNEL_DMA /* cl507c.h */ 0x0000927c 773f012e29Smrg 783f012e29Smrg#define NV50_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000507d 793f012e29Smrg#define G82_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000827d 803f012e29Smrg#define GT200_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000837d 813f012e29Smrg#define GT214_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000857d 823f012e29Smrg#define GT206_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000887d 833f012e29Smrg#define GF110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000907d 843f012e29Smrg#define GK104_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000917d 853f012e29Smrg#define GK110_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000927d 863f012e29Smrg#define GM107_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000947d 873f012e29Smrg#define GM204_DISP_CORE_CHANNEL_DMA /* cl507d.h */ 0x0000957d 883f012e29Smrg 893f012e29Smrg#define NV50_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000507e 903f012e29Smrg#define G82_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000827e 913f012e29Smrg#define GT200_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000837e 923f012e29Smrg#define GT214_DISP_OVERLAY_CHANNEL_DMA /* cl507e.h */ 0x0000857e 933f012e29Smrg#define GF110_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000907e 943f012e29Smrg#define GK104_DISP_OVERLAY_CONTROL_DMA /* cl507e.h */ 0x0000917e 953f012e29Smrg 963f012e29Smrg#define FERMI_A /* cl9097.h */ 0x00009097 973f012e29Smrg#define FERMI_B /* cl9097.h */ 0x00009197 983f012e29Smrg#define FERMI_C /* cl9097.h */ 0x00009297 993f012e29Smrg 1003f012e29Smrg#define KEPLER_A /* cl9097.h */ 0x0000a097 1013f012e29Smrg#define KEPLER_B /* cl9097.h */ 0x0000a197 1023f012e29Smrg#define KEPLER_C /* cl9097.h */ 0x0000a297 1033f012e29Smrg 1043f012e29Smrg#define MAXWELL_A /* cl9097.h */ 0x0000b097 1053f012e29Smrg#define MAXWELL_B /* cl9097.h */ 0x0000b197 1063f012e29Smrg 1073f012e29Smrg#define NV74_BSP 0x000074b0 1083f012e29Smrg 1093f012e29Smrg#define GT212_MSVLD 0x000085b1 1103f012e29Smrg#define IGT21A_MSVLD 0x000086b1 1113f012e29Smrg#define G98_MSVLD 0x000088b1 1123f012e29Smrg#define GF100_MSVLD 0x000090b1 1133f012e29Smrg#define GK104_MSVLD 0x000095b1 1143f012e29Smrg 1153f012e29Smrg#define GT212_MSPDEC 0x000085b2 1163f012e29Smrg#define G98_MSPDEC 0x000088b2 1173f012e29Smrg#define GF100_MSPDEC 0x000090b2 1183f012e29Smrg#define GK104_MSPDEC 0x000095b2 1193f012e29Smrg 1203f012e29Smrg#define GT212_MSPPP 0x000085b3 1213f012e29Smrg#define G98_MSPPP 0x000088b3 1223f012e29Smrg#define GF100_MSPPP 0x000090b3 1233f012e29Smrg 1243f012e29Smrg#define G98_SEC 0x000088b4 1253f012e29Smrg 1263f012e29Smrg#define GT212_DMA 0x000085b5 1273f012e29Smrg#define FERMI_DMA 0x000090b5 1283f012e29Smrg#define KEPLER_DMA_COPY_A 0x0000a0b5 1293f012e29Smrg#define MAXWELL_DMA_COPY_A 0x0000b0b5 1303f012e29Smrg 1313f012e29Smrg#define FERMI_DECOMPRESS 0x000090b8 1323f012e29Smrg 1333f012e29Smrg#define FERMI_COMPUTE_A 0x000090c0 1343f012e29Smrg#define FERMI_COMPUTE_B 0x000091c0 1353f012e29Smrg#define KEPLER_COMPUTE_A 0x0000a0c0 1363f012e29Smrg#define KEPLER_COMPUTE_B 0x0000a1c0 1373f012e29Smrg#define MAXWELL_COMPUTE_A 0x0000b0c0 1383f012e29Smrg#define MAXWELL_COMPUTE_B 0x0000b1c0 1393f012e29Smrg 1403f012e29Smrg#define NV74_CIPHER 0x000074c1 1413f012e29Smrg#endif 142