amdgpu_test.h revision 00a23bda
13f012e29Smrg/*
23f012e29Smrg * Copyright 2014 Advanced Micro Devices, Inc.
33f012e29Smrg *
43f012e29Smrg * Permission is hereby granted, free of charge, to any person obtaining a
53f012e29Smrg * copy of this software and associated documentation files (the "Software"),
63f012e29Smrg * to deal in the Software without restriction, including without limitation
73f012e29Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
83f012e29Smrg * and/or sell copies of the Software, and to permit persons to whom the
93f012e29Smrg * Software is furnished to do so, subject to the following conditions:
103f012e29Smrg *
113f012e29Smrg * The above copyright notice and this permission notice shall be included in
123f012e29Smrg * all copies or substantial portions of the Software.
133f012e29Smrg *
143f012e29Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
153f012e29Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
163f012e29Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
173f012e29Smrg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
183f012e29Smrg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
193f012e29Smrg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
203f012e29Smrg * OTHER DEALINGS IN THE SOFTWARE.
213f012e29Smrg *
223f012e29Smrg*/
233f012e29Smrg
243f012e29Smrg#ifndef _AMDGPU_TEST_H_
253f012e29Smrg#define _AMDGPU_TEST_H_
263f012e29Smrg
273f012e29Smrg#include "amdgpu.h"
283f012e29Smrg#include "amdgpu_drm.h"
293f012e29Smrg
303f012e29Smrg/**
313f012e29Smrg * Define max. number of card in system which we are able to handle
323f012e29Smrg */
333f012e29Smrg#define MAX_CARDS_SUPPORTED     4
343f012e29Smrg
353f012e29Smrg/* Forward reference for array to keep "drm" handles */
363f012e29Smrgextern int drm_amdgpu[MAX_CARDS_SUPPORTED];
373f012e29Smrg
38037b3c26Smrg/* Global variables */
39037b3c26Smrgextern int open_render_node;
40037b3c26Smrg
413f012e29Smrg/*************************  Basic test suite ********************************/
423f012e29Smrg
433f012e29Smrg/*
443f012e29Smrg * Define basic test suite to serve as the starting point for future testing
453f012e29Smrg*/
463f012e29Smrg
473f012e29Smrg/**
483f012e29Smrg * Initialize basic test suite
493f012e29Smrg */
503f012e29Smrgint suite_basic_tests_init();
513f012e29Smrg
523f012e29Smrg/**
533f012e29Smrg * Deinitialize basic test suite
543f012e29Smrg */
553f012e29Smrgint suite_basic_tests_clean();
563f012e29Smrg
573f012e29Smrg/**
583f012e29Smrg * Tests in basic test suite
593f012e29Smrg */
603f012e29Smrgextern CU_TestInfo basic_tests[];
613f012e29Smrg
623f012e29Smrg/**
633f012e29Smrg * Initialize bo test suite
643f012e29Smrg */
653f012e29Smrgint suite_bo_tests_init();
663f012e29Smrg
673f012e29Smrg/**
683f012e29Smrg * Deinitialize bo test suite
693f012e29Smrg */
703f012e29Smrgint suite_bo_tests_clean();
713f012e29Smrg
723f012e29Smrg/**
733f012e29Smrg * Tests in bo test suite
743f012e29Smrg */
753f012e29Smrgextern CU_TestInfo bo_tests[];
763f012e29Smrg
773f012e29Smrg/**
783f012e29Smrg * Initialize cs test suite
793f012e29Smrg */
803f012e29Smrgint suite_cs_tests_init();
813f012e29Smrg
823f012e29Smrg/**
833f012e29Smrg * Deinitialize cs test suite
843f012e29Smrg */
853f012e29Smrgint suite_cs_tests_clean();
863f012e29Smrg
8700a23bdaSmrg/**
8800a23bdaSmrg * Decide if the suite is enabled by default or not.
8900a23bdaSmrg */
9000a23bdaSmrgCU_BOOL suite_cs_tests_enable(void);
9100a23bdaSmrg
923f012e29Smrg/**
933f012e29Smrg * Tests in cs test suite
943f012e29Smrg */
953f012e29Smrgextern CU_TestInfo cs_tests[];
963f012e29Smrg
973f012e29Smrg/**
983f012e29Smrg * Initialize vce test suite
993f012e29Smrg */
1003f012e29Smrgint suite_vce_tests_init();
1013f012e29Smrg
1023f012e29Smrg/**
1033f012e29Smrg * Deinitialize vce test suite
1043f012e29Smrg */
1053f012e29Smrgint suite_vce_tests_clean();
1063f012e29Smrg
10700a23bdaSmrg/**
10800a23bdaSmrg * Decide if the suite is enabled by default or not.
10900a23bdaSmrg */
11000a23bdaSmrgCU_BOOL suite_vce_tests_enable(void);
11100a23bdaSmrg
1123f012e29Smrg/**
1133f012e29Smrg * Tests in vce test suite
1143f012e29Smrg */
1153f012e29Smrgextern CU_TestInfo vce_tests[];
1163f012e29Smrg
117d8807b2fSmrg/**
118d8807b2fSmrg+ * Initialize vcn test suite
119d8807b2fSmrg+ */
120d8807b2fSmrgint suite_vcn_tests_init();
121d8807b2fSmrg
122d8807b2fSmrg/**
123d8807b2fSmrg+ * Deinitialize vcn test suite
124d8807b2fSmrg+ */
125d8807b2fSmrgint suite_vcn_tests_clean();
126d8807b2fSmrg
12700a23bdaSmrg/**
12800a23bdaSmrg * Decide if the suite is enabled by default or not.
12900a23bdaSmrg */
13000a23bdaSmrgCU_BOOL suite_vcn_tests_enable(void);
13100a23bdaSmrg
132d8807b2fSmrg/**
133d8807b2fSmrg+ * Tests in vcn test suite
134d8807b2fSmrg+ */
135d8807b2fSmrgextern CU_TestInfo vcn_tests[];
136d8807b2fSmrg
137d8807b2fSmrg/**
138d8807b2fSmrg * Initialize uvd enc test suite
139d8807b2fSmrg */
140d8807b2fSmrgint suite_uvd_enc_tests_init();
141d8807b2fSmrg
142d8807b2fSmrg/**
143d8807b2fSmrg * Deinitialize uvd enc test suite
144d8807b2fSmrg */
145d8807b2fSmrgint suite_uvd_enc_tests_clean();
146d8807b2fSmrg
14700a23bdaSmrg/**
14800a23bdaSmrg * Decide if the suite is enabled by default or not.
14900a23bdaSmrg */
15000a23bdaSmrgCU_BOOL suite_uvd_enc_tests_enable(void);
15100a23bdaSmrg
152d8807b2fSmrg/**
153d8807b2fSmrg * Tests in uvd enc test suite
154d8807b2fSmrg */
155d8807b2fSmrgextern CU_TestInfo uvd_enc_tests[];
156d8807b2fSmrg
15700a23bdaSmrg/**
15800a23bdaSmrg * Initialize deadlock test suite
15900a23bdaSmrg */
16000a23bdaSmrgint suite_deadlock_tests_init();
16100a23bdaSmrg
16200a23bdaSmrg/**
16300a23bdaSmrg * Deinitialize deadlock test suite
16400a23bdaSmrg */
16500a23bdaSmrgint suite_deadlock_tests_clean();
16600a23bdaSmrg
16700a23bdaSmrg/**
16800a23bdaSmrg * Decide if the suite is enabled by default or not.
16900a23bdaSmrg */
17000a23bdaSmrgCU_BOOL suite_deadlock_tests_enable(void);
17100a23bdaSmrg
17200a23bdaSmrg/**
17300a23bdaSmrg * Tests in uvd enc test suite
17400a23bdaSmrg */
17500a23bdaSmrgextern CU_TestInfo deadlock_tests[];
17600a23bdaSmrg
17700a23bdaSmrg/**
17800a23bdaSmrg * Initialize vm test suite
17900a23bdaSmrg */
18000a23bdaSmrgint suite_vm_tests_init();
18100a23bdaSmrg
18200a23bdaSmrg/**
18300a23bdaSmrg * Deinitialize deadlock test suite
18400a23bdaSmrg */
18500a23bdaSmrgint suite_vm_tests_clean();
18600a23bdaSmrg
18700a23bdaSmrg/**
18800a23bdaSmrg * Decide if the suite is enabled by default or not.
18900a23bdaSmrg */
19000a23bdaSmrgCU_BOOL suite_vm_tests_enable(void);
19100a23bdaSmrg
19200a23bdaSmrg/**
19300a23bdaSmrg * Tests in vm test suite
19400a23bdaSmrg */
19500a23bdaSmrgextern CU_TestInfo vm_tests[];
19600a23bdaSmrg
1973f012e29Smrg/**
1983f012e29Smrg * Helper functions
1993f012e29Smrg */
2003f012e29Smrgstatic inline amdgpu_bo_handle gpu_mem_alloc(
2013f012e29Smrg					amdgpu_device_handle device_handle,
2023f012e29Smrg					uint64_t size,
2033f012e29Smrg					uint64_t alignment,
2043f012e29Smrg					uint32_t type,
2053f012e29Smrg					uint64_t flags,
2063f012e29Smrg					uint64_t *vmc_addr,
2073f012e29Smrg					amdgpu_va_handle *va_handle)
2083f012e29Smrg{
2093f012e29Smrg	struct amdgpu_bo_alloc_request req = {0};
2103f012e29Smrg	amdgpu_bo_handle buf_handle;
2113f012e29Smrg	int r;
2123f012e29Smrg
2133f012e29Smrg	CU_ASSERT_NOT_EQUAL(vmc_addr, NULL);
2143f012e29Smrg
2153f012e29Smrg	req.alloc_size = size;
2163f012e29Smrg	req.phys_alignment = alignment;
2173f012e29Smrg	req.preferred_heap = type;
2183f012e29Smrg	req.flags = flags;
2193f012e29Smrg
2203f012e29Smrg	r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
2213f012e29Smrg	CU_ASSERT_EQUAL(r, 0);
2223f012e29Smrg
2233f012e29Smrg	r = amdgpu_va_range_alloc(device_handle,
2243f012e29Smrg				  amdgpu_gpu_va_range_general,
2253f012e29Smrg				  size, alignment, 0, vmc_addr,
2263f012e29Smrg				  va_handle, 0);
2273f012e29Smrg	CU_ASSERT_EQUAL(r, 0);
2283f012e29Smrg
2293f012e29Smrg	r = amdgpu_bo_va_op(buf_handle, 0, size, *vmc_addr, 0, AMDGPU_VA_OP_MAP);
2303f012e29Smrg	CU_ASSERT_EQUAL(r, 0);
2313f012e29Smrg
2323f012e29Smrg	return buf_handle;
2333f012e29Smrg}
2343f012e29Smrg
2353f012e29Smrgstatic inline int gpu_mem_free(amdgpu_bo_handle bo,
2363f012e29Smrg			       amdgpu_va_handle va_handle,
2373f012e29Smrg			       uint64_t vmc_addr,
2383f012e29Smrg			       uint64_t size)
2393f012e29Smrg{
2403f012e29Smrg	int r;
2413f012e29Smrg
2423f012e29Smrg	r = amdgpu_bo_va_op(bo, 0, size, vmc_addr, 0, AMDGPU_VA_OP_UNMAP);
2433f012e29Smrg	CU_ASSERT_EQUAL(r, 0);
2443f012e29Smrg
2453f012e29Smrg	r = amdgpu_va_range_free(va_handle);
2463f012e29Smrg	CU_ASSERT_EQUAL(r, 0);
2473f012e29Smrg
2483f012e29Smrg	r = amdgpu_bo_free(bo);
2493f012e29Smrg	CU_ASSERT_EQUAL(r, 0);
2503f012e29Smrg
2513f012e29Smrg	return 0;
2523f012e29Smrg}
2533f012e29Smrg
25400a23bdaSmrgstatic inline int
25500a23bdaSmrgamdgpu_bo_alloc_wrap(amdgpu_device_handle dev, unsigned size,
25600a23bdaSmrg		     unsigned alignment, unsigned heap, uint64_t flags,
25700a23bdaSmrg		     amdgpu_bo_handle *bo)
25800a23bdaSmrg{
25900a23bdaSmrg	struct amdgpu_bo_alloc_request request = {};
26000a23bdaSmrg	amdgpu_bo_handle buf_handle;
26100a23bdaSmrg	int r;
26200a23bdaSmrg
26300a23bdaSmrg	request.alloc_size = size;
26400a23bdaSmrg	request.phys_alignment = alignment;
26500a23bdaSmrg	request.preferred_heap = heap;
26600a23bdaSmrg	request.flags = flags;
26700a23bdaSmrg
26800a23bdaSmrg	r = amdgpu_bo_alloc(dev, &request, &buf_handle);
26900a23bdaSmrg	if (r)
27000a23bdaSmrg		return r;
27100a23bdaSmrg
27200a23bdaSmrg	*bo = buf_handle;
27300a23bdaSmrg
27400a23bdaSmrg	return 0;
27500a23bdaSmrg}
27600a23bdaSmrg
2773f012e29Smrgstatic inline int
2783f012e29Smrgamdgpu_bo_alloc_and_map(amdgpu_device_handle dev, unsigned size,
2793f012e29Smrg			unsigned alignment, unsigned heap, uint64_t flags,
2803f012e29Smrg			amdgpu_bo_handle *bo, void **cpu, uint64_t *mc_address,
2813f012e29Smrg			amdgpu_va_handle *va_handle)
2823f012e29Smrg{
2833f012e29Smrg	struct amdgpu_bo_alloc_request request = {};
2843f012e29Smrg	amdgpu_bo_handle buf_handle;
2853f012e29Smrg	amdgpu_va_handle handle;
2863f012e29Smrg	uint64_t vmc_addr;
2873f012e29Smrg	int r;
2883f012e29Smrg
2893f012e29Smrg	request.alloc_size = size;
2903f012e29Smrg	request.phys_alignment = alignment;
2913f012e29Smrg	request.preferred_heap = heap;
2923f012e29Smrg	request.flags = flags;
2933f012e29Smrg
2943f012e29Smrg	r = amdgpu_bo_alloc(dev, &request, &buf_handle);
2953f012e29Smrg	if (r)
2963f012e29Smrg		return r;
2973f012e29Smrg
2983f012e29Smrg	r = amdgpu_va_range_alloc(dev,
2993f012e29Smrg				  amdgpu_gpu_va_range_general,
3003f012e29Smrg				  size, alignment, 0, &vmc_addr,
3013f012e29Smrg				  &handle, 0);
3023f012e29Smrg	if (r)
3033f012e29Smrg		goto error_va_alloc;
3043f012e29Smrg
3053f012e29Smrg	r = amdgpu_bo_va_op(buf_handle, 0, size, vmc_addr, 0, AMDGPU_VA_OP_MAP);
3063f012e29Smrg	if (r)
3073f012e29Smrg		goto error_va_map;
3083f012e29Smrg
3093f012e29Smrg	r = amdgpu_bo_cpu_map(buf_handle, cpu);
3103f012e29Smrg	if (r)
3113f012e29Smrg		goto error_cpu_map;
3123f012e29Smrg
3133f012e29Smrg	*bo = buf_handle;
3143f012e29Smrg	*mc_address = vmc_addr;
3153f012e29Smrg	*va_handle = handle;
3163f012e29Smrg
3173f012e29Smrg	return 0;
3183f012e29Smrg
3193f012e29Smrgerror_cpu_map:
3203f012e29Smrg	amdgpu_bo_cpu_unmap(buf_handle);
3213f012e29Smrg
3223f012e29Smrgerror_va_map:
3233f012e29Smrg	amdgpu_bo_va_op(buf_handle, 0, size, vmc_addr, 0, AMDGPU_VA_OP_UNMAP);
3243f012e29Smrg
3253f012e29Smrgerror_va_alloc:
3263f012e29Smrg	amdgpu_bo_free(buf_handle);
3273f012e29Smrg	return r;
3283f012e29Smrg}
3293f012e29Smrg
3303f012e29Smrgstatic inline int
3313f012e29Smrgamdgpu_bo_unmap_and_free(amdgpu_bo_handle bo, amdgpu_va_handle va_handle,
3323f012e29Smrg			 uint64_t mc_addr, uint64_t size)
3333f012e29Smrg{
3343f012e29Smrg	amdgpu_bo_cpu_unmap(bo);
3353f012e29Smrg	amdgpu_bo_va_op(bo, 0, size, mc_addr, 0, AMDGPU_VA_OP_UNMAP);
3363f012e29Smrg	amdgpu_va_range_free(va_handle);
3373f012e29Smrg	amdgpu_bo_free(bo);
3383f012e29Smrg
3393f012e29Smrg	return 0;
3403f012e29Smrg
3413f012e29Smrg}
3423f012e29Smrg
3433f012e29Smrgstatic inline int
3443f012e29Smrgamdgpu_get_bo_list(amdgpu_device_handle dev, amdgpu_bo_handle bo1,
3453f012e29Smrg		   amdgpu_bo_handle bo2, amdgpu_bo_list_handle *list)
3463f012e29Smrg{
3473f012e29Smrg	amdgpu_bo_handle resources[] = {bo1, bo2};
3483f012e29Smrg
3493f012e29Smrg	return amdgpu_bo_list_create(dev, bo2 ? 2 : 1, resources, NULL, list);
3503f012e29Smrg}
3513f012e29Smrg
35200a23bdaSmrg
35300a23bdaSmrgstatic inline CU_ErrorCode amdgpu_set_suite_active(const char *suite_name,
35400a23bdaSmrg							  CU_BOOL active)
35500a23bdaSmrg{
35600a23bdaSmrg	CU_ErrorCode r = CU_set_suite_active(CU_get_suite(suite_name), active);
35700a23bdaSmrg
35800a23bdaSmrg	if (r != CUE_SUCCESS)
35900a23bdaSmrg		fprintf(stderr, "Failed to obtain suite %s\n", suite_name);
36000a23bdaSmrg
36100a23bdaSmrg	return r;
36200a23bdaSmrg}
36300a23bdaSmrg
36400a23bdaSmrgstatic inline CU_ErrorCode amdgpu_set_test_active(const char *suite_name,
36500a23bdaSmrg				  const char *test_name, CU_BOOL active)
36600a23bdaSmrg{
36700a23bdaSmrg	CU_ErrorCode r;
36800a23bdaSmrg	CU_pSuite pSuite = CU_get_suite(suite_name);
36900a23bdaSmrg
37000a23bdaSmrg	if (!pSuite) {
37100a23bdaSmrg		fprintf(stderr, "Failed to obtain suite %s\n",
37200a23bdaSmrg				suite_name);
37300a23bdaSmrg		return CUE_NOSUITE;
37400a23bdaSmrg	}
37500a23bdaSmrg
37600a23bdaSmrg	r = CU_set_test_active(CU_get_test(pSuite, test_name), active);
37700a23bdaSmrg	if (r != CUE_SUCCESS)
37800a23bdaSmrg		fprintf(stderr, "Failed to obtain test %s\n", test_name);
37900a23bdaSmrg
38000a23bdaSmrg	return r;
38100a23bdaSmrg}
38200a23bdaSmrg
3833f012e29Smrg#endif  /* #ifdef _AMDGPU_TEST_H_ */
384