deadlock_tests.c revision 5324fb0d
1/* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22*/ 23 24#include <stdio.h> 25#include <stdlib.h> 26#include <unistd.h> 27#ifdef HAVE_ALLOCA_H 28# include <alloca.h> 29#endif 30 31#include "CUnit/Basic.h" 32 33#include "amdgpu_test.h" 34#include "amdgpu_drm.h" 35#include "amdgpu_internal.h" 36 37#include <pthread.h> 38 39 40/* 41 * This defines the delay in MS after which memory location designated for 42 * compression against reference value is written to, unblocking command 43 * processor 44 */ 45#define WRITE_MEM_ADDRESS_DELAY_MS 100 46 47#define PACKET_TYPE3 3 48 49#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 50 (((op) & 0xFF) << 8) | \ 51 ((n) & 0x3FFF) << 16) 52 53#define PACKET3_WAIT_REG_MEM 0x3C 54#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 55 /* 0 - always 56 * 1 - < 57 * 2 - <= 58 * 3 - == 59 * 4 - != 60 * 5 - >= 61 * 6 - > 62 */ 63#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 64 /* 0 - reg 65 * 1 - mem 66 */ 67#define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 68 /* 0 - wait_reg_mem 69 * 1 - wr_wait_wr_reg 70 */ 71#define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 72 /* 0 - me 73 * 1 - pfp 74 */ 75 76#define PACKET3_WRITE_DATA 0x37 77#define WRITE_DATA_DST_SEL(x) ((x) << 8) 78 /* 0 - register 79 * 1 - memory (sync - via GRBM) 80 * 2 - gl2 81 * 3 - gds 82 * 4 - reserved 83 * 5 - memory (async - direct) 84 */ 85#define WR_ONE_ADDR (1 << 16) 86#define WR_CONFIRM (1 << 20) 87#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 88 /* 0 - LRU 89 * 1 - Stream 90 */ 91#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 92 /* 0 - me 93 * 1 - pfp 94 * 2 - ce 95 */ 96 97#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54f 98 99#define SDMA_PKT_HEADER_OP(x) (x & 0xff) 100#define SDMA_OP_POLL_REGMEM 8 101 102static amdgpu_device_handle device_handle; 103static uint32_t major_version; 104static uint32_t minor_version; 105 106static pthread_t stress_thread; 107static uint32_t *ptr; 108 109int use_uc_mtype = 0; 110 111static void amdgpu_deadlock_helper(unsigned ip_type); 112static void amdgpu_deadlock_gfx(void); 113static void amdgpu_deadlock_compute(void); 114static void amdgpu_illegal_reg_access(); 115static void amdgpu_illegal_mem_access(); 116static void amdgpu_deadlock_sdma(void); 117 118CU_BOOL suite_deadlock_tests_enable(void) 119{ 120 CU_BOOL enable = CU_TRUE; 121 122 if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, 123 &minor_version, &device_handle)) 124 return CU_FALSE; 125 126 /* 127 * Only enable for ASICs supporting GPU reset and for which it's enabled 128 * by default (currently GFX8/9 dGPUS) 129 */ 130 if (device_handle->info.family_id != AMDGPU_FAMILY_VI && 131 device_handle->info.family_id != AMDGPU_FAMILY_AI && 132 device_handle->info.family_id != AMDGPU_FAMILY_CI) { 133 printf("\n\nGPU reset is not enabled for the ASIC, deadlock suite disabled\n"); 134 enable = CU_FALSE; 135 } 136 137 if (device_handle->info.family_id >= AMDGPU_FAMILY_AI) 138 use_uc_mtype = 1; 139 140 if (amdgpu_device_deinitialize(device_handle)) 141 return CU_FALSE; 142 143 return enable; 144} 145 146int suite_deadlock_tests_init(void) 147{ 148 int r; 149 150 r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, 151 &minor_version, &device_handle); 152 153 if (r) { 154 if ((r == -EACCES) && (errno == EACCES)) 155 printf("\n\nError:%s. " 156 "Hint:Try to run this test program as root.", 157 strerror(errno)); 158 return CUE_SINIT_FAILED; 159 } 160 161 return CUE_SUCCESS; 162} 163 164int suite_deadlock_tests_clean(void) 165{ 166 int r = amdgpu_device_deinitialize(device_handle); 167 168 if (r == 0) 169 return CUE_SUCCESS; 170 else 171 return CUE_SCLEAN_FAILED; 172} 173 174 175CU_TestInfo deadlock_tests[] = { 176 { "gfx ring block test (set amdgpu.lockup_timeout=50)", amdgpu_deadlock_gfx }, 177 { "compute ring block test (set amdgpu.lockup_timeout=50)", amdgpu_deadlock_compute }, 178 { "sdma ring block test (set amdgpu.lockup_timeout=50)", amdgpu_deadlock_sdma }, 179 { "illegal reg access test", amdgpu_illegal_reg_access }, 180 { "illegal mem access test (set amdgpu.vm_fault_stop=2)", amdgpu_illegal_mem_access }, 181 CU_TEST_INFO_NULL, 182}; 183 184static void *write_mem_address(void *data) 185{ 186 int i; 187 188 /* useconds_t range is [0, 1,000,000] so use loop for waits > 1s */ 189 for (i = 0; i < WRITE_MEM_ADDRESS_DELAY_MS; i++) 190 usleep(1000); 191 192 ptr[256] = 0x1; 193 194 return 0; 195} 196 197static void amdgpu_deadlock_gfx(void) 198{ 199 amdgpu_deadlock_helper(AMDGPU_HW_IP_GFX); 200} 201 202static void amdgpu_deadlock_compute(void) 203{ 204 amdgpu_deadlock_helper(AMDGPU_HW_IP_COMPUTE); 205} 206 207static void amdgpu_deadlock_helper(unsigned ip_type) 208{ 209 amdgpu_context_handle context_handle; 210 amdgpu_bo_handle ib_result_handle; 211 void *ib_result_cpu; 212 uint64_t ib_result_mc_address; 213 struct amdgpu_cs_request ibs_request; 214 struct amdgpu_cs_ib_info ib_info; 215 struct amdgpu_cs_fence fence_status; 216 uint32_t expired; 217 int i, r; 218 amdgpu_bo_list_handle bo_list; 219 amdgpu_va_handle va_handle; 220 221 r = pthread_create(&stress_thread, NULL, write_mem_address, NULL); 222 CU_ASSERT_EQUAL(r, 0); 223 224 r = amdgpu_cs_ctx_create(device_handle, &context_handle); 225 CU_ASSERT_EQUAL(r, 0); 226 227 r = amdgpu_bo_alloc_and_map_raw(device_handle, 4096, 4096, 228 AMDGPU_GEM_DOMAIN_GTT, 0, use_uc_mtype ? AMDGPU_VM_MTYPE_UC : 0, 229 &ib_result_handle, &ib_result_cpu, 230 &ib_result_mc_address, &va_handle); 231 CU_ASSERT_EQUAL(r, 0); 232 233 r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, 234 &bo_list); 235 CU_ASSERT_EQUAL(r, 0); 236 237 ptr = ib_result_cpu; 238 239 ptr[0] = PACKET3(PACKET3_WAIT_REG_MEM, 5); 240 ptr[1] = (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 241 WAIT_REG_MEM_FUNCTION(4) | /* != */ 242 WAIT_REG_MEM_ENGINE(0)); /* me */ 243 ptr[2] = (ib_result_mc_address + 256*4) & 0xfffffffc; 244 ptr[3] = ((ib_result_mc_address + 256*4) >> 32) & 0xffffffff; 245 ptr[4] = 0x00000000; /* reference value */ 246 ptr[5] = 0xffffffff; /* and mask */ 247 ptr[6] = 0x00000004; /* poll interval */ 248 249 for (i = 7; i < 16; ++i) 250 ptr[i] = 0xffff1000; 251 252 253 ptr[256] = 0x0; /* the memory we wait on to change */ 254 255 256 257 memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); 258 ib_info.ib_mc_address = ib_result_mc_address; 259 ib_info.size = 16; 260 261 memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request)); 262 ibs_request.ip_type = ip_type; 263 ibs_request.ring = 0; 264 ibs_request.number_of_ibs = 1; 265 ibs_request.ibs = &ib_info; 266 ibs_request.resources = bo_list; 267 ibs_request.fence_info.handle = NULL; 268 for (i = 0; i < 200; i++) { 269 r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1); 270 CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1); 271 272 } 273 274 memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence)); 275 fence_status.context = context_handle; 276 fence_status.ip_type = ip_type; 277 fence_status.ip_instance = 0; 278 fence_status.ring = 0; 279 fence_status.fence = ibs_request.seq_no; 280 281 r = amdgpu_cs_query_fence_status(&fence_status, 282 AMDGPU_TIMEOUT_INFINITE,0, &expired); 283 CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1); 284 285 pthread_join(stress_thread, NULL); 286 287 r = amdgpu_bo_list_destroy(bo_list); 288 CU_ASSERT_EQUAL(r, 0); 289 290 r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, 291 ib_result_mc_address, 4096); 292 CU_ASSERT_EQUAL(r, 0); 293 294 r = amdgpu_cs_ctx_free(context_handle); 295 CU_ASSERT_EQUAL(r, 0); 296} 297 298static void amdgpu_deadlock_sdma(void) 299{ 300 amdgpu_context_handle context_handle; 301 amdgpu_bo_handle ib_result_handle; 302 void *ib_result_cpu; 303 uint64_t ib_result_mc_address; 304 struct amdgpu_cs_request ibs_request; 305 struct amdgpu_cs_ib_info ib_info; 306 struct amdgpu_cs_fence fence_status; 307 uint32_t expired; 308 int i, r; 309 amdgpu_bo_list_handle bo_list; 310 amdgpu_va_handle va_handle; 311 struct drm_amdgpu_info_hw_ip info; 312 uint32_t ring_id; 313 314 r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_DMA, 0, &info); 315 CU_ASSERT_EQUAL(r, 0); 316 317 r = amdgpu_cs_ctx_create(device_handle, &context_handle); 318 CU_ASSERT_EQUAL(r, 0); 319 320 for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) { 321 r = pthread_create(&stress_thread, NULL, write_mem_address, NULL); 322 CU_ASSERT_EQUAL(r, 0); 323 324 r = amdgpu_bo_alloc_and_map_raw(device_handle, 4096, 4096, 325 AMDGPU_GEM_DOMAIN_GTT, 0, use_uc_mtype ? AMDGPU_VM_MTYPE_UC : 0, 326 &ib_result_handle, &ib_result_cpu, 327 &ib_result_mc_address, &va_handle); 328 CU_ASSERT_EQUAL(r, 0); 329 330 r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, 331 &bo_list); 332 CU_ASSERT_EQUAL(r, 0); 333 334 ptr = ib_result_cpu; 335 i = 0; 336 337 ptr[i++] = SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | 338 (0 << 26) | /* WAIT_REG_MEM */ 339 (4 << 28) | /* != */ 340 (1 << 31); /* memory */ 341 ptr[i++] = (ib_result_mc_address + 256*4) & 0xfffffffc; 342 ptr[i++] = ((ib_result_mc_address + 256*4) >> 32) & 0xffffffff; 343 ptr[i++] = 0x00000000; /* reference value */ 344 ptr[i++] = 0xffffffff; /* and mask */ 345 ptr[i++] = 4 | /* poll interval */ 346 (0xfff << 16); /* retry count */ 347 348 for (; i < 16; i++) 349 ptr[i] = 0; 350 351 ptr[256] = 0x0; /* the memory we wait on to change */ 352 353 memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); 354 ib_info.ib_mc_address = ib_result_mc_address; 355 ib_info.size = 16; 356 357 memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request)); 358 ibs_request.ip_type = AMDGPU_HW_IP_DMA; 359 ibs_request.ring = ring_id; 360 ibs_request.number_of_ibs = 1; 361 ibs_request.ibs = &ib_info; 362 ibs_request.resources = bo_list; 363 ibs_request.fence_info.handle = NULL; 364 365 for (i = 0; i < 200; i++) { 366 r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1); 367 CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1); 368 369 } 370 371 memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence)); 372 fence_status.context = context_handle; 373 fence_status.ip_type = AMDGPU_HW_IP_DMA; 374 fence_status.ip_instance = 0; 375 fence_status.ring = ring_id; 376 fence_status.fence = ibs_request.seq_no; 377 378 r = amdgpu_cs_query_fence_status(&fence_status, 379 AMDGPU_TIMEOUT_INFINITE,0, &expired); 380 CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1); 381 382 pthread_join(stress_thread, NULL); 383 384 r = amdgpu_bo_list_destroy(bo_list); 385 CU_ASSERT_EQUAL(r, 0); 386 387 r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, 388 ib_result_mc_address, 4096); 389 CU_ASSERT_EQUAL(r, 0); 390 } 391 r = amdgpu_cs_ctx_free(context_handle); 392 CU_ASSERT_EQUAL(r, 0); 393} 394 395static void bad_access_helper(int reg_access) 396{ 397 amdgpu_context_handle context_handle; 398 amdgpu_bo_handle ib_result_handle; 399 void *ib_result_cpu; 400 uint64_t ib_result_mc_address; 401 struct amdgpu_cs_request ibs_request; 402 struct amdgpu_cs_ib_info ib_info; 403 struct amdgpu_cs_fence fence_status; 404 uint32_t expired; 405 int i, r; 406 amdgpu_bo_list_handle bo_list; 407 amdgpu_va_handle va_handle; 408 409 r = amdgpu_cs_ctx_create(device_handle, &context_handle); 410 CU_ASSERT_EQUAL(r, 0); 411 412 r = amdgpu_bo_alloc_and_map_raw(device_handle, 4096, 4096, 413 AMDGPU_GEM_DOMAIN_GTT, 0, 0, 414 &ib_result_handle, &ib_result_cpu, 415 &ib_result_mc_address, &va_handle); 416 CU_ASSERT_EQUAL(r, 0); 417 418 r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, 419 &bo_list); 420 CU_ASSERT_EQUAL(r, 0); 421 422 ptr = ib_result_cpu; 423 i = 0; 424 425 ptr[i++] = PACKET3(PACKET3_WRITE_DATA, 3); 426 ptr[i++] = (reg_access ? WRITE_DATA_DST_SEL(0) : WRITE_DATA_DST_SEL(5))| WR_CONFIRM; 427 ptr[i++] = reg_access ? mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR : 0xdeadbee0; 428 ptr[i++] = 0; 429 ptr[i++] = 0xdeadbeef; 430 431 for (; i < 16; ++i) 432 ptr[i] = 0xffff1000; 433 434 memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); 435 ib_info.ib_mc_address = ib_result_mc_address; 436 ib_info.size = 16; 437 438 memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request)); 439 ibs_request.ip_type = AMDGPU_HW_IP_GFX; 440 ibs_request.ring = 0; 441 ibs_request.number_of_ibs = 1; 442 ibs_request.ibs = &ib_info; 443 ibs_request.resources = bo_list; 444 ibs_request.fence_info.handle = NULL; 445 446 r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1); 447 CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1); 448 449 450 memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence)); 451 fence_status.context = context_handle; 452 fence_status.ip_type = AMDGPU_HW_IP_GFX; 453 fence_status.ip_instance = 0; 454 fence_status.ring = 0; 455 fence_status.fence = ibs_request.seq_no; 456 457 r = amdgpu_cs_query_fence_status(&fence_status, 458 AMDGPU_TIMEOUT_INFINITE,0, &expired); 459 CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1); 460 461 r = amdgpu_bo_list_destroy(bo_list); 462 CU_ASSERT_EQUAL(r, 0); 463 464 r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, 465 ib_result_mc_address, 4096); 466 CU_ASSERT_EQUAL(r, 0); 467 468 r = amdgpu_cs_ctx_free(context_handle); 469 CU_ASSERT_EQUAL(r, 0); 470} 471 472static void amdgpu_illegal_reg_access() 473{ 474 bad_access_helper(1); 475} 476 477static void amdgpu_illegal_mem_access() 478{ 479 bad_access_helper(0); 480} 481