deadlock_tests.c revision 6532f28e
1/* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22*/ 23 24#include <stdio.h> 25#include <stdlib.h> 26#include <unistd.h> 27#ifdef HAVE_ALLOCA_H 28# include <alloca.h> 29#endif 30 31#include "CUnit/Basic.h" 32 33#include "amdgpu_test.h" 34#include "amdgpu_drm.h" 35#include "amdgpu_internal.h" 36 37#include <pthread.h> 38 39 40/* 41 * This defines the delay in MS after which memory location designated for 42 * compression against reference value is written to, unblocking command 43 * processor 44 */ 45#define WRITE_MEM_ADDRESS_DELAY_MS 100 46 47#define PACKET_TYPE3 3 48 49#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 50 (((op) & 0xFF) << 8) | \ 51 ((n) & 0x3FFF) << 16) 52 53#define PACKET3_WAIT_REG_MEM 0x3C 54#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 55 /* 0 - always 56 * 1 - < 57 * 2 - <= 58 * 3 - == 59 * 4 - != 60 * 5 - >= 61 * 6 - > 62 */ 63#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 64 /* 0 - reg 65 * 1 - mem 66 */ 67#define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 68 /* 0 - wait_reg_mem 69 * 1 - wr_wait_wr_reg 70 */ 71#define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 72 /* 0 - me 73 * 1 - pfp 74 */ 75 76#define PACKET3_WRITE_DATA 0x37 77#define WRITE_DATA_DST_SEL(x) ((x) << 8) 78 /* 0 - register 79 * 1 - memory (sync - via GRBM) 80 * 2 - gl2 81 * 3 - gds 82 * 4 - reserved 83 * 5 - memory (async - direct) 84 */ 85#define WR_ONE_ADDR (1 << 16) 86#define WR_CONFIRM (1 << 20) 87#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 88 /* 0 - LRU 89 * 1 - Stream 90 */ 91#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 92 /* 0 - me 93 * 1 - pfp 94 * 2 - ce 95 */ 96 97#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54f 98 99static amdgpu_device_handle device_handle; 100static uint32_t major_version; 101static uint32_t minor_version; 102 103static pthread_t stress_thread; 104static uint32_t *ptr; 105 106int use_uc_mtype = 0; 107 108static void amdgpu_deadlock_helper(unsigned ip_type); 109static void amdgpu_deadlock_gfx(void); 110static void amdgpu_deadlock_compute(void); 111static void amdgpu_illegal_reg_access(); 112static void amdgpu_illegal_mem_access(); 113 114CU_BOOL suite_deadlock_tests_enable(void) 115{ 116 CU_BOOL enable = CU_TRUE; 117 118 if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, 119 &minor_version, &device_handle)) 120 return CU_FALSE; 121 122 /* 123 * Only enable for ASICs supporting GPU reset and for which it's enabled 124 * by default (currently GFX8/9 dGPUS) 125 */ 126 if (device_handle->info.family_id != AMDGPU_FAMILY_VI && 127 device_handle->info.family_id != AMDGPU_FAMILY_AI && 128 device_handle->info.family_id != AMDGPU_FAMILY_CI) { 129 printf("\n\nGPU reset is not enabled for the ASIC, deadlock suite disabled\n"); 130 enable = CU_FALSE; 131 } 132 133 if (device_handle->info.family_id >= AMDGPU_FAMILY_AI) 134 use_uc_mtype = 1; 135 136 if (amdgpu_device_deinitialize(device_handle)) 137 return CU_FALSE; 138 139 return enable; 140} 141 142int suite_deadlock_tests_init(void) 143{ 144 int r; 145 146 r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, 147 &minor_version, &device_handle); 148 149 if (r) { 150 if ((r == -EACCES) && (errno == EACCES)) 151 printf("\n\nError:%s. " 152 "Hint:Try to run this test program as root.", 153 strerror(errno)); 154 return CUE_SINIT_FAILED; 155 } 156 157 return CUE_SUCCESS; 158} 159 160int suite_deadlock_tests_clean(void) 161{ 162 int r = amdgpu_device_deinitialize(device_handle); 163 164 if (r == 0) 165 return CUE_SUCCESS; 166 else 167 return CUE_SCLEAN_FAILED; 168} 169 170 171CU_TestInfo deadlock_tests[] = { 172 { "gfx ring block test (set amdgpu.lockup_timeout=50)", amdgpu_deadlock_gfx }, 173 { "compute ring block test (set amdgpu.lockup_timeout=50)", amdgpu_deadlock_compute }, 174 { "illegal reg access test", amdgpu_illegal_reg_access }, 175 { "illegal mem access test (set amdgpu.vm_fault_stop=2)", amdgpu_illegal_mem_access }, 176 CU_TEST_INFO_NULL, 177}; 178 179static void *write_mem_address(void *data) 180{ 181 int i; 182 183 /* useconds_t range is [0, 1,000,000] so use loop for waits > 1s */ 184 for (i = 0; i < WRITE_MEM_ADDRESS_DELAY_MS; i++) 185 usleep(1000); 186 187 ptr[256] = 0x1; 188 189 return 0; 190} 191 192static void amdgpu_deadlock_gfx(void) 193{ 194 amdgpu_deadlock_helper(AMDGPU_HW_IP_GFX); 195} 196 197static void amdgpu_deadlock_compute(void) 198{ 199 amdgpu_deadlock_helper(AMDGPU_HW_IP_COMPUTE); 200} 201 202static void amdgpu_deadlock_helper(unsigned ip_type) 203{ 204 amdgpu_context_handle context_handle; 205 amdgpu_bo_handle ib_result_handle; 206 void *ib_result_cpu; 207 uint64_t ib_result_mc_address; 208 struct amdgpu_cs_request ibs_request; 209 struct amdgpu_cs_ib_info ib_info; 210 struct amdgpu_cs_fence fence_status; 211 uint32_t expired; 212 int i, r; 213 amdgpu_bo_list_handle bo_list; 214 amdgpu_va_handle va_handle; 215 216 r = pthread_create(&stress_thread, NULL, write_mem_address, NULL); 217 CU_ASSERT_EQUAL(r, 0); 218 219 r = amdgpu_cs_ctx_create(device_handle, &context_handle); 220 CU_ASSERT_EQUAL(r, 0); 221 222 r = amdgpu_bo_alloc_and_map_raw(device_handle, 4096, 4096, 223 AMDGPU_GEM_DOMAIN_GTT, 0, use_uc_mtype ? AMDGPU_VM_MTYPE_UC : 0, 224 &ib_result_handle, &ib_result_cpu, 225 &ib_result_mc_address, &va_handle); 226 CU_ASSERT_EQUAL(r, 0); 227 228 r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, 229 &bo_list); 230 CU_ASSERT_EQUAL(r, 0); 231 232 ptr = ib_result_cpu; 233 234 ptr[0] = PACKET3(PACKET3_WAIT_REG_MEM, 5); 235 ptr[1] = (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ 236 WAIT_REG_MEM_FUNCTION(4) | /* != */ 237 WAIT_REG_MEM_ENGINE(0)); /* me */ 238 ptr[2] = (ib_result_mc_address + 256*4) & 0xfffffffc; 239 ptr[3] = ((ib_result_mc_address + 256*4) >> 32) & 0xffffffff; 240 ptr[4] = 0x00000000; /* reference value */ 241 ptr[5] = 0xffffffff; /* and mask */ 242 ptr[6] = 0x00000004; /* poll interval */ 243 244 for (i = 7; i < 16; ++i) 245 ptr[i] = 0xffff1000; 246 247 248 ptr[256] = 0x0; /* the memory we wait on to change */ 249 250 251 252 memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); 253 ib_info.ib_mc_address = ib_result_mc_address; 254 ib_info.size = 16; 255 256 memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request)); 257 ibs_request.ip_type = ip_type; 258 ibs_request.ring = 0; 259 ibs_request.number_of_ibs = 1; 260 ibs_request.ibs = &ib_info; 261 ibs_request.resources = bo_list; 262 ibs_request.fence_info.handle = NULL; 263 264 for (i = 0; i < 200; i++) { 265 r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1); 266 CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1); 267 268 } 269 270 memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence)); 271 fence_status.context = context_handle; 272 fence_status.ip_type = ip_type; 273 fence_status.ip_instance = 0; 274 fence_status.ring = 0; 275 fence_status.fence = ibs_request.seq_no; 276 277 r = amdgpu_cs_query_fence_status(&fence_status, 278 AMDGPU_TIMEOUT_INFINITE,0, &expired); 279 CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1); 280 281 pthread_join(stress_thread, NULL); 282 283 r = amdgpu_bo_list_destroy(bo_list); 284 CU_ASSERT_EQUAL(r, 0); 285 286 r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, 287 ib_result_mc_address, 4096); 288 CU_ASSERT_EQUAL(r, 0); 289 290 r = amdgpu_cs_ctx_free(context_handle); 291 CU_ASSERT_EQUAL(r, 0); 292} 293 294static void bad_access_helper(int reg_access) 295{ 296 amdgpu_context_handle context_handle; 297 amdgpu_bo_handle ib_result_handle; 298 void *ib_result_cpu; 299 uint64_t ib_result_mc_address; 300 struct amdgpu_cs_request ibs_request; 301 struct amdgpu_cs_ib_info ib_info; 302 struct amdgpu_cs_fence fence_status; 303 uint32_t expired; 304 int i, r; 305 amdgpu_bo_list_handle bo_list; 306 amdgpu_va_handle va_handle; 307 308 r = amdgpu_cs_ctx_create(device_handle, &context_handle); 309 CU_ASSERT_EQUAL(r, 0); 310 311 r = amdgpu_bo_alloc_and_map_raw(device_handle, 4096, 4096, 312 AMDGPU_GEM_DOMAIN_GTT, 0, 0, 313 &ib_result_handle, &ib_result_cpu, 314 &ib_result_mc_address, &va_handle); 315 CU_ASSERT_EQUAL(r, 0); 316 317 r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, 318 &bo_list); 319 CU_ASSERT_EQUAL(r, 0); 320 321 ptr = ib_result_cpu; 322 i = 0; 323 324 ptr[i++] = PACKET3(PACKET3_WRITE_DATA, 3); 325 ptr[i++] = (reg_access ? WRITE_DATA_DST_SEL(0) : WRITE_DATA_DST_SEL(5))| WR_CONFIRM; 326 ptr[i++] = reg_access ? mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR : 0xdeadbee0; 327 ptr[i++] = 0; 328 ptr[i++] = 0xdeadbeef; 329 330 for (; i < 16; ++i) 331 ptr[i] = 0xffff1000; 332 333 memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); 334 ib_info.ib_mc_address = ib_result_mc_address; 335 ib_info.size = 16; 336 337 memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request)); 338 ibs_request.ip_type = AMDGPU_HW_IP_GFX; 339 ibs_request.ring = 0; 340 ibs_request.number_of_ibs = 1; 341 ibs_request.ibs = &ib_info; 342 ibs_request.resources = bo_list; 343 ibs_request.fence_info.handle = NULL; 344 345 r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1); 346 CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1); 347 348 349 memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence)); 350 fence_status.context = context_handle; 351 fence_status.ip_type = AMDGPU_HW_IP_GFX; 352 fence_status.ip_instance = 0; 353 fence_status.ring = 0; 354 fence_status.fence = ibs_request.seq_no; 355 356 r = amdgpu_cs_query_fence_status(&fence_status, 357 AMDGPU_TIMEOUT_INFINITE,0, &expired); 358 CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1); 359 360 r = amdgpu_bo_list_destroy(bo_list); 361 CU_ASSERT_EQUAL(r, 0); 362 363 r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, 364 ib_result_mc_address, 4096); 365 CU_ASSERT_EQUAL(r, 0); 366 367 r = amdgpu_cs_ctx_free(context_handle); 368 CU_ASSERT_EQUAL(r, 0); 369} 370 371static void amdgpu_illegal_reg_access() 372{ 373 bad_access_helper(1); 374} 375 376static void amdgpu_illegal_mem_access() 377{ 378 bad_access_helper(0); 379} 380