shader_code.h revision b0ab5608
1/* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22*/ 23 24#ifndef _shader_code_h_ 25#define _shader_code_h_ 26 27#ifndef ARRAY_SIZE 28#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) 29#endif 30 31enum amdgpu_test_gfx_version { 32 AMDGPU_TEST_GFX_V9 = 0, 33 AMDGPU_TEST_GFX_V10, 34 AMDGPU_TEST_GFX_V11, 35 AMDGPU_TEST_GFX_MAX, 36}; 37 38enum cs_type { 39 CS_BUFFERCLEAR = 0, 40 CS_BUFFERCOPY, 41 CS_HANG, 42 CS_HANG_SLOW, 43}; 44 45enum ps_type { 46 PS_CONST, 47 PS_TEX, 48 PS_HANG, 49 PS_HANG_SLOW 50}; 51 52enum vs_type { 53 VS_RECTPOSTEXFAST, 54}; 55 56struct reg_info { 57 uint32_t reg_offset; ///< Memory mapped register offset 58 uint32_t reg_value; ///< register value 59}; 60 61#include "shader_code_hang.h" 62#include "shader_code_gfx9.h" 63#include "shader_code_gfx10.h" 64#include "shader_code_gfx11.h" 65 66struct shader_test_cs_shader { 67 const uint32_t *shader; 68 uint32_t shader_size; 69 const struct reg_info *sh_reg; 70 uint32_t num_sh_reg; 71 const struct reg_info *context_reg; 72 uint32_t num_context_reg; 73}; 74 75struct shader_test_ps_shader { 76 const uint32_t *shader; 77 unsigned shader_size; 78 const uint32_t patchinfo_code_size; 79 const uint32_t *patchinfo_code; 80 const uint32_t *patchinfo_code_offset; 81 const struct reg_info *sh_reg; 82 const uint32_t num_sh_reg; 83 const struct reg_info *context_reg; 84 const uint32_t num_context_reg; 85}; 86 87struct shader_test_vs_shader { 88 const uint32_t *shader; 89 uint32_t shader_size; 90 const struct reg_info *sh_reg; 91 uint32_t num_sh_reg; 92 const struct reg_info *context_reg; 93 uint32_t num_context_reg; 94}; 95 96static const struct shader_test_cs_shader shader_test_cs[AMDGPU_TEST_GFX_MAX][2] = { 97 // gfx9, cs_bufferclear 98 {{bufferclear_cs_shader_gfx9, sizeof(bufferclear_cs_shader_gfx9), bufferclear_cs_shader_registers_gfx9, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx9)}, 99 // gfx9, cs_buffercopy 100 {buffercopy_cs_shader_gfx9, sizeof(buffercopy_cs_shader_gfx9), bufferclear_cs_shader_registers_gfx9, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx9)}}, 101 // gfx10, cs_bufferclear 102 {{bufferclear_cs_shader_gfx10, sizeof(bufferclear_cs_shader_gfx10), bufferclear_cs_shader_registers_gfx9, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx9)}, 103 // gfx10, cs_buffercopy 104 {buffercopy_cs_shader_gfx10, sizeof(bufferclear_cs_shader_gfx10), bufferclear_cs_shader_registers_gfx9, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx9)}}, 105 // gfx11, cs_bufferclear 106 {{bufferclear_cs_shader_gfx11, sizeof(bufferclear_cs_shader_gfx11), bufferclear_cs_shader_registers_gfx11, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx11)}, 107 // gfx11, cs_buffercopy 108 {buffercopy_cs_shader_gfx11, sizeof(bufferclear_cs_shader_gfx11), bufferclear_cs_shader_registers_gfx11, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx11)}}, 109}; 110 111#define SHADER_PS_INFO(_ps, _n) \ 112 {ps_##_ps##_shader_gfx##_n, sizeof(ps_##_ps##_shader_gfx##_n), \ 113 ps_##_ps##_shader_patchinfo_code_size_gfx##_n, \ 114 ps_##_ps##_shader_patchinfo_code_gfx##_n, \ 115 ps_##_ps##_shader_patchinfo_offset_gfx##_n, \ 116 ps_##_ps##_sh_registers_gfx##_n, ps_##_ps##_num_sh_registers_gfx##_n, \ 117 ps_##_ps##_context_registers_gfx##_n, ps_##_ps##_num_context_registers_gfx##_n} 118static const struct shader_test_ps_shader shader_test_ps[AMDGPU_TEST_GFX_MAX][2] = { 119 {SHADER_PS_INFO(const, 9), SHADER_PS_INFO(tex, 9)}, 120 {SHADER_PS_INFO(const, 10), SHADER_PS_INFO(tex, 10)}, 121 {SHADER_PS_INFO(const, 11), SHADER_PS_INFO(tex, 11)}, 122}; 123 124#define SHADER_VS_INFO(_vs, _n) \ 125 {vs_##_vs##_shader_gfx##_n, sizeof(vs_##_vs##_shader_gfx##_n), \ 126 vs_##_vs##_sh_registers_gfx##_n, vs_##_vs##_num_sh_registers_gfx##_n, \ 127 vs_##_vs##_context_registers_gfx##_n, vs_##_vs##_num_context_registers_gfx##_n} 128static const struct shader_test_vs_shader shader_test_vs[AMDGPU_TEST_GFX_MAX][1] = { 129 {SHADER_VS_INFO(RectPosTexFast, 9)}, 130 {SHADER_VS_INFO(RectPosTexFast, 10)}, 131 {SHADER_VS_INFO(RectPosTexFast, 11)}, 132}; 133 134struct shader_test_gfx_info { 135 const uint32_t *preamble_cache; 136 uint32_t size_preamble_cache; 137 const uint32_t *cached_cmd; 138 uint32_t size_cached_cmd; 139 uint32_t sh_reg_base; 140 uint32_t context_reg_base; 141}; 142 143#define SHADER_TEST_GFX_INFO(_n) \ 144 preamblecache_gfx##_n, sizeof(preamblecache_gfx##_n), \ 145 cached_cmd_gfx##_n, sizeof(cached_cmd_gfx##_n), \ 146 sh_reg_base_gfx##_n, context_reg_base_gfx##_n 147 148static struct shader_test_gfx_info shader_test_gfx_info[AMDGPU_TEST_GFX_MAX] = { 149 {SHADER_TEST_GFX_INFO(9),}, 150 {SHADER_TEST_GFX_INFO(10),}, 151 {SHADER_TEST_GFX_INFO(11),}, 152}; 153#endif 154