vce_tests.c revision 00a23bda
1/* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22*/ 23 24#ifdef HAVE_CONFIG_H 25#include "config.h" 26#endif 27 28#include <stdio.h> 29#include <inttypes.h> 30 31#include "CUnit/Basic.h" 32 33#include "util_math.h" 34 35#include "amdgpu_test.h" 36#include "amdgpu_drm.h" 37#include "amdgpu_internal.h" 38 39#include "vce_ib.h" 40#include "frame.h" 41 42#define IB_SIZE 4096 43#define MAX_RESOURCES 16 44 45struct amdgpu_vce_bo { 46 amdgpu_bo_handle handle; 47 amdgpu_va_handle va_handle; 48 uint64_t addr; 49 uint64_t size; 50 uint8_t *ptr; 51}; 52 53struct amdgpu_vce_encode { 54 unsigned width; 55 unsigned height; 56 struct amdgpu_vce_bo vbuf; 57 struct amdgpu_vce_bo bs[2]; 58 struct amdgpu_vce_bo fb[2]; 59 struct amdgpu_vce_bo cpb; 60 unsigned ib_len; 61 bool two_instance; 62}; 63 64static amdgpu_device_handle device_handle; 65static uint32_t major_version; 66static uint32_t minor_version; 67static uint32_t family_id; 68static uint32_t vce_harvest_config; 69 70static amdgpu_context_handle context_handle; 71static amdgpu_bo_handle ib_handle; 72static amdgpu_va_handle ib_va_handle; 73static uint64_t ib_mc_address; 74static uint32_t *ib_cpu; 75 76static struct amdgpu_vce_encode enc; 77static amdgpu_bo_handle resources[MAX_RESOURCES]; 78static unsigned num_resources; 79 80static void amdgpu_cs_vce_create(void); 81static void amdgpu_cs_vce_encode(void); 82static void amdgpu_cs_vce_destroy(void); 83 84CU_TestInfo vce_tests[] = { 85 { "VCE create", amdgpu_cs_vce_create }, 86 { "VCE encode", amdgpu_cs_vce_encode }, 87 { "VCE destroy", amdgpu_cs_vce_destroy }, 88 CU_TEST_INFO_NULL, 89}; 90 91 92CU_BOOL suite_vce_tests_enable(void) 93{ 94 if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, 95 &minor_version, &device_handle)) 96 return CU_FALSE; 97 98 family_id = device_handle->info.family_id; 99 100 if (amdgpu_device_deinitialize(device_handle)) 101 return CU_FALSE; 102 103 104 if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI) { 105 printf("\n\nThe ASIC NOT support VCE, suite disabled\n"); 106 return CU_FALSE; 107 } 108 109 return CU_TRUE; 110} 111 112int suite_vce_tests_init(void) 113{ 114 int r; 115 116 r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, 117 &minor_version, &device_handle); 118 if (r) { 119 if ((r == -EACCES) && (errno == EACCES)) 120 printf("\n\nError:%s. " 121 "Hint:Try to run this test program as root.", 122 strerror(errno)); 123 124 return CUE_SINIT_FAILED; 125 } 126 127 family_id = device_handle->info.family_id; 128 vce_harvest_config = device_handle->info.vce_harvest_config; 129 130 r = amdgpu_cs_ctx_create(device_handle, &context_handle); 131 if (r) 132 return CUE_SINIT_FAILED; 133 134 r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096, 135 AMDGPU_GEM_DOMAIN_GTT, 0, 136 &ib_handle, (void**)&ib_cpu, 137 &ib_mc_address, &ib_va_handle); 138 if (r) 139 return CUE_SINIT_FAILED; 140 141 memset(&enc, 0, sizeof(struct amdgpu_vce_encode)); 142 143 return CUE_SUCCESS; 144} 145 146int suite_vce_tests_clean(void) 147{ 148 int r; 149 150 r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, 151 ib_mc_address, IB_SIZE); 152 if (r) 153 return CUE_SCLEAN_FAILED; 154 155 r = amdgpu_cs_ctx_free(context_handle); 156 if (r) 157 return CUE_SCLEAN_FAILED; 158 159 r = amdgpu_device_deinitialize(device_handle); 160 if (r) 161 return CUE_SCLEAN_FAILED; 162 163 return CUE_SUCCESS; 164} 165 166static int submit(unsigned ndw, unsigned ip) 167{ 168 struct amdgpu_cs_request ibs_request = {0}; 169 struct amdgpu_cs_ib_info ib_info = {0}; 170 struct amdgpu_cs_fence fence_status = {0}; 171 uint32_t expired; 172 int r; 173 174 ib_info.ib_mc_address = ib_mc_address; 175 ib_info.size = ndw; 176 177 ibs_request.ip_type = ip; 178 179 r = amdgpu_bo_list_create(device_handle, num_resources, resources, 180 NULL, &ibs_request.resources); 181 if (r) 182 return r; 183 184 ibs_request.number_of_ibs = 1; 185 ibs_request.ibs = &ib_info; 186 ibs_request.fence_info.handle = NULL; 187 188 r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1); 189 if (r) 190 return r; 191 192 r = amdgpu_bo_list_destroy(ibs_request.resources); 193 if (r) 194 return r; 195 196 fence_status.context = context_handle; 197 fence_status.ip_type = ip; 198 fence_status.fence = ibs_request.seq_no; 199 200 r = amdgpu_cs_query_fence_status(&fence_status, 201 AMDGPU_TIMEOUT_INFINITE, 202 0, &expired); 203 if (r) 204 return r; 205 206 return 0; 207} 208 209static void alloc_resource(struct amdgpu_vce_bo *vce_bo, unsigned size, unsigned domain) 210{ 211 struct amdgpu_bo_alloc_request req = {0}; 212 amdgpu_bo_handle buf_handle; 213 amdgpu_va_handle va_handle; 214 uint64_t va = 0; 215 int r; 216 217 req.alloc_size = ALIGN(size, 4096); 218 req.preferred_heap = domain; 219 r = amdgpu_bo_alloc(device_handle, &req, &buf_handle); 220 CU_ASSERT_EQUAL(r, 0); 221 r = amdgpu_va_range_alloc(device_handle, 222 amdgpu_gpu_va_range_general, 223 req.alloc_size, 1, 0, &va, 224 &va_handle, 0); 225 CU_ASSERT_EQUAL(r, 0); 226 r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, 227 AMDGPU_VA_OP_MAP); 228 CU_ASSERT_EQUAL(r, 0); 229 vce_bo->addr = va; 230 vce_bo->handle = buf_handle; 231 vce_bo->size = req.alloc_size; 232 vce_bo->va_handle = va_handle; 233 r = amdgpu_bo_cpu_map(vce_bo->handle, (void **)&vce_bo->ptr); 234 CU_ASSERT_EQUAL(r, 0); 235 memset(vce_bo->ptr, 0, size); 236 r = amdgpu_bo_cpu_unmap(vce_bo->handle); 237 CU_ASSERT_EQUAL(r, 0); 238} 239 240static void free_resource(struct amdgpu_vce_bo *vce_bo) 241{ 242 int r; 243 244 r = amdgpu_bo_va_op(vce_bo->handle, 0, vce_bo->size, 245 vce_bo->addr, 0, AMDGPU_VA_OP_UNMAP); 246 CU_ASSERT_EQUAL(r, 0); 247 248 r = amdgpu_va_range_free(vce_bo->va_handle); 249 CU_ASSERT_EQUAL(r, 0); 250 251 r = amdgpu_bo_free(vce_bo->handle); 252 CU_ASSERT_EQUAL(r, 0); 253 memset(vce_bo, 0, sizeof(*vce_bo)); 254} 255 256static void amdgpu_cs_vce_create(void) 257{ 258 unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; 259 int len, r; 260 261 enc.width = vce_create[6]; 262 enc.height = vce_create[7]; 263 264 num_resources = 0; 265 alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT); 266 resources[num_resources++] = enc.fb[0].handle; 267 resources[num_resources++] = ib_handle; 268 269 len = 0; 270 memcpy(ib_cpu, vce_session, sizeof(vce_session)); 271 len += sizeof(vce_session) / 4; 272 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo)); 273 len += sizeof(vce_taskinfo) / 4; 274 memcpy((ib_cpu + len), vce_create, sizeof(vce_create)); 275 ib_cpu[len + 8] = ALIGN(enc.width, align); 276 ib_cpu[len + 9] = ALIGN(enc.width, align); 277 len += sizeof(vce_create) / 4; 278 memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback)); 279 ib_cpu[len + 2] = enc.fb[0].addr >> 32; 280 ib_cpu[len + 3] = enc.fb[0].addr; 281 len += sizeof(vce_feedback) / 4; 282 283 r = submit(len, AMDGPU_HW_IP_VCE); 284 CU_ASSERT_EQUAL(r, 0); 285 286 free_resource(&enc.fb[0]); 287} 288 289static void amdgpu_cs_vce_config(void) 290{ 291 int len = 0, r; 292 293 memcpy((ib_cpu + len), vce_session, sizeof(vce_session)); 294 len += sizeof(vce_session) / 4; 295 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo)); 296 ib_cpu[len + 3] = 2; 297 ib_cpu[len + 6] = 0xffffffff; 298 len += sizeof(vce_taskinfo) / 4; 299 memcpy((ib_cpu + len), vce_rate_ctrl, sizeof(vce_rate_ctrl)); 300 len += sizeof(vce_rate_ctrl) / 4; 301 memcpy((ib_cpu + len), vce_config_ext, sizeof(vce_config_ext)); 302 len += sizeof(vce_config_ext) / 4; 303 memcpy((ib_cpu + len), vce_motion_est, sizeof(vce_motion_est)); 304 len += sizeof(vce_motion_est) / 4; 305 memcpy((ib_cpu + len), vce_rdo, sizeof(vce_rdo)); 306 len += sizeof(vce_rdo) / 4; 307 memcpy((ib_cpu + len), vce_pic_ctrl, sizeof(vce_pic_ctrl)); 308 len += sizeof(vce_pic_ctrl) / 4; 309 310 r = submit(len, AMDGPU_HW_IP_VCE); 311 CU_ASSERT_EQUAL(r, 0); 312} 313 314static void amdgpu_cs_vce_encode_idr(struct amdgpu_vce_encode *enc) 315{ 316 317 uint64_t luma_offset, chroma_offset; 318 unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; 319 unsigned luma_size = ALIGN(enc->width, align) * ALIGN(enc->height, 16); 320 int len = 0, i, r; 321 322 luma_offset = enc->vbuf.addr; 323 chroma_offset = luma_offset + luma_size; 324 325 memcpy((ib_cpu + len), vce_session, sizeof(vce_session)); 326 len += sizeof(vce_session) / 4; 327 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo)); 328 len += sizeof(vce_taskinfo) / 4; 329 memcpy((ib_cpu + len), vce_bs_buffer, sizeof(vce_bs_buffer)); 330 ib_cpu[len + 2] = enc->bs[0].addr >> 32; 331 ib_cpu[len + 3] = enc->bs[0].addr; 332 len += sizeof(vce_bs_buffer) / 4; 333 memcpy((ib_cpu + len), vce_context_buffer, sizeof(vce_context_buffer)); 334 ib_cpu[len + 2] = enc->cpb.addr >> 32; 335 ib_cpu[len + 3] = enc->cpb.addr; 336 len += sizeof(vce_context_buffer) / 4; 337 memcpy((ib_cpu + len), vce_aux_buffer, sizeof(vce_aux_buffer)); 338 for (i = 0; i < 8; ++i) 339 ib_cpu[len + 2 + i] = luma_size * 1.5 * (i + 2); 340 for (i = 0; i < 8; ++i) 341 ib_cpu[len + 10 + i] = luma_size * 1.5; 342 len += sizeof(vce_aux_buffer) / 4; 343 memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback)); 344 ib_cpu[len + 2] = enc->fb[0].addr >> 32; 345 ib_cpu[len + 3] = enc->fb[0].addr; 346 len += sizeof(vce_feedback) / 4; 347 memcpy((ib_cpu + len), vce_encode, sizeof(vce_encode)); 348 ib_cpu[len + 9] = luma_offset >> 32; 349 ib_cpu[len + 10] = luma_offset; 350 ib_cpu[len + 11] = chroma_offset >> 32; 351 ib_cpu[len + 12] = chroma_offset; 352 ib_cpu[len + 14] = ALIGN(enc->width, align); 353 ib_cpu[len + 15] = ALIGN(enc->width, align); 354 ib_cpu[len + 73] = luma_size * 1.5; 355 ib_cpu[len + 74] = luma_size * 2.5; 356 len += sizeof(vce_encode) / 4; 357 enc->ib_len = len; 358 if (!enc->two_instance) { 359 r = submit(len, AMDGPU_HW_IP_VCE); 360 CU_ASSERT_EQUAL(r, 0); 361 } 362} 363 364static void amdgpu_cs_vce_encode_p(struct amdgpu_vce_encode *enc) 365{ 366 uint64_t luma_offset, chroma_offset; 367 int len, i, r; 368 unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; 369 unsigned luma_size = ALIGN(enc->width, align) * ALIGN(enc->height, 16); 370 371 len = (enc->two_instance) ? enc->ib_len : 0; 372 luma_offset = enc->vbuf.addr; 373 chroma_offset = luma_offset + luma_size; 374 375 if (!enc->two_instance) { 376 memcpy((ib_cpu + len), vce_session, sizeof(vce_session)); 377 len += sizeof(vce_session) / 4; 378 } 379 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo)); 380 len += sizeof(vce_taskinfo) / 4; 381 memcpy((ib_cpu + len), vce_bs_buffer, sizeof(vce_bs_buffer)); 382 ib_cpu[len + 2] = enc->bs[1].addr >> 32; 383 ib_cpu[len + 3] = enc->bs[1].addr; 384 len += sizeof(vce_bs_buffer) / 4; 385 memcpy((ib_cpu + len), vce_context_buffer, sizeof(vce_context_buffer)); 386 ib_cpu[len + 2] = enc->cpb.addr >> 32; 387 ib_cpu[len + 3] = enc->cpb.addr; 388 len += sizeof(vce_context_buffer) / 4; 389 memcpy((ib_cpu + len), vce_aux_buffer, sizeof(vce_aux_buffer)); 390 for (i = 0; i < 8; ++i) 391 ib_cpu[len + 2 + i] = luma_size * 1.5 * (i + 2); 392 for (i = 0; i < 8; ++i) 393 ib_cpu[len + 10 + i] = luma_size * 1.5; 394 len += sizeof(vce_aux_buffer) / 4; 395 memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback)); 396 ib_cpu[len + 2] = enc->fb[1].addr >> 32; 397 ib_cpu[len + 3] = enc->fb[1].addr; 398 len += sizeof(vce_feedback) / 4; 399 memcpy((ib_cpu + len), vce_encode, sizeof(vce_encode)); 400 ib_cpu[len + 2] = 0; 401 ib_cpu[len + 9] = luma_offset >> 32; 402 ib_cpu[len + 10] = luma_offset; 403 ib_cpu[len + 11] = chroma_offset >> 32; 404 ib_cpu[len + 12] = chroma_offset; 405 ib_cpu[len + 14] = ALIGN(enc->width, align); 406 ib_cpu[len + 15] = ALIGN(enc->width, align); 407 ib_cpu[len + 18] = 0; 408 ib_cpu[len + 19] = 0; 409 ib_cpu[len + 56] = 3; 410 ib_cpu[len + 57] = 0; 411 ib_cpu[len + 58] = 0; 412 ib_cpu[len + 59] = luma_size * 1.5; 413 ib_cpu[len + 60] = luma_size * 2.5; 414 ib_cpu[len + 73] = 0; 415 ib_cpu[len + 74] = luma_size; 416 ib_cpu[len + 81] = 1; 417 ib_cpu[len + 82] = 1; 418 len += sizeof(vce_encode) / 4; 419 420 r = submit(len, AMDGPU_HW_IP_VCE); 421 CU_ASSERT_EQUAL(r, 0); 422} 423 424static void check_result(struct amdgpu_vce_encode *enc) 425{ 426 uint64_t sum; 427 uint32_t s[2] = {180325, 15946}; 428 uint32_t *ptr, size; 429 int i, j, r; 430 431 for (i = 0; i < 2; ++i) { 432 r = amdgpu_bo_cpu_map(enc->fb[i].handle, (void **)&enc->fb[i].ptr); 433 CU_ASSERT_EQUAL(r, 0); 434 ptr = (uint32_t *)enc->fb[i].ptr; 435 size = ptr[4] - ptr[9]; 436 r = amdgpu_bo_cpu_unmap(enc->fb[i].handle); 437 CU_ASSERT_EQUAL(r, 0); 438 r = amdgpu_bo_cpu_map(enc->bs[i].handle, (void **)&enc->bs[i].ptr); 439 CU_ASSERT_EQUAL(r, 0); 440 for (j = 0, sum = 0; j < size; ++j) 441 sum += enc->bs[i].ptr[j]; 442 CU_ASSERT_EQUAL(sum, s[i]); 443 r = amdgpu_bo_cpu_unmap(enc->bs[i].handle); 444 CU_ASSERT_EQUAL(r, 0); 445 } 446} 447 448static void amdgpu_cs_vce_encode(void) 449{ 450 uint32_t vbuf_size, bs_size = 0x154000, cpb_size; 451 unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; 452 int i, r; 453 454 vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5; 455 cpb_size = vbuf_size * 10; 456 num_resources = 0; 457 alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT); 458 resources[num_resources++] = enc.fb[0].handle; 459 alloc_resource(&enc.fb[1], 4096, AMDGPU_GEM_DOMAIN_GTT); 460 resources[num_resources++] = enc.fb[1].handle; 461 alloc_resource(&enc.bs[0], bs_size, AMDGPU_GEM_DOMAIN_GTT); 462 resources[num_resources++] = enc.bs[0].handle; 463 alloc_resource(&enc.bs[1], bs_size, AMDGPU_GEM_DOMAIN_GTT); 464 resources[num_resources++] = enc.bs[1].handle; 465 alloc_resource(&enc.vbuf, vbuf_size, AMDGPU_GEM_DOMAIN_VRAM); 466 resources[num_resources++] = enc.vbuf.handle; 467 alloc_resource(&enc.cpb, cpb_size, AMDGPU_GEM_DOMAIN_VRAM); 468 resources[num_resources++] = enc.cpb.handle; 469 resources[num_resources++] = ib_handle; 470 471 r = amdgpu_bo_cpu_map(enc.vbuf.handle, (void **)&enc.vbuf.ptr); 472 CU_ASSERT_EQUAL(r, 0); 473 474 memset(enc.vbuf.ptr, 0, vbuf_size); 475 for (i = 0; i < enc.height; ++i) { 476 memcpy(enc.vbuf.ptr, (frame + i * enc.width), enc.width); 477 enc.vbuf.ptr += ALIGN(enc.width, align); 478 } 479 for (i = 0; i < enc.height / 2; ++i) { 480 memcpy(enc.vbuf.ptr, ((frame + enc.height * enc.width) + i * enc.width), enc.width); 481 enc.vbuf.ptr += ALIGN(enc.width, align); 482 } 483 484 r = amdgpu_bo_cpu_unmap(enc.vbuf.handle); 485 CU_ASSERT_EQUAL(r, 0); 486 487 amdgpu_cs_vce_config(); 488 489 if (family_id >= AMDGPU_FAMILY_VI) { 490 vce_taskinfo[3] = 3; 491 amdgpu_cs_vce_encode_idr(&enc); 492 amdgpu_cs_vce_encode_p(&enc); 493 check_result(&enc); 494 495 /* two pipes */ 496 vce_encode[16] = 0; 497 amdgpu_cs_vce_encode_idr(&enc); 498 amdgpu_cs_vce_encode_p(&enc); 499 check_result(&enc); 500 501 /* two instances */ 502 if (vce_harvest_config == 0) { 503 enc.two_instance = true; 504 vce_taskinfo[2] = 0x83; 505 vce_taskinfo[4] = 1; 506 amdgpu_cs_vce_encode_idr(&enc); 507 vce_taskinfo[2] = 0xffffffff; 508 vce_taskinfo[4] = 2; 509 amdgpu_cs_vce_encode_p(&enc); 510 check_result(&enc); 511 } 512 } else { 513 vce_taskinfo[3] = 3; 514 vce_encode[16] = 0; 515 amdgpu_cs_vce_encode_idr(&enc); 516 amdgpu_cs_vce_encode_p(&enc); 517 check_result(&enc); 518 } 519 520 free_resource(&enc.fb[0]); 521 free_resource(&enc.fb[1]); 522 free_resource(&enc.bs[0]); 523 free_resource(&enc.bs[1]); 524 free_resource(&enc.vbuf); 525 free_resource(&enc.cpb); 526} 527 528static void amdgpu_cs_vce_destroy(void) 529{ 530 int len, r; 531 532 num_resources = 0; 533 alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT); 534 resources[num_resources++] = enc.fb[0].handle; 535 resources[num_resources++] = ib_handle; 536 537 len = 0; 538 memcpy(ib_cpu, vce_session, sizeof(vce_session)); 539 len += sizeof(vce_session) / 4; 540 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo)); 541 ib_cpu[len + 3] = 1; 542 len += sizeof(vce_taskinfo) / 4; 543 memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback)); 544 ib_cpu[len + 2] = enc.fb[0].addr >> 32; 545 ib_cpu[len + 3] = enc.fb[0].addr; 546 len += sizeof(vce_feedback) / 4; 547 memcpy((ib_cpu + len), vce_destroy, sizeof(vce_destroy)); 548 len += sizeof(vce_destroy) / 4; 549 550 r = submit(len, AMDGPU_HW_IP_VCE); 551 CU_ASSERT_EQUAL(r, 0); 552 553 free_resource(&enc.fb[0]); 554} 555