vce_tests.c revision 3f012e29
1/* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22*/ 23 24#ifdef HAVE_CONFIG_H 25#include "config.h" 26#endif 27 28#include <stdio.h> 29#include <inttypes.h> 30 31#include "CUnit/Basic.h" 32 33#include "util_math.h" 34 35#include "amdgpu_test.h" 36#include "amdgpu_drm.h" 37#include "amdgpu_internal.h" 38 39#include "vce_ib.h" 40#include "frame.h" 41 42#define IB_SIZE 4096 43#define MAX_RESOURCES 16 44 45struct amdgpu_vce_bo { 46 amdgpu_bo_handle handle; 47 amdgpu_va_handle va_handle; 48 uint64_t addr; 49 uint64_t size; 50 uint8_t *ptr; 51}; 52 53struct amdgpu_vce_encode { 54 unsigned width; 55 unsigned height; 56 struct amdgpu_vce_bo vbuf; 57 struct amdgpu_vce_bo bs[2]; 58 struct amdgpu_vce_bo fb[2]; 59 struct amdgpu_vce_bo cpb; 60 unsigned ib_len; 61 bool two_instance; 62}; 63 64static amdgpu_device_handle device_handle; 65static uint32_t major_version; 66static uint32_t minor_version; 67static uint32_t family_id; 68static uint32_t vce_harvest_config; 69 70static amdgpu_context_handle context_handle; 71static amdgpu_bo_handle ib_handle; 72static amdgpu_va_handle ib_va_handle; 73static uint64_t ib_mc_address; 74static uint32_t *ib_cpu; 75 76static struct amdgpu_vce_encode enc; 77static amdgpu_bo_handle resources[MAX_RESOURCES]; 78static unsigned num_resources; 79 80static void amdgpu_cs_vce_create(void); 81static void amdgpu_cs_vce_encode(void); 82static void amdgpu_cs_vce_destroy(void); 83 84CU_TestInfo vce_tests[] = { 85 { "VCE create", amdgpu_cs_vce_create }, 86 { "VCE encode", amdgpu_cs_vce_encode }, 87 { "VCE destroy", amdgpu_cs_vce_destroy }, 88 CU_TEST_INFO_NULL, 89}; 90 91int suite_vce_tests_init(void) 92{ 93 int r; 94 95 r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, 96 &minor_version, &device_handle); 97 if (r) 98 return CUE_SINIT_FAILED; 99 100 family_id = device_handle->info.family_id; 101 vce_harvest_config = device_handle->info.vce_harvest_config; 102 103 r = amdgpu_cs_ctx_create(device_handle, &context_handle); 104 if (r) 105 return CUE_SINIT_FAILED; 106 107 r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096, 108 AMDGPU_GEM_DOMAIN_GTT, 0, 109 &ib_handle, (void**)&ib_cpu, 110 &ib_mc_address, &ib_va_handle); 111 if (r) 112 return CUE_SINIT_FAILED; 113 114 memset(&enc, 0, sizeof(struct amdgpu_vce_encode)); 115 116 return CUE_SUCCESS; 117} 118 119int suite_vce_tests_clean(void) 120{ 121 int r; 122 123 r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, 124 ib_mc_address, IB_SIZE); 125 if (r) 126 return CUE_SCLEAN_FAILED; 127 128 r = amdgpu_cs_ctx_free(context_handle); 129 if (r) 130 return CUE_SCLEAN_FAILED; 131 132 r = amdgpu_device_deinitialize(device_handle); 133 if (r) 134 return CUE_SCLEAN_FAILED; 135 136 return CUE_SUCCESS; 137} 138 139static int submit(unsigned ndw, unsigned ip) 140{ 141 struct amdgpu_cs_request ibs_request = {0}; 142 struct amdgpu_cs_ib_info ib_info = {0}; 143 struct amdgpu_cs_fence fence_status = {0}; 144 uint32_t expired; 145 int r; 146 147 ib_info.ib_mc_address = ib_mc_address; 148 ib_info.size = ndw; 149 150 ibs_request.ip_type = ip; 151 152 r = amdgpu_bo_list_create(device_handle, num_resources, resources, 153 NULL, &ibs_request.resources); 154 if (r) 155 return r; 156 157 ibs_request.number_of_ibs = 1; 158 ibs_request.ibs = &ib_info; 159 ibs_request.fence_info.handle = NULL; 160 161 r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1); 162 if (r) 163 return r; 164 165 r = amdgpu_bo_list_destroy(ibs_request.resources); 166 if (r) 167 return r; 168 169 fence_status.context = context_handle; 170 fence_status.ip_type = ip; 171 fence_status.fence = ibs_request.seq_no; 172 173 r = amdgpu_cs_query_fence_status(&fence_status, 174 AMDGPU_TIMEOUT_INFINITE, 175 0, &expired); 176 if (r) 177 return r; 178 179 return 0; 180} 181 182static void alloc_resource(struct amdgpu_vce_bo *vce_bo, unsigned size, unsigned domain) 183{ 184 struct amdgpu_bo_alloc_request req = {0}; 185 amdgpu_bo_handle buf_handle; 186 amdgpu_va_handle va_handle; 187 uint64_t va = 0; 188 int r; 189 190 req.alloc_size = ALIGN(size, 4096); 191 req.preferred_heap = domain; 192 r = amdgpu_bo_alloc(device_handle, &req, &buf_handle); 193 CU_ASSERT_EQUAL(r, 0); 194 r = amdgpu_va_range_alloc(device_handle, 195 amdgpu_gpu_va_range_general, 196 req.alloc_size, 1, 0, &va, 197 &va_handle, 0); 198 CU_ASSERT_EQUAL(r, 0); 199 r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, 200 AMDGPU_VA_OP_MAP); 201 CU_ASSERT_EQUAL(r, 0); 202 vce_bo->addr = va; 203 vce_bo->handle = buf_handle; 204 vce_bo->size = req.alloc_size; 205 vce_bo->va_handle = va_handle; 206 r = amdgpu_bo_cpu_map(vce_bo->handle, (void **)&vce_bo->ptr); 207 CU_ASSERT_EQUAL(r, 0); 208 memset(vce_bo->ptr, 0, size); 209 r = amdgpu_bo_cpu_unmap(vce_bo->handle); 210 CU_ASSERT_EQUAL(r, 0); 211} 212 213static void free_resource(struct amdgpu_vce_bo *vce_bo) 214{ 215 int r; 216 217 r = amdgpu_bo_va_op(vce_bo->handle, 0, vce_bo->size, 218 vce_bo->addr, 0, AMDGPU_VA_OP_UNMAP); 219 CU_ASSERT_EQUAL(r, 0); 220 221 r = amdgpu_va_range_free(vce_bo->va_handle); 222 CU_ASSERT_EQUAL(r, 0); 223 224 r = amdgpu_bo_free(vce_bo->handle); 225 CU_ASSERT_EQUAL(r, 0); 226 memset(vce_bo, 0, sizeof(*vce_bo)); 227} 228 229static void amdgpu_cs_vce_create(void) 230{ 231 int len, r; 232 233 enc.width = vce_create[6]; 234 enc.height = vce_create[7]; 235 236 num_resources = 0; 237 alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT); 238 resources[num_resources++] = enc.fb[0].handle; 239 resources[num_resources++] = ib_handle; 240 241 len = 0; 242 memcpy(ib_cpu, vce_session, sizeof(vce_session)); 243 len += sizeof(vce_session) / 4; 244 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo)); 245 len += sizeof(vce_taskinfo) / 4; 246 memcpy((ib_cpu + len), vce_create, sizeof(vce_create)); 247 len += sizeof(vce_create) / 4; 248 memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback)); 249 ib_cpu[len + 2] = enc.fb[0].addr >> 32; 250 ib_cpu[len + 3] = enc.fb[0].addr; 251 len += sizeof(vce_feedback) / 4; 252 253 r = submit(len, AMDGPU_HW_IP_VCE); 254 CU_ASSERT_EQUAL(r, 0); 255 256 free_resource(&enc.fb[0]); 257} 258 259static void amdgpu_cs_vce_config(void) 260{ 261 int len = 0, r; 262 263 memcpy((ib_cpu + len), vce_session, sizeof(vce_session)); 264 len += sizeof(vce_session) / 4; 265 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo)); 266 ib_cpu[len + 3] = 2; 267 ib_cpu[len + 6] = 0xffffffff; 268 len += sizeof(vce_taskinfo) / 4; 269 memcpy((ib_cpu + len), vce_rate_ctrl, sizeof(vce_rate_ctrl)); 270 len += sizeof(vce_rate_ctrl) / 4; 271 memcpy((ib_cpu + len), vce_config_ext, sizeof(vce_config_ext)); 272 len += sizeof(vce_config_ext) / 4; 273 memcpy((ib_cpu + len), vce_motion_est, sizeof(vce_motion_est)); 274 len += sizeof(vce_motion_est) / 4; 275 memcpy((ib_cpu + len), vce_rdo, sizeof(vce_rdo)); 276 len += sizeof(vce_rdo) / 4; 277 memcpy((ib_cpu + len), vce_pic_ctrl, sizeof(vce_pic_ctrl)); 278 len += sizeof(vce_pic_ctrl) / 4; 279 280 r = submit(len, AMDGPU_HW_IP_VCE); 281 CU_ASSERT_EQUAL(r, 0); 282} 283 284static void amdgpu_cs_vce_encode_idr(struct amdgpu_vce_encode *enc) 285{ 286 287 uint64_t luma_offset, chroma_offset; 288 int len = 0, r; 289 290 luma_offset = enc->vbuf.addr; 291 chroma_offset = luma_offset + enc->width * enc->height; 292 293 memcpy((ib_cpu + len), vce_session, sizeof(vce_session)); 294 len += sizeof(vce_session) / 4; 295 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo)); 296 len += sizeof(vce_taskinfo) / 4; 297 memcpy((ib_cpu + len), vce_bs_buffer, sizeof(vce_bs_buffer)); 298 ib_cpu[len + 2] = enc->bs[0].addr >> 32; 299 ib_cpu[len + 3] = enc->bs[0].addr; 300 len += sizeof(vce_bs_buffer) / 4; 301 memcpy((ib_cpu + len), vce_context_buffer, sizeof(vce_context_buffer)); 302 ib_cpu[len + 2] = enc->cpb.addr >> 32; 303 ib_cpu[len + 3] = enc->cpb.addr; 304 len += sizeof(vce_context_buffer) / 4; 305 memcpy((ib_cpu + len), vce_aux_buffer, sizeof(vce_aux_buffer)); 306 len += sizeof(vce_aux_buffer) / 4; 307 memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback)); 308 ib_cpu[len + 2] = enc->fb[0].addr >> 32; 309 ib_cpu[len + 3] = enc->fb[0].addr; 310 len += sizeof(vce_feedback) / 4; 311 memcpy((ib_cpu + len), vce_encode, sizeof(vce_encode)); 312 ib_cpu[len + 9] = luma_offset >> 32; 313 ib_cpu[len + 10] = luma_offset; 314 ib_cpu[len + 11] = chroma_offset >> 32; 315 ib_cpu[len + 12] = chroma_offset; 316 ib_cpu[len + 73] = 0x7800; 317 ib_cpu[len + 74] = 0x7800 + 0x5000; 318 len += sizeof(vce_encode) / 4; 319 enc->ib_len = len; 320 if (!enc->two_instance) { 321 r = submit(len, AMDGPU_HW_IP_VCE); 322 CU_ASSERT_EQUAL(r, 0); 323 } 324} 325 326static void amdgpu_cs_vce_encode_p(struct amdgpu_vce_encode *enc) 327{ 328 uint64_t luma_offset, chroma_offset; 329 int len, r; 330 331 len = (enc->two_instance) ? enc->ib_len : 0; 332 luma_offset = enc->vbuf.addr; 333 chroma_offset = luma_offset + enc->width * enc->height; 334 335 if (!enc->two_instance) { 336 memcpy((ib_cpu + len), vce_session, sizeof(vce_session)); 337 len += sizeof(vce_session) / 4; 338 } 339 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo)); 340 len += sizeof(vce_taskinfo) / 4; 341 memcpy((ib_cpu + len), vce_bs_buffer, sizeof(vce_bs_buffer)); 342 ib_cpu[len + 2] = enc->bs[1].addr >> 32; 343 ib_cpu[len + 3] = enc->bs[1].addr; 344 len += sizeof(vce_bs_buffer) / 4; 345 memcpy((ib_cpu + len), vce_context_buffer, sizeof(vce_context_buffer)); 346 ib_cpu[len + 2] = enc->cpb.addr >> 32; 347 ib_cpu[len + 3] = enc->cpb.addr; 348 len += sizeof(vce_context_buffer) / 4; 349 memcpy((ib_cpu + len), vce_aux_buffer, sizeof(vce_aux_buffer)); 350 len += sizeof(vce_aux_buffer) / 4; 351 memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback)); 352 ib_cpu[len + 2] = enc->fb[1].addr >> 32; 353 ib_cpu[len + 3] = enc->fb[1].addr; 354 len += sizeof(vce_feedback) / 4; 355 memcpy((ib_cpu + len), vce_encode, sizeof(vce_encode)); 356 ib_cpu[len + 2] = 0; 357 ib_cpu[len + 9] = luma_offset >> 32; 358 ib_cpu[len + 10] = luma_offset; 359 ib_cpu[len + 11] = chroma_offset >> 32; 360 ib_cpu[len + 12] = chroma_offset; 361 ib_cpu[len + 18] = 0; 362 ib_cpu[len + 19] = 0; 363 ib_cpu[len + 56] = 3; 364 ib_cpu[len + 57] = 0; 365 ib_cpu[len + 58] = 0; 366 ib_cpu[len + 59] = 0x7800; 367 ib_cpu[len + 60] = 0x7800 + 0x5000; 368 ib_cpu[len + 73] = 0; 369 ib_cpu[len + 74] = 0x5000; 370 ib_cpu[len + 81] = 1; 371 ib_cpu[len + 82] = 1; 372 len += sizeof(vce_encode) / 4; 373 374 r = submit(len, AMDGPU_HW_IP_VCE); 375 CU_ASSERT_EQUAL(r, 0); 376} 377 378static void check_result(struct amdgpu_vce_encode *enc) 379{ 380 uint64_t sum; 381 uint32_t s[2] = {180325, 15946}; 382 uint32_t *ptr, size; 383 int i, j, r; 384 385 for (i = 0; i < 2; ++i) { 386 r = amdgpu_bo_cpu_map(enc->fb[i].handle, (void **)&enc->fb[i].ptr); 387 CU_ASSERT_EQUAL(r, 0); 388 ptr = (uint32_t *)enc->fb[i].ptr; 389 size = ptr[4] - ptr[9]; 390 r = amdgpu_bo_cpu_unmap(enc->fb[i].handle); 391 CU_ASSERT_EQUAL(r, 0); 392 r = amdgpu_bo_cpu_map(enc->bs[i].handle, (void **)&enc->bs[i].ptr); 393 CU_ASSERT_EQUAL(r, 0); 394 for (j = 0, sum = 0; j < size; ++j) 395 sum += enc->bs[i].ptr[j]; 396 CU_ASSERT_EQUAL(sum, s[i]); 397 r = amdgpu_bo_cpu_unmap(enc->bs[i].handle); 398 CU_ASSERT_EQUAL(r, 0); 399 } 400} 401 402static void amdgpu_cs_vce_encode(void) 403{ 404 uint32_t vbuf_size, bs_size = 0x154000, cpb_size; 405 int r; 406 407 vbuf_size = enc.width * enc.height * 1.5; 408 cpb_size = vbuf_size * 10; 409 num_resources = 0; 410 alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT); 411 resources[num_resources++] = enc.fb[0].handle; 412 alloc_resource(&enc.fb[1], 4096, AMDGPU_GEM_DOMAIN_GTT); 413 resources[num_resources++] = enc.fb[1].handle; 414 alloc_resource(&enc.bs[0], bs_size, AMDGPU_GEM_DOMAIN_GTT); 415 resources[num_resources++] = enc.bs[0].handle; 416 alloc_resource(&enc.bs[1], bs_size, AMDGPU_GEM_DOMAIN_GTT); 417 resources[num_resources++] = enc.bs[1].handle; 418 alloc_resource(&enc.vbuf, vbuf_size, AMDGPU_GEM_DOMAIN_VRAM); 419 resources[num_resources++] = enc.vbuf.handle; 420 alloc_resource(&enc.cpb, cpb_size, AMDGPU_GEM_DOMAIN_VRAM); 421 resources[num_resources++] = enc.cpb.handle; 422 resources[num_resources++] = ib_handle; 423 424 r = amdgpu_bo_cpu_map(enc.vbuf.handle, (void **)&enc.vbuf.ptr); 425 CU_ASSERT_EQUAL(r, 0); 426 memcpy(enc.vbuf.ptr, frame, sizeof(frame)); 427 r = amdgpu_bo_cpu_unmap(enc.vbuf.handle); 428 CU_ASSERT_EQUAL(r, 0); 429 430 amdgpu_cs_vce_config(); 431 432 if (family_id >= AMDGPU_FAMILY_VI) { 433 vce_taskinfo[3] = 3; 434 amdgpu_cs_vce_encode_idr(&enc); 435 amdgpu_cs_vce_encode_p(&enc); 436 check_result(&enc); 437 438 /* two pipes */ 439 vce_encode[16] = 0; 440 amdgpu_cs_vce_encode_idr(&enc); 441 amdgpu_cs_vce_encode_p(&enc); 442 check_result(&enc); 443 444 /* two instances */ 445 if (vce_harvest_config == 0) { 446 enc.two_instance = true; 447 vce_taskinfo[2] = 0x83; 448 vce_taskinfo[4] = 1; 449 amdgpu_cs_vce_encode_idr(&enc); 450 vce_taskinfo[2] = 0xffffffff; 451 vce_taskinfo[4] = 2; 452 amdgpu_cs_vce_encode_p(&enc); 453 check_result(&enc); 454 } 455 } else { 456 vce_taskinfo[3] = 3; 457 vce_encode[16] = 0; 458 amdgpu_cs_vce_encode_idr(&enc); 459 amdgpu_cs_vce_encode_p(&enc); 460 check_result(&enc); 461 } 462 463 free_resource(&enc.fb[0]); 464 free_resource(&enc.fb[1]); 465 free_resource(&enc.bs[0]); 466 free_resource(&enc.bs[1]); 467 free_resource(&enc.vbuf); 468 free_resource(&enc.cpb); 469} 470 471static void amdgpu_cs_vce_destroy(void) 472{ 473 int len, r; 474 475 num_resources = 0; 476 alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT); 477 resources[num_resources++] = enc.fb[0].handle; 478 resources[num_resources++] = ib_handle; 479 480 len = 0; 481 memcpy(ib_cpu, vce_session, sizeof(vce_session)); 482 len += sizeof(vce_session) / 4; 483 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo)); 484 ib_cpu[len + 3] = 1; 485 len += sizeof(vce_taskinfo) / 4; 486 memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback)); 487 ib_cpu[len + 2] = enc.fb[0].addr >> 32; 488 ib_cpu[len + 3] = enc.fb[0].addr; 489 len += sizeof(vce_feedback) / 4; 490 memcpy((ib_cpu + len), vce_destroy, sizeof(vce_destroy)); 491 len += sizeof(vce_destroy) / 4; 492 493 r = submit(len, AMDGPU_HW_IP_VCE); 494 CU_ASSERT_EQUAL(r, 0); 495 496 free_resource(&enc.fb[0]); 497} 498