vcn_tests.c revision 9bd392ad 
1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22*/
23
24#include <stdio.h>
25#include <inttypes.h>
26
27#include "CUnit/Basic.h"
28
29#include "util_math.h"
30
31#include "amdgpu_test.h"
32#include "amdgpu_drm.h"
33#include "amdgpu_internal.h"
34#include "decode_messages.h"
35
36#define IB_SIZE		4096
37#define MAX_RESOURCES	16
38
39struct amdgpu_vcn_bo {
40	amdgpu_bo_handle handle;
41	amdgpu_va_handle va_handle;
42	uint64_t addr;
43	uint64_t size;
44	uint8_t *ptr;
45};
46
47struct amdgpu_vcn_reg {
48	uint32_t data0;
49	uint32_t data1;
50	uint32_t cmd;
51	uint32_t nop;
52	uint32_t cntl;
53};
54
55static amdgpu_device_handle device_handle;
56static uint32_t major_version;
57static uint32_t minor_version;
58static uint32_t family_id;
59static uint32_t asic_id;
60
61static amdgpu_context_handle context_handle;
62static amdgpu_bo_handle ib_handle;
63static amdgpu_va_handle ib_va_handle;
64static uint64_t ib_mc_address;
65static uint32_t *ib_cpu;
66
67static amdgpu_bo_handle resources[MAX_RESOURCES];
68static unsigned num_resources;
69static struct amdgpu_vcn_reg reg;
70
71static void amdgpu_cs_vcn_dec_create(void);
72static void amdgpu_cs_vcn_dec_decode(void);
73static void amdgpu_cs_vcn_dec_destroy(void);
74
75static void amdgpu_cs_vcn_enc_create(void);
76static void amdgpu_cs_vcn_enc_encode(void);
77static void amdgpu_cs_vcn_enc_destroy(void);
78
79CU_TestInfo vcn_tests[] = {
80
81	{ "VCN DEC create",  amdgpu_cs_vcn_dec_create },
82	{ "VCN DEC decode",  amdgpu_cs_vcn_dec_decode },
83	{ "VCN DEC destroy",  amdgpu_cs_vcn_dec_destroy },
84
85	{ "VCN ENC create",  amdgpu_cs_vcn_enc_create },
86	{ "VCN ENC decode",  amdgpu_cs_vcn_enc_encode },
87	{ "VCN ENC destroy",  amdgpu_cs_vcn_enc_destroy },
88	CU_TEST_INFO_NULL,
89};
90
91CU_BOOL suite_vcn_tests_enable(void)
92{
93
94	if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
95				   &minor_version, &device_handle))
96		return CU_FALSE;
97
98	family_id = device_handle->info.family_id;
99	asic_id = device_handle->info.asic_id;
100
101	if (amdgpu_device_deinitialize(device_handle))
102			return CU_FALSE;
103
104
105	if (family_id < AMDGPU_FAMILY_RV) {
106		printf("\n\nThe ASIC NOT support VCN, suite disabled\n");
107		return CU_FALSE;
108	}
109
110	if (family_id == AMDGPU_FAMILY_RV) {
111		if (asic_id == 0x1636) {
112			reg.data0 = 0x504;
113			reg.data1 = 0x505;
114			reg.cmd = 0x503;
115			reg.nop = 0x53f;
116			reg.cntl = 0x506;
117		} else {
118			reg.data0 = 0x81c4;
119			reg.data1 = 0x81c5;
120			reg.cmd = 0x81c3;
121			reg.nop = 0x81ff;
122			reg.cntl = 0x81c6;
123		}
124	} else if (family_id == AMDGPU_FAMILY_NV) {
125		reg.data0 = 0x504;
126		reg.data1 = 0x505;
127		reg.cmd = 0x503;
128		reg.nop = 0x53f;
129		reg.cntl = 0x506;
130	} else
131		return CU_FALSE;
132
133	return CU_TRUE;
134}
135
136int suite_vcn_tests_init(void)
137{
138	int r;
139
140	r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
141				     &minor_version, &device_handle);
142	if (r)
143		return CUE_SINIT_FAILED;
144
145	family_id = device_handle->info.family_id;
146
147	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
148	if (r)
149		return CUE_SINIT_FAILED;
150
151	r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
152				    AMDGPU_GEM_DOMAIN_GTT, 0,
153				    &ib_handle, (void**)&ib_cpu,
154				    &ib_mc_address, &ib_va_handle);
155	if (r)
156		return CUE_SINIT_FAILED;
157
158	return CUE_SUCCESS;
159}
160
161int suite_vcn_tests_clean(void)
162{
163	int r;
164
165	r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
166			     ib_mc_address, IB_SIZE);
167	if (r)
168		return CUE_SCLEAN_FAILED;
169
170	r = amdgpu_cs_ctx_free(context_handle);
171	if (r)
172		return CUE_SCLEAN_FAILED;
173
174	r = amdgpu_device_deinitialize(device_handle);
175	if (r)
176		return CUE_SCLEAN_FAILED;
177
178	return CUE_SUCCESS;
179}
180
181static int submit(unsigned ndw, unsigned ip)
182{
183	struct amdgpu_cs_request ibs_request = {0};
184	struct amdgpu_cs_ib_info ib_info = {0};
185	struct amdgpu_cs_fence fence_status = {0};
186	uint32_t expired;
187	int r;
188
189	ib_info.ib_mc_address = ib_mc_address;
190	ib_info.size = ndw;
191
192	ibs_request.ip_type = ip;
193
194	r = amdgpu_bo_list_create(device_handle, num_resources, resources,
195				  NULL, &ibs_request.resources);
196	if (r)
197		return r;
198
199	ibs_request.number_of_ibs = 1;
200	ibs_request.ibs = &ib_info;
201	ibs_request.fence_info.handle = NULL;
202
203	r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
204	if (r)
205		return r;
206
207	r = amdgpu_bo_list_destroy(ibs_request.resources);
208	if (r)
209		return r;
210
211	fence_status.context = context_handle;
212	fence_status.ip_type = ip;
213	fence_status.fence = ibs_request.seq_no;
214
215	r = amdgpu_cs_query_fence_status(&fence_status,
216					 AMDGPU_TIMEOUT_INFINITE,
217					 0, &expired);
218	if (r)
219		return r;
220
221	return 0;
222}
223
224static void alloc_resource(struct amdgpu_vcn_bo *vcn_bo,
225			unsigned size, unsigned domain)
226{
227	struct amdgpu_bo_alloc_request req = {0};
228	amdgpu_bo_handle buf_handle;
229	amdgpu_va_handle va_handle;
230	uint64_t va = 0;
231	int r;
232
233	req.alloc_size = ALIGN(size, 4096);
234	req.preferred_heap = domain;
235	r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
236	CU_ASSERT_EQUAL(r, 0);
237	r = amdgpu_va_range_alloc(device_handle,
238				  amdgpu_gpu_va_range_general,
239				  req.alloc_size, 1, 0, &va,
240				  &va_handle, 0);
241	CU_ASSERT_EQUAL(r, 0);
242	r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
243			    AMDGPU_VA_OP_MAP);
244	CU_ASSERT_EQUAL(r, 0);
245	vcn_bo->addr = va;
246	vcn_bo->handle = buf_handle;
247	vcn_bo->size = req.alloc_size;
248	vcn_bo->va_handle = va_handle;
249	r = amdgpu_bo_cpu_map(vcn_bo->handle, (void **)&vcn_bo->ptr);
250	CU_ASSERT_EQUAL(r, 0);
251	memset(vcn_bo->ptr, 0, size);
252	r = amdgpu_bo_cpu_unmap(vcn_bo->handle);
253	CU_ASSERT_EQUAL(r, 0);
254}
255
256static void free_resource(struct amdgpu_vcn_bo *vcn_bo)
257{
258	int r;
259
260	r = amdgpu_bo_va_op(vcn_bo->handle, 0, vcn_bo->size,
261			    vcn_bo->addr, 0, AMDGPU_VA_OP_UNMAP);
262	CU_ASSERT_EQUAL(r, 0);
263
264	r = amdgpu_va_range_free(vcn_bo->va_handle);
265	CU_ASSERT_EQUAL(r, 0);
266
267	r = amdgpu_bo_free(vcn_bo->handle);
268	CU_ASSERT_EQUAL(r, 0);
269	memset(vcn_bo, 0, sizeof(*vcn_bo));
270}
271
272static void vcn_dec_cmd(uint64_t addr, unsigned cmd, int *idx)
273{
274	ib_cpu[(*idx)++] = reg.data0;
275	ib_cpu[(*idx)++] = addr;
276	ib_cpu[(*idx)++] = reg.data1;
277	ib_cpu[(*idx)++] = addr >> 32;
278	ib_cpu[(*idx)++] = reg.cmd;
279	ib_cpu[(*idx)++] = cmd << 1;
280}
281
282static void amdgpu_cs_vcn_dec_create(void)
283{
284	struct amdgpu_vcn_bo msg_buf;
285	int len, r;
286
287	num_resources  = 0;
288	alloc_resource(&msg_buf, 4096, AMDGPU_GEM_DOMAIN_GTT);
289	resources[num_resources++] = msg_buf.handle;
290	resources[num_resources++] = ib_handle;
291
292	r = amdgpu_bo_cpu_map(msg_buf.handle, (void **)&msg_buf.ptr);
293	CU_ASSERT_EQUAL(r, 0);
294
295	memset(msg_buf.ptr, 0, 4096);
296	memcpy(msg_buf.ptr, vcn_dec_create_msg, sizeof(vcn_dec_create_msg));
297
298	len = 0;
299	ib_cpu[len++] = reg.data0;
300	ib_cpu[len++] = msg_buf.addr;
301	ib_cpu[len++] = reg.data1;
302	ib_cpu[len++] = msg_buf.addr >> 32;
303	ib_cpu[len++] = reg.cmd;
304	ib_cpu[len++] = 0;
305	for (; len % 16; ) {
306		ib_cpu[len++] = reg.nop;
307		ib_cpu[len++] = 0;
308	}
309
310	r = submit(len, AMDGPU_HW_IP_VCN_DEC);
311	CU_ASSERT_EQUAL(r, 0);
312
313	free_resource(&msg_buf);
314}
315
316static void amdgpu_cs_vcn_dec_decode(void)
317{
318	const unsigned dpb_size = 15923584, dt_size = 737280;
319	uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr, sum;
320	struct amdgpu_vcn_bo dec_buf;
321	int size, len, i, r;
322	uint8_t *dec;
323
324	size = 4*1024; /* msg */
325	size += 4*1024; /* fb */
326	size += 4096; /*it_scaling_table*/
327	size += ALIGN(sizeof(uvd_bitstream), 4*1024);
328	size += ALIGN(dpb_size, 4*1024);
329	size += ALIGN(dt_size, 4*1024);
330
331	num_resources  = 0;
332	alloc_resource(&dec_buf, size, AMDGPU_GEM_DOMAIN_GTT);
333	resources[num_resources++] = dec_buf.handle;
334	resources[num_resources++] = ib_handle;
335
336	r = amdgpu_bo_cpu_map(dec_buf.handle, (void **)&dec_buf.ptr);
337	dec = dec_buf.ptr;
338
339	CU_ASSERT_EQUAL(r, 0);
340	memset(dec_buf.ptr, 0, size);
341	memcpy(dec_buf.ptr, vcn_dec_decode_msg, sizeof(vcn_dec_decode_msg));
342	memcpy(dec_buf.ptr + sizeof(vcn_dec_decode_msg),
343			avc_decode_msg, sizeof(avc_decode_msg));
344
345	dec += 4*1024;
346	memcpy(dec, feedback_msg, sizeof(feedback_msg));
347	dec += 4*1024;
348	memcpy(dec, uvd_it_scaling_table, sizeof(uvd_it_scaling_table));
349
350	dec += 4*1024;
351	memcpy(dec, uvd_bitstream, sizeof(uvd_bitstream));
352
353	dec += ALIGN(sizeof(uvd_bitstream), 4*1024);
354
355	dec += ALIGN(dpb_size, 4*1024);
356
357	msg_addr = dec_buf.addr;
358	fb_addr = msg_addr + 4*1024;
359	it_addr = fb_addr + 4*1024;
360	bs_addr = it_addr + 4*1024;
361	dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024);
362	ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024);
363	dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024);
364
365	len = 0;
366	vcn_dec_cmd(msg_addr, 0x0, &len);
367	vcn_dec_cmd(dpb_addr, 0x1, &len);
368	vcn_dec_cmd(dt_addr, 0x2, &len);
369	vcn_dec_cmd(fb_addr, 0x3, &len);
370	vcn_dec_cmd(bs_addr, 0x100, &len);
371	vcn_dec_cmd(it_addr, 0x204, &len);
372	vcn_dec_cmd(ctx_addr, 0x206, &len);
373
374	ib_cpu[len++] = reg.cntl;
375	ib_cpu[len++] = 0x1;
376	for (; len % 16; ) {
377		ib_cpu[len++] = reg.nop;
378		ib_cpu[len++] = 0;
379	}
380
381	r = submit(len, AMDGPU_HW_IP_VCN_DEC);
382	CU_ASSERT_EQUAL(r, 0);
383
384	for (i = 0, sum = 0; i < dt_size; ++i)
385		sum += dec[i];
386
387	CU_ASSERT_EQUAL(sum, SUM_DECODE);
388
389	free_resource(&dec_buf);
390}
391
392static void amdgpu_cs_vcn_dec_destroy(void)
393{
394	struct amdgpu_vcn_bo msg_buf;
395	int len, r;
396
397	num_resources  = 0;
398	alloc_resource(&msg_buf, 1024, AMDGPU_GEM_DOMAIN_GTT);
399	resources[num_resources++] = msg_buf.handle;
400	resources[num_resources++] = ib_handle;
401
402	r = amdgpu_bo_cpu_map(msg_buf.handle, (void **)&msg_buf.ptr);
403	CU_ASSERT_EQUAL(r, 0);
404
405	memset(msg_buf.ptr, 0, 1024);
406	memcpy(msg_buf.ptr, vcn_dec_destroy_msg, sizeof(vcn_dec_destroy_msg));
407
408	len = 0;
409	ib_cpu[len++] = reg.data0;
410	ib_cpu[len++] = msg_buf.addr;
411	ib_cpu[len++] = reg.data1;
412	ib_cpu[len++] = msg_buf.addr >> 32;
413	ib_cpu[len++] = reg.cmd;
414	ib_cpu[len++] = 0;
415	for (; len % 16; ) {
416		ib_cpu[len++] = reg.nop;
417		ib_cpu[len++] = 0;
418	}
419
420	r = submit(len, AMDGPU_HW_IP_VCN_DEC);
421	CU_ASSERT_EQUAL(r, 0);
422
423	free_resource(&msg_buf);
424}
425
426static void amdgpu_cs_vcn_enc_create(void)
427{
428	/* TODO */
429}
430
431static void amdgpu_cs_vcn_enc_encode(void)
432{
433	/* TODO */
434}
435
436static void amdgpu_cs_vcn_enc_destroy(void)
437{
438	/* TODO */
439}
440