vm_tests.c revision 00a23bda
100a23bdaSmrg/* 200a23bdaSmrg * Copyright 2017 Advanced Micro Devices, Inc. 300a23bdaSmrg * 400a23bdaSmrg * Permission is hereby granted, free of charge, to any person obtaining a 500a23bdaSmrg * copy of this software and associated documentation files (the "Software"), 600a23bdaSmrg * to deal in the Software without restriction, including without limitation 700a23bdaSmrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 800a23bdaSmrg * and/or sell copies of the Software, and to permit persons to whom the 900a23bdaSmrg * Software is furnished to do so, subject to the following conditions: 1000a23bdaSmrg * 1100a23bdaSmrg * The above copyright notice and this permission notice shall be included in 1200a23bdaSmrg * all copies or substantial portions of the Software. 1300a23bdaSmrg * 1400a23bdaSmrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1500a23bdaSmrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1600a23bdaSmrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1700a23bdaSmrg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 1800a23bdaSmrg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 1900a23bdaSmrg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2000a23bdaSmrg * OTHER DEALINGS IN THE SOFTWARE. 2100a23bdaSmrg * 2200a23bdaSmrg*/ 2300a23bdaSmrg 2400a23bdaSmrg#ifdef HAVE_CONFIG_H 2500a23bdaSmrg#include "config.h" 2600a23bdaSmrg#endif 2700a23bdaSmrg 2800a23bdaSmrg#include "CUnit/Basic.h" 2900a23bdaSmrg 3000a23bdaSmrg#include "amdgpu_test.h" 3100a23bdaSmrg#include "amdgpu_drm.h" 3200a23bdaSmrg#include "amdgpu_internal.h" 3300a23bdaSmrg 3400a23bdaSmrgstatic amdgpu_device_handle device_handle; 3500a23bdaSmrgstatic uint32_t major_version; 3600a23bdaSmrgstatic uint32_t minor_version; 3700a23bdaSmrg 3800a23bdaSmrg 3900a23bdaSmrgstatic void amdgpu_vmid_reserve_test(void); 4000a23bdaSmrg 4100a23bdaSmrgCU_BOOL suite_vm_tests_enable(void) 4200a23bdaSmrg{ 4300a23bdaSmrg CU_BOOL enable = CU_TRUE; 4400a23bdaSmrg 4500a23bdaSmrg if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, 4600a23bdaSmrg &minor_version, &device_handle)) 4700a23bdaSmrg return CU_FALSE; 4800a23bdaSmrg 4900a23bdaSmrg if (device_handle->info.family_id == AMDGPU_FAMILY_SI) { 5000a23bdaSmrg printf("\n\nCurrently hangs the CP on this ASIC, VM suite disabled\n"); 5100a23bdaSmrg enable = CU_FALSE; 5200a23bdaSmrg } 5300a23bdaSmrg 5400a23bdaSmrg if (amdgpu_device_deinitialize(device_handle)) 5500a23bdaSmrg return CU_FALSE; 5600a23bdaSmrg 5700a23bdaSmrg return enable; 5800a23bdaSmrg} 5900a23bdaSmrg 6000a23bdaSmrgint suite_vm_tests_init(void) 6100a23bdaSmrg{ 6200a23bdaSmrg int r; 6300a23bdaSmrg 6400a23bdaSmrg r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, 6500a23bdaSmrg &minor_version, &device_handle); 6600a23bdaSmrg 6700a23bdaSmrg if (r) { 6800a23bdaSmrg if ((r == -EACCES) && (errno == EACCES)) 6900a23bdaSmrg printf("\n\nError:%s. " 7000a23bdaSmrg "Hint:Try to run this test program as root.", 7100a23bdaSmrg strerror(errno)); 7200a23bdaSmrg return CUE_SINIT_FAILED; 7300a23bdaSmrg } 7400a23bdaSmrg 7500a23bdaSmrg return CUE_SUCCESS; 7600a23bdaSmrg} 7700a23bdaSmrg 7800a23bdaSmrgint suite_vm_tests_clean(void) 7900a23bdaSmrg{ 8000a23bdaSmrg int r = amdgpu_device_deinitialize(device_handle); 8100a23bdaSmrg 8200a23bdaSmrg if (r == 0) 8300a23bdaSmrg return CUE_SUCCESS; 8400a23bdaSmrg else 8500a23bdaSmrg return CUE_SCLEAN_FAILED; 8600a23bdaSmrg} 8700a23bdaSmrg 8800a23bdaSmrg 8900a23bdaSmrgCU_TestInfo vm_tests[] = { 9000a23bdaSmrg { "resere vmid test", amdgpu_vmid_reserve_test }, 9100a23bdaSmrg CU_TEST_INFO_NULL, 9200a23bdaSmrg}; 9300a23bdaSmrg 9400a23bdaSmrgstatic void amdgpu_vmid_reserve_test(void) 9500a23bdaSmrg{ 9600a23bdaSmrg amdgpu_context_handle context_handle; 9700a23bdaSmrg amdgpu_bo_handle ib_result_handle; 9800a23bdaSmrg void *ib_result_cpu; 9900a23bdaSmrg uint64_t ib_result_mc_address; 10000a23bdaSmrg struct amdgpu_cs_request ibs_request; 10100a23bdaSmrg struct amdgpu_cs_ib_info ib_info; 10200a23bdaSmrg struct amdgpu_cs_fence fence_status; 10300a23bdaSmrg uint32_t expired, flags; 10400a23bdaSmrg int i, r; 10500a23bdaSmrg amdgpu_bo_list_handle bo_list; 10600a23bdaSmrg amdgpu_va_handle va_handle; 10700a23bdaSmrg static uint32_t *ptr; 10800a23bdaSmrg 10900a23bdaSmrg r = amdgpu_cs_ctx_create(device_handle, &context_handle); 11000a23bdaSmrg CU_ASSERT_EQUAL(r, 0); 11100a23bdaSmrg 11200a23bdaSmrg flags = 0; 11300a23bdaSmrg r = amdgpu_vm_reserve_vmid(device_handle, flags); 11400a23bdaSmrg CU_ASSERT_EQUAL(r, 0); 11500a23bdaSmrg 11600a23bdaSmrg 11700a23bdaSmrg r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, 11800a23bdaSmrg AMDGPU_GEM_DOMAIN_GTT, 0, 11900a23bdaSmrg &ib_result_handle, &ib_result_cpu, 12000a23bdaSmrg &ib_result_mc_address, &va_handle); 12100a23bdaSmrg CU_ASSERT_EQUAL(r, 0); 12200a23bdaSmrg 12300a23bdaSmrg r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, 12400a23bdaSmrg &bo_list); 12500a23bdaSmrg CU_ASSERT_EQUAL(r, 0); 12600a23bdaSmrg 12700a23bdaSmrg ptr = ib_result_cpu; 12800a23bdaSmrg 12900a23bdaSmrg for (i = 0; i < 16; ++i) 13000a23bdaSmrg ptr[i] = 0xffff1000; 13100a23bdaSmrg 13200a23bdaSmrg memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); 13300a23bdaSmrg ib_info.ib_mc_address = ib_result_mc_address; 13400a23bdaSmrg ib_info.size = 16; 13500a23bdaSmrg 13600a23bdaSmrg memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request)); 13700a23bdaSmrg ibs_request.ip_type = AMDGPU_HW_IP_GFX; 13800a23bdaSmrg ibs_request.ring = 0; 13900a23bdaSmrg ibs_request.number_of_ibs = 1; 14000a23bdaSmrg ibs_request.ibs = &ib_info; 14100a23bdaSmrg ibs_request.resources = bo_list; 14200a23bdaSmrg ibs_request.fence_info.handle = NULL; 14300a23bdaSmrg 14400a23bdaSmrg r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1); 14500a23bdaSmrg CU_ASSERT_EQUAL(r, 0); 14600a23bdaSmrg 14700a23bdaSmrg 14800a23bdaSmrg memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence)); 14900a23bdaSmrg fence_status.context = context_handle; 15000a23bdaSmrg fence_status.ip_type = AMDGPU_HW_IP_GFX; 15100a23bdaSmrg fence_status.ip_instance = 0; 15200a23bdaSmrg fence_status.ring = 0; 15300a23bdaSmrg fence_status.fence = ibs_request.seq_no; 15400a23bdaSmrg 15500a23bdaSmrg r = amdgpu_cs_query_fence_status(&fence_status, 15600a23bdaSmrg AMDGPU_TIMEOUT_INFINITE,0, &expired); 15700a23bdaSmrg CU_ASSERT_EQUAL(r, 0); 15800a23bdaSmrg 15900a23bdaSmrg r = amdgpu_bo_list_destroy(bo_list); 16000a23bdaSmrg CU_ASSERT_EQUAL(r, 0); 16100a23bdaSmrg 16200a23bdaSmrg r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, 16300a23bdaSmrg ib_result_mc_address, 4096); 16400a23bdaSmrg CU_ASSERT_EQUAL(r, 0); 16500a23bdaSmrg 16600a23bdaSmrg flags = 0; 16700a23bdaSmrg r = amdgpu_vm_unreserve_vmid(device_handle, flags); 16800a23bdaSmrg CU_ASSERT_EQUAL(r, 0); 16900a23bdaSmrg 17000a23bdaSmrg 17100a23bdaSmrg r = amdgpu_cs_ctx_free(context_handle); 17200a23bdaSmrg CU_ASSERT_EQUAL(r, 0); 17300a23bdaSmrg} 174