1/*
2 * Copyright © 2014 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24#ifndef VC4_QPU_DEFINES_H
25#define VC4_QPU_DEFINES_H
26
27enum qpu_op_add {
28        QPU_A_NOP,
29        QPU_A_FADD,
30        QPU_A_FSUB,
31        QPU_A_FMIN,
32        QPU_A_FMAX,
33        QPU_A_FMINABS,
34        QPU_A_FMAXABS,
35        QPU_A_FTOI,
36        QPU_A_ITOF,
37        QPU_A_ADD = 12,
38        QPU_A_SUB,
39        QPU_A_SHR,
40        QPU_A_ASR,
41        QPU_A_ROR,
42        QPU_A_SHL,
43        QPU_A_MIN,
44        QPU_A_MAX,
45        QPU_A_AND,
46        QPU_A_OR,
47        QPU_A_XOR,
48        QPU_A_NOT,
49        QPU_A_CLZ,
50        QPU_A_V8ADDS = 30,
51        QPU_A_V8SUBS = 31,
52};
53
54enum qpu_op_mul {
55        QPU_M_NOP,
56        QPU_M_FMUL,
57        QPU_M_MUL24,
58        QPU_M_V8MULD,
59        QPU_M_V8MIN,
60        QPU_M_V8MAX,
61        QPU_M_V8ADDS,
62        QPU_M_V8SUBS,
63};
64
65enum qpu_raddr {
66        QPU_R_FRAG_PAYLOAD_ZW = 15, /* W for A file, Z for B file */
67        /* 0-31 are the plain regfile a or b fields */
68        QPU_R_UNIF = 32,
69        QPU_R_VARY = 35,
70        QPU_R_ELEM_QPU = 38,
71        QPU_R_NOP,
72        QPU_R_XY_PIXEL_COORD = 41,
73        QPU_R_MS_REV_FLAGS = 42,
74        QPU_R_VPM = 48,
75        QPU_R_VPM_LD_BUSY,
76        QPU_R_VPM_LD_WAIT,
77        QPU_R_MUTEX_ACQUIRE,
78};
79
80enum qpu_waddr {
81        /* 0-31 are the plain regfile a or b fields */
82        QPU_W_ACC0 = 32, /* aka r0 */
83        QPU_W_ACC1,
84        QPU_W_ACC2,
85        QPU_W_ACC3,
86        QPU_W_TMU_NOSWAP,
87        QPU_W_ACC5,
88        QPU_W_HOST_INT,
89        QPU_W_NOP,
90        QPU_W_UNIFORMS_ADDRESS,
91        QPU_W_QUAD_XY, /* X for regfile a, Y for regfile b */
92        QPU_W_MS_FLAGS = 42,
93        QPU_W_REV_FLAG = 42,
94        QPU_W_TLB_STENCIL_SETUP = 43,
95        QPU_W_TLB_Z,
96        QPU_W_TLB_COLOR_MS,
97        QPU_W_TLB_COLOR_ALL,
98        QPU_W_TLB_ALPHA_MASK,
99        QPU_W_VPM,
100        QPU_W_VPMVCD_SETUP, /* LD for regfile a, ST for regfile b */
101        QPU_W_VPM_ADDR, /* LD for regfile a, ST for regfile b */
102        QPU_W_MUTEX_RELEASE,
103        QPU_W_SFU_RECIP,
104        QPU_W_SFU_RECIPSQRT,
105        QPU_W_SFU_EXP,
106        QPU_W_SFU_LOG,
107        QPU_W_TMU0_S,
108        QPU_W_TMU0_T,
109        QPU_W_TMU0_R,
110        QPU_W_TMU0_B,
111        QPU_W_TMU1_S,
112        QPU_W_TMU1_T,
113        QPU_W_TMU1_R,
114        QPU_W_TMU1_B,
115};
116
117enum qpu_sig_bits {
118        QPU_SIG_SW_BREAKPOINT,
119        QPU_SIG_NONE,
120        QPU_SIG_THREAD_SWITCH,
121        QPU_SIG_PROG_END,
122        QPU_SIG_WAIT_FOR_SCOREBOARD,
123        QPU_SIG_SCOREBOARD_UNLOCK,
124        QPU_SIG_LAST_THREAD_SWITCH,
125        QPU_SIG_COVERAGE_LOAD,
126        QPU_SIG_COLOR_LOAD,
127        QPU_SIG_COLOR_LOAD_END,
128        QPU_SIG_LOAD_TMU0,
129        QPU_SIG_LOAD_TMU1,
130        QPU_SIG_ALPHA_MASK_LOAD,
131        QPU_SIG_SMALL_IMM,
132        QPU_SIG_LOAD_IMM,
133        QPU_SIG_BRANCH
134};
135
136enum qpu_mux {
137        /* hardware mux values */
138        QPU_MUX_R0,
139        QPU_MUX_R1,
140        QPU_MUX_R2,
141        QPU_MUX_R3,
142        QPU_MUX_R4,
143        QPU_MUX_R5,
144        QPU_MUX_A,
145        QPU_MUX_B,
146
147        /**
148         * Non-hardware mux value, stores a small immediate field to be
149         * programmed into raddr_b in the qpu_reg.index.
150         */
151        QPU_MUX_SMALL_IMM,
152};
153
154enum qpu_cond {
155        QPU_COND_NEVER,
156        QPU_COND_ALWAYS,
157        QPU_COND_ZS,
158        QPU_COND_ZC,
159        QPU_COND_NS,
160        QPU_COND_NC,
161        QPU_COND_CS,
162        QPU_COND_CC,
163};
164
165enum qpu_pack_mul {
166        QPU_PACK_MUL_NOP,
167        QPU_PACK_MUL_8888 = 3, /* replicated to each 8 bits of the 32-bit dst. */
168        QPU_PACK_MUL_8A,
169        QPU_PACK_MUL_8B,
170        QPU_PACK_MUL_8C,
171        QPU_PACK_MUL_8D,
172};
173
174enum qpu_pack_a {
175        QPU_PACK_A_NOP,
176        /* convert to 16 bit float if float input, or to int16. */
177        QPU_PACK_A_16A,
178        QPU_PACK_A_16B,
179        /* replicated to each 8 bits of the 32-bit dst. */
180        QPU_PACK_A_8888,
181        /* Convert to 8-bit unsigned int. */
182        QPU_PACK_A_8A,
183        QPU_PACK_A_8B,
184        QPU_PACK_A_8C,
185        QPU_PACK_A_8D,
186
187        /* Saturating variants of the previous instructions. */
188        QPU_PACK_A_32_SAT, /* int-only */
189        QPU_PACK_A_16A_SAT, /* int or float */
190        QPU_PACK_A_16B_SAT,
191        QPU_PACK_A_8888_SAT,
192        QPU_PACK_A_8A_SAT,
193        QPU_PACK_A_8B_SAT,
194        QPU_PACK_A_8C_SAT,
195        QPU_PACK_A_8D_SAT,
196};
197
198enum qpu_unpack {
199        QPU_UNPACK_NOP,
200        QPU_UNPACK_16A,
201        QPU_UNPACK_16B,
202        QPU_UNPACK_8D_REP,
203        QPU_UNPACK_8A,
204        QPU_UNPACK_8B,
205        QPU_UNPACK_8C,
206        QPU_UNPACK_8D,
207};
208
209#define QPU_MASK(high, low) ((((uint64_t)1<<((high)-(low)+1))-1)<<(low))
210/* Using the GNU statement expression extension */
211#define QPU_SET_FIELD(value, field)                                       \
212        ({                                                                \
213                uint64_t fieldval = (uint64_t)(value) << field ## _SHIFT; \
214                assert((fieldval & ~ field ## _MASK) == 0);               \
215                fieldval & field ## _MASK;                                \
216         })
217
218#define QPU_GET_FIELD(word, field) ((uint32_t)(((word)  & field ## _MASK) >> field ## _SHIFT))
219
220#define QPU_UPDATE_FIELD(inst, value, field)                              \
221        (((inst) & ~(field ## _MASK)) | QPU_SET_FIELD(value, field))
222
223#define QPU_SIG_SHIFT                   60
224#define QPU_SIG_MASK                    QPU_MASK(63, 60)
225
226#define QPU_UNPACK_SHIFT                57
227#define QPU_UNPACK_MASK                 QPU_MASK(59, 57)
228
229/**
230 * If set, the pack field means PACK_MUL or R4 packing, instead of normal
231 * regfile a packing.
232 */
233#define QPU_PM                          ((uint64_t)1 << 56)
234
235#define QPU_PACK_SHIFT                  52
236#define QPU_PACK_MASK                   QPU_MASK(55, 52)
237
238#define QPU_COND_ADD_SHIFT              49
239#define QPU_COND_ADD_MASK               QPU_MASK(51, 49)
240#define QPU_COND_MUL_SHIFT              46
241#define QPU_COND_MUL_MASK               QPU_MASK(48, 46)
242
243#define QPU_SF                          ((uint64_t)1 << 45)
244
245#define QPU_WADDR_ADD_SHIFT             38
246#define QPU_WADDR_ADD_MASK              QPU_MASK(43, 38)
247#define QPU_WADDR_MUL_SHIFT             32
248#define QPU_WADDR_MUL_MASK              QPU_MASK(37, 32)
249
250#define QPU_OP_MUL_SHIFT                29
251#define QPU_OP_MUL_MASK                 QPU_MASK(31, 29)
252
253#define QPU_RADDR_A_SHIFT               18
254#define QPU_RADDR_A_MASK                QPU_MASK(23, 18)
255#define QPU_RADDR_B_SHIFT               12
256#define QPU_RADDR_B_MASK                QPU_MASK(17, 12)
257#define QPU_SMALL_IMM_SHIFT             12
258#define QPU_SMALL_IMM_MASK              QPU_MASK(17, 12)
259
260#define QPU_ADD_A_SHIFT                 9
261#define QPU_ADD_A_MASK                  QPU_MASK(11, 9)
262#define QPU_ADD_B_SHIFT                 6
263#define QPU_ADD_B_MASK                  QPU_MASK(8, 6)
264#define QPU_MUL_A_SHIFT                 3
265#define QPU_MUL_A_MASK                  QPU_MASK(5, 3)
266#define QPU_MUL_B_SHIFT                 0
267#define QPU_MUL_B_MASK                  QPU_MASK(2, 0)
268
269#define QPU_WS                          ((uint64_t)1 << 44)
270
271#define QPU_OP_ADD_SHIFT                24
272#define QPU_OP_ADD_MASK                 QPU_MASK(28, 24)
273
274#endif /* VC4_QPU_DEFINES_H */
275