ast_mode.c revision cf503b78
1/* 2 * Copyright (c) 2005 ASPEED Technology Inc. 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that 7 * copyright notice and this permission notice appear in supporting 8 * documentation, and that the name of the authors not be used in 9 * advertising or publicity pertaining to distribution of the software without 10 * specific, written prior permission. The authors makes no representations 11 * about the suitability of this software for any purpose. It is provided 12 * "as is" without express or implied warranty. 13 * 14 * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 20 * PERFORMANCE OF THIS SOFTWARE. 21 */ 22 23#ifdef HAVE_CONFIG_H 24#include <config.h> 25#endif 26#include "xf86.h" 27#include "xf86_OSproc.h" 28#include "xf86cmap.h" 29#include "compiler.h" 30#include "vgaHW.h" 31#include "mipointer.h" 32#include "micmap.h" 33 34#include "fb.h" 35#include "regionstr.h" 36#include "xf86xv.h" 37#include <X11/extensions/Xv.h> 38 39#include "xf86Pci.h" 40 41/* framebuffer offscreen manager */ 42#include "xf86fbman.h" 43 44/* include xaa includes */ 45#include "xaarop.h" 46 47/* H/W cursor support */ 48#include "xf86Cursor.h" 49 50/* usleep() */ 51#include <unistd.h> 52 53/* Driver specific headers */ 54#include "ast.h" 55#include "ast_mode.h" 56#include "ast_vgatool.h" 57 58static VBIOS_STDTABLE_STRUCT StdTable[] = { 59 /* MD_2_3_400 */ 60 { 61 0x67, 62 {0x00,0x03,0x00,0x02}, 63 {0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f, 64 0x00,0x4f,0x0d,0x0e,0x00,0x00,0x00,0x00, 65 0x9c,0x8e,0x8f,0x28,0x1f,0x96,0xb9,0xa3, 66 0xff}, 67 {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07, 68 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, 69 0x0c,0x00,0x0f,0x08}, 70 {0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x00, 71 0xff} 72 }, 73 /* Mode12/ExtEGATable */ 74 { 75 0xe3, 76 {0x01,0x0f,0x00,0x06}, 77 {0x5f,0x4f,0x50,0x82,0x55,0x81,0x0b,0x3e, 78 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, 79 0xe9,0x8b,0xdf,0x28,0x00,0xe7,0x04,0xe3, 80 0xff}, 81 {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07, 82 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, 83 0x01,0x00,0x0f,0x00}, 84 {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, 85 0xff} 86 }, 87 /* ExtVGATable */ 88 { 89 0x2f, 90 {0x01,0x0f,0x00,0x0e}, 91 {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, 92 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, 93 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, 94 0xff}, 95 {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, 96 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, 97 0x01,0x00,0x00,0x00}, 98 {0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0f, 99 0xff} 100 }, 101 /* ExtHiCTable */ 102 { 103 0x2f, 104 {0x01,0x0f,0x00,0x0e}, 105 {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, 106 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, 107 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, 108 0xff}, 109 {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, 110 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, 111 0x01,0x00,0x00,0x00}, 112 {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, 113 0xff} 114 }, 115 /* ExtTrueCTable */ 116 { 117 0x2f, 118 {0x01,0x0f,0x00,0x0e}, 119 {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, 120 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, 121 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, 122 0xff}, 123 {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, 124 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, 125 0x01,0x00,0x00,0x00}, 126 {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, 127 0xff} 128 }, 129}; 130 131static VBIOS_ENHTABLE_STRUCT Res640x480Table[] = { 132 { 800, 640, 8, 96, 525, 480, 2, 2, VCLK25_175, /* 60Hz */ 133 (SyncNN | HBorder | VBorder | Charx8Dot), 60, 1, 0x2E }, 134 { 832, 640, 16, 40, 520, 480, 1, 3, VCLK31_5, /* 72Hz */ 135 (SyncNN | HBorder | VBorder | Charx8Dot), 72, 2, 0x2E }, 136 { 840, 640, 16, 64, 500, 480, 1, 3, VCLK31_5, /* 75Hz */ 137 (SyncNN | Charx8Dot) , 75, 3, 0x2E }, 138 { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* 85Hz */ 139 (SyncNN | Charx8Dot) , 85, 4, 0x2E }, 140 { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* end */ 141 (SyncNN | Charx8Dot) , 0xFF, 4, 0x2E }, 142}; 143 144 145static VBIOS_ENHTABLE_STRUCT Res800x600Table[] = { 146 {1024, 800, 24, 72, 625, 600, 1, 2, VCLK36, /* 56Hz */ 147 (SyncPP | Charx8Dot), 56, 1, 0x30 }, 148 {1056, 800, 40, 128, 628, 600, 1, 4, VCLK40, /* 60Hz */ 149 (SyncPP | Charx8Dot), 60, 2, 0x30 }, 150 {1040, 800, 56, 120, 666, 600, 37, 6, VCLK50, /* 72Hz */ 151 (SyncPP | Charx8Dot), 72, 3, 0x30 }, 152 {1056, 800, 16, 80, 625, 600, 1, 3, VCLK49_5, /* 75Hz */ 153 (SyncPP | Charx8Dot), 75, 4, 0x30 }, 154 {1048, 800, 32, 64, 631, 600, 1, 3, VCLK56_25, /* 85Hz */ 155 (SyncPP | Charx8Dot), 84, 5, 0x30 }, 156 {1048, 800, 32, 64, 631, 600, 1, 3, VCLK56_25, /* end */ 157 (SyncPP | Charx8Dot), 0xFF, 5, 0x30 }, 158}; 159 160static VBIOS_ENHTABLE_STRUCT Res1024x768Table[] = { 161 {1344, 1024, 24, 136, 806, 768, 3, 6, VCLK65, /* 60Hz */ 162 (SyncNN | Charx8Dot), 60, 1, 0x31 }, 163 {1328, 1024, 24, 136, 806, 768, 3, 6, VCLK75, /* 70Hz */ 164 (SyncNN | Charx8Dot), 70, 2, 0x31 }, 165 {1312, 1024, 16, 96, 800, 768, 1, 3, VCLK78_75, /* 75Hz */ 166 (SyncPP | Charx8Dot), 75, 3, 0x31 }, 167 {1376, 1024, 48, 96, 808, 768, 1, 3, VCLK94_5, /* 85Hz */ 168 (SyncPP | Charx8Dot), 84, 4, 0x31 }, 169 {1376, 1024, 48, 96, 808, 768, 1, 3, VCLK94_5, /* end */ 170 (SyncPP | Charx8Dot), 0xFF, 4, 0x31 }, 171}; 172 173static VBIOS_ENHTABLE_STRUCT Res1280x1024Table[] = { 174 {1688, 1280, 48, 112, 1066, 1024, 1, 3, VCLK108, /* 60Hz */ 175 (SyncPP | Charx8Dot), 60, 1, 0x32 }, 176 {1688, 1280, 16, 144, 1066, 1024, 1, 3, VCLK135, /* 75Hz */ 177 (SyncPP | Charx8Dot), 75, 2, 0x32 }, 178 {1728, 1280, 64, 160, 1072, 1024, 1, 3, VCLK157_5, /* 85Hz */ 179 (SyncPP | Charx8Dot), 85, 3, 0x32 }, 180 {1728, 1280, 64, 160, 1072, 1024, 1, 3, VCLK157_5, /* end */ 181 (SyncPP | Charx8Dot), 0xFF, 3, 0x32 }, 182}; 183 184static VBIOS_ENHTABLE_STRUCT Res1600x1200Table[] = { 185 {2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162, /* 60Hz */ 186 (SyncPP | Charx8Dot), 60, 1, 0x33 }, 187 {2160, 1600, 64, 192, 1250, 1200, 1, 3, VCLK162, /* end */ 188 (SyncPP | Charx8Dot), 0xFF, 1, 0x33 }, 189}; 190 191/* 16:9 */ 192static VBIOS_ENHTABLE_STRUCT Res1360x768Table[] = { 193 {1792, 1360, 64,112, 795, 768, 3, 6, VCLK85_5, /* 60Hz */ 194 (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x39 }, 195 {1792, 1360, 64,112, 795, 768, 3, 6, VCLK85_5, /* end */ 196 (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x39 }, 197}; 198 199static VBIOS_ENHTABLE_STRUCT Res1600x900Table[] = { 200 {2112, 1600, 88,168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ 201 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x3A }, 202 {1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75, /* 60Hz CVT RB */ 203 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x3A }, 204 {1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75, /* end */ 205 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x3A }, 206}; 207 208static VBIOS_ENHTABLE_STRUCT Res1920x1080Table[] = { 209 {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* HDTV 60Hz */ 210 (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x38 }, 211 {2200, 1920, 88, 44, 1125, 1080, 4, 5, VCLK148_5, /* end */ 212 (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x38 }, 213}; 214 215/* 16:10 */ 216static VBIOS_ENHTABLE_STRUCT Res1280x800Table[] = { 217 {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz CVT */ 218 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x35 }, 219 {1440, 1280, 48, 32, 823, 800, 3, 6, VCLK71, /* 60Hz CVT RB */ 220 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 35 }, 221 {1440, 1280, 48, 32, 823, 800, 3, 6, VCLK71, /* 60Hz CVT RB */ 222 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 35 }, 223}; 224 225static VBIOS_ENHTABLE_STRUCT Res1440x900Table[] = { 226 {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz CVT */ 227 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x36 }, 228 {1600, 1440, 48, 32, 926, 900, 3, 6, VCLK88_75, /* 60Hz CVT RB */ 229 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x36 }, 230 {1600, 1440, 48, 32, 926, 900, 3, 6, VCLK88_75, /* 60Hz CVT RB */ 231 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x36 }, 232}; 233 234static VBIOS_ENHTABLE_STRUCT Res1680x1050Table[] = { 235 {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz CVT */ 236 (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x37 }, 237 {1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119, /* 60Hz CVT RB */ 238 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x37 }, 239 {1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119, /* 60Hz CVT RB */ 240 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x37 }, 241}; 242 243static VBIOS_ENHTABLE_STRUCT Res1920x1200Table[] = { 244 {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz */ 245 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x34 }, 246 {2080, 1920, 48, 32, 1235, 1200, 3, 6, VCLK154, /* 60Hz */ 247 (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x34 }, 248}; 249 250static VBIOS_DCLK_INFO DCLKTable [] = { 251 {0x2C, 0xE7, 0x03}, /* 00: VCLK25_175 */ 252 {0x95, 0x62, 0x03}, /* 01: VCLK28_322 */ 253 {0x67, 0x63, 0x01}, /* 02: VCLK31_5 */ 254 {0x76, 0x63, 0x01}, /* 03: VCLK36 */ 255 {0xEE, 0x67, 0x01}, /* 04: VCLK40 */ 256 {0x82, 0x62, 0x01}, /* 05: VCLK49_5 */ 257 {0xC6, 0x64, 0x01}, /* 06: VCLK50 */ 258 {0x94, 0x62, 0x01}, /* 07: VCLK56_25 */ 259 {0x80, 0x64, 0x00}, /* 08: VCLK65 */ 260 {0x7B, 0x63, 0x00}, /* 09: VCLK75 */ 261 {0x67, 0x62, 0x00}, /* 0A: VCLK78_75 */ 262 {0x7C, 0x62, 0x00}, /* 0B: VCLK94_5 */ 263 {0x8E, 0x62, 0x00}, /* 0C: VCLK108 */ 264 {0x85, 0x24, 0x00}, /* 0D: VCLK135 */ 265 {0x67, 0x22, 0x00}, /* 0E: VCLK157_5 */ 266 {0x6A, 0x22, 0x00}, /* 0F: VCLK162 */ 267 {0x4d, 0x4c, 0x80}, /* 10: VCLK154 */ 268 {0xa7, 0x78, 0x80}, /* 11: VCLK83.5 */ 269 {0x28, 0x49, 0x80}, /* 12: VCLK106.5 */ 270 {0x37, 0x49, 0x80}, /* 13: VCLK146.25 */ 271 {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */ 272 {0x47, 0x6c, 0x80}, /* 15: VCLK71 */ 273 {0x25, 0x65, 0x80}, /* 16: VCLK88.75 */ 274 {0x77, 0x58, 0x80}, /* 17: VCLK119 */ 275 {0x32, 0x67, 0x80}, /* 18: VCLK85_5 */ 276 {0x6a, 0x6d, 0x80}, /* 19: VCLK97_75 */ 277 {0x3b, 0x2c, 0x81}, /* 1A: VCLK118_25 */ 278}; 279 280static VBIOS_DCLK_INFO DCLKTable_AST2100 [] = { 281 {0x2C, 0xE7, 0x03}, /* 00: VCLK25_175 */ 282 {0x95, 0x62, 0x03}, /* 01: VCLK28_322 */ 283 {0x67, 0x63, 0x01}, /* 02: VCLK31_5 */ 284 {0x76, 0x63, 0x01}, /* 03: VCLK36 */ 285 {0xEE, 0x67, 0x01}, /* 04: VCLK40 */ 286 {0x82, 0x62, 0x01}, /* 05: VCLK49_5 */ 287 {0xC6, 0x64, 0x01}, /* 06: VCLK50 */ 288 {0x94, 0x62, 0x01}, /* 07: VCLK56_25 */ 289 {0x80, 0x64, 0x00}, /* 08: VCLK65 */ 290 {0x7B, 0x63, 0x00}, /* 09: VCLK75 */ 291 {0x67, 0x62, 0x00}, /* 0A: VCLK78_75 */ 292 {0x7C, 0x62, 0x00}, /* 0B: VCLK94_5 */ 293 {0x8E, 0x62, 0x00}, /* 0C: VCLK108 */ 294 {0x85, 0x24, 0x00}, /* 0D: VCLK135 */ 295 {0x67, 0x22, 0x00}, /* 0E: VCLK157_5 */ 296 {0x6A, 0x22, 0x00}, /* 0F: VCLK162 */ 297 {0x4d, 0x4c, 0x80}, /* 10: VCLK154 */ 298 {0x68, 0x6f, 0x80}, /* 11: VCLK83.5 */ 299 {0x28, 0x49, 0x80}, /* 12: VCLK106.5 */ 300 {0x37, 0x49, 0x80}, /* 13: VCLK146.25 */ 301 {0x1f, 0x45, 0x80}, /* 14: VCLK148.5 */ 302 {0x47, 0x6c, 0x80}, /* 15: VCLK71 */ 303 {0x25, 0x65, 0x80}, /* 16: VCLK88.75 */ 304 {0x77, 0x58, 0x80}, /* 17: VCLK119 */ 305 {0x32, 0x67, 0x80}, /* 18: VCLK85_5 */ 306 {0x6a, 0x6d, 0x80}, /* 19: VCLK97_75 */ 307 {0x3b, 0x2c, 0x81}, /* 1A: VCLK118_25 */ 308}; 309 310static VBIOS_DAC_INFO DAC_TEXT[] = { 311 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x2a }, { 0x00, 0x2a, 0x00 }, { 0x00, 0x2a, 0x2a }, 312 { 0x2a, 0x00, 0x00 }, { 0x2a, 0x00, 0x2a }, { 0x2a, 0x2a, 0x00 }, { 0x2a, 0x2a, 0x2a }, 313 { 0x00, 0x00, 0x15 }, { 0x00, 0x00, 0x3f }, { 0x00, 0x2a, 0x15 }, { 0x00, 0x2a, 0x3f }, 314 { 0x2a, 0x00, 0x15 }, { 0x2a, 0x00, 0x3f }, { 0x2a, 0x2a, 0x15 }, { 0x2a, 0x2a, 0x3f }, 315 { 0x00, 0x15, 0x00 }, { 0x00, 0x15, 0x2a }, { 0x00, 0x3f, 0x00 }, { 0x00, 0x3f, 0x2a }, 316 { 0x2a, 0x15, 0x00 }, { 0x2a, 0x15, 0x2a }, { 0x2a, 0x3f, 0x00 }, { 0x2a, 0x3f, 0x2a }, 317 { 0x00, 0x15, 0x15 }, { 0x00, 0x15, 0x3f }, { 0x00, 0x3f, 0x15 }, { 0x00, 0x3f, 0x3f }, 318 { 0x2a, 0x15, 0x15 }, { 0x2a, 0x15, 0x3f }, { 0x2a, 0x3f, 0x15 }, { 0x2a, 0x3f, 0x3f }, 319 { 0x15, 0x00, 0x00 }, { 0x15, 0x00, 0x2a }, { 0x15, 0x2a, 0x00 }, { 0x15, 0x2a, 0x2a }, 320 { 0x3f, 0x00, 0x00 }, { 0x3f, 0x00, 0x2a }, { 0x3f, 0x2a, 0x00 }, { 0x3f, 0x2a, 0x2a }, 321 { 0x15, 0x00, 0x15 }, { 0x15, 0x00, 0x3f }, { 0x15, 0x2a, 0x15 }, { 0x15, 0x2a, 0x3f }, 322 { 0x3f, 0x00, 0x15 }, { 0x3f, 0x00, 0x3f }, { 0x3f, 0x2a, 0x15 }, { 0x3f, 0x2a, 0x3f }, 323 { 0x15, 0x15, 0x00 }, { 0x15, 0x15, 0x2a }, { 0x15, 0x3f, 0x00 }, { 0x15, 0x3f, 0x2a }, 324 { 0x3f, 0x15, 0x00 }, { 0x3f, 0x15, 0x2a }, { 0x3f, 0x3f, 0x00 }, { 0x3f, 0x3f, 0x2a }, 325 { 0x15, 0x15, 0x15 }, { 0x15, 0x15, 0x3f }, { 0x15, 0x3f, 0x15 }, { 0x15, 0x3f, 0x3f }, 326 { 0x3f, 0x15, 0x15 }, { 0x3f, 0x15, 0x3f }, { 0x3f, 0x3f, 0x15 }, { 0x3f, 0x3f, 0x3f }, 327}; 328 329static VBIOS_DAC_INFO DAC_EGA[] = { 330 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x2a }, { 0x00, 0x2a, 0x00 }, { 0x00, 0x2a, 0x2a }, 331 { 0x2a, 0x00, 0x00 }, { 0x2a, 0x00, 0x2a }, { 0x2a, 0x2a, 0x00 }, { 0x2a, 0x2a, 0x2a }, 332 { 0x00, 0x00, 0x15 }, { 0x00, 0x00, 0x3f }, { 0x00, 0x2a, 0x15 }, { 0x00, 0x2a, 0x3f }, 333 { 0x2a, 0x00, 0x15 }, { 0x2a, 0x00, 0x3f }, { 0x2a, 0x2a, 0x15 }, { 0x2a, 0x2a, 0x3f }, 334 { 0x00, 0x15, 0x00 }, { 0x00, 0x15, 0x2a }, { 0x00, 0x3f, 0x00 }, { 0x00, 0x3f, 0x2a }, 335 { 0x2a, 0x15, 0x00 }, { 0x2a, 0x15, 0x2a }, { 0x2a, 0x3f, 0x00 }, { 0x2a, 0x3f, 0x2a }, 336 { 0x00, 0x15, 0x15 }, { 0x00, 0x15, 0x3f }, { 0x00, 0x3f, 0x15 }, { 0x00, 0x3f, 0x3f }, 337 { 0x2a, 0x15, 0x15 }, { 0x2a, 0x15, 0x3f }, { 0x2a, 0x3f, 0x15 }, { 0x2a, 0x3f, 0x3f }, 338 { 0x15, 0x00, 0x00 }, { 0x15, 0x00, 0x2a }, { 0x15, 0x2a, 0x00 }, { 0x15, 0x2a, 0x2a }, 339 { 0x3f, 0x00, 0x00 }, { 0x3f, 0x00, 0x2a }, { 0x3f, 0x2a, 0x00 }, { 0x3f, 0x2a, 0x2a }, 340 { 0x15, 0x00, 0x15 }, { 0x15, 0x00, 0x3f }, { 0x15, 0x2a, 0x15 }, { 0x15, 0x2a, 0x3f }, 341 { 0x3f, 0x00, 0x15 }, { 0x3f, 0x00, 0x3f }, { 0x3f, 0x2a, 0x15 }, { 0x3f, 0x2a, 0x3f }, 342 { 0x15, 0x15, 0x00 }, { 0x15, 0x15, 0x2a }, { 0x15, 0x3f, 0x00 }, { 0x15, 0x3f, 0x2a }, 343 { 0x3f, 0x15, 0x00 }, { 0x3f, 0x15, 0x2a }, { 0x3f, 0x3f, 0x00 }, { 0x3f, 0x3f, 0x2a }, 344 { 0x15, 0x15, 0x15 }, { 0x15, 0x15, 0x3f }, { 0x15, 0x3f, 0x15 }, { 0x15, 0x3f, 0x3f }, 345 { 0x3f, 0x15, 0x15 }, { 0x3f, 0x15, 0x3f }, { 0x3f, 0x3f, 0x15 }, { 0x3f, 0x3f, 0x3f }, 346}; 347 348static VBIOS_DAC_INFO DAC_VGA[] = { 349 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x2a }, { 0x00, 0x2a, 0x00 }, { 0x00, 0x2a, 0x2a }, 350 { 0x2a, 0x00, 0x00 }, { 0x2a, 0x00, 0x2a }, { 0x2a, 0x15, 0x00 }, { 0x2a, 0x2a, 0x2a }, 351 { 0x15, 0x15, 0x15 }, { 0x15, 0x15, 0x3f }, { 0x15, 0x3f, 0x15 }, { 0x15, 0x3f, 0x3f }, 352 { 0x3f, 0x15, 0x15 }, { 0x3f, 0x15, 0x3f }, { 0x3f, 0x3f, 0x15 }, { 0x3f, 0x3f, 0x3f }, 353 { 0x00, 0x00, 0x00 }, { 0x05, 0x05, 0x05 }, { 0x08, 0x08, 0x08 }, { 0x0b, 0x0b, 0x0b }, 354 { 0x0e, 0x0e, 0x0e }, { 0x11, 0x11, 0x11 }, { 0x14, 0x14, 0x14 }, { 0x18, 0x18, 0x18 }, 355 { 0x1c, 0x1c, 0x1c }, { 0x20, 0x20, 0x20 }, { 0x24, 0x24, 0x24 }, { 0x28, 0x28, 0x28 }, 356 { 0x2d, 0x2d, 0x2d }, { 0x32, 0x32, 0x32 }, { 0x38, 0x38, 0x38 }, { 0x3f, 0x3f, 0x3f }, 357 { 0x00, 0x00, 0x3f }, { 0x10, 0x00, 0x3f }, { 0x1f, 0x00, 0x3f }, { 0x2f, 0x00, 0x3f }, 358 { 0x3f, 0x00, 0x3f }, { 0x3f, 0x00, 0x2f }, { 0x3f, 0x00, 0x1f }, { 0x3f, 0x00, 0x10 }, 359 { 0x3f, 0x00, 0x00 }, { 0x3f, 0x10, 0x00 }, { 0x3f, 0x1f, 0x00 }, { 0x3f, 0x2f, 0x00 }, 360 { 0x3f, 0x3f, 0x00 }, { 0x2f, 0x3f, 0x00 }, { 0x1f, 0x3f, 0x00 }, { 0x10, 0x3f, 0x00 }, 361 { 0x00, 0x3f, 0x00 }, { 0x00, 0x3f, 0x10 }, { 0x00, 0x3f, 0x1f }, { 0x00, 0x3f, 0x2f }, 362 { 0x00, 0x3f, 0x3f }, { 0x00, 0x2f, 0x3f }, { 0x00, 0x1f, 0x3f }, { 0x00, 0x10, 0x3f }, 363 { 0x1f, 0x1f, 0x3f }, { 0x27, 0x1f, 0x3f }, { 0x2f, 0x1f, 0x3f }, { 0x37, 0x1f, 0x3f }, 364 { 0x3f, 0x1f, 0x3f }, { 0x3f, 0x1f, 0x37 }, { 0x3f, 0x1f, 0x2f }, { 0x3f, 0x1f, 0x27 }, 365 { 0x3f, 0x1f, 0x1f }, { 0x3f, 0x27, 0x1f }, { 0x3f, 0x2f, 0x1f }, { 0x3f, 0x37, 0x1f }, 366 { 0x3f, 0x3f, 0x1f }, { 0x37, 0x3f, 0x1f }, { 0x2f, 0x3f, 0x1f }, { 0x27, 0x3f, 0x1f }, 367 { 0x1f, 0x3f, 0x1f }, { 0x1f, 0x3f, 0x27 }, { 0x1f, 0x3f, 0x2f }, { 0x1f, 0x3f, 0x37 }, 368 { 0x1f, 0x3f, 0x3f }, { 0x1f, 0x37, 0x3f }, { 0x1f, 0x2f, 0x3f }, { 0x1f, 0x27, 0x3f }, 369 { 0x2d, 0x2d, 0x3f }, { 0x31, 0x2d, 0x3f }, { 0x36, 0x2d, 0x3f }, { 0x3a, 0x2d, 0x3f }, 370 { 0x3f, 0x2d, 0x3f }, { 0x3f, 0x2d, 0x3a }, { 0x3f, 0x2d, 0x36 }, { 0x3f, 0x2d, 0x31 }, 371 { 0x3f, 0x2d, 0x2d }, { 0x3f, 0x31, 0x2d }, { 0x3f, 0x36, 0x2d }, { 0x3f, 0x3a, 0x2d }, 372 { 0x3f, 0x3f, 0x2d }, { 0x3a, 0x3f, 0x2d }, { 0x36, 0x3f, 0x2d }, { 0x31, 0x3f, 0x2d }, 373 { 0x2d, 0x3f, 0x2d }, { 0x2d, 0x3f, 0x31 }, { 0x2d, 0x3f, 0x36 }, { 0x2d, 0x3f, 0x3a }, 374 { 0x2d, 0x3f, 0x3f }, { 0x2d, 0x3a, 0x3f }, { 0x2d, 0x36, 0x3f }, { 0x2d, 0x31, 0x3f }, 375 { 0x00, 0x00, 0x1c }, { 0x07, 0x00, 0x1c }, { 0x0e, 0x00, 0x1c }, { 0x15, 0x00, 0x1c }, 376 { 0x1c, 0x00, 0x1c }, { 0x1c, 0x00, 0x15 }, { 0x1c, 0x00, 0x0e }, { 0x1c, 0x00, 0x07 }, 377 { 0x1c, 0x00, 0x00 }, { 0x1c, 0x07, 0x00 }, { 0x1c, 0x0e, 0x00 }, { 0x1c, 0x15, 0x00 }, 378 { 0x1c, 0x1c, 0x00 }, { 0x15, 0x1c, 0x00 }, { 0x0e, 0x1c, 0x00 }, { 0x07, 0x1c, 0x00 }, 379 { 0x00, 0x1c, 0x00 }, { 0x00, 0x1c, 0x07 }, { 0x00, 0x1c, 0x0e }, { 0x00, 0x1c, 0x15 }, 380 { 0x00, 0x1c, 0x1c }, { 0x00, 0x15, 0x1c }, { 0x00, 0x0e, 0x1c }, { 0x00, 0x07, 0x1c }, 381 { 0x0e, 0x0e, 0x1c }, { 0x11, 0x0e, 0x1c }, { 0x15, 0x0e, 0x1c }, { 0x18, 0x0e, 0x1c }, 382 { 0x1c, 0x0e, 0x1c }, { 0x1c, 0x0e, 0x18 }, { 0x1c, 0x0e, 0x15 }, { 0x1c, 0x0e, 0x11 }, 383 { 0x1c, 0x0e, 0x0e }, { 0x1c, 0x11, 0x0e }, { 0x1c, 0x15, 0x0e }, { 0x1c, 0x18, 0x0e }, 384 { 0x1c, 0x1c, 0x0e }, { 0x18, 0x1c, 0x0e }, { 0x15, 0x1c, 0x0e }, { 0x11, 0x1c, 0x0e }, 385 { 0x0e, 0x1c, 0x0e }, { 0x0e, 0x1c, 0x11 }, { 0x0e, 0x1c, 0x15 }, { 0x0e, 0x1c, 0x18 }, 386 { 0x0e, 0x1c, 0x1c }, { 0x0e, 0x18, 0x1c }, { 0x0e, 0x15, 0x1c }, { 0x0e, 0x11, 0x1c }, 387 { 0x14, 0x14, 0x1c }, { 0x16, 0x14, 0x1c }, { 0x18, 0x14, 0x1c }, { 0x1a, 0x14, 0x1c }, 388 { 0x1c, 0x14, 0x1c }, { 0x1c, 0x14, 0x1a }, { 0x1c, 0x14, 0x18 }, { 0x1c, 0x14, 0x16 }, 389 { 0x1c, 0x14, 0x14 }, { 0x1c, 0x16, 0x14 }, { 0x1c, 0x18, 0x14 }, { 0x1c, 0x1a, 0x14 }, 390 { 0x1c, 0x1c, 0x14 }, { 0x1a, 0x1c, 0x14 }, { 0x18, 0x1c, 0x14 }, { 0x16, 0x1c, 0x14 }, 391 { 0x14, 0x1c, 0x14 }, { 0x14, 0x1c, 0x16 }, { 0x14, 0x1c, 0x18 }, { 0x14, 0x1c, 0x1a }, 392 { 0x14, 0x1c, 0x1c }, { 0x14, 0x1a, 0x1c }, { 0x14, 0x18, 0x1c }, { 0x14, 0x16, 0x1c }, 393 { 0x00, 0x00, 0x10 }, { 0x04, 0x00, 0x10 }, { 0x08, 0x00, 0x10 }, { 0x0c, 0x00, 0x10 }, 394 { 0x10, 0x00, 0x10 }, { 0x10, 0x00, 0x0c }, { 0x10, 0x00, 0x08 }, { 0x10, 0x00, 0x04 }, 395 { 0x10, 0x00, 0x00 }, { 0x10, 0x04, 0x00 }, { 0x10, 0x08, 0x00 }, { 0x10, 0x0c, 0x00 }, 396 { 0x10, 0x10, 0x00 }, { 0x0c, 0x10, 0x00 }, { 0x08, 0x10, 0x00 }, { 0x04, 0x10, 0x00 }, 397 { 0x00, 0x10, 0x00 }, { 0x00, 0x10, 0x04 }, { 0x00, 0x10, 0x08 }, { 0x00, 0x10, 0x0c }, 398 { 0x00, 0x10, 0x10 }, { 0x00, 0x0c, 0x10 }, { 0x00, 0x08, 0x10 }, { 0x00, 0x04, 0x10 }, 399 { 0x08, 0x08, 0x10 }, { 0x0a, 0x08, 0x10 }, { 0x0c, 0x08, 0x10 }, { 0x0e, 0x08, 0x10 }, 400 { 0x10, 0x08, 0x10 }, { 0x10, 0x08, 0x0e }, { 0x10, 0x08, 0x0c }, { 0x10, 0x08, 0x0a }, 401 { 0x10, 0x08, 0x08 }, { 0x10, 0x0a, 0x08 }, { 0x10, 0x0c, 0x08 }, { 0x10, 0x0e, 0x08 }, 402 { 0x10, 0x10, 0x08 }, { 0x0e, 0x10, 0x08 }, { 0x0c, 0x10, 0x08 }, { 0x0a, 0x10, 0x08 }, 403 { 0x08, 0x10, 0x08 }, { 0x08, 0x10, 0x0a }, { 0x08, 0x10, 0x0c }, { 0x08, 0x10, 0x0e }, 404 { 0x08, 0x10, 0x10 }, { 0x08, 0x0e, 0x10 }, { 0x08, 0x0c, 0x10 }, { 0x08, 0x0a, 0x10 }, 405 { 0x0b, 0x0b, 0x10 }, { 0x0c, 0x0b, 0x10 }, { 0x0d, 0x0b, 0x10 }, { 0x0f, 0x0b, 0x10 }, 406 { 0x10, 0x0b, 0x10 }, { 0x10, 0x0b, 0x0f }, { 0x10, 0x0b, 0x0d }, { 0x10, 0x0b, 0x0c }, 407 { 0x10, 0x0b, 0x0b }, { 0x10, 0x0c, 0x0b }, { 0x10, 0x0d, 0x0b }, { 0x10, 0x0f, 0x0b }, 408 { 0x10, 0x10, 0x0b }, { 0x0f, 0x10, 0x0b }, { 0x0d, 0x10, 0x0b }, { 0x0c, 0x10, 0x0b }, 409 { 0x0b, 0x10, 0x0b }, { 0x0b, 0x10, 0x0c }, { 0x0b, 0x10, 0x0d }, { 0x0b, 0x10, 0x0f }, 410 { 0x0b, 0x10, 0x10 }, { 0x0b, 0x0f, 0x10 }, { 0x0b, 0x0d, 0x10 }, { 0x0b, 0x0c, 0x10 }, 411 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, 412 { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, 413}; 414 415/* Prototype type declaration*/ 416static Bool bGetAST1000VGAModeInfo(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 417static void vSetStdReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 418static void vSetCRTCReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 419static void vSetOffsetReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 420static void vSetDCLKReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 421static void vSetExtReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 422static void vSetSyncReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 423static Bool bSetDACReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 424static BOOL bSetAST1180CRTCReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 425static BOOL bSetAST1180OffsetReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 426static BOOL bSetAST1180DCLKReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 427static BOOL bSetAST1180ExtReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 428static void vInitChrontelReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo); 429 430Bool 431ASTSetMode(ScrnInfoPtr pScrn, DisplayModePtr mode) 432{ 433 ASTRecPtr pAST; 434 VBIOS_MODE_INFO vgamodeinfo; 435 436 pAST = ASTPTR(pScrn); 437 438 /* pre set mode */ 439 bGetAST1000VGAModeInfo(pScrn, mode, &vgamodeinfo); 440 441 /* set mode */ 442 if (pAST->jChipType == AST1180) 443 { 444 bASTInitAST1180(pScrn); 445 446 bSetAST1180CRTCReg(pScrn, mode, &vgamodeinfo); 447 bSetAST1180OffsetReg(pScrn, mode, &vgamodeinfo); 448 bSetAST1180DCLKReg(pScrn, mode, &vgamodeinfo); 449 bSetAST1180ExtReg(pScrn, mode, &vgamodeinfo); 450 451 vInitChrontelReg(pScrn, mode, &vgamodeinfo); 452 } 453 else 454 { 455 vASTOpenKey(pScrn); 456 bASTRegInit(pScrn); 457 458 vAST1000DisplayOff(pScrn); 459 460 vSetStdReg(pScrn, mode, &vgamodeinfo); 461 vSetCRTCReg(pScrn, mode, &vgamodeinfo); 462 vSetOffsetReg(pScrn, mode, &vgamodeinfo); 463 vSetDCLKReg(pScrn, mode, &vgamodeinfo); 464 vSetExtReg(pScrn, mode, &vgamodeinfo); 465 vSetSyncReg(pScrn, mode, &vgamodeinfo); 466 bSetDACReg(pScrn, mode, &vgamodeinfo); 467 468 vAST1000DisplayOn(pScrn); 469 } 470 471 /* post set mode */ 472#ifdef Accel_2D 473 if (!pAST->noAccel) { 474 if (!bASTEnable2D(pScrn, pAST)) { 475 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Enable 2D failed\n"); 476 pAST->noAccel = TRUE; 477 } 478 } 479#endif 480#ifdef HWC 481 if (!pAST->noHWC) { 482 if (!bASTInitHWC(pScrn, pAST)) { 483 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Init HWC failed\n"); 484 pAST->noHWC = TRUE; 485 } 486 } 487#endif 488 489 return (TRUE); 490} 491 492 493static Bool bGetAST1000VGAModeInfo(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 494{ 495 ASTRecPtr pAST; 496 ULONG ulModeID, ulColorIndex, ulRefreshRate, ulRefreshRateIndex = 0; 497 ULONG ulHBorder, ulVBorder; 498 499 pAST = ASTPTR(pScrn); 500 501 switch (pScrn->bitsPerPixel) 502 { 503 case 8: 504 pVGAModeInfo->pStdTableEntry = (PVBIOS_STDTABLE_STRUCT) &StdTable[VGAModeIndex]; 505 ulColorIndex = VGAModeIndex-1; 506 break; 507 case 16: 508 pVGAModeInfo->pStdTableEntry = (PVBIOS_STDTABLE_STRUCT) &StdTable[HiCModeIndex]; 509 ulColorIndex = HiCModeIndex; 510 break; 511 case 24: 512 case 32: 513 pVGAModeInfo->pStdTableEntry = (PVBIOS_STDTABLE_STRUCT) &StdTable[TrueCModeIndex]; 514 ulColorIndex = TrueCModeIndex; 515 break; 516 default: 517 return (FALSE); 518 } 519 520 switch (mode->CrtcHDisplay) 521 { 522 case 640: 523 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res640x480Table[ulRefreshRateIndex]; 524 break; 525 case 800: 526 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res800x600Table[ulRefreshRateIndex]; 527 break; 528 case 1024: 529 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1024x768Table[ulRefreshRateIndex]; 530 break; 531 case 1280: 532 if (mode->CrtcVDisplay == 800) 533 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1280x800Table[ulRefreshRateIndex]; 534 else 535 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1280x1024Table[ulRefreshRateIndex]; 536 break; 537 case 1360: 538 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1360x768Table[ulRefreshRateIndex]; 539 break; 540 case 1440: 541 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1440x900Table[ulRefreshRateIndex]; 542 break; 543 case 1600: 544 if (mode->CrtcVDisplay == 900) 545 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1600x900Table[ulRefreshRateIndex]; 546 else 547 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1600x1200Table[ulRefreshRateIndex]; 548 break; 549 case 1680: 550 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1680x1050Table[ulRefreshRateIndex]; 551 break; 552 case 1920: 553 if (mode->CrtcVDisplay == 1080) 554 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1920x1080Table[ulRefreshRateIndex]; 555 else 556 pVGAModeInfo->pEnhTableEntry = (PVBIOS_ENHTABLE_STRUCT) &Res1920x1200Table[ulRefreshRateIndex]; 557 break; 558 default: 559 return (FALSE); 560 } 561 562 /* Get Proper Mode Index */ 563 if (pVGAModeInfo->pEnhTableEntry->Flags & WideScreenMode) 564 { 565 /* parsing for wide screen reduced blank mode */ 566 if ((mode->Flags & V_NVSYNC) && (mode->Flags & V_PHSYNC)) /* CVT RB */ 567 pVGAModeInfo->pEnhTableEntry++; 568 } 569 else 570 { 571 ulRefreshRate = (mode->Clock * 1000) / (mode->HTotal * mode->VTotal); 572 573 while (pVGAModeInfo->pEnhTableEntry->ulRefreshRate < ulRefreshRate) 574 { 575 pVGAModeInfo->pEnhTableEntry++; 576 if ((pVGAModeInfo->pEnhTableEntry->ulRefreshRate > ulRefreshRate) || 577 (pVGAModeInfo->pEnhTableEntry->ulRefreshRate == 0xFF)) 578 { 579 pVGAModeInfo->pEnhTableEntry--; 580 break; 581 } 582 } 583 } 584 585 /* Update mode CRTC info */ 586 ulHBorder = (pVGAModeInfo->pEnhTableEntry->Flags & HBorder) ? 8:0; 587 ulVBorder = (pVGAModeInfo->pEnhTableEntry->Flags & VBorder) ? 8:0; 588 589 mode->CrtcHTotal = (int) pVGAModeInfo->pEnhTableEntry->HT; 590 mode->CrtcHBlankStart = (int) (pVGAModeInfo->pEnhTableEntry->HDE + ulHBorder); 591 mode->CrtcHBlankEnd = (int) (pVGAModeInfo->pEnhTableEntry->HT - ulHBorder); 592 mode->CrtcHSyncStart = (int) (pVGAModeInfo->pEnhTableEntry->HDE + ulHBorder 593 + pVGAModeInfo->pEnhTableEntry->HFP); 594 mode->CrtcHSyncEnd = (int) (pVGAModeInfo->pEnhTableEntry->HDE + ulHBorder 595 + pVGAModeInfo->pEnhTableEntry->HFP 596 + pVGAModeInfo->pEnhTableEntry->HSYNC); 597 598 mode->CrtcVTotal = (int) pVGAModeInfo->pEnhTableEntry->VT; 599 mode->CrtcVBlankStart = (int) (pVGAModeInfo->pEnhTableEntry->VDE + ulVBorder); 600 mode->CrtcVBlankEnd = (int) (pVGAModeInfo->pEnhTableEntry->VT - ulVBorder); 601 mode->CrtcVSyncStart = (int) (pVGAModeInfo->pEnhTableEntry->VDE + ulVBorder 602 + pVGAModeInfo->pEnhTableEntry->VFP); 603 mode->CrtcVSyncEnd = (int) (pVGAModeInfo->pEnhTableEntry->VDE + ulVBorder 604 + pVGAModeInfo->pEnhTableEntry->VFP 605 + pVGAModeInfo->pEnhTableEntry->VSYNC); 606 607 /* Write mode info to scratch */ 608 ulRefreshRateIndex = pVGAModeInfo->pEnhTableEntry->ulRefreshRateIndex; 609 ulModeID = pVGAModeInfo->pEnhTableEntry->ulModeID; 610 611 if (pAST->jChipType == AST1180) 612 { 613 /* TODO */ 614 } 615 else 616 { 617 SetIndexReg(CRTC_PORT, 0x8C, (UCHAR) ((ulColorIndex & 0x0F) << 4)); 618 SetIndexReg(CRTC_PORT, 0x8D, (UCHAR) (ulRefreshRateIndex & 0xFF)); 619 SetIndexReg(CRTC_PORT, 0x8E, (UCHAR) (ulModeID & 0xFF)); 620 621 /* NewModeInfo */ 622 SetIndexReg(CRTC_PORT, 0x91, 0x00); /* clear signature */ 623 if (pVGAModeInfo->pEnhTableEntry->Flags & NewModeInfo) 624 { 625 SetIndexReg(CRTC_PORT, 0x91, 0xA8); /* signature */ 626 SetIndexReg(CRTC_PORT, 0x92, (UCHAR) (pScrn->bitsPerPixel) ); 627 SetIndexReg(CRTC_PORT, 0x93, (UCHAR) (mode->Clock / 1000) ); 628 SetIndexReg(CRTC_PORT, 0x94, (UCHAR) (mode->CrtcHDisplay) ); 629 SetIndexReg(CRTC_PORT, 0x95, (UCHAR) (mode->CrtcHDisplay >> 8) ); /* color depth */ 630 SetIndexReg(CRTC_PORT, 0x96, (UCHAR) (mode->CrtcVDisplay) ); 631 SetIndexReg(CRTC_PORT, 0x97, (UCHAR) (mode->CrtcVDisplay >> 8) ); /* color depth */ 632 } 633 } 634 635 return (TRUE); 636} 637 638static void vSetStdReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 639{ 640 641 PVBIOS_STDTABLE_STRUCT pStdModePtr; 642 ASTRecPtr pAST; 643 ULONG i; 644 UCHAR jReg; 645 646 pStdModePtr = pVGAModeInfo->pStdTableEntry; 647 pAST = ASTPTR(pScrn); 648 649 /* Set Misc */ 650 jReg = pStdModePtr->MISC; 651 SetReg(MISC_PORT_WRITE,jReg); 652 653 /* Set Seq */ 654 SetIndexReg(SEQ_PORT,0x00, 0x03); 655 for (i=0; i<4; i++) 656 { 657 jReg = pStdModePtr->SEQ[i]; 658 if (!i) (jReg |= 0x20); /* display off */ 659 SetIndexReg(SEQ_PORT,(UCHAR) (i+1), jReg); 660 } 661 662 /* Set CRTC */ 663 SetIndexRegMask(CRTC_PORT,0x11, 0x7F, 0x00); 664 for (i=0; i<25; i++) 665 { 666 jReg = pStdModePtr->CRTC[i]; 667 SetIndexReg(CRTC_PORT,(UCHAR) i, jReg); 668 } 669 670 /* Set AR */ 671 jReg = GetReg(INPUT_STATUS1_READ); 672 for (i=0; i<20; i++) 673 { 674 jReg = pStdModePtr->AR[i]; 675 SetReg(AR_PORT_WRITE, (UCHAR) i); 676 SetReg(AR_PORT_WRITE, jReg); 677 } 678 SetReg(AR_PORT_WRITE, 0x14); 679 SetReg(AR_PORT_WRITE, 0x00); 680 681 jReg = GetReg(INPUT_STATUS1_READ); 682 SetReg (AR_PORT_WRITE, 0x20); /* set POS */ 683 684 /* Set GR */ 685 for (i=0; i<9; i++) 686 { 687 jReg = pStdModePtr->GR[i]; 688 SetIndexReg(GR_PORT,(UCHAR) i, jReg); 689 690 } 691 692 693} 694 695static void 696vSetCRTCReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 697{ 698 ASTRecPtr pAST; 699 USHORT usTemp; 700 UCHAR jReg05, jReg07, jReg09, jRegAC, jRegAD, jRegAE; 701 702 pAST = ASTPTR(pScrn); 703 jReg05 = jReg07 = jReg09 = jRegAC = jRegAD = jRegAE = 0; 704 705 /* unlock CRTC */ 706 SetIndexRegMask(CRTC_PORT,0x11, 0x7F, 0x00); 707 708 /* Horizontal Timing Programming */ 709 usTemp = (mode->CrtcHTotal >> 3) - 5; 710 if (usTemp & 0x100) jRegAC |= 0x01; /* HT D[8] */ 711 SetIndexRegMask(CRTC_PORT,0x00, 0x00, (UCHAR) usTemp); 712 usTemp = (mode->CrtcHDisplay >> 3) - 1; 713 if (usTemp & 0x100) jRegAC |= 0x04; /* HDE D[8] */ 714 SetIndexRegMask(CRTC_PORT,0x01, 0x00, (UCHAR) usTemp); 715 usTemp = (mode->CrtcHBlankStart >> 3) - 1; 716 if (usTemp & 0x100) jRegAC |= 0x10; /* HBS D[8] */ 717 SetIndexRegMask(CRTC_PORT,0x02, 0x00, (UCHAR) usTemp); 718 usTemp = ((mode->CrtcHBlankEnd >> 3) - 1) & 0x7F; 719 if (usTemp & 0x20) jReg05 |= 0x80; /* HBE D[5] */ 720 if (usTemp & 0x40) jRegAD |= 0x01; /* HBE D[6] */ 721 SetIndexRegMask(CRTC_PORT,0x03, 0xE0, (UCHAR) (usTemp & 0x1F)); 722 usTemp = (mode->CrtcHSyncStart >> 3 ) - 1; 723 if (usTemp & 0x100) jRegAC |= 0x40; /* HRS D[5] */ 724 SetIndexRegMask(CRTC_PORT,0x04, 0x00, (UCHAR) (usTemp)); 725 usTemp = ((mode->CrtcHSyncEnd >> 3 ) - 1) & 0x3F; 726 if (usTemp & 0x20) jRegAD |= 0x04; /* HRE D[5] */ 727 SetIndexRegMask(CRTC_PORT,0x05, 0x60, (UCHAR) ((usTemp & 0x1F) | jReg05)); 728 729 SetIndexRegMask(CRTC_PORT,0xAC, 0x00, (UCHAR) jRegAC); 730 SetIndexRegMask(CRTC_PORT,0xAD, 0x00, (UCHAR) jRegAD); 731 732 /* Vetical Timing Programming */ 733 usTemp = (mode->CrtcVTotal) - 2; 734 if (usTemp & 0x100) jReg07 |= 0x01; /* VT D[8] */ 735 if (usTemp & 0x200) jReg07 |= 0x20; 736 if (usTemp & 0x400) jRegAE |= 0x01; /* VT D[10] */ 737 SetIndexRegMask(CRTC_PORT,0x06, 0x00, (UCHAR) usTemp); 738 usTemp = (mode->CrtcVSyncStart) - 1; 739 if (usTemp & 0x100) jReg07 |= 0x04; /* VRS D[8] */ 740 if (usTemp & 0x200) jReg07 |= 0x80; /* VRS D[9] */ 741 if (usTemp & 0x400) jRegAE |= 0x08; /* VRS D[10] */ 742 SetIndexRegMask(CRTC_PORT,0x10, 0x00, (UCHAR) usTemp); 743 usTemp = ((mode->CrtcVSyncEnd) - 1) & 0x3F; 744 if (usTemp & 0x10) jRegAE |= 0x20; /* VRE D[4] */ 745 if (usTemp & 0x20) jRegAE |= 0x40; /* VRE D[5] */ 746 SetIndexRegMask(CRTC_PORT,0x11, 0x70, (UCHAR) (usTemp & 0x0F)); 747 usTemp = (mode->CrtcVDisplay) - 1; 748 if (usTemp & 0x100) jReg07 |= 0x02; /* VDE D[8] */ 749 if (usTemp & 0x200) jReg07 |= 0x40; /* VDE D[9] */ 750 if (usTemp & 0x400) jRegAE |= 0x02; /* VDE D[10] */ 751 SetIndexRegMask(CRTC_PORT,0x12, 0x00, (UCHAR) usTemp); 752 usTemp = (mode->CrtcVBlankStart) - 1; 753 if (usTemp & 0x100) jReg07 |= 0x08; /* VBS D[8] */ 754 if (usTemp & 0x200) jReg09 |= 0x20; /* VBS D[9] */ 755 if (usTemp & 0x400) jRegAE |= 0x04; /* VBS D[10] */ 756 SetIndexRegMask(CRTC_PORT,0x15, 0x00, (UCHAR) usTemp); 757 usTemp = (mode->CrtcVBlankEnd) - 1 ; 758 if (usTemp & 0x100) jRegAE |= 0x10; /* VBE D[8] */ 759 SetIndexRegMask(CRTC_PORT,0x16, 0x00, (UCHAR) usTemp); 760 761 SetIndexRegMask(CRTC_PORT,0x07, 0x00, (UCHAR) jReg07); 762 SetIndexRegMask(CRTC_PORT,0x09, 0xDF, (UCHAR) jReg09); 763 SetIndexRegMask(CRTC_PORT,0xAE, 0x00, (UCHAR) (jRegAE | 0x80)); /* disable line compare */ 764 765 /* lock CRTC */ 766 SetIndexRegMask(CRTC_PORT,0x11, 0x7F, 0x80); 767 768} 769 770static void vSetOffsetReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 771{ 772 ASTRecPtr pAST; 773 USHORT usOffset; 774 775 pAST = ASTPTR(pScrn); 776 777 usOffset = pAST->VideoModeInfo.ScreenPitch >> 3; /* Unit: char */ 778 779 SetIndexReg(CRTC_PORT,0x13, (UCHAR) (usOffset & 0xFF)); 780 SetIndexReg(CRTC_PORT,0xB0, (UCHAR) ((usOffset >> 8) & 0x3F)); 781 782} 783 784static void vSetDCLKReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 785{ 786 PVBIOS_ENHTABLE_STRUCT pEnhModePtr; 787 PVBIOS_DCLK_INFO pDCLKPtr; 788 ASTRecPtr pAST; 789 790 pAST = ASTPTR(pScrn); 791 792 pEnhModePtr = pVGAModeInfo->pEnhTableEntry; 793 if ((pAST->jChipType == AST2100) || (pAST->jChipType == AST1100) || (pAST->jChipType == AST2200) || (pAST->jChipType == AST2150) || (pAST->jChipType == AST2300) || (pAST->jChipType == AST2400)) 794 pDCLKPtr = &DCLKTable_AST2100[pEnhModePtr->DCLKIndex]; 795 else 796 pDCLKPtr = &DCLKTable[pEnhModePtr->DCLKIndex]; 797 798 SetIndexRegMask(CRTC_PORT,0xC0, 0x00, pDCLKPtr->Param1); 799 SetIndexRegMask(CRTC_PORT,0xC1, 0x00, pDCLKPtr->Param2); 800 SetIndexRegMask(CRTC_PORT,0xBB, 0x0F, (pDCLKPtr->Param3 & 0x80) | ((pDCLKPtr->Param3 & 0x03) << 4) ); 801 802} 803 804 805static void vSetExtReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 806{ 807 808 ASTRecPtr pAST; 809 UCHAR jRegA0, jRegA3, jRegA8; 810 811 pAST = ASTPTR(pScrn); 812 813 jRegA0=jRegA3=jRegA8=0; 814 /* Mode Type Setting */ 815 switch (pScrn->bitsPerPixel) { 816 case 8: 817 jRegA0 = 0x70; 818 jRegA3 = 0x01; 819 jRegA8 = 0x00; 820 break; 821 case 15: 822 case 16: 823 jRegA0 = 0x70; 824 jRegA3 = 0x04; 825 jRegA8 = 0x02; 826 break; 827 case 32: 828 jRegA0 = 0x70; 829 jRegA3 = 0x08; 830 jRegA8 = 0x02; 831 break; 832 } 833 SetIndexRegMask(CRTC_PORT,0xA0, 0x8F, (UCHAR) jRegA0); 834 SetIndexRegMask(CRTC_PORT,0xA3, 0xF0, (UCHAR) jRegA3); 835 SetIndexRegMask(CRTC_PORT,0xA8, 0xFD, (UCHAR) jRegA8); 836 837#if defined(__sparc__) 838 UCHAR jRegA2 = 0x80; 839 if ((pScrn->bitsPerPixel == 15) || (pScrn->bitsPerPixel == 16) ) 840 jRegA2 |= 0x40; 841 SetIndexRegMask(CRTC_PORT,0xA2, 0x3F, (UCHAR) jRegA2); 842#endif 843 844 /* Set Threshold */ 845 if ((pAST->jChipType == AST2300) || (pAST->jChipType == AST2400)) 846 { 847 SetIndexReg(CRTC_PORT,0xA7, 0x78); 848 SetIndexReg(CRTC_PORT,0xA6, 0x60); 849 } 850 else if ((pAST->jChipType == AST2100) || (pAST->jChipType == AST1100) || (pAST->jChipType == AST2200) || (pAST->jChipType == AST2150) ) 851 { 852 SetIndexReg(CRTC_PORT,0xA7, 0x3F); 853 SetIndexReg(CRTC_PORT,0xA6, 0x2F); 854 } 855 else 856 { 857 SetIndexReg(CRTC_PORT,0xA7, 0x2F); 858 SetIndexReg(CRTC_PORT,0xA6, 0x1F); 859 } 860 861} 862 863static void vSetSyncReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 864{ 865 PVBIOS_ENHTABLE_STRUCT pEnhModePtr; 866 ASTRecPtr pAST; 867 UCHAR jReg; 868 869 pAST = ASTPTR(pScrn); 870 pEnhModePtr = pVGAModeInfo->pEnhTableEntry; 871 872 jReg = GetReg(MISC_PORT_READ); 873 jReg |= (UCHAR) (pEnhModePtr->Flags & SyncNN); 874 SetReg(MISC_PORT_WRITE,jReg); 875 876} 877 878static Bool bSetDACReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 879{ 880 PVBIOS_DAC_INFO pDACPtr; 881 ASTRecPtr pAST; 882 ULONG i, ulDACNumber; 883 UCHAR DACR, DACG, DACB; 884 885 pAST = ASTPTR(pScrn); 886 887 switch (pScrn->bitsPerPixel) 888 { 889 case 8: 890 ulDACNumber = DAC_NUM_VGA; 891 pDACPtr = (PVBIOS_DAC_INFO) &DAC_VGA[0]; 892 break; 893 default: 894 return (FALSE); 895 } 896 897 for (i=0; i<ulDACNumber; i++) 898 { 899 DACR = pDACPtr->DACR; 900 DACG = pDACPtr->DACG; 901 DACB = pDACPtr->DACB; 902 903 VGA_LOAD_PALETTE_INDEX (i, DACR, DACG, DACB); 904 905 pDACPtr++; 906 } 907 908 return (TRUE); 909 910} 911 912static ULONG AST1180DCLKTable [] = { 913 0x0008676b, /* 00: VCLK25_175 */ 914 0x00086342, /* 01: VCLK28_322 */ 915 0x00086568, /* 02: VCLK31_5 */ 916 0x00082118, /* 03: VCLK36 */ 917 0x0008232e, /* 04: VCLK40 */ 918 0x000c256d, /* 05: VCLK49_5 */ 919 0x00082016, /* 06: VCLK50 */ 920 0x000c0010, /* 07: VCLK56_25 */ 921 0x000c0332, /* 08: VCLK65 */ 922 0x00080010, /* 09: VCLK75 */ 923 0x000c033d, /* 0A: VCLK78_75 */ 924 0x000c0568, /* 0B: VCLK94_5 */ 925 0x00040118, /* 0C: VCLK108 */ 926 0x00040334, /* 0D: VCLK135 */ 927 0x0004033d, /* 0E: VCLK157_5 */ 928 0x00040018, /* 0F: VCLK162 */ 929 0x00040123, /* 10: VCLK154 */ 930 0x000c0669, /* 11: VCLK83_5 */ 931 0x0004074b, /* 12: VCLK106_5 */ 932 0x0004022d, /* 13: VCLK146_25 */ 933 0x00040769, /* 14: VCLK148_5 */ 934}; 935 936static BOOL bSetAST1180CRTCReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 937{ 938 ASTRecPtr pAST = ASTPTR(pScrn); 939 940 ULONG HTIndex, HRIndex, VTIndex, VRIndex; 941 ULONG HT, HDE, HBS, HBE, HRS, HRE; 942 ULONG VT, VDE, VBS, VBE, VRS, VRE; 943 ULONG HT2, HDE2, HRS2, HRE2; 944 ULONG VT2, VDE2, VRS2, VRE2; 945 946 /* Reg. Index Select */ 947 { 948 HTIndex = AST1180_VGA1_HTREG; 949 HRIndex = AST1180_VGA1_HRREG; 950 VTIndex = AST1180_VGA1_VTREG; 951 VRIndex = AST1180_VGA1_VRREG; 952 } 953 954 /* Get CRTC Info */ 955 HT = mode->CrtcHTotal; 956 HDE= mode->CrtcHDisplay; 957 HBS= mode->CrtcHBlankStart; 958 HBE= mode->CrtcHBlankEnd; 959 HRS= mode->CrtcHSyncStart; 960 HRE= mode->CrtcHSyncEnd; 961 VT = mode->CrtcVTotal; 962 VDE= mode->CrtcVDisplay; 963 VBS= mode->CrtcVBlankStart; 964 VBE= mode->CrtcVBlankEnd; 965 VRS= mode->CrtcVSyncStart; 966 VRE= mode->CrtcVSyncEnd; 967 968 /* Calculate CRTC Reg Setting */ 969 HT2 = HT - 1; 970 HDE2 = HDE - 1; 971 HRS2 = HRS - 1; 972 HRE2 = HRE - 1; 973 VT2 = VT - 1; 974 VDE2 = VDE - 1; 975 VRS2 = VRS - 1; 976 VRE2 = VRE - 1; 977 978 /* Write Reg */ 979 WriteAST1180SOC(AST1180_GFX_BASE + HTIndex, (ULONG)(HDE2 << 16) | (ULONG) (HT2)); 980 WriteAST1180SOC(AST1180_GFX_BASE + HRIndex, (ULONG)(HRE2 << 16) | (ULONG) (HRS2)); 981 WriteAST1180SOC(AST1180_GFX_BASE + VTIndex, (ULONG)(VDE2 << 16) | (ULONG) (VT2)); 982 WriteAST1180SOC(AST1180_GFX_BASE + VRIndex, (ULONG)(VRE2 << 16) | (ULONG) (VRS2)); 983 984 return (TRUE); 985 986} /* bSetAST1180CRTCReg */ 987 988static BOOL bSetAST1180OffsetReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 989{ 990 ASTRecPtr pAST = ASTPTR(pScrn); 991 ULONG ulOffset, ulTermalCount; 992 993 ulOffset = pAST->VideoModeInfo.ScreenPitch; 994 ulTermalCount = (pAST->VideoModeInfo.ScreenPitch + 7) >> 3; 995 996 /* Write Reg */ 997 WriteAST1180SOC(AST1180_GFX_BASE + AST1180_VGA1_OFFSET, (ULONG) (ulTermalCount << 16) | (ULONG) (ulOffset)); 998 999 return (TRUE); 1000 1001} /* bSetAST1180OffsetReg */ 1002 1003static BOOL bSetAST1180DCLKReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 1004{ 1005 PVBIOS_ENHTABLE_STRUCT pEnhModePtr; 1006 ASTRecPtr pAST = ASTPTR(pScrn); 1007 ULONG ulDCLK; 1008 1009 pEnhModePtr = pVGAModeInfo->pEnhTableEntry; 1010 ulDCLK = AST1180DCLKTable[pEnhModePtr->DCLKIndex]; 1011 if (pEnhModePtr->Flags & HalfDCLK) 1012 ulDCLK |= 0x00400000; /* D[22]: div by 2 */ 1013 WriteAST1180SOC(AST1180_GFX_BASE + AST1180_VGA1_PLL, ulDCLK); 1014 1015 return (TRUE); 1016} 1017 1018static BOOL bSetAST1180ExtReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 1019{ 1020 PVBIOS_ENHTABLE_STRUCT pEnhModePtr; 1021 ASTRecPtr pAST = ASTPTR(pScrn); 1022 1023 ULONG ulCtlRegIndex, ulCtlReg; /* enable display */ 1024 ULONG ulCtlReg2Index, ulCtlReg2 = 0x80; /* single edge */ 1025 ULONG ulThresholdRegIndex ; /* Threshold */ 1026 ULONG ulStartAddressIndex; /* ulStartAddress */ 1027 ULONG ulStartAddress = pAST->ulVRAMBase; 1028 1029 /* Reg. Index Select */ 1030 { 1031 ulCtlRegIndex = AST1180_VGA1_CTRL; 1032 ulCtlReg2Index = AST1180_VGA1_CTRL2; 1033 ulThresholdRegIndex = AST1180_VGA1_THRESHOLD; 1034 ulStartAddressIndex = AST1180_VGA1_STARTADDR; 1035 } 1036 1037 /* Mode Type Setting */ 1038 ulCtlReg = 0x30000000; 1039 { 1040 switch (pScrn->bitsPerPixel) { 1041 case 15: 1042 case 16: 1043 ulCtlReg |= 0x100001; /* RGB565, SCREEN OFF, ENABLE */ 1044 break; 1045 case 32: 1046 ulCtlReg |= 0x100101; /* XRGB8888, SCREEN OFF, ENABLE */ 1047 break; 1048 } 1049 } 1050 1051 /* Polarity */ 1052 pEnhModePtr = pVGAModeInfo->pEnhTableEntry; 1053 ulCtlReg |= (ULONG) (pEnhModePtr->Flags & SyncNN) << 10; 1054 1055 /* Single/Dual Edge */ 1056 ulCtlReg2 |= 0x40; /* dual-edge */ 1057 1058 /* Write Reg */ 1059 WriteAST1180SOC(AST1180_GFX_BASE + ulStartAddressIndex, ulStartAddress); 1060 WriteAST1180SOC(AST1180_GFX_BASE + ulThresholdRegIndex, ((ULONG) CRT_HIGH_THRESHOLD_VALUE << 8) | (ULONG) (CRT_LOW_THRESHOLD_VALUE)); 1061 WriteAST1180SOC(AST1180_GFX_BASE + ulCtlReg2Index, ulCtlReg2); 1062 WriteAST1180SOC(AST1180_GFX_BASE + ulCtlRegIndex, ulCtlReg); 1063 1064 return (TRUE); 1065 1066} /* bSetAST1180ExtReg */ 1067 1068#define I2C_BASE_AST1180 0x80fcb000 1069#define I2C_DEVICEADDR_AST1180 0x0EC /* slave addr */ 1070 1071static void SetChrontelReg(ASTRecPtr pAST, UCHAR jChannel, UCHAR jIndex, UCHAR jData ) 1072{ 1073 ULONG ulData, ulI2CAddr, ulI2CPortBase; 1074 ULONG retry; 1075 1076 { 1077 ulI2CPortBase = I2C_BASE_AST1180 + 0x40 * jChannel; 1078 ulI2CAddr = I2C_DEVICEADDR_AST1180; 1079 } 1080 1081 WriteAST1180SOC(ulI2CPortBase + 0x00, 0x00); 1082 WriteAST1180SOC(ulI2CPortBase + 0x04, 0x77743355); 1083 WriteAST1180SOC(ulI2CPortBase + 0x08, 0x0); 1084 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1085 WriteAST1180SOC(ulI2CPortBase + 0x00, 0x1); 1086 WriteAST1180SOC(ulI2CPortBase + 0x0C, 0xAF); 1087 WriteAST1180SOC(ulI2CPortBase + 0x20, ulI2CAddr); 1088 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x03); 1089 retry = 0; 1090 do { 1091 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1092 usleep(10); 1093 if (retry++ > 1000) 1094 goto Exit_SetChrontelReg; 1095 } while (!(ulData & 0x01)); 1096 1097 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1098 WriteAST1180SOC(ulI2CPortBase + 0x20, (ULONG) jIndex); 1099 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x02); 1100 do { 1101 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1102 } while (!(ulData & 0x01)); 1103 1104 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1105 WriteAST1180SOC(ulI2CPortBase + 0x20, (ULONG) jData); 1106 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x02); 1107 do { 1108 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1109 } while (!(ulData & 0x01)); 1110 1111 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1112 WriteAST1180SOC(ulI2CPortBase + 0x0C, 0xBF); 1113 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x20); 1114 do { 1115 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1116 } while (!(ulData & 0x10)); 1117 1118 ReadAST1180SOC(ulI2CPortBase + 0x0C, ulData); 1119 ulData &= 0xffffffef; 1120 WriteAST1180SOC(ulI2CPortBase + 0x0C, ulData); 1121 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1122 1123Exit_SetChrontelReg: 1124 ; 1125} 1126 1127static UCHAR GetChrontelReg(ASTRecPtr pAST, UCHAR jChannel, UCHAR jIndex) 1128{ 1129 ULONG ulData, ulI2CAddr, ulI2CPortBase; 1130 UCHAR jData; 1131 ULONG retry; 1132 1133 { 1134 ulI2CPortBase = I2C_BASE_AST1180 + 0x40 * jChannel; 1135 ulI2CAddr = I2C_DEVICEADDR_AST1180; 1136 } 1137 1138 WriteAST1180SOC(ulI2CPortBase + 0x00, 0x00); 1139 WriteAST1180SOC(ulI2CPortBase + 0x04, 0x77743355); 1140 WriteAST1180SOC(ulI2CPortBase + 0x08, 0x0); 1141 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1142 WriteAST1180SOC(ulI2CPortBase + 0x00, 0x1); 1143 WriteAST1180SOC(ulI2CPortBase + 0x0C, 0xAF); 1144 WriteAST1180SOC(ulI2CPortBase + 0x20, ulI2CAddr); 1145 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x03); 1146 retry = 0; 1147 do { 1148 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1149 usleep(10); 1150 if (retry++ > 1000) 1151 return 0; 1152 } while (!(ulData & 0x01)); 1153 1154 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1155 WriteAST1180SOC(ulI2CPortBase + 0x20, (ULONG) jIndex); 1156 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x02); 1157 do { 1158 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1159 } while (!(ulData & 0x01)); 1160 1161 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1162 WriteAST1180SOC(ulI2CPortBase + 0x20, (ULONG) (ulI2CAddr + 1) ); 1163 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x1B); 1164 do { 1165 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1166 } while (!(ulData & 0x04)); 1167 1168 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1169 WriteAST1180SOC(ulI2CPortBase + 0x0C, 0xBF); 1170 WriteAST1180SOC(ulI2CPortBase + 0x14, 0x20); 1171 do { 1172 ReadAST1180SOC(ulI2CPortBase + 0x10, ulData); 1173 } while (!(ulData & 0x10)); 1174 1175 ReadAST1180SOC(ulI2CPortBase + 0x0C, ulData); 1176 ulData &= 0xffffffef; 1177 WriteAST1180SOC(ulI2CPortBase + 0x0C, ulData); 1178 WriteAST1180SOC(ulI2CPortBase + 0x10, 0xffffffff); 1179 1180 ReadAST1180SOC(ulI2CPortBase + 0x20, ulData); 1181 jData = (UCHAR) ((ulData & 0xFF00) >> 8); 1182 1183 return (jData); 1184} 1185 1186static void vInitChrontelReg(ScrnInfoPtr pScrn, DisplayModePtr mode, PVBIOS_MODE_INFO pVGAModeInfo) 1187{ 1188 1189 PVBIOS_ENHTABLE_STRUCT pEnhModePtr = pVGAModeInfo->pEnhTableEntry; 1190 ASTRecPtr pAST = ASTPTR(pScrn); 1191 ULONG ulDCLK = 65; /* todo */ 1192 UCHAR jReg; 1193 1194 jReg = GetChrontelReg(pAST, 1, 0x4A); /* get vendor id */ 1195 if (jReg == 0x95) 1196 { 1197 jReg = GetChrontelReg(pAST, 1, 0x20); /* DVI/D-Sub */ 1198 if (jReg & 0x20) /* DVI */ 1199 { 1200 1201 /* DVI PLL Filter */ 1202 if (ulDCLK > 65) 1203 { 1204 SetChrontelReg(pAST, 1, 0x33, 0x06); 1205 SetChrontelReg(pAST, 1, 0x34, 0x26); 1206 SetChrontelReg(pAST, 1, 0x36, 0xA0); 1207 } 1208 else 1209 { 1210 SetChrontelReg(pAST, 1, 0x33, 0x08); 1211 SetChrontelReg(pAST, 1, 0x34, 0x16); 1212 SetChrontelReg(pAST, 1, 0x36, 0x60); 1213 } 1214 1215 SetChrontelReg(pAST, 1, 0x49, 0xc0); 1216 } 1217 else /* D-Sub */ 1218 { 1219 1220 SetChrontelReg(pAST, 1, 0x21, 0x09); 1221 SetChrontelReg(pAST, 1, 0x49, 0x00); 1222 SetChrontelReg(pAST, 1, 0x56, 0x00); 1223 } 1224 } 1225 1226} 1227 1228