1/*
2 * RadeonHD R6xx, R7xx Register documentation
3 *
4 * Copyright (C) 2008-2009  Advanced Micro Devices, Inc.
5 * Copyright (C) 2008-2009  Matthias Hopf
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included
15 * in all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
21 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _R600_REG_H_
26#define _R600_REG_H_
27
28/*
29 * Register definitions
30 */
31
32#include "r600_reg_auto_r6xx.h"
33#include "r600_reg_r6xx.h"
34#include "r600_reg_r7xx.h"
35
36
37/* SET_*_REG offsets + ends */
38#define SET_CONFIG_REG_offset  0x00008000
39#define SET_CONFIG_REG_end     0x0000ac00
40#define SET_CONTEXT_REG_offset 0x00028000
41#define SET_CONTEXT_REG_end    0x00029000
42#define SET_ALU_CONST_offset   0x00030000
43#define SET_ALU_CONST_end      0x00032000
44#define SET_RESOURCE_offset    0x00038000
45#define SET_RESOURCE_end       0x0003c000
46#define SET_SAMPLER_offset     0x0003c000
47#define SET_SAMPLER_end        0x0003cff0
48#define SET_CTL_CONST_offset   0x0003cff0
49#define SET_CTL_CONST_end      0x0003e200
50#define SET_LOOP_CONST_offset  0x0003e200
51#define SET_LOOP_CONST_end     0x0003e380
52#define SET_BOOL_CONST_offset  0x0003e380
53#define SET_BOOL_CONST_end     0x0003e38c
54
55
56/* packet3 IT_SURFACE_BASE_UPDATE bits */
57enum {
58	DEPTH_BASE    = (1 << 0),
59	COLOR0_BASE   = (1 << 1),
60	COLOR1_BASE   = (1 << 2),
61	COLOR2_BASE   = (1 << 3),
62	COLOR3_BASE   = (1 << 4),
63	COLOR4_BASE   = (1 << 5),
64	COLOR5_BASE   = (1 << 6),
65	COLOR6_BASE   = (1 << 7),
66	COLOR7_BASE   = (1 << 8),
67	STRMOUT_BASE0 = (1 << 9),
68	STRMOUT_BASE1 = (1 << 10),
69	STRMOUT_BASE2 = (1 << 11),
70	STRMOUT_BASE3 = (1 << 12),
71	COHER_BASE0   = (1 << 13),
72	COHER_BASE1   = (1 << 14),
73};
74
75/* Packet3 commands */
76enum {
77    IT_NOP                               = 0x10,
78    IT_INDIRECT_BUFFER_END               = 0x17,
79    IT_SET_PREDICATION                   = 0x20,
80    IT_REG_RMW                           = 0x21,
81    IT_COND_EXEC                         = 0x22,
82    IT_PRED_EXEC                         = 0x23,
83    IT_START_3D_CMDBUF                   = 0x24,
84    IT_DRAW_INDEX_2                      = 0x27,
85    IT_CONTEXT_CONTROL                   = 0x28,
86    IT_DRAW_INDEX_IMMD_BE                = 0x29,
87    IT_INDEX_TYPE                        = 0x2A,
88    IT_DRAW_INDEX                        = 0x2B,
89    IT_DRAW_INDEX_AUTO                   = 0x2D,
90    IT_DRAW_INDEX_IMMD                   = 0x2E,
91    IT_NUM_INSTANCES                     = 0x2F,
92    IT_STRMOUT_BUFFER_UPDATE             = 0x34,
93    IT_INDIRECT_BUFFER_MP                = 0x38,
94    IT_MEM_SEMAPHORE                     = 0x39,
95    IT_MPEG_INDEX                        = 0x3A,
96    IT_WAIT_REG_MEM                      = 0x3C,
97    IT_MEM_WRITE                         = 0x3D,
98    IT_INDIRECT_BUFFER                   = 0x32,
99    IT_CP_INTERRUPT                      = 0x40,
100    IT_SURFACE_SYNC                      = 0x43,
101    IT_ME_INITIALIZE                     = 0x44,
102    IT_COND_WRITE                        = 0x45,
103    IT_EVENT_WRITE                       = 0x46,
104    IT_EVENT_WRITE_EOP                   = 0x47,
105    IT_ONE_REG_WRITE                     = 0x57,
106    IT_SET_CONFIG_REG                    = 0x68,
107    IT_SET_CONTEXT_REG                   = 0x69,
108    IT_SET_ALU_CONST                     = 0x6A,
109    IT_SET_BOOL_CONST                    = 0x6B,
110    IT_SET_LOOP_CONST                    = 0x6C,
111    IT_SET_RESOURCE                      = 0x6D,
112    IT_SET_SAMPLER                       = 0x6E,
113    IT_SET_CTL_CONST                     = 0x6F,
114    IT_SURFACE_BASE_UPDATE               = 0x73,
115} ;
116
117/* IT_WAIT_REG_MEM operation encoding */
118
119#define IT_WAIT_ALWAYS          (0 << 0)
120#define IT_WAIT_LT              (1 << 0)
121#define IT_WAIT_LE              (2 << 0)
122#define IT_WAIT_EQ              (3 << 0)
123#define IT_WAIT_NE              (4 << 0)
124#define IT_WAIT_GE              (5 << 0)
125#define IT_WAIT_GT              (6 << 0)
126#define IT_WAIT_REG             (0 << 4)
127#define IT_WAIT_MEM             (1 << 4)
128
129#define IT_WAIT_ADDR(x)         ((x) >> 2)
130
131/* IT_INDEX_TYPE */
132#define IT_INDEX_TYPE_SWAP_MODE(x) ((x) << 2)
133
134#endif
135