1#ifndef __R600_STATE_H__
2#define __R600_STATE_H__
3
4
5#include "xf86drm.h"
6
7typedef int bool_t;
8
9#define CLEAR(x) memset (&x, 0, sizeof(x))
10
11/* Sequencer / thread handling */
12typedef struct {
13    int ps_prio;
14    int vs_prio;
15    int gs_prio;
16    int es_prio;
17    int num_ps_gprs;
18    int num_vs_gprs;
19    int num_gs_gprs;
20    int num_es_gprs;
21    int num_temp_gprs;
22    int num_ps_threads;
23    int num_vs_threads;
24    int num_gs_threads;
25    int num_es_threads;
26    int num_ps_stack_entries;
27    int num_vs_stack_entries;
28    int num_gs_stack_entries;
29    int num_es_stack_entries;
30} sq_config_t;
31
32/* Color buffer / render target */
33typedef struct {
34    int id;
35    int w;
36    int h;
37    uint64_t base;
38    int format;
39    int endian;
40    int array_mode;						// tiling
41    int number_type;
42    int read_size;
43    int comp_swap;
44    int tile_mode;
45    int blend_clamp;
46    int clear_color;
47    int blend_bypass;
48    int blend_float32;
49    int simple_float;
50    int round_mode;
51    int tile_compact;
52    int source_format;
53    /* 2D related CB state */
54    uint32_t pmask;
55    int rop;
56    int blend_enable;
57    uint32_t blendcntl;
58    struct radeon_bo *bo;
59    struct radeon_surface *surface;
60} cb_config_t;
61
62/* Depth buffer */
63typedef struct {
64    int w;
65    int h;
66    uint64_t base;
67    int format;
68    int read_size;
69    int array_mode;						// tiling
70    int tile_surface_en;
71    int tile_compact;
72    int zrange_precision;
73    struct radeon_bo *bo;
74} db_config_t;
75
76/* Shader */
77typedef struct {
78    uint64_t shader_addr;
79    uint32_t shader_size;
80    int num_gprs;
81    int stack_size;
82    int dx10_clamp;
83    int prime_cache_pgm_en;
84    int prime_cache_on_draw;
85    int fetch_cache_lines;
86    int prime_cache_en;
87    int prime_cache_on_const;
88    int clamp_consts;
89    int export_mode;
90    int uncached_first_inst;
91    struct radeon_bo *bo;
92} shader_config_t;
93
94/* Vertex buffer / vtx resource */
95typedef struct {
96    int id;
97    uint64_t vb_addr;
98    uint32_t vtx_num_entries;
99    uint32_t vtx_size_dw;
100    int clamp_x;
101    int format;
102    int num_format_all;
103    int format_comp_all;
104    int srf_mode_all;
105    int endian;
106    int mem_req_size;
107    struct radeon_bo *bo;
108} vtx_resource_t;
109
110/* Texture resource */
111typedef struct {
112    int id;
113    int w;
114    int h;
115    int pitch;
116    int depth;
117    int dim;
118    int tile_mode;
119    int tile_type;
120    int format;
121    uint64_t base;
122    uint64_t mip_base;
123    uint32_t size;
124    int format_comp_x;
125    int format_comp_y;
126    int format_comp_z;
127    int format_comp_w;
128    int num_format_all;
129    int srf_mode_all;
130    int force_degamma;
131    int endian;
132    int request_size;
133    int dst_sel_x;
134    int dst_sel_y;
135    int dst_sel_z;
136    int dst_sel_w;
137    int base_level;
138    int last_level;
139    int base_array;
140    int last_array;
141    int mpeg_clamp;
142    int perf_modulation;
143    int interlaced;
144    struct radeon_bo *bo;
145    struct radeon_bo *mip_bo;
146    struct radeon_surface *surface;
147} tex_resource_t;
148
149/* Texture sampler */
150typedef struct {
151    int				id;
152    /* Clamping */
153    int				clamp_x, clamp_y, clamp_z;
154    int		       		border_color;
155    /* Filtering */
156    int				xy_mag_filter, xy_min_filter;
157    int				z_filter;
158    int				mip_filter;
159    bool_t			high_precision_filter;	/* ? */
160    int				perf_mip;		/* ? 0-7 */
161    int				perf_z;			/* ? 3 */
162    /* LoD selection */
163    int				min_lod, max_lod;	/* 0-0x3ff */
164    int                         lod_bias;		/* 0-0xfff (signed?) */
165    int                         lod_bias2;		/* ? 0-0xfff (signed?) */
166    bool_t			lod_uses_minor_axis;	/* ? */
167    /* Other stuff */
168    bool_t			point_sampling_clamp;	/* ? */
169    bool_t			tex_array_override;	/* ? */
170    bool_t                      mc_coord_truncate;	/* ? */
171    bool_t			force_degamma;		/* ? */
172    bool_t			fetch_4;		/* ? */
173    bool_t			sample_is_pcf;		/* ? */
174    bool_t			type;			/* ? */
175    int				depth_compare;		/* only depth textures? */
176    int				chroma_key;
177} tex_sampler_t;
178
179/* Draw command */
180typedef struct {
181    uint32_t prim_type;
182    uint32_t vgt_draw_initiator;
183    uint32_t index_type;
184    uint32_t num_instances;
185    uint32_t num_indices;
186} draw_config_t;
187
188#define BEGIN_BATCH(n)				\
189do {					\
190    radeon_ddx_cs_start(pScrn, (n), __FILE__, __func__, __LINE__);	\
191} while(0)
192#define END_BATCH()				\
193do {					\
194    radeon_cs_end(info->cs, __FILE__, __func__, __LINE__);	\
195} while(0)
196#define RELOC_BATCH(bo, rd, wd)					\
197do {							\
198    int _ret;								\
199    _ret = radeon_cs_write_reloc(info->cs, (bo), (rd), (wd), 0);	\
200    if (_ret) ErrorF("reloc emit failure %d (%s %d)\n", _ret, __func__, __LINE__); \
201} while(0)
202#define E32(dword)                                                  \
203do {                                                                    \
204    radeon_cs_write_dword(info->cs, (dword));			\
205} while (0)
206
207#define EFLOAT(val)							\
208do {								        \
209    union { float f; uint32_t d; } a;                                   \
210    a.f = (val);								\
211    E32(a.d);							\
212} while (0)
213
214#define PACK3(cmd, num)	       					\
215do {                                                                    \
216    E32(RADEON_CP_PACKET3 | ((cmd) << 8) | ((((num) - 1) & 0x3fff) << 16)); \
217} while (0)
218
219/* write num registers, start at reg */
220/* If register falls in a special area, special commands are issued */
221#define PACK0(reg, num)                                             \
222do {                                                                    \
223    if ((reg) >= SET_CONFIG_REG_offset && (reg) < SET_CONFIG_REG_end) {	\
224	PACK3(IT_SET_CONFIG_REG, (num) + 1);			\
225	E32(((reg) - SET_CONFIG_REG_offset) >> 2);		\
226    } else if ((reg) >= SET_CONTEXT_REG_offset && (reg) < SET_CONTEXT_REG_end) { \
227	PACK3(IT_SET_CONTEXT_REG, (num) + 1);			\
228	E32(((reg) - SET_CONTEXT_REG_offset) >> 2);		\
229    } else if ((reg) >= SET_ALU_CONST_offset && (reg) < SET_ALU_CONST_end) { \
230	PACK3(IT_SET_ALU_CONST, (num) + 1);			\
231	E32(((reg) - SET_ALU_CONST_offset) >> 2);			\
232    } else if ((reg) >= SET_RESOURCE_offset && (reg) < SET_RESOURCE_end) { \
233	PACK3(IT_SET_RESOURCE, num + 1);				\
234	E32(((reg) - SET_RESOURCE_offset) >> 2);			\
235    } else if ((reg) >= SET_SAMPLER_offset && (reg) < SET_SAMPLER_end) { \
236	PACK3(IT_SET_SAMPLER, (num) + 1);				\
237	E32((reg - SET_SAMPLER_offset) >> 2);			\
238    } else if ((reg) >= SET_CTL_CONST_offset && (reg) < SET_CTL_CONST_end) { \
239	PACK3(IT_SET_CTL_CONST, (num) + 1);			\
240	E32(((reg) - SET_CTL_CONST_offset) >> 2);		\
241    } else if ((reg) >= SET_LOOP_CONST_offset && (reg) < SET_LOOP_CONST_end) { \
242	PACK3(IT_SET_LOOP_CONST, (num) + 1);			\
243	E32(((reg) - SET_LOOP_CONST_offset) >> 2);		\
244    } else if ((reg) >= SET_BOOL_CONST_offset && (reg) < SET_BOOL_CONST_end) { \
245	PACK3(IT_SET_BOOL_CONST, (num) + 1);			\
246	E32(((reg) - SET_BOOL_CONST_offset) >> 2);		\
247    } else {								\
248	E32(CP_PACKET0 ((reg), (num) - 1));			\
249    }									\
250} while (0)
251
252/* write a single register */
253#define EREG(reg, val)							\
254do {								        \
255    PACK0((reg), 1);						\
256    E32((val));							\
257} while (0)
258
259void R600CPFlushIndirect(ScrnInfoPtr pScrn);
260void R600IBDiscard(ScrnInfoPtr pScrn);
261
262void
263r600_wait_3d_idle_clean(ScrnInfoPtr pScrn);
264void
265r600_wait_3d_idle(ScrnInfoPtr pScrn);
266void
267r600_start_3d(ScrnInfoPtr pScrn);
268void
269r600_set_blend_color(ScrnInfoPtr pScrn, float *color);
270void
271r600_set_render_target(ScrnInfoPtr pScrn, cb_config_t *cb_conf, uint32_t domain);
272void
273r600_cp_wait_vline_sync(ScrnInfoPtr pScrn, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop);
274void
275r600_set_spi(ScrnInfoPtr pScrn, int vs_export_count, int num_interp);
276void
277r600_fs_setup(ScrnInfoPtr pScrn, shader_config_t *fs_conf, uint32_t domain);
278void
279r600_vs_setup(ScrnInfoPtr pScrn, shader_config_t *vs_conf, uint32_t domain);
280void
281r600_ps_setup(ScrnInfoPtr pScrn, shader_config_t *ps_conf, uint32_t domain);
282void
283r600_set_alu_consts(ScrnInfoPtr pScrn, int offset, int count, float *const_buf);
284void
285r600_set_bool_consts(ScrnInfoPtr pScrn, int offset, uint32_t val);
286void
287r600_set_tex_resource(ScrnInfoPtr pScrn, tex_resource_t *tex_res, uint32_t domain);
288void
289r600_set_tex_sampler (ScrnInfoPtr pScrn, tex_sampler_t *s);
290void
291r600_set_screen_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
292void
293r600_set_vport_scissor(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2);
294void
295r600_set_generic_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
296void
297r600_set_window_scissor(ScrnInfoPtr pScrn, int x1, int y1, int x2, int y2);
298void
299r600_set_clip_rect(ScrnInfoPtr pScrn, int id, int x1, int y1, int x2, int y2);
300void
301r600_set_default_state(ScrnInfoPtr pScrn);
302void
303r600_draw_immd(ScrnInfoPtr pScrn, draw_config_t *draw_conf, uint32_t *indices);
304void
305r600_draw_auto(ScrnInfoPtr pScrn, draw_config_t *draw_conf);
306
307void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size);
308
309Bool
310R600SetAccelState(ScrnInfoPtr pScrn,
311		  struct r600_accel_object *src0,
312		  struct r600_accel_object *src1,
313		  struct r600_accel_object *dst,
314		  uint32_t vs_offset, uint32_t ps_offset,
315		  int rop, Pixel planemask);
316
317extern Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index);
318extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index);
319extern void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
320				    int depth, int usage_hint, int bitsPerPixel,
321				    int *new_pitch);
322extern void RADEONEXADestroyPixmap(ScreenPtr pScreen, void *driverPriv);
323extern Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix);
324extern Bool RADEONEXASharePixmapBacking(PixmapPtr ppix, ScreenPtr secondary, void **handle_p);
325extern Bool RADEONEXASetSharedPixmapBacking(PixmapPtr ppix, void *handle);
326#endif
327