1/* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining 8 * a copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation on the rights to use, copy, modify, merge, 11 * publish, distribute, sublicense, and/or sell copies of the Software, 12 * and to permit persons to whom the Software is furnished to do so, 13 * subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 */ 28 29#ifdef HAVE_CONFIG_H 30#include "config.h" 31#endif 32 33/* 34 * Authors: 35 * Kevin E. Martin <martin@xfree86.org> 36 * Rickard E. Faith <faith@valinux.com> 37 * Alan Hourihane <alanh@fairlite.demon.co.uk> 38 * 39 * Credits: 40 * 41 * Thanks to Ani Joshi <ajoshi@shell.unixbox.com> for providing source 42 * code to his Radeon driver. Portions of this file are based on the 43 * initialization code for that driver. 44 * 45 * References: 46 * 47 * !!!! FIXME !!!! 48 * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical 49 * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April 50 * 1999. 51 * 52 * RAGE 128 Software Development Manual (Technical Reference Manual P/N 53 * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. 54 * 55 * Notes on unimplemented XAA optimizations: 56 * 57 * SetClipping: This has been removed as XAA expects 16bit registers 58 * for full clipping. 59 * TwoPointLine: The Radeon supports this. Not Bresenham. 60 * DashedLine with non-power-of-two pattern length: Apparently, there is 61 * no way to set the length of the pattern -- it is always 62 * assumed to be 8 or 32 (or 1024?). 63 * ScreenToScreenColorExpandFill: See p. 4-17 of the Technical Reference 64 * Manual where it states that monochrome expansion of frame 65 * buffer data is not supported. 66 * CPUToScreenColorExpandFill, direct: The implementation here uses a hybrid 67 * direct/indirect method. If we had more data registers, 68 * then we could do better. If XAA supported a trigger write 69 * address, the code would be simpler. 70 * Color8x8PatternFill: Apparently, an 8x8 color brush cannot take an 8x8 71 * pattern from frame buffer memory. 72 * ImageWrites: Same as CPUToScreenColorExpandFill 73 * 74 */ 75 76#include <errno.h> 77#include <string.h> 78#include <assert.h> 79 /* Driver data structures */ 80#include "radeon.h" 81#include "radeon_glamor.h" 82#include "radeon_reg.h" 83#include "r600_reg.h" 84#include "radeon_probe.h" 85#include "radeon_version.h" 86 87#include "ati_pciids_gen.h" 88 89 /* Line support */ 90#include "miline.h" 91 92 /* X and server generic header files */ 93#include "xf86.h" 94 95static int RADEONDRMGetNumPipes(ScrnInfoPtr pScrn, int *num_pipes) 96{ 97 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 98 struct drm_radeon_info np2; 99 np2.value = (unsigned long)num_pipes; 100 np2.request = RADEON_INFO_NUM_GB_PIPES; 101 return drmCommandWriteRead(pRADEONEnt->fd, DRM_RADEON_INFO, &np2, sizeof(np2)); 102} 103 104/* Initialize the acceleration hardware */ 105void RADEONEngineInit(ScrnInfoPtr pScrn) 106{ 107 RADEONInfoPtr info = RADEONPTR(pScrn); 108 info->accel_state->num_gb_pipes = 0; 109 110 if (info->directRenderingEnabled && (IS_R300_3D || IS_R500_3D)) { 111 int num_pipes; 112 113 if(RADEONDRMGetNumPipes(pScrn, &num_pipes) < 0) { 114 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 115 "Failed to determine num pipes from DRM, falling back to " 116 "manual look-up!\n"); 117 info->accel_state->num_gb_pipes = 0; 118 } else { 119 info->accel_state->num_gb_pipes = num_pipes; 120 } 121 } 122} 123 124int radeon_cs_space_remaining(ScrnInfoPtr pScrn) 125{ 126 RADEONInfoPtr info = RADEONPTR(pScrn); 127 128 return (info->cs->ndw - info->cs->cdw); 129} 130 131void RADEONCopySwap(uint8_t *dst, uint8_t *src, unsigned int size, int swap) 132{ 133 switch(swap) { 134 case RADEON_HOST_DATA_SWAP_HDW: 135 { 136 unsigned int *d = (unsigned int *)dst; 137 unsigned int *s = (unsigned int *)src; 138 unsigned int nwords = size >> 2; 139 140 for (; nwords > 0; --nwords, ++d, ++s) 141 *d = ((*s & 0xffff) << 16) | ((*s >> 16) & 0xffff); 142 return; 143 } 144 case RADEON_HOST_DATA_SWAP_32BIT: 145 { 146 unsigned int *d = (unsigned int *)dst; 147 unsigned int *s = (unsigned int *)src; 148 unsigned int nwords = size >> 2; 149 150 for (; nwords > 0; --nwords, ++d, ++s) 151#ifdef __powerpc__ 152 asm volatile("stwbrx %0,0,%1" : : "r" (*s), "r" (d)); 153#else 154 *d = ((*s >> 24) & 0xff) | ((*s >> 8) & 0xff00) 155 | ((*s & 0xff00) << 8) | ((*s & 0xff) << 24); 156#endif 157 return; 158 } 159 case RADEON_HOST_DATA_SWAP_16BIT: 160 { 161 unsigned short *d = (unsigned short *)dst; 162 unsigned short *s = (unsigned short *)src; 163 unsigned int nwords = size >> 1; 164 165 for (; nwords > 0; --nwords, ++d, ++s) 166#ifdef __powerpc__ 167 asm volatile("sthbrx %0,0,%1" : : "r" (*s), "r" (d)); 168#else 169 *d = (*s >> 8) | (*s << 8); 170#endif 171 return; 172 } 173 } 174 if (src != dst) 175 memcpy(dst, src, size); 176} 177 178 179 180Bool RADEONAccelInit(ScreenPtr pScreen) 181{ 182 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 183 RADEONInfoPtr info = RADEONPTR(pScrn); 184 185 if (info->directRenderingEnabled) { 186 if (info->use_glamor) { 187 if (!radeon_glamor_init(pScreen)) { 188 info->use_glamor = FALSE; 189 return FALSE; 190 } 191 } else if (info->ChipFamily >= CHIP_FAMILY_CEDAR) { 192 if (!EVERGREENDrawInit(pScreen)) 193 return FALSE; 194 } else 195 if (info->ChipFamily >= CHIP_FAMILY_R600) { 196 if (!R600DrawInit(pScreen)) 197 return FALSE; 198 } else { 199 if (!RADEONDrawInit(pScreen)) 200 return FALSE; 201 } 202 } 203 return TRUE; 204} 205 206static void RADEONInit3DEngineInternal(ScrnInfoPtr pScrn) 207{ 208 RADEONInfoPtr info = RADEONPTR(pScrn); 209 uint32_t gb_tile_config, vap_cntl; 210 211 info->accel_state->texW[0] = info->accel_state->texH[0] = 212 info->accel_state->texW[1] = info->accel_state->texH[1] = 1; 213 214 if (IS_R300_3D || IS_R500_3D) { 215 216 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16); 217 218 switch(info->accel_state->num_gb_pipes) { 219 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break; 220 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; 221 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; 222 default: 223 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; 224 } 225 226 BEGIN_RING(2*3); 227 OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); 228 OUT_RING_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); 229 OUT_RING_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 230 ADVANCE_RING(); 231 232 BEGIN_RING(2*3); 233 OUT_RING_REG(R300_GB_AA_CONFIG, 0); 234 OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); 235 OUT_RING_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); 236 ADVANCE_RING(); 237 238 BEGIN_RING(2*4); 239 OUT_RING_REG(R300_GA_POLY_MODE, R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); 240 OUT_RING_REG(R300_GA_ROUND_MODE, (R300_GEOMETRY_ROUND_NEAREST | 241 R300_COLOR_ROUND_NEAREST)); 242 OUT_RING_REG(R300_GA_COLOR_CONTROL, (R300_RGB0_SHADING_GOURAUD | 243 R300_ALPHA0_SHADING_GOURAUD | 244 R300_RGB1_SHADING_GOURAUD | 245 R300_ALPHA1_SHADING_GOURAUD | 246 R300_RGB2_SHADING_GOURAUD | 247 R300_ALPHA2_SHADING_GOURAUD | 248 R300_RGB3_SHADING_GOURAUD | 249 R300_ALPHA3_SHADING_GOURAUD)); 250 OUT_RING_REG(R300_GA_OFFSET, 0); 251 ADVANCE_RING(); 252 253 BEGIN_RING(2*5); 254 OUT_RING_REG(R300_SU_TEX_WRAP, 0); 255 OUT_RING_REG(R300_SU_POLY_OFFSET_ENABLE, 0); 256 OUT_RING_REG(R300_SU_CULL_MODE, R300_FACE_NEG); 257 OUT_RING_REG(R300_SU_DEPTH_SCALE, 0x4b7fffff); 258 OUT_RING_REG(R300_SU_DEPTH_OFFSET, 0); 259 ADVANCE_RING(); 260 261 /* setup the VAP */ 262 if (info->accel_state->has_tcl) 263 vap_cntl = ((5 << R300_PVS_NUM_SLOTS_SHIFT) | 264 (5 << R300_PVS_NUM_CNTLRS_SHIFT) | 265 (9 << R300_VF_MAX_VTX_NUM_SHIFT)); 266 else 267 vap_cntl = ((10 << R300_PVS_NUM_SLOTS_SHIFT) | 268 (5 << R300_PVS_NUM_CNTLRS_SHIFT) | 269 (5 << R300_VF_MAX_VTX_NUM_SHIFT)); 270 271 if ((info->ChipFamily == CHIP_FAMILY_R300) || 272 (info->ChipFamily == CHIP_FAMILY_R350)) 273 vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT); 274 else if (info->ChipFamily == CHIP_FAMILY_RV530) 275 vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT); 276 else if ((info->ChipFamily == CHIP_FAMILY_RV410) || 277 (info->ChipFamily == CHIP_FAMILY_R420)) 278 vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT); 279 else if ((info->ChipFamily == CHIP_FAMILY_R520) || 280 (info->ChipFamily == CHIP_FAMILY_R580) || 281 (info->ChipFamily == CHIP_FAMILY_RV560) || 282 (info->ChipFamily == CHIP_FAMILY_RV570)) 283 vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT); 284 else 285 vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT); 286 287 if (info->accel_state->has_tcl) 288 BEGIN_RING(2*15); 289 else 290 BEGIN_RING(2*9); 291 OUT_RING_REG(R300_VAP_VTX_STATE_CNTL, 0); 292 OUT_RING_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); 293 294 if (info->accel_state->has_tcl) 295 OUT_RING_REG(R300_VAP_CNTL_STATUS, 0); 296 else 297 OUT_RING_REG(R300_VAP_CNTL_STATUS, R300_PVS_BYPASS); 298 OUT_RING_REG(R300_VAP_CNTL, vap_cntl); 299 OUT_RING_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); 300 OUT_RING_REG(R300_VAP_VTE_CNTL, R300_VTX_XY_FMT | R300_VTX_Z_FMT); 301 OUT_RING_REG(R300_VAP_PSC_SGN_NORM_CNTL, 0); 302 303 OUT_RING_REG(R300_VAP_PROG_STREAM_CNTL_EXT_0, 304 ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_0_SHIFT) | 305 (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_0_SHIFT) | 306 (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_0_SHIFT) | 307 (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_0_SHIFT) | 308 ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) 309 << R300_WRITE_ENA_0_SHIFT) | 310 (R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_1_SHIFT) | 311 (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_1_SHIFT) | 312 (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_1_SHIFT) | 313 (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_1_SHIFT) | 314 ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) 315 << R300_WRITE_ENA_1_SHIFT))); 316 OUT_RING_REG(R300_VAP_PROG_STREAM_CNTL_EXT_1, 317 ((R300_SWIZZLE_SELECT_X << R300_SWIZZLE_SELECT_X_2_SHIFT) | 318 (R300_SWIZZLE_SELECT_Y << R300_SWIZZLE_SELECT_Y_2_SHIFT) | 319 (R300_SWIZZLE_SELECT_Z << R300_SWIZZLE_SELECT_Z_2_SHIFT) | 320 (R300_SWIZZLE_SELECT_W << R300_SWIZZLE_SELECT_W_2_SHIFT) | 321 ((R300_WRITE_ENA_X | R300_WRITE_ENA_Y | R300_WRITE_ENA_Z | R300_WRITE_ENA_W) 322 << R300_WRITE_ENA_2_SHIFT))); 323 324 if (info->accel_state->has_tcl) { 325 OUT_RING_REG(R300_VAP_PVS_FLOW_CNTL_OPC, 0); 326 OUT_RING_REG(R300_VAP_GB_VERT_CLIP_ADJ, 0x3f800000); 327 OUT_RING_REG(R300_VAP_GB_VERT_DISC_ADJ, 0x3f800000); 328 OUT_RING_REG(R300_VAP_GB_HORZ_CLIP_ADJ, 0x3f800000); 329 OUT_RING_REG(R300_VAP_GB_HORZ_DISC_ADJ, 0x3f800000); 330 OUT_RING_REG(R300_VAP_CLIP_CNTL, R300_CLIP_DISABLE); 331 } 332 ADVANCE_RING(); 333 334 /* pre-load the vertex shaders */ 335 if (info->accel_state->has_tcl) { 336 BEGIN_RING(2*37); 337 /* exa composite shader program */ 338 OUT_RING_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(0)); 339 /* PVS inst 0 - dst X,Y */ 340 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 341 (R300_PVS_DST_OPCODE(R300_VE_ADD) | 342 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 343 R300_PVS_DST_OFFSET(0) | 344 R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | 345 R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); 346 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 347 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 348 R300_PVS_SRC_OFFSET(0) | 349 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 350 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 351 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 352 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1))); 353 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 354 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 355 R300_PVS_SRC_OFFSET(0) | 356 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 357 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 358 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 359 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 360 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 361 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 362 R300_PVS_SRC_OFFSET(0) | 363 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 364 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 365 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 366 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 367 368 /* PVS inst 1 - src X */ 369 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 370 (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) | 371 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) | 372 R300_PVS_DST_OFFSET(0) | 373 R300_PVS_DST_WE_X)); 374 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 375 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 376 R300_PVS_SRC_OFFSET(6) | 377 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 378 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 379 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) | 380 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 381 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 382 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | 383 R300_PVS_SRC_OFFSET(0) | 384 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 385 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 386 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | 387 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 388 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 389 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 390 R300_PVS_SRC_OFFSET(6) | 391 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 392 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 393 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 394 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 395 396 /* PVS inst 2 - src Y */ 397 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 398 (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) | 399 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) | 400 R300_PVS_DST_OFFSET(0) | 401 R300_PVS_DST_WE_Y)); 402 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 403 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 404 R300_PVS_SRC_OFFSET(6) | 405 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 406 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 407 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) | 408 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 409 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 410 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | 411 R300_PVS_SRC_OFFSET(1) | 412 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 413 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 414 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | 415 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 416 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 417 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 418 R300_PVS_SRC_OFFSET(6) | 419 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 420 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 421 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 422 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 423 424 /* PVS inst 3 - src X / w */ 425 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 426 (R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) | 427 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 428 R300_PVS_DST_OFFSET(1) | 429 R300_PVS_DST_WE_X)); 430 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 431 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) | 432 R300_PVS_SRC_OFFSET(0) | 433 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 434 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 435 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 436 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 437 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 438 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | 439 R300_PVS_SRC_OFFSET(0) | 440 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_W) | 441 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 442 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 443 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 444 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 445 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 446 R300_PVS_SRC_OFFSET(6) | 447 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 448 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 449 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 450 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 451 452 /* PVS inst 4 - src y / h */ 453 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 454 (R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) | 455 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 456 R300_PVS_DST_OFFSET(1) | 457 R300_PVS_DST_WE_Y)); 458 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 459 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) | 460 R300_PVS_SRC_OFFSET(0) | 461 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 462 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 463 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 464 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 465 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 466 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | 467 R300_PVS_SRC_OFFSET(1) | 468 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 469 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_W) | 470 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 471 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 472 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 473 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 474 R300_PVS_SRC_OFFSET(6) | 475 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 476 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 477 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 478 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 479 480 /* PVS inst 5 - mask X */ 481 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 482 (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) | 483 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) | 484 R300_PVS_DST_OFFSET(0) | 485 R300_PVS_DST_WE_Z)); 486 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 487 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 488 R300_PVS_SRC_OFFSET(7) | 489 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 490 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 491 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) | 492 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 493 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 494 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | 495 R300_PVS_SRC_OFFSET(2) | 496 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 497 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 498 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | 499 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 500 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 501 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 502 R300_PVS_SRC_OFFSET(7) | 503 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 504 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 505 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 506 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 507 508 /* PVS inst 6 - mask Y */ 509 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 510 (R300_PVS_DST_OPCODE(R300_VE_DOT_PRODUCT) | 511 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_TEMPORARY) | 512 R300_PVS_DST_OFFSET(0) | 513 R300_PVS_DST_WE_W)); 514 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 515 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 516 R300_PVS_SRC_OFFSET(7) | 517 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 518 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 519 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_1) | 520 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 521 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 522 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | 523 R300_PVS_SRC_OFFSET(3) | 524 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 525 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 526 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_Z) | 527 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 528 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 529 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 530 R300_PVS_SRC_OFFSET(7) | 531 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 532 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 533 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 534 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 535 536 /* PVS inst 7 - mask X / w */ 537 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 538 (R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) | 539 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 540 R300_PVS_DST_OFFSET(2) | 541 R300_PVS_DST_WE_X)); 542 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 543 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) | 544 R300_PVS_SRC_OFFSET(0) | 545 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_Z) | 546 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 547 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 548 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 549 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 550 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | 551 R300_PVS_SRC_OFFSET(2) | 552 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_W) | 553 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 554 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 555 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 556 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 557 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 558 R300_PVS_SRC_OFFSET(6) | 559 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 560 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 561 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 562 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 563 564 /* PVS inst 8 - mask y / h */ 565 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 566 (R300_PVS_DST_OPCODE(R300_VE_MULTIPLY) | 567 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 568 R300_PVS_DST_OFFSET(2) | 569 R300_PVS_DST_WE_Y)); 570 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 571 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_TEMPORARY) | 572 R300_PVS_SRC_OFFSET(0) | 573 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 574 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_W) | 575 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 576 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 577 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 578 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_CONSTANT) | 579 R300_PVS_SRC_OFFSET(3) | 580 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 581 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_W) | 582 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 583 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 584 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 585 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 586 R300_PVS_SRC_OFFSET(6) | 587 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 588 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 589 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 590 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 591 ADVANCE_RING(); 592 593 /* Xv shader program */ 594 BEGIN_RING(2*9); 595 OUT_RING_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(9)); 596 597 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 598 (R300_PVS_DST_OPCODE(R300_VE_ADD) | 599 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 600 R300_PVS_DST_OFFSET(0) | 601 R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | 602 R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); 603 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 604 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 605 R300_PVS_SRC_OFFSET(0) | 606 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 607 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 608 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 609 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1))); 610 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 611 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 612 R300_PVS_SRC_OFFSET(0) | 613 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 614 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 615 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 616 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 617 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 618 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 619 R300_PVS_SRC_OFFSET(0) | 620 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 621 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 622 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 623 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 624 625 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 626 (R300_PVS_DST_OPCODE(R300_VE_ADD) | 627 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 628 R300_PVS_DST_OFFSET(1) | 629 R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y)); 630 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 631 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 632 R300_PVS_SRC_OFFSET(6) | 633 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 634 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 635 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 636 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1))); 637 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 638 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 639 R300_PVS_SRC_OFFSET(6) | 640 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 641 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 642 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 643 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 644 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 645 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 646 R300_PVS_SRC_OFFSET(6) | 647 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 648 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 649 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 650 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 651 ADVANCE_RING(); 652 653 /* Xv bicubic shader program */ 654 BEGIN_RING(2*13); 655 OUT_RING_REG(R300_VAP_PVS_VECTOR_INDX_REG, R300_PVS_VECTOR_INST_INDEX(11)); 656 /* PVS inst 0 */ 657 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 658 (R300_PVS_DST_OPCODE(R300_VE_ADD) | 659 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 660 R300_PVS_DST_OFFSET(0) | 661 R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | 662 R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); 663 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 664 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 665 R300_PVS_SRC_OFFSET(0) | 666 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 667 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 668 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 669 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1))); 670 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 671 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 672 R300_PVS_SRC_OFFSET(0) | 673 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 674 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 675 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 676 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 677 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 678 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 679 R300_PVS_SRC_OFFSET(0) | 680 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 681 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 682 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 683 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 684 685 /* PVS inst 1 */ 686 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 687 (R300_PVS_DST_OPCODE(R300_VE_ADD) | 688 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 689 R300_PVS_DST_OFFSET(1) | 690 R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | 691 R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); 692 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 693 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 694 R300_PVS_SRC_OFFSET(6) | 695 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 696 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 697 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 698 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1))); 699 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 700 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 701 R300_PVS_SRC_OFFSET(6) | 702 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 703 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 704 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 705 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 706 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 707 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 708 R300_PVS_SRC_OFFSET(6) | 709 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 710 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 711 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 712 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 713 714 /* PVS inst 2 */ 715 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 716 (R300_PVS_DST_OPCODE(R300_VE_ADD) | 717 R300_PVS_DST_REG_TYPE(R300_PVS_DST_REG_OUT) | 718 R300_PVS_DST_OFFSET(2) | 719 R300_PVS_DST_WE_X | R300_PVS_DST_WE_Y | 720 R300_PVS_DST_WE_Z | R300_PVS_DST_WE_W)); 721 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 722 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 723 R300_PVS_SRC_OFFSET(7) | 724 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_X) | 725 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_Y) | 726 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 727 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_1))); 728 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 729 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 730 R300_PVS_SRC_OFFSET(7) | 731 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 732 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 733 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 734 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 735 OUT_RING_REG(R300_VAP_PVS_VECTOR_DATA_REG, 736 (R300_PVS_SRC_REG_TYPE(R300_PVS_SRC_REG_INPUT) | 737 R300_PVS_SRC_OFFSET(7) | 738 R300_PVS_SRC_SWIZZLE_X(R300_PVS_SRC_SELECT_FORCE_0) | 739 R300_PVS_SRC_SWIZZLE_Y(R300_PVS_SRC_SELECT_FORCE_0) | 740 R300_PVS_SRC_SWIZZLE_Z(R300_PVS_SRC_SELECT_FORCE_0) | 741 R300_PVS_SRC_SWIZZLE_W(R300_PVS_SRC_SELECT_FORCE_0))); 742 ADVANCE_RING(); 743 } 744 745 /* pre-load the RS instructions */ 746 BEGIN_RING(2*4); 747 if (IS_R300_3D) { 748 /* rasterizer source table 749 * R300_RS_TEX_PTR is the offset into the input RS stream 750 * 0,1 are tex0 751 * 2,3 are tex1 752 */ 753 OUT_RING_REG(R300_RS_IP_0, 754 (R300_RS_TEX_PTR(0) | 755 R300_RS_SEL_S(R300_RS_SEL_C0) | 756 R300_RS_SEL_T(R300_RS_SEL_C1) | 757 R300_RS_SEL_R(R300_RS_SEL_K0) | 758 R300_RS_SEL_Q(R300_RS_SEL_K1))); 759 OUT_RING_REG(R300_RS_IP_1, 760 (R300_RS_TEX_PTR(2) | 761 R300_RS_SEL_S(R300_RS_SEL_C0) | 762 R300_RS_SEL_T(R300_RS_SEL_C1) | 763 R300_RS_SEL_R(R300_RS_SEL_K0) | 764 R300_RS_SEL_Q(R300_RS_SEL_K1))); 765 /* src tex */ 766 /* R300_INST_TEX_ID - select the RS source table entry 767 * R300_INST_TEX_ADDR - the FS temp register for the texture data 768 */ 769 OUT_RING_REG(R300_RS_INST_0, (R300_INST_TEX_ID(0) | 770 R300_RS_INST_TEX_CN_WRITE | 771 R300_INST_TEX_ADDR(0))); 772 /* mask tex */ 773 OUT_RING_REG(R300_RS_INST_1, (R300_INST_TEX_ID(1) | 774 R300_RS_INST_TEX_CN_WRITE | 775 R300_INST_TEX_ADDR(1))); 776 777 } else { 778 /* rasterizer source table 779 * R300_RS_TEX_PTR is the offset into the input RS stream 780 * 0,1 are tex0 781 * 2,3 are tex1 782 */ 783 OUT_RING_REG(R500_RS_IP_0, ((0 << R500_RS_IP_TEX_PTR_S_SHIFT) | 784 (1 << R500_RS_IP_TEX_PTR_T_SHIFT) | 785 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | 786 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); 787 788 OUT_RING_REG(R500_RS_IP_1, ((2 << R500_RS_IP_TEX_PTR_S_SHIFT) | 789 (3 << R500_RS_IP_TEX_PTR_T_SHIFT) | 790 (R500_RS_IP_PTR_K0 << R500_RS_IP_TEX_PTR_R_SHIFT) | 791 (R500_RS_IP_PTR_K1 << R500_RS_IP_TEX_PTR_Q_SHIFT))); 792 /* src tex */ 793 /* R500_RS_INST_TEX_ID_SHIFT - select the RS source table entry 794 * R500_RS_INST_TEX_ADDR_SHIFT - the FS temp register for the texture data 795 */ 796 OUT_RING_REG(R500_RS_INST_0, ((0 << R500_RS_INST_TEX_ID_SHIFT) | 797 R500_RS_INST_TEX_CN_WRITE | 798 (0 << R500_RS_INST_TEX_ADDR_SHIFT))); 799 /* mask tex */ 800 OUT_RING_REG(R500_RS_INST_1, ((1 << R500_RS_INST_TEX_ID_SHIFT) | 801 R500_RS_INST_TEX_CN_WRITE | 802 (1 << R500_RS_INST_TEX_ADDR_SHIFT))); 803 } 804 ADVANCE_RING(); 805 806 if (IS_R300_3D) 807 BEGIN_RING(2*4); 808 else { 809 BEGIN_RING(2*6); 810 OUT_RING_REG(R300_US_CONFIG, R500_ZERO_TIMES_ANYTHING_EQUALS_ZERO); 811 OUT_RING_REG(R500_US_FC_CTRL, 0); 812 } 813 OUT_RING_REG(R300_US_W_FMT, 0); 814 OUT_RING_REG(R300_US_OUT_FMT_1, (R300_OUT_FMT_UNUSED | 815 R300_OUT_FMT_C0_SEL_BLUE | 816 R300_OUT_FMT_C1_SEL_GREEN | 817 R300_OUT_FMT_C2_SEL_RED | 818 R300_OUT_FMT_C3_SEL_ALPHA)); 819 OUT_RING_REG(R300_US_OUT_FMT_2, (R300_OUT_FMT_UNUSED | 820 R300_OUT_FMT_C0_SEL_BLUE | 821 R300_OUT_FMT_C1_SEL_GREEN | 822 R300_OUT_FMT_C2_SEL_RED | 823 R300_OUT_FMT_C3_SEL_ALPHA)); 824 OUT_RING_REG(R300_US_OUT_FMT_3, (R300_OUT_FMT_UNUSED | 825 R300_OUT_FMT_C0_SEL_BLUE | 826 R300_OUT_FMT_C1_SEL_GREEN | 827 R300_OUT_FMT_C2_SEL_RED | 828 R300_OUT_FMT_C3_SEL_ALPHA)); 829 ADVANCE_RING(); 830 831 832 BEGIN_RING(2*3); 833 OUT_RING_REG(R300_FG_DEPTH_SRC, 0); 834 OUT_RING_REG(R300_FG_FOG_BLEND, 0); 835 OUT_RING_REG(R300_FG_ALPHA_FUNC, 0); 836 ADVANCE_RING(); 837 838 BEGIN_RING(2*13); 839 OUT_RING_REG(R300_RB3D_ABLENDCNTL, 0); 840 OUT_RING_REG(R300_RB3D_ZSTENCILCNTL, 0); 841 OUT_RING_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE); 842 OUT_RING_REG(R300_RB3D_BW_CNTL, 0); 843 OUT_RING_REG(R300_RB3D_ZCNTL, 0); 844 OUT_RING_REG(R300_RB3D_ZTOP, 0); 845 OUT_RING_REG(R300_RB3D_ROPCNTL, 0); 846 847 OUT_RING_REG(R300_RB3D_AARESOLVE_CTL, 0); 848 OUT_RING_REG(R300_RB3D_COLOR_CHANNEL_MASK, (R300_BLUE_MASK_EN | 849 R300_GREEN_MASK_EN | 850 R300_RED_MASK_EN | 851 R300_ALPHA_MASK_EN)); 852 OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); 853 OUT_RING_REG(R300_RB3D_CCTL, 0); 854 OUT_RING_REG(R300_RB3D_DITHER_CTL, 0); 855 OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D | R300_DC_FREE_3D); 856 ADVANCE_RING(); 857 858 BEGIN_RING(2*5); 859 OUT_RING_REG(R300_SC_EDGERULE, 0xA5294A5); 860 if (IS_R300_3D) { 861 /* clip has offset 1440 */ 862 OUT_RING_REG(R300_SC_CLIP_0_A, ((1440 << R300_CLIP_X_SHIFT) | 863 (1440 << R300_CLIP_Y_SHIFT))); 864 OUT_RING_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) | 865 (4080 << R300_CLIP_Y_SHIFT))); 866 } else { 867 OUT_RING_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) | 868 (0 << R300_CLIP_Y_SHIFT))); 869 OUT_RING_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) | 870 (4080 << R300_CLIP_Y_SHIFT))); 871 } 872 OUT_RING_REG(R300_SC_CLIP_RULE, 0xAAAA); 873 OUT_RING_REG(R300_SC_SCREENDOOR, 0xffffff); 874 ADVANCE_RING(); 875 } else if (IS_R200_3D) { 876 877 BEGIN_RING(2*6); 878 if (info->ChipFamily == CHIP_FAMILY_RS300) { 879 OUT_RING_REG(R200_SE_VAP_CNTL_STATUS, RADEON_TCL_BYPASS); 880 } else { 881 OUT_RING_REG(R200_SE_VAP_CNTL_STATUS, 0); 882 } 883 OUT_RING_REG(R200_PP_CNTL_X, 0); 884 OUT_RING_REG(R200_PP_TXMULTI_CTL_0, 0); 885 OUT_RING_REG(R200_SE_VTX_STATE_CNTL, 0); 886 OUT_RING_REG(R200_SE_VTE_CNTL, 0); 887 OUT_RING_REG(R200_SE_VAP_CNTL, R200_VAP_FORCE_W_TO_ONE | 888 R200_VAP_VF_MAX_VTX_NUM); 889 ADVANCE_RING(); 890 891 BEGIN_RING(2*4); 892 OUT_RING_REG(R200_RE_AUX_SCISSOR_CNTL, 0); 893 OUT_RING_REG(R200_RE_CNTL, 0); 894 OUT_RING_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); 895 OUT_RING_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | 896 RADEON_BFACE_SOLID | 897 RADEON_FFACE_SOLID | 898 RADEON_VTX_PIX_CENTER_OGL | 899 RADEON_ROUND_MODE_ROUND | 900 RADEON_ROUND_PREC_4TH_PIX)); 901 ADVANCE_RING(); 902 } else { 903 BEGIN_RING(2*2); 904 if ((info->ChipFamily == CHIP_FAMILY_RADEON) || 905 (info->ChipFamily == CHIP_FAMILY_RV200)) 906 OUT_RING_REG(RADEON_SE_CNTL_STATUS, 0); 907 else 908 OUT_RING_REG(RADEON_SE_CNTL_STATUS, RADEON_TCL_BYPASS); 909 OUT_RING_REG(RADEON_SE_COORD_FMT, 910 RADEON_VTX_XY_PRE_MULT_1_OVER_W0 | 911 RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 | 912 RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 | 913 RADEON_TEX1_W_ROUTING_USE_W0); 914 ADVANCE_RING(); 915 916 BEGIN_RING(2*2); 917 OUT_RING_REG(RADEON_RB3D_PLANEMASK, 0xffffffff); 918 OUT_RING_REG(RADEON_SE_CNTL, (RADEON_DIFFUSE_SHADE_GOURAUD | 919 RADEON_BFACE_SOLID | 920 RADEON_FFACE_SOLID | 921 RADEON_VTX_PIX_CENTER_OGL | 922 RADEON_ROUND_MODE_ROUND | 923 RADEON_ROUND_PREC_4TH_PIX)); 924 ADVANCE_RING(); 925 } 926 927} 928 929/* inserts a wait for vline in the command stream */ 930void RADEONWaitForVLine(ScrnInfoPtr pScrn, PixmapPtr pPix, 931 xf86CrtcPtr crtc, int start, int stop) 932{ 933 RADEONInfoPtr info = RADEONPTR(pScrn); 934 drmmode_crtc_private_ptr drmmode_crtc; 935 936 if (!crtc) 937 return; 938 939 if (!crtc->enabled) 940 return; 941 942 if (pPix != pScrn->pScreen->GetScreenPixmap(pScrn->pScreen)) 943 return; 944 945 start = max(start, crtc->y); 946 stop = min(stop, crtc->y + crtc->mode.VDisplay); 947 948 if (start >= stop) 949 return; 950 951 if (!IS_AVIVO_VARIANT) { 952 /* on pre-r5xx vline starts at CRTC scanout */ 953 start -= crtc->y; 954 stop -= crtc->y; 955 } 956 957 drmmode_crtc = crtc->driver_private; 958 959 BEGIN_RING(2*3); 960 if (IS_AVIVO_VARIANT) { 961 OUT_RING_REG(AVIVO_D1MODE_VLINE_START_END, /* this is just a marker */ 962 ((start << AVIVO_D1MODE_VLINE_START_SHIFT) | 963 (stop << AVIVO_D1MODE_VLINE_END_SHIFT) | 964 AVIVO_D1MODE_VLINE_INV)); 965 } else { 966 OUT_RING_REG(RADEON_CRTC_GUI_TRIG_VLINE, /* another placeholder */ 967 ((start << RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT) | 968 (stop << RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT) | 969 RADEON_CRTC_GUI_TRIG_VLINE_INV | 970 RADEON_CRTC_GUI_TRIG_VLINE_STALL)); 971 } 972 OUT_RING_REG(RADEON_WAIT_UNTIL, (RADEON_WAIT_CRTC_VLINE | 973 RADEON_ENG_DISPLAY_SELECT_CRTC0)); 974 975 OUT_RING(CP_PACKET3(RADEON_CP_PACKET3_NOP, 0)); 976 OUT_RING(drmmode_crtc->mode_crtc->crtc_id); 977 ADVANCE_RING(); 978} 979 980 981void RADEONInit3DEngine(ScrnInfoPtr pScrn) 982{ 983 RADEONInfoPtr info = RADEONPTR (pScrn); 984 985 if (info->directRenderingEnabled) { 986 RADEONInit3DEngineInternal(pScrn); 987 } 988 info->accel_state->XInited3D = TRUE; 989} 990