10d16fef4Smrg/*
20d16fef4Smrg * Copyright © 2007 Red Hat, Inc.
30d16fef4Smrg * Copyright © 2015 Advanced Micro Devices, Inc.
40d16fef4Smrg *
50d16fef4Smrg * Permission is hereby granted, free of charge, to any person obtaining a
60d16fef4Smrg * copy of this software and associated documentation files (the "Software"),
70d16fef4Smrg * to deal in the Software without restriction, including without limitation
80d16fef4Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
90d16fef4Smrg * and/or sell copies of the Software, and to permit persons to whom the
100d16fef4Smrg * Software is furnished to do so, subject to the following conditions:
110d16fef4Smrg *
120d16fef4Smrg * The above copyright notice and this permission notice (including the next
130d16fef4Smrg * paragraph) shall be included in all copies or substantial portions of the
140d16fef4Smrg * Software.
150d16fef4Smrg *
160d16fef4Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
170d16fef4Smrg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
180d16fef4Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
190d16fef4Smrg * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
200d16fef4Smrg * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
210d16fef4Smrg * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
220d16fef4Smrg * SOFTWARE.
230d16fef4Smrg *
240d16fef4Smrg * Authors:
250d16fef4Smrg *    Dave Airlie <airlied@redhat.com>
260d16fef4Smrg *
270d16fef4Smrg */
280d16fef4Smrg
290d16fef4Smrg#ifndef _RADEON_DRM_QUEUE_H_
300d16fef4Smrg#define _RADEON_DRM_QUEUE_H_
310d16fef4Smrg
327314432eSmrg#define RADEON_DRM_QUEUE_ERROR 0
337314432eSmrg
340d16fef4Smrg#define RADEON_DRM_QUEUE_CLIENT_DEFAULT serverClient
350d16fef4Smrg#define RADEON_DRM_QUEUE_ID_DEFAULT ~0ULL
360d16fef4Smrg
370d16fef4Smrgstruct radeon_drm_queue_entry;
380d16fef4Smrg
390d16fef4Smrgtypedef void (*radeon_drm_handler_proc)(xf86CrtcPtr crtc, uint32_t seq,
400d16fef4Smrg					uint64_t usec, void *data);
410d16fef4Smrgtypedef void (*radeon_drm_abort_proc)(xf86CrtcPtr crtc, void *data);
420d16fef4Smrg
4339413783Smrgvoid radeon_drm_queue_handle_deferred(xf86CrtcPtr crtc);
440d16fef4Smrguintptr_t radeon_drm_queue_alloc(xf86CrtcPtr crtc, ClientPtr client,
450d16fef4Smrg				 uint64_t id, void *data,
460d16fef4Smrg				 radeon_drm_handler_proc handler,
47446f62d6Smrg				 radeon_drm_abort_proc abort,
48446f62d6Smrg				 Bool is_flip);
490d16fef4Smrgvoid radeon_drm_abort_client(ClientPtr client);
500d16fef4Smrgvoid radeon_drm_abort_entry(uintptr_t seq);
510d16fef4Smrgvoid radeon_drm_abort_id(uint64_t id);
5239413783Smrgint radeon_drm_handle_event(int fd, drmEventContext *event_context);
5339413783Smrgvoid radeon_drm_wait_pending_flip(xf86CrtcPtr crtc);
5439413783Smrgvoid radeon_drm_queue_init(ScrnInfoPtr scrn);
550d16fef4Smrgvoid radeon_drm_queue_close(ScrnInfoPtr scrn);
560d16fef4Smrg
570d16fef4Smrg#endif /* _RADEON_DRM_QUEUE_H_ */
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