1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 *                VA Linux Systems Inc., Fremont, California.
4 *
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation on the rights to use, copy, modify, merge,
11 * publish, distribute, sublicense, and/or sell copies of the Software,
12 * and to permit persons to whom the Software is furnished to do so,
13 * subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial
17 * portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
22 * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 */
28
29/*
30 * Authors:
31 *   Kevin E. Martin <martin@xfree86.org>
32 *
33 * Modified by Marc Aurele La France <tsi@xfree86.org> for ATI driver merge.
34 */
35
36#ifndef _RADEON_PROBE_H_
37#define _RADEON_PROBE_H_ 1
38
39#include <stdint.h>
40#include "xorg-server.h"
41#include "xf86str.h"
42#include "xf86DDC.h"
43#include "randrstr.h"
44
45#include "xf86Crtc.h"
46
47#ifdef XSERVER_PLATFORM_BUS
48#include "xf86platformBus.h"
49#endif
50
51#include "compat-api.h"
52#include "exa.h"
53
54extern DriverRec RADEON;
55
56typedef enum {
57    CHIP_FAMILY_UNKNOW,
58    CHIP_FAMILY_LEGACY,
59    CHIP_FAMILY_RADEON,
60    CHIP_FAMILY_RV100,
61    CHIP_FAMILY_RS100,    /* U1 (IGP320M) or A3 (IGP320)*/
62    CHIP_FAMILY_RV200,
63    CHIP_FAMILY_RS200,    /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */
64    CHIP_FAMILY_R200,
65    CHIP_FAMILY_RV250,
66    CHIP_FAMILY_RS300,    /* RS300/RS350 */
67    CHIP_FAMILY_RV280,
68    CHIP_FAMILY_R300,
69    CHIP_FAMILY_R350,
70    CHIP_FAMILY_RV350,
71    CHIP_FAMILY_RV380,    /* RV370/RV380/M22/M24 */
72    CHIP_FAMILY_R420,     /* R420/R423/M18 */
73    CHIP_FAMILY_RV410,    /* RV410, M26 */
74    CHIP_FAMILY_RS400,    /* xpress 200, 200m (RS400) Intel */
75    CHIP_FAMILY_RS480,    /* xpress 200, 200m (RS410/480/482/485) AMD */
76    CHIP_FAMILY_RV515,    /* rv515 */
77    CHIP_FAMILY_R520,    /* r520 */
78    CHIP_FAMILY_RV530,    /* rv530 */
79    CHIP_FAMILY_R580,    /* r580 */
80    CHIP_FAMILY_RV560,   /* rv560 */
81    CHIP_FAMILY_RV570,   /* rv570 */
82    CHIP_FAMILY_RS600,
83    CHIP_FAMILY_RS690,
84    CHIP_FAMILY_RS740,
85    CHIP_FAMILY_R600,    /* r600 */
86    CHIP_FAMILY_RV610,
87    CHIP_FAMILY_RV630,
88    CHIP_FAMILY_RV670,
89    CHIP_FAMILY_RV620,
90    CHIP_FAMILY_RV635,
91    CHIP_FAMILY_RS780,
92    CHIP_FAMILY_RS880,
93    CHIP_FAMILY_RV770,   /* r700 */
94    CHIP_FAMILY_RV730,
95    CHIP_FAMILY_RV710,
96    CHIP_FAMILY_RV740,
97    CHIP_FAMILY_CEDAR,   /* evergreen */
98    CHIP_FAMILY_REDWOOD,
99    CHIP_FAMILY_JUNIPER,
100    CHIP_FAMILY_CYPRESS,
101    CHIP_FAMILY_HEMLOCK,
102    CHIP_FAMILY_PALM,
103    CHIP_FAMILY_SUMO,
104    CHIP_FAMILY_SUMO2,
105    CHIP_FAMILY_BARTS,
106    CHIP_FAMILY_TURKS,
107    CHIP_FAMILY_CAICOS,
108    CHIP_FAMILY_CAYMAN,
109    CHIP_FAMILY_ARUBA,
110    CHIP_FAMILY_TAHITI,
111    CHIP_FAMILY_PITCAIRN,
112    CHIP_FAMILY_VERDE,
113    CHIP_FAMILY_OLAND,
114    CHIP_FAMILY_HAINAN,
115    CHIP_FAMILY_BONAIRE,
116    CHIP_FAMILY_KAVERI,
117    CHIP_FAMILY_KABINI,
118    CHIP_FAMILY_HAWAII,
119    CHIP_FAMILY_MULLINS,
120    CHIP_FAMILY_LAST
121} RADEONChipFamily;
122
123typedef struct {
124    uint32_t pci_device_id;
125    RADEONChipFamily chip_family;
126    int mobility;
127    int igp;
128    int nocrtc2;
129    int nointtvout;
130    int singledac;
131} RADEONCardInfo;
132
133typedef struct
134{
135    Bool              HasCRTC2;         /* All cards except original Radeon  */
136    Bool has_page_flip_target;
137
138    int fd;                             /* for sharing across zaphod heads   */
139    int fd_ref;
140    unsigned long     fd_wakeup_registered; /* server generation for which fd has been registered for wakeup handling */
141    int fd_wakeup_ref;
142    unsigned int assigned_crtcs;
143    unsigned int num_scrns;
144    ScrnInfoPtr scrn[6];
145#ifdef XSERVER_PLATFORM_BUS
146    struct xf86_platform_device *platform_dev;
147#endif
148    char *render_node;
149} RADEONEntRec, *RADEONEntPtr;
150
151extern const OptionInfoRec *RADEONOptionsWeak(void);
152
153extern Bool                 RADEONPreInit_KMS(ScrnInfoPtr, int);
154extern Bool                 RADEONScreenInit_KMS(ScreenPtr pScreen, int argc, char **argv);
155extern Bool                 RADEONSwitchMode_KMS(ScrnInfoPtr pScrn, DisplayModePtr mode);
156extern void                 RADEONAdjustFrame_KMS(ScrnInfoPtr pScrn, int x, int y);
157extern Bool                 RADEONEnterVT_KMS(ScrnInfoPtr pScrn);
158extern void                 RADEONLeaveVT_KMS(ScrnInfoPtr pScrn);
159extern void                 RADEONFreeScreen_KMS(ScrnInfoPtr pScrn);
160
161extern ModeStatus           RADEONValidMode(ScrnInfoPtr pScrn, DisplayModePtr mode,
162					    Bool verbose, int flag);
163#endif /* _RADEON_PROBE_H_ */
164