1/*
2 * Evergreen shaders
3 *
4 * Copyright (C) 2010  Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24/*
25 * Shader macros
26 */
27
28#ifndef __SHADER_H__
29#define __SHADER_H__
30
31#include "radeon.h"
32
33/* Oder of instructions: All CF, All ALU, All Tex/Vtx fetches */
34
35
36// CF insts
37// addr
38#define ADDR(x)  (x)
39// jumptable
40#define JUMPTABLE_SEL(x) (x)
41// pc
42#define POP_COUNT(x)      (x)
43// const
44#define CF_CONST(x)       (x)
45// cond
46#define COND(x)        (x)		// SQ_COND_*
47// count
48#define I_COUNT(x)        ((x) ? ((x) - 1) : 0)
49// vpm
50#define VALID_PIXEL_MODE(x) (x)
51// eop
52#define END_OF_PROGRAM(x)   (x)
53// cf inst
54#define CF_INST(x)        (x)		// SQ_CF_INST_*
55// wqm
56#define WHOLE_QUAD_MODE(x)  (x)
57// barrier
58#define BARRIER(x)          (x)
59//kb0
60#define KCACHE_BANK0(x)          (x)
61//kb1
62#define KCACHE_BANK1(x)          (x)
63// km0/1
64#define KCACHE_MODE0(x)          (x)
65#define KCACHE_MODE1(x)          (x)	// SQ_CF_KCACHE_*
66//
67#define KCACHE_ADDR0(x)          (x)
68#define KCACHE_ADDR1(x)          (x)
69
70#define ALT_CONST(x)            (x)
71
72#define ARRAY_BASE(x)        (x)
73// export pixel
74#define CF_PIXEL_MRT0         0
75#define CF_PIXEL_MRT1         1
76#define CF_PIXEL_MRT2         2
77#define CF_PIXEL_MRT3         3
78#define CF_PIXEL_MRT4         4
79#define CF_PIXEL_MRT5         5
80#define CF_PIXEL_MRT6         6
81#define CF_PIXEL_MRT7         7
82// computed Z
83#define CF_COMPUTED_Z         61
84// export pos
85#define CF_POS0               60
86#define CF_POS1               61
87#define CF_POS2               62
88#define CF_POS3               63
89// export param
90// 0...31
91#define TYPE(x)              (x)	// SQ_EXPORT_*
92#define RW_GPR(x)            (x)
93#define RW_REL(x)            (x)
94#define ABSOLUTE                  0
95#define RELATIVE                  1
96#define INDEX_GPR(x)            (x)
97#define ELEM_SIZE(x)            (x ? (x - 1) : 0)
98#define BURST_COUNT(x)          (x ? (x - 1) : 0)
99#define MARK(x)         (x)
100
101// swiz
102#define SRC_SEL_X(x)    (x)		// SQ_SEL_* each
103#define SRC_SEL_Y(x)    (x)
104#define SRC_SEL_Z(x)    (x)
105#define SRC_SEL_W(x)    (x)
106
107#define CF_DWORD0(addr, jmptbl) cpu_to_le32(((addr) | ((jmptbl) << 24)))
108#define CF_DWORD1(pc, cf_const, cond, count, vpm, eop, cf_inst, wqm, b) \
109    cpu_to_le32((((pc) << 0) | ((cf_const) << 3) | ((cond) << 8) | ((count) << 10) | \
110		 ((vpm) << 20) | ((eop) << 21) | ((cf_inst) << 22) | ((wqm) << 30) | ((b) << 31)))
111
112#define CF_ALU_DWORD0(addr, kb0, kb1, km0) cpu_to_le32((((addr) << 0) | ((kb0) << 22) | ((kb1) << 26) | ((km0) << 30)))
113#define CF_ALU_DWORD1(km1, kcache_addr0, kcache_addr1, count, alt_const, cf_inst, wqm, b) \
114    cpu_to_le32((((km1) << 0) | ((kcache_addr0) << 2) | ((kcache_addr1) << 10) | \
115		 ((count) << 18) | ((alt_const) << 25) | ((cf_inst) << 26) | ((wqm) << 30) | ((b) << 31)))
116
117#define CF_ALLOC_IMP_EXP_DWORD0(array_base, type, rw_gpr, rr, index_gpr, es) \
118    cpu_to_le32((((array_base) << 0) | ((type) << 13) | ((rw_gpr) << 15) | ((rr) << 22) | \
119		 ((index_gpr) << 23) | ((es) << 30)))
120#define CF_ALLOC_IMP_EXP_DWORD1_SWIZ(sel_x, sel_y, sel_z, sel_w, bc, vpm, eop, cf_inst, m, b) \
121    cpu_to_le32((((sel_x) << 0) | ((sel_y) << 3) | ((sel_z) << 6) | ((sel_w) << 9) | \
122		 ((bc) << 16) | ((vpm) << 20) | ((eop) << 21) | ((cf_inst) << 22) | \
123		 ((m) << 30) | ((b) << 31)))
124
125// ALU clause insts
126#define SRC0_SEL(x)        (x)
127#define SRC1_SEL(x)        (x)
128#define SRC2_SEL(x)        (x)
129// src[0-2]_sel
130//   0-127 GPR
131// 128-159 kcache constants bank 0
132// 160-191 kcache constants bank 1
133// 192-255 inline const values
134// 256-287 kcache constants bank 2
135// 288-319 kcache constants bank 3
136// 219-255 special SQ_ALU_SRC_* (0, 1, etc.)
137// 488-520 src param space
138#define ALU_SRC_GPR_BASE        0
139#define ALU_SRC_KCACHE0_BASE  128
140#define ALU_SRC_KCACHE1_BASE  160
141#define ALU_SRC_INLINE_K_BASE 192
142#define ALU_SRC_KCACHE2_BASE  256
143#define ALU_SRC_KCACHE3_BASE  288
144#define ALU_SRC_PARAM_BASE    448
145
146#define SRC0_REL(x)        (x)
147#define SRC1_REL(x)        (x)
148#define SRC2_REL(x)        (x)
149// elem
150#define SRC0_ELEM(x)        (x)
151#define SRC1_ELEM(x)        (x)
152#define SRC2_ELEM(x)        (x)
153#define ELEM_X        0
154#define ELEM_Y        1
155#define ELEM_Z        2
156#define ELEM_W        3
157// neg
158#define SRC0_NEG(x)        (x)
159#define SRC1_NEG(x)        (x)
160#define SRC2_NEG(x)        (x)
161// im
162#define INDEX_MODE(x)    (x)		// SQ_INDEX_*
163// ps
164#define PRED_SEL(x)      (x)		// SQ_PRED_SEL_*
165// last
166#define LAST(x)          (x)
167// abs
168#define SRC0_ABS(x)       (x)
169#define SRC1_ABS(x)       (x)
170// uem
171#define UPDATE_EXECUTE_MASK(x) (x)
172// up
173#define UPDATE_PRED(x)      (x)
174// wm
175#define WRITE_MASK(x)   (x)
176// omod
177#define OMOD(x)        (x)		// SQ_ALU_OMOD_*
178// alu inst
179#define ALU_INST(x)        (x)		// SQ_ALU_INST_*
180//bs
181#define BANK_SWIZZLE(x)        (x)	// SQ_ALU_VEC_*
182#define DST_GPR(x)        (x)
183#define DST_REL(x)        (x)
184#define DST_ELEM(x)       (x)
185#define CLAMP(x)          (x)
186
187#define ALU_DWORD0(src0_sel, s0r, s0e, s0n, src1_sel, s1r, s1e, s1n, im, ps, last) \
188    cpu_to_le32((((src0_sel) << 0) | ((s0r) << 9) | ((s0e) << 10) | ((s0n) << 12) | \
189		 ((src1_sel) << 13) | ((s1r) << 22) | ((s1e) << 23) | ((s1n) << 25) | \
190		 ((im) << 26) | ((ps) << 29) | ((last) << 31)))
191
192#define ALU_DWORD1_OP2(s0a, s1a, uem, up, wm, omod, alu_inst, bs, dst_gpr, dr, de, clamp) \
193    cpu_to_le32((((s0a) << 0) | ((s1a) << 1) | ((uem) << 2) | ((up) << 3) | ((wm) << 4) | \
194		 ((omod) << 5) | ((alu_inst) << 7) | ((bs) << 18) | ((dst_gpr) << 21) | \
195		 ((dr) << 28) | ((de) << 29) | ((clamp) << 31)))
196
197#define ALU_DWORD1_OP3(src2_sel, s2r, s2e, s2n, alu_inst, bs, dst_gpr, dr, de, clamp) \
198    cpu_to_le32((((src2_sel) << 0) | ((s2r) << 9) | ((s2e) << 10) | ((s2n) << 12) | \
199		 ((alu_inst) << 13) | ((bs) << 18) | ((dst_gpr) << 21) | ((dr) << 28) | \
200		 ((de) << 29) | ((clamp) << 31)))
201
202// VTX clause insts
203// vxt insts
204#define VTX_INST(x)        (x)		// SQ_VTX_INST_*
205
206// fetch type
207#define FETCH_TYPE(x)        (x)	// SQ_VTX_FETCH_*
208
209#define FETCH_WHOLE_QUAD(x)        (x)
210#define BUFFER_ID(x)        (x)
211#define SRC_GPR(x)          (x)
212#define SRC_REL(x)          (x)
213#define MEGA_FETCH_COUNT(x)        ((x) ? ((x) - 1) : 0)
214
215#define DST_SEL_X(x)          (x)
216#define DST_SEL_Y(x)          (x)
217#define DST_SEL_Z(x)          (x)
218#define DST_SEL_W(x)          (x)
219#define USE_CONST_FIELDS(x)   (x)
220#define DATA_FORMAT(x)        (x)
221// num format
222#define NUM_FORMAT_ALL(x)     (x)	// SQ_NUM_FORMAT_*
223// format comp
224#define FORMAT_COMP_ALL(x)     (x)	// SQ_FORMAT_COMP_*
225// sma
226#define SRF_MODE_ALL(x)     (x)
227#define SRF_MODE_ZERO_CLAMP_MINUS_ONE      0
228#define SRF_MODE_NO_ZERO                   1
229#define OFFSET(x)     (x)
230// endian swap
231#define ENDIAN_SWAP(x)     (x)		// SQ_ENDIAN_*
232#define CONST_BUF_NO_STRIDE(x)     (x)
233// mf
234#define MEGA_FETCH(x)     (x)
235#define BUFFER_INDEX_MODE(x) (x)
236
237#define VTX_DWORD0(vtx_inst, ft, fwq, buffer_id, src_gpr, sr, ssx, mfc) \
238    cpu_to_le32((((vtx_inst) << 0) | ((ft) << 5) | ((fwq) << 7) | ((buffer_id) << 8) | \
239		 ((src_gpr) << 16) | ((sr) << 23) | ((ssx) << 24) | ((mfc) << 26)))
240#define VTX_DWORD1_GPR(dst_gpr, dr, dsx, dsy, dsz, dsw, ucf, data_format, nfa, fca, sma) \
241    cpu_to_le32((((dst_gpr) << 0) | ((dr) << 7) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \
242		 ((ucf) << 21) | ((data_format) << 22) | ((nfa) << 28) | ((fca) << 30) | ((sma) << 31)))
243#define VTX_DWORD2(offset, es, cbns, mf, alt_const, bim)			\
244    cpu_to_le32((((offset) << 0) | ((es) << 16) | ((cbns) << 18) | ((mf) << 19) | ((alt_const) << 20) | ((bim) << 21)))
245#define VTX_DWORD_PAD cpu_to_le32(0x00000000)
246
247// TEX clause insts
248// tex insts
249#define TEX_INST(x)     (x)		// SQ_TEX_INST_*
250#define INST_MOD(x)     (x)
251#define FETCH_WHOLE_QUAD(x)     (x)
252#define RESOURCE_ID(x)          (x)
253#define RESOURCE_INDEX_MODE(x)          (x)
254#define SAMPLER_INDEX_MODE(x)          (x)
255
256#define LOD_BIAS(x)     (x)
257//ct
258#define COORD_TYPE_X(x)     (x)
259#define COORD_TYPE_Y(x)     (x)
260#define COORD_TYPE_Z(x)     (x)
261#define COORD_TYPE_W(x)     (x)
262#define TEX_UNNORMALIZED                0
263#define TEX_NORMALIZED                  1
264#define OFFSET_X(x) (((int)(x) * 2) & 0x1f) /* 4:1-bits 2's-complement fixed-point: [-8.0..7.5] */
265#define OFFSET_Y(x) (((int)(x) * 2) & 0x1f)
266#define OFFSET_Z(x) (((int)(x) * 2) & 0x1f)
267#define SAMPLER_ID(x)     (x)
268
269#define TEX_DWORD0(tex_inst, im, fwq, resource_id, src_gpr, sr, ac, rim, sim) \
270    cpu_to_le32((((tex_inst) << 0) | ((im) << 5) | ((fwq) << 7) | ((resource_id) << 8) | \
271		 ((src_gpr) << 16) | ((sr) << 23) | ((ac) << 24) | ((rim) << 25) | ((sim) << 27)))
272#define TEX_DWORD1(dst_gpr, dr, dsx, dsy, dsz, dsw, lod_bias, ctx, cty, ctz, ctw) \
273    cpu_to_le32((((dst_gpr) << 0) | ((dr) << 7) | ((dsx) << 9) | ((dsy) << 12) | ((dsz) << 15) | ((dsw) << 18) | \
274		 ((lod_bias) << 21) | ((ctx) << 28) | ((cty) << 29) | ((ctz) << 30) | ((ctw) << 31)))
275#define TEX_DWORD2(offset_x, offset_y, offset_z, sampler_id, ssx, ssy, ssz, ssw) \
276    cpu_to_le32((((offset_x) << 0) | ((offset_y) << 5) | ((offset_z) << 10) | ((sampler_id) << 15) | \
277		 ((ssx) << 20) | ((ssy) << 23) | ((ssz) << 26) | ((ssw) << 29)))
278#define TEX_DWORD_PAD cpu_to_le32(0x00000000)
279
280extern int evergreen_solid_vs(RADEONChipFamily ChipSet, uint32_t* vs);
281extern int evergreen_solid_ps(RADEONChipFamily ChipSet, uint32_t* ps);
282
283extern int evergreen_copy_vs(RADEONChipFamily ChipSet, uint32_t* vs);
284extern int evergreen_copy_ps(RADEONChipFamily ChipSet, uint32_t* ps);
285
286extern int evergreen_xv_vs(RADEONChipFamily ChipSet, uint32_t* shader);
287extern int evergreen_xv_ps(RADEONChipFamily ChipSet, uint32_t* shader);
288
289extern int evergreen_comp_vs(RADEONChipFamily ChipSet, uint32_t* vs);
290extern int evergreen_comp_ps(RADEONChipFamily ChipSet, uint32_t* ps);
291
292#endif
293