legacy_crtc.c revision 1764dec5
1/* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining 8 * a copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation on the rights to use, copy, modify, merge, 11 * publish, distribute, sublicense, and/or sell copies of the Software, 12 * and to permit persons to whom the Software is furnished to do so, 13 * subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 */ 28 29#ifdef HAVE_CONFIG_H 30#include "config.h" 31#endif 32 33#include <string.h> 34#include <stdio.h> 35 36/* X and server generic header files */ 37#include "xf86.h" 38#include "xf86_OSproc.h" 39#include "vgaHW.h" 40#include "xf86Modes.h" 41 42/* Driver data structures */ 43#include "radeon.h" 44#include "radeon_reg.h" 45#include "radeon_macros.h" 46#include "radeon_probe.h" 47#include "radeon_version.h" 48#include "radeon_atombios.h" 49 50#ifdef XF86DRI 51#define _XF86DRI_SERVER_ 52#include "radeon_drm.h" 53#include "sarea.h" 54#ifdef DRM_IOCTL_MODESET_CTL 55#include <sys/ioctl.h> 56#endif 57#endif 58 59/* Write common registers */ 60void 61RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, 62 RADEONSavePtr restore) 63{ 64 RADEONInfoPtr info = RADEONPTR(pScrn); 65 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 66 unsigned char *RADEONMMIO = info->MMIO; 67 68 if (info->IsSecondary) 69 return; 70 71 OUTREG(RADEON_OVR_CLR, restore->ovr_clr); 72 OUTREG(RADEON_OVR_WID_LEFT_RIGHT, restore->ovr_wid_left_right); 73 OUTREG(RADEON_OVR_WID_TOP_BOTTOM, restore->ovr_wid_top_bottom); 74 OUTREG(RADEON_OV0_SCALE_CNTL, restore->ov0_scale_cntl); 75 OUTREG(RADEON_SUBPIC_CNTL, restore->subpic_cntl); 76 OUTREG(RADEON_VIPH_CONTROL, restore->viph_control); 77 OUTREG(RADEON_I2C_CNTL_1, restore->i2c_cntl_1); 78 OUTREG(RADEON_GEN_INT_CNTL, restore->gen_int_cntl); 79 OUTREG(RADEON_CAP0_TRIG_CNTL, restore->cap0_trig_cntl); 80 OUTREG(RADEON_CAP1_TRIG_CNTL, restore->cap1_trig_cntl); 81 OUTREG(RADEON_BUS_CNTL, restore->bus_cntl); 82 OUTREG(RADEON_SURFACE_CNTL, restore->surface_cntl); 83 84 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 85 (info->ChipFamily == CHIP_FAMILY_RS480)) { 86 OUTREG(RS400_DISP2_REQ_CNTL1, restore->disp2_req_cntl1); 87 OUTREG(RS400_DISP2_REQ_CNTL2, restore->disp2_req_cntl2); 88 OUTREG(RS400_DMIF_MEM_CNTL1, restore->dmif_mem_cntl1); 89 OUTREG(RS400_DISP1_REQ_CNTL1, restore->disp1_req_cntl1); 90 } 91 92 /* Workaround for the VT switching problem in dual-head mode. This 93 * problem only occurs on RV style chips, typically when a FP and 94 * CRT are connected. 95 */ 96 if (pRADEONEnt->HasCRTC2 && 97 info->ChipFamily != CHIP_FAMILY_R200 && 98 !IS_R300_VARIANT) { 99 uint32_t tmp; 100 101 tmp = INREG(RADEON_DAC_CNTL2); 102 OUTREG(RADEON_DAC_CNTL2, tmp & ~RADEON_DAC2_DAC_CLK_SEL); 103 usleep(100000); 104 } 105} 106 107void 108RADEONRestoreCrtcBase(ScrnInfoPtr pScrn, 109 RADEONSavePtr restore) 110{ 111 RADEONInfoPtr info = RADEONPTR(pScrn); 112 unsigned char *RADEONMMIO = info->MMIO; 113 114 if (IS_R300_VARIANT) 115 OUTREG(R300_CRTC_TILE_X0_Y0, restore->crtc_tile_x0_y0); 116 OUTREG(RADEON_CRTC_OFFSET_CNTL, restore->crtc_offset_cntl); 117 OUTREG(RADEON_CRTC_OFFSET, restore->crtc_offset); 118} 119 120void 121RADEONRestoreCrtc2Base(ScrnInfoPtr pScrn, 122 RADEONSavePtr restore) 123{ 124 RADEONInfoPtr info = RADEONPTR(pScrn); 125 unsigned char *RADEONMMIO = info->MMIO; 126 127 if (IS_R300_VARIANT) 128 OUTREG(R300_CRTC2_TILE_X0_Y0, restore->crtc2_tile_x0_y0); 129 OUTREG(RADEON_CRTC2_OFFSET_CNTL, restore->crtc2_offset_cntl); 130 OUTREG(RADEON_CRTC2_OFFSET, restore->crtc2_offset); 131} 132 133/* Write CRTC registers */ 134void 135RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn, 136 RADEONSavePtr restore) 137{ 138 RADEONInfoPtr info = RADEONPTR(pScrn); 139 unsigned char *RADEONMMIO = info->MMIO; 140 141 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 142 "Programming CRTC1, offset: 0x%08x\n", 143 (unsigned)restore->crtc_offset); 144 145 /* We prevent the CRTC from hitting the memory controller until 146 * fully programmed 147 */ 148 OUTREG(RADEON_CRTC_GEN_CNTL, restore->crtc_gen_cntl | 149 RADEON_CRTC_DISP_REQ_EN_B); 150 151 OUTREGP(RADEON_CRTC_EXT_CNTL, 152 restore->crtc_ext_cntl, 153 RADEON_CRTC_VSYNC_DIS | 154 RADEON_CRTC_HSYNC_DIS | 155 RADEON_CRTC_DISPLAY_DIS); 156 157 OUTREG(RADEON_CRTC_H_TOTAL_DISP, restore->crtc_h_total_disp); 158 OUTREG(RADEON_CRTC_H_SYNC_STRT_WID, restore->crtc_h_sync_strt_wid); 159 OUTREG(RADEON_CRTC_V_TOTAL_DISP, restore->crtc_v_total_disp); 160 OUTREG(RADEON_CRTC_V_SYNC_STRT_WID, restore->crtc_v_sync_strt_wid); 161 162 RADEONRestoreCrtcBase(pScrn, restore); 163 164 OUTREG(RADEON_CRTC_PITCH, restore->crtc_pitch); 165 OUTREG(RADEON_DISP_MERGE_CNTL, restore->disp_merge_cntl); 166 167 if (info->IsDellServer) { 168 OUTREG(RADEON_TV_DAC_CNTL, restore->tv_dac_cntl); 169 OUTREG(RADEON_DISP_HW_DEBUG, restore->disp_hw_debug); 170 OUTREG(RADEON_DAC_CNTL2, restore->dac2_cntl); 171 OUTREG(RADEON_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl); 172 } 173 174 OUTREG(RADEON_CRTC_GEN_CNTL, restore->crtc_gen_cntl); 175} 176 177/* Write CRTC2 registers */ 178void 179RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, 180 RADEONSavePtr restore) 181{ 182 RADEONInfoPtr info = RADEONPTR(pScrn); 183 unsigned char *RADEONMMIO = info->MMIO; 184 /* uint32_t crtc2_gen_cntl;*/ 185 186 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 187 "Programming CRTC2, offset: 0x%08x\n", 188 (unsigned)restore->crtc2_offset); 189 190 /* We prevent the CRTC from hitting the memory controller until 191 * fully programmed 192 */ 193 OUTREG(RADEON_CRTC2_GEN_CNTL, 194 restore->crtc2_gen_cntl | RADEON_CRTC2_VSYNC_DIS | 195 RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_DIS | 196 RADEON_CRTC2_DISP_REQ_EN_B); 197 198 OUTREG(RADEON_CRTC2_H_TOTAL_DISP, restore->crtc2_h_total_disp); 199 OUTREG(RADEON_CRTC2_H_SYNC_STRT_WID, restore->crtc2_h_sync_strt_wid); 200 OUTREG(RADEON_CRTC2_V_TOTAL_DISP, restore->crtc2_v_total_disp); 201 OUTREG(RADEON_CRTC2_V_SYNC_STRT_WID, restore->crtc2_v_sync_strt_wid); 202 203 OUTREG(RADEON_FP_H2_SYNC_STRT_WID, restore->fp_h2_sync_strt_wid); 204 OUTREG(RADEON_FP_V2_SYNC_STRT_WID, restore->fp_v2_sync_strt_wid); 205 206 RADEONRestoreCrtc2Base(pScrn, restore); 207 208 OUTREG(RADEON_CRTC2_PITCH, restore->crtc2_pitch); 209 OUTREG(RADEON_DISP2_MERGE_CNTL, restore->disp2_merge_cntl); 210 211 OUTREG(RADEON_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl); 212 213} 214 215static void 216RADEONPLLWaitForReadUpdateComplete(ScrnInfoPtr pScrn) 217{ 218 int i = 0; 219 220 /* FIXME: Certain revisions of R300 can't recover here. Not sure of 221 the cause yet, but this workaround will mask the problem for now. 222 Other chips usually will pass at the very first test, so the 223 workaround shouldn't have any effect on them. */ 224 for (i = 0; 225 (i < 10000 && 226 INPLL(pScrn, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); 227 i++); 228} 229 230static void 231RADEONPLLWriteUpdate(ScrnInfoPtr pScrn) 232{ 233 while (INPLL(pScrn, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); 234 235 OUTPLLP(pScrn, RADEON_PPLL_REF_DIV, 236 RADEON_PPLL_ATOMIC_UPDATE_W, 237 ~(RADEON_PPLL_ATOMIC_UPDATE_W)); 238} 239 240static void 241RADEONPLL2WaitForReadUpdateComplete(ScrnInfoPtr pScrn) 242{ 243 int i = 0; 244 245 /* FIXME: Certain revisions of R300 can't recover here. Not sure of 246 the cause yet, but this workaround will mask the problem for now. 247 Other chips usually will pass at the very first test, so the 248 workaround shouldn't have any effect on them. */ 249 for (i = 0; 250 (i < 10000 && 251 INPLL(pScrn, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); 252 i++); 253} 254 255static void 256RADEONPLL2WriteUpdate(ScrnInfoPtr pScrn) 257{ 258 while (INPLL(pScrn, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); 259 260 OUTPLLP(pScrn, RADEON_P2PLL_REF_DIV, 261 RADEON_P2PLL_ATOMIC_UPDATE_W, 262 ~(RADEON_P2PLL_ATOMIC_UPDATE_W)); 263} 264 265static uint8_t 266RADEONComputePLLGain(uint16_t reference_freq, uint16_t ref_div, 267 uint16_t fb_div) 268{ 269 unsigned vcoFreq; 270 271 if (!ref_div) 272 return 1; 273 274 vcoFreq = ((unsigned)reference_freq * fb_div) / ref_div; 275 276 /* 277 * This is horribly crude: the VCO frequency range is divided into 278 * 3 parts, each part having a fixed PLL gain value. 279 */ 280 if (vcoFreq >= 30000) 281 /* 282 * [300..max] MHz : 7 283 */ 284 return 7; 285 else if (vcoFreq >= 18000) 286 /* 287 * [180..300) MHz : 4 288 */ 289 return 4; 290 else 291 /* 292 * [0..180) MHz : 1 293 */ 294 return 1; 295} 296 297/* Write PLL registers */ 298void 299RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, 300 RADEONSavePtr restore) 301{ 302 RADEONInfoPtr info = RADEONPTR(pScrn); 303 unsigned char *RADEONMMIO = info->MMIO; 304 uint8_t pllGain; 305 306#if defined(__powerpc__) 307 /* apparently restoring the pll causes a hang??? */ 308 if ((info->MacModel == RADEON_MAC_IBOOK) || 309 (info->MacModel == RADEON_MAC_MINI_INTERNAL)) 310 return; 311#endif 312 313 pllGain = RADEONComputePLLGain(info->pll.reference_freq, 314 restore->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK, 315 restore->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK); 316 317 if (info->IsMobility) { 318 /* A temporal workaround for the occational blanking on certain laptop panels. 319 This appears to related to the PLL divider registers (fail to lock?). 320 It occurs even when all dividers are the same with their old settings. 321 In this case we really don't need to fiddle with PLL registers. 322 By doing this we can avoid the blanking problem with some panels. 323 */ 324 if ((restore->ppll_ref_div == (INPLL(pScrn, RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && 325 (restore->ppll_div_3 == (INPLL(pScrn, RADEON_PPLL_DIV_3) & 326 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) { 327 OUTREGP(RADEON_CLOCK_CNTL_INDEX, 328 RADEON_PLL_DIV_SEL, 329 ~(RADEON_PLL_DIV_SEL)); 330 RADEONPllErrataAfterIndex(info); 331 return; 332 } 333 } 334 335 OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL, 336 RADEON_VCLK_SRC_SEL_CPUCLK, 337 ~(RADEON_VCLK_SRC_SEL_MASK)); 338 339 OUTPLLP(pScrn, 340 RADEON_PPLL_CNTL, 341 RADEON_PPLL_RESET 342 | RADEON_PPLL_ATOMIC_UPDATE_EN 343 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN 344 | ((uint32_t)pllGain << RADEON_PPLL_PVG_SHIFT), 345 ~(RADEON_PPLL_RESET 346 | RADEON_PPLL_ATOMIC_UPDATE_EN 347 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN 348 | RADEON_PPLL_PVG_MASK)); 349 350 OUTREGP(RADEON_CLOCK_CNTL_INDEX, 351 RADEON_PLL_DIV_SEL, 352 ~(RADEON_PLL_DIV_SEL)); 353 RADEONPllErrataAfterIndex(info); 354 355 if (IS_R300_VARIANT || 356 (info->ChipFamily == CHIP_FAMILY_RS300) || 357 (info->ChipFamily == CHIP_FAMILY_RS400) || 358 (info->ChipFamily == CHIP_FAMILY_RS480)) { 359 if (restore->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { 360 /* When restoring console mode, use saved PPLL_REF_DIV 361 * setting. 362 */ 363 OUTPLLP(pScrn, RADEON_PPLL_REF_DIV, 364 restore->ppll_ref_div, 365 0); 366 } else { 367 /* R300 uses ref_div_acc field as real ref divider */ 368 OUTPLLP(pScrn, RADEON_PPLL_REF_DIV, 369 (restore->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), 370 ~R300_PPLL_REF_DIV_ACC_MASK); 371 } 372 } else { 373 OUTPLLP(pScrn, RADEON_PPLL_REF_DIV, 374 restore->ppll_ref_div, 375 ~RADEON_PPLL_REF_DIV_MASK); 376 } 377 378 OUTPLLP(pScrn, RADEON_PPLL_DIV_3, 379 restore->ppll_div_3, 380 ~RADEON_PPLL_FB3_DIV_MASK); 381 382 OUTPLLP(pScrn, RADEON_PPLL_DIV_3, 383 restore->ppll_div_3, 384 ~RADEON_PPLL_POST3_DIV_MASK); 385 386 RADEONPLLWriteUpdate(pScrn); 387 RADEONPLLWaitForReadUpdateComplete(pScrn); 388 389 OUTPLL(pScrn, RADEON_HTOTAL_CNTL, restore->htotal_cntl); 390 391 OUTPLLP(pScrn, RADEON_PPLL_CNTL, 392 0, 393 ~(RADEON_PPLL_RESET 394 | RADEON_PPLL_SLEEP 395 | RADEON_PPLL_ATOMIC_UPDATE_EN 396 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); 397 398 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 399 "Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", 400 restore->ppll_ref_div, 401 restore->ppll_div_3, 402 (unsigned)restore->htotal_cntl, 403 INPLL(pScrn, RADEON_PPLL_CNTL)); 404 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 405 "Wrote: rd=%d, fd=%d, pd=%d\n", 406 restore->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK, 407 restore->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK, 408 (restore->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16); 409 410 usleep(50000); /* Let the clock to lock */ 411 412 OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL, 413 RADEON_VCLK_SRC_SEL_PPLLCLK, 414 ~(RADEON_VCLK_SRC_SEL_MASK)); 415 416 /*OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, restore->vclk_ecp_cntl);*/ 417 418 ErrorF("finished PLL1\n"); 419 420} 421 422/* Write PLL2 registers */ 423void 424RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, 425 RADEONSavePtr restore) 426{ 427 RADEONInfoPtr info = RADEONPTR(pScrn); 428 uint8_t pllGain; 429 430 pllGain = RADEONComputePLLGain(info->pll.reference_freq, 431 restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, 432 restore->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK); 433 434 435 OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 436 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 437 ~(RADEON_PIX2CLK_SRC_SEL_MASK)); 438 439 OUTPLLP(pScrn, 440 RADEON_P2PLL_CNTL, 441 RADEON_P2PLL_RESET 442 | RADEON_P2PLL_ATOMIC_UPDATE_EN 443 | ((uint32_t)pllGain << RADEON_P2PLL_PVG_SHIFT), 444 ~(RADEON_P2PLL_RESET 445 | RADEON_P2PLL_ATOMIC_UPDATE_EN 446 | RADEON_P2PLL_PVG_MASK)); 447 448 449 OUTPLLP(pScrn, RADEON_P2PLL_REF_DIV, 450 restore->p2pll_ref_div, 451 ~RADEON_P2PLL_REF_DIV_MASK); 452 453 OUTPLLP(pScrn, RADEON_P2PLL_DIV_0, 454 restore->p2pll_div_0, 455 ~RADEON_P2PLL_FB0_DIV_MASK); 456 457 OUTPLLP(pScrn, RADEON_P2PLL_DIV_0, 458 restore->p2pll_div_0, 459 ~RADEON_P2PLL_POST0_DIV_MASK); 460 461 RADEONPLL2WriteUpdate(pScrn); 462 RADEONPLL2WaitForReadUpdateComplete(pScrn); 463 464 OUTPLL(pScrn, RADEON_HTOTAL2_CNTL, restore->htotal_cntl2); 465 466 OUTPLLP(pScrn, RADEON_P2PLL_CNTL, 467 0, 468 ~(RADEON_P2PLL_RESET 469 | RADEON_P2PLL_SLEEP 470 | RADEON_P2PLL_ATOMIC_UPDATE_EN)); 471 472 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 473 "Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n", 474 (unsigned)restore->p2pll_ref_div, 475 (unsigned)restore->p2pll_div_0, 476 (unsigned)restore->htotal_cntl2, 477 INPLL(pScrn, RADEON_P2PLL_CNTL)); 478 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 479 "Wrote2: rd=%u, fd=%u, pd=%u\n", 480 (unsigned)restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, 481 (unsigned)restore->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK, 482 (unsigned)((restore->p2pll_div_0 & 483 RADEON_P2PLL_POST0_DIV_MASK) >>16)); 484 485 usleep(5000); /* Let the clock to lock */ 486 487 OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 488 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 489 ~(RADEON_PIX2CLK_SRC_SEL_MASK)); 490 491 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, restore->pixclks_cntl); 492 493 ErrorF("finished PLL2\n"); 494 495} 496 497/* Read common registers */ 498void 499RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) 500{ 501 RADEONInfoPtr info = RADEONPTR(pScrn); 502 unsigned char *RADEONMMIO = info->MMIO; 503 504 save->ovr_clr = INREG(RADEON_OVR_CLR); 505 save->ovr_wid_left_right = INREG(RADEON_OVR_WID_LEFT_RIGHT); 506 save->ovr_wid_top_bottom = INREG(RADEON_OVR_WID_TOP_BOTTOM); 507 save->ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL); 508 save->subpic_cntl = INREG(RADEON_SUBPIC_CNTL); 509 save->viph_control = INREG(RADEON_VIPH_CONTROL); 510 save->i2c_cntl_1 = INREG(RADEON_I2C_CNTL_1); 511 save->gen_int_cntl = INREG(RADEON_GEN_INT_CNTL); 512 save->cap0_trig_cntl = INREG(RADEON_CAP0_TRIG_CNTL); 513 save->cap1_trig_cntl = INREG(RADEON_CAP1_TRIG_CNTL); 514 save->bus_cntl = INREG(RADEON_BUS_CNTL); 515 save->surface_cntl = INREG(RADEON_SURFACE_CNTL); 516 save->grph_buffer_cntl = INREG(RADEON_GRPH_BUFFER_CNTL); 517 save->grph2_buffer_cntl = INREG(RADEON_GRPH2_BUFFER_CNTL); 518 519 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 520 (info->ChipFamily == CHIP_FAMILY_RS480)) { 521 save->disp2_req_cntl1 = INREG(RS400_DISP2_REQ_CNTL1); 522 save->disp2_req_cntl2 = INREG(RS400_DISP2_REQ_CNTL2); 523 save->dmif_mem_cntl1 = INREG(RS400_DMIF_MEM_CNTL1); 524 save->disp1_req_cntl1 = INREG(RS400_DISP1_REQ_CNTL1); 525 } 526} 527 528/* Read CRTC registers */ 529void 530RADEONSaveCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) 531{ 532 RADEONInfoPtr info = RADEONPTR(pScrn); 533 unsigned char *RADEONMMIO = info->MMIO; 534 535 save->crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); 536 save->crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL); 537 save->crtc_h_total_disp = INREG(RADEON_CRTC_H_TOTAL_DISP); 538 save->crtc_h_sync_strt_wid = INREG(RADEON_CRTC_H_SYNC_STRT_WID); 539 save->crtc_v_total_disp = INREG(RADEON_CRTC_V_TOTAL_DISP); 540 save->crtc_v_sync_strt_wid = INREG(RADEON_CRTC_V_SYNC_STRT_WID); 541 542 save->crtc_offset = INREG(RADEON_CRTC_OFFSET); 543 save->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL); 544 save->crtc_pitch = INREG(RADEON_CRTC_PITCH); 545 save->disp_merge_cntl = INREG(RADEON_DISP_MERGE_CNTL); 546 547 if (IS_R300_VARIANT) 548 save->crtc_tile_x0_y0 = INREG(R300_CRTC_TILE_X0_Y0); 549 550 if (info->IsDellServer) { 551 save->tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL); 552 save->dac2_cntl = INREG(RADEON_DAC_CNTL2); 553 save->disp_hw_debug = INREG (RADEON_DISP_HW_DEBUG); 554 save->crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); 555 } 556 557 /* track if the crtc is enabled for text restore */ 558 if (save->crtc_ext_cntl & RADEON_CRTC_DISPLAY_DIS) 559 info->crtc_on = FALSE; 560 else 561 info->crtc_on = TRUE; 562 563} 564 565/* Read CRTC2 registers */ 566void 567RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save) 568{ 569 RADEONInfoPtr info = RADEONPTR(pScrn); 570 unsigned char *RADEONMMIO = info->MMIO; 571 572 save->crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); 573 save->crtc2_h_total_disp = INREG(RADEON_CRTC2_H_TOTAL_DISP); 574 save->crtc2_h_sync_strt_wid = INREG(RADEON_CRTC2_H_SYNC_STRT_WID); 575 save->crtc2_v_total_disp = INREG(RADEON_CRTC2_V_TOTAL_DISP); 576 save->crtc2_v_sync_strt_wid = INREG(RADEON_CRTC2_V_SYNC_STRT_WID); 577 578 save->crtc2_offset = INREG(RADEON_CRTC2_OFFSET); 579 save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL); 580 save->crtc2_pitch = INREG(RADEON_CRTC2_PITCH); 581 582 if (IS_R300_VARIANT) 583 save->crtc2_tile_x0_y0 = INREG(R300_CRTC2_TILE_X0_Y0); 584 585 save->fp_h2_sync_strt_wid = INREG (RADEON_FP_H2_SYNC_STRT_WID); 586 save->fp_v2_sync_strt_wid = INREG (RADEON_FP_V2_SYNC_STRT_WID); 587 588 save->disp2_merge_cntl = INREG(RADEON_DISP2_MERGE_CNTL); 589 590 /* track if the crtc is enabled for text restore */ 591 if (save->crtc2_gen_cntl & RADEON_CRTC2_DISP_DIS) 592 info->crtc2_on = FALSE; 593 else 594 info->crtc2_on = TRUE; 595 596} 597 598/* Read PLL registers */ 599void 600RADEONSavePLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) 601{ 602 save->ppll_ref_div = INPLL(pScrn, RADEON_PPLL_REF_DIV); 603 save->ppll_div_3 = INPLL(pScrn, RADEON_PPLL_DIV_3); 604 save->htotal_cntl = INPLL(pScrn, RADEON_HTOTAL_CNTL); 605 save->vclk_ecp_cntl = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); 606 607 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 608 "Read: 0x%08x 0x%08x 0x%08x\n", 609 save->ppll_ref_div, 610 save->ppll_div_3, 611 (unsigned)save->htotal_cntl); 612 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 613 "Read: rd=%d, fd=%d, pd=%d\n", 614 save->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK, 615 save->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK, 616 (save->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16); 617} 618 619/* Read PLL registers */ 620void 621RADEONSavePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save) 622{ 623 save->p2pll_ref_div = INPLL(pScrn, RADEON_P2PLL_REF_DIV); 624 save->p2pll_div_0 = INPLL(pScrn, RADEON_P2PLL_DIV_0); 625 save->htotal_cntl2 = INPLL(pScrn, RADEON_HTOTAL2_CNTL); 626 save->pixclks_cntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL); 627 628 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 629 "Read: 0x%08x 0x%08x 0x%08x\n", 630 (unsigned)save->p2pll_ref_div, 631 (unsigned)save->p2pll_div_0, 632 (unsigned)save->htotal_cntl2); 633 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 634 "Read: rd=%u, fd=%u, pd=%u\n", 635 (unsigned)(save->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK), 636 (unsigned)(save->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK), 637 (unsigned)((save->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK) 638 >> 16)); 639} 640 641void 642radeon_crtc_modeset_ioctl(xf86CrtcPtr crtc, Bool post) 643{ 644#if defined(XF86DRI) && defined(DRM_IOCTL_MODESET_CTL) 645 RADEONInfoPtr info = RADEONPTR(crtc->scrn); 646 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 647 struct drm_modeset_ctl modeset; 648 unsigned char *RADEONMMIO = info->MMIO; 649 650 if (!info->directRenderingEnabled) 651 return; 652 653 if (info->ChipFamily >= CHIP_FAMILY_R600) 654 return; 655 656 modeset.crtc = radeon_crtc->crtc_id; 657 modeset.cmd = post ? _DRM_POST_MODESET : _DRM_PRE_MODESET; 658 659 ioctl(info->dri->drmFD, DRM_IOCTL_MODESET_CTL, &modeset); 660 661 info->ModeReg->gen_int_cntl = INREG( RADEON_GEN_INT_CNTL ); 662#endif 663} 664 665void 666legacy_crtc_dpms(xf86CrtcPtr crtc, int mode) 667{ 668 uint32_t mask; 669 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 670 RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn); 671 unsigned char *RADEONMMIO = pRADEONEnt->MMIO; 672 673 if (radeon_crtc->crtc_id) 674 mask = (RADEON_CRTC2_EN | 675 RADEON_CRTC2_DISP_DIS | 676 RADEON_CRTC2_VSYNC_DIS | 677 RADEON_CRTC2_HSYNC_DIS | 678 RADEON_CRTC2_DISP_REQ_EN_B); 679 else 680 mask = (RADEON_CRTC_DISPLAY_DIS | 681 RADEON_CRTC_HSYNC_DIS | 682 RADEON_CRTC_VSYNC_DIS); 683 684 switch(mode) { 685 case DPMSModeOn: 686 if (radeon_crtc->crtc_id) { 687 OUTREGP(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~mask); 688 } else { 689 OUTREGP(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | RADEON_CRTC_DISP_REQ_EN_B)); 690 OUTREGP(RADEON_CRTC_EXT_CNTL, 0, ~mask); 691 } 692 break; 693 case DPMSModeStandby: 694 case DPMSModeSuspend: 695 case DPMSModeOff: 696 if (radeon_crtc->crtc_id) { 697 OUTREGP(RADEON_CRTC2_GEN_CNTL, mask, ~mask); 698 } else { 699 OUTREGP(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | RADEON_CRTC_DISP_REQ_EN_B)); 700 OUTREGP(RADEON_CRTC_EXT_CNTL, mask, ~mask); 701 } 702 break; 703 } 704} 705 706 707/* Define common registers for requested video mode */ 708void 709RADEONInitCommonRegisters(RADEONSavePtr save, RADEONInfoPtr info) 710{ 711 save->ovr_clr = 0; 712 save->ovr_wid_left_right = 0; 713 save->ovr_wid_top_bottom = 0; 714 save->ov0_scale_cntl = 0; 715 save->subpic_cntl = 0; 716 save->viph_control = 0; 717 save->i2c_cntl_1 = 0; 718 save->rbbm_soft_reset = 0; 719 save->cap0_trig_cntl = 0; 720 save->cap1_trig_cntl = 0; 721 save->bus_cntl = info->BusCntl; 722 723 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 724 (info->ChipFamily == CHIP_FAMILY_RS480)) { 725 save->disp2_req_cntl1 = info->SavedReg->disp2_req_cntl1; 726 save->disp2_req_cntl2 = info->SavedReg->disp2_req_cntl2; 727 save->dmif_mem_cntl1 = info->SavedReg->dmif_mem_cntl1; 728 save->disp1_req_cntl1 = info->SavedReg->disp1_req_cntl1; 729 } 730 731 /* 732 * If bursts are enabled, turn on discards 733 * Radeon doesn't have write bursts 734 */ 735 if (save->bus_cntl & (RADEON_BUS_READ_BURST)) 736 save->bus_cntl |= RADEON_BUS_RD_DISCARD_EN; 737} 738 739void 740RADEONInitSurfaceCntl(xf86CrtcPtr crtc, RADEONSavePtr save) 741{ 742 save->surface_cntl = 0; 743 744#if X_BYTE_ORDER == X_BIG_ENDIAN 745 /* We must set both apertures as they can be both used to map the entire 746 * video memory. -BenH. 747 */ 748 switch (crtc->scrn->bitsPerPixel) { 749 case 16: 750 save->surface_cntl |= RADEON_NONSURF_AP0_SWP_16BPP; 751 save->surface_cntl |= RADEON_NONSURF_AP1_SWP_16BPP; 752 break; 753 754 case 32: 755 save->surface_cntl |= RADEON_NONSURF_AP0_SWP_32BPP; 756 save->surface_cntl |= RADEON_NONSURF_AP1_SWP_32BPP; 757 break; 758 } 759#endif 760 761} 762 763void 764RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save, 765 int x, int y) 766{ 767 ScrnInfoPtr pScrn = crtc->scrn; 768 RADEONInfoPtr info = RADEONPTR(pScrn); 769 int Base; 770#ifdef XF86DRI 771 drm_radeon_sarea_t *pSAREAPriv; 772 XF86DRISAREAPtr pSAREA; 773#endif 774 775 save->crtc_offset = pScrn->fbOffset; 776#ifdef XF86DRI 777 if (info->dri && info->dri->allowPageFlip) 778 save->crtc_offset_cntl = RADEON_CRTC_OFFSET_FLIP_CNTL; 779 else 780#endif 781 save->crtc_offset_cntl = 0; 782 783 if (info->tilingEnabled && (crtc->rotatedData == NULL)) { 784 if (IS_R300_VARIANT) 785 save->crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | 786 R300_CRTC_MICRO_TILE_BUFFER_DIS | 787 R300_CRTC_MACRO_TILE_EN); 788 else 789 save->crtc_offset_cntl |= RADEON_CRTC_TILE_EN; 790 } 791 else { 792 if (IS_R300_VARIANT) 793 save->crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | 794 R300_CRTC_MICRO_TILE_BUFFER_DIS | 795 R300_CRTC_MACRO_TILE_EN); 796 else 797 save->crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN; 798 } 799 800 Base = pScrn->fbOffset; 801 802 if (info->tilingEnabled && (crtc->rotatedData == NULL)) { 803 if (IS_R300_VARIANT) { 804 /* On r300/r400 when tiling is enabled crtc_offset is set to the address of 805 * the surface. the x/y offsets are handled by the X_Y tile reg for each crtc 806 * Makes tiling MUCH easier. 807 */ 808 save->crtc_tile_x0_y0 = x | (y << 16); 809 Base &= ~0x7ff; 810 } else { 811 /* note we cannot really simply use the info->ModeReg.crtc_offset_cntl value, since the 812 drm might have set FLIP_CNTL since we wrote that. Unfortunately FLIP_CNTL causes 813 flickering when scrolling vertically in a virtual screen, possibly because crtc will 814 pick up the new offset value at the end of each scanline, but the new offset_cntl value 815 only after a vsync. We'd probably need to wait (in drm) for vsync and only then update 816 OFFSET and OFFSET_CNTL, if the y coord has changed. Seems hard to fix. */ 817 /*save->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL) & ~0xf;*/ 818#if 0 819 /* try to get rid of flickering when scrolling at least for 2d */ 820#ifdef XF86DRI 821 if (!info->have3DWindows) 822#endif 823 save->crtc_offset_cntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL; 824#endif 825 826 int byteshift = info->CurrentLayout.bitsPerPixel >> 4; 827 /* crtc uses 256(bytes)x8 "half-tile" start addresses? */ 828 int tile_addr = (((y >> 3) * info->CurrentLayout.displayWidth + x) >> (8 - byteshift)) << 11; 829 Base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); 830 save->crtc_offset_cntl = save->crtc_offset_cntl | (y % 16); 831 } 832 } 833 else { 834 int offset = y * info->CurrentLayout.displayWidth + x; 835 switch (info->CurrentLayout.pixel_code) { 836 case 15: 837 case 16: offset *= 2; break; 838 case 24: offset *= 3; break; 839 case 32: offset *= 4; break; 840 } 841 Base += offset; 842 } 843 844 if (crtc->rotatedData != NULL) { 845 Base = pScrn->fbOffset + (char *)crtc->rotatedData - (char *)info->FB; 846 } 847 848 Base &= ~7; /* 3 lower bits are always 0 */ 849 850 851#ifdef XF86DRI 852 if (info->directRenderingInited) { 853 /* note cannot use pScrn->pScreen since this is unitialized when called from 854 RADEONScreenInit, and we need to call from there to get mergedfb + pageflip working */ 855 /*** NOTE: r3/4xx will need sarea and drm pageflip updates to handle the xytile regs for 856 *** pageflipping! 857 ***/ 858 pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]); 859 /* can't get at sarea in a semi-sane way? */ 860 pSAREA = (void *)((char*)pSAREAPriv - sizeof(XF86DRISAREARec)); 861 862 pSAREA->frame.x = (Base / info->CurrentLayout.pixel_bytes) 863 % info->CurrentLayout.displayWidth; 864 pSAREA->frame.y = (Base / info->CurrentLayout.pixel_bytes) 865 / info->CurrentLayout.displayWidth; 866 pSAREA->frame.width = pScrn->frameX1 - x + 1; 867 pSAREA->frame.height = pScrn->frameY1 - y + 1; 868 869 if (pSAREAPriv->pfCurrentPage == 1) { 870 Base += info->dri->backOffset - info->dri->frontOffset; 871 } 872 } 873#endif 874 save->crtc_offset = Base; 875 876} 877 878/* Define CRTC registers for requested video mode */ 879static Bool 880RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save, 881 DisplayModePtr mode) 882{ 883 ScrnInfoPtr pScrn = crtc->scrn; 884 RADEONInfoPtr info = RADEONPTR(pScrn); 885 int format; 886 int hsync_start; 887 int hsync_wid; 888 int vsync_wid; 889 890 switch (info->CurrentLayout.pixel_code) { 891 case 4: format = 1; break; 892 case 8: format = 2; break; 893 case 15: format = 3; break; /* 555 */ 894 case 16: format = 4; break; /* 565 */ 895 case 24: format = 5; break; /* RGB */ 896 case 32: format = 6; break; /* xRGB */ 897 default: 898 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 899 "Unsupported pixel depth (%d)\n", 900 info->CurrentLayout.bitsPerPixel); 901 return FALSE; 902 } 903 904 /*save->bios_4_scratch = info->SavedReg->bios_4_scratch;*/ 905 save->crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN 906 | (format << 8) 907 | ((mode->Flags & V_DBLSCAN) 908 ? RADEON_CRTC_DBL_SCAN_EN 909 : 0) 910 | ((mode->Flags & V_CSYNC) 911 ? RADEON_CRTC_CSYNC_EN 912 : 0) 913 | ((mode->Flags & V_INTERLACE) 914 ? RADEON_CRTC_INTERLACE_EN 915 : 0)); 916 917 save->crtc_ext_cntl |= (RADEON_XCRT_CNT_EN| 918 RADEON_CRTC_VSYNC_DIS | 919 RADEON_CRTC_HSYNC_DIS | 920 RADEON_CRTC_DISPLAY_DIS); 921 922 save->disp_merge_cntl = info->SavedReg->disp_merge_cntl; 923 save->disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 924 925 save->crtc_h_total_disp = ((((mode->CrtcHTotal / 8) - 1) & 0x3ff) 926 | ((((mode->CrtcHDisplay / 8) - 1) & 0x1ff) 927 << 16)); 928 929 hsync_wid = (mode->CrtcHSyncEnd - mode->CrtcHSyncStart) / 8; 930 if (!hsync_wid) hsync_wid = 1; 931 hsync_start = mode->CrtcHSyncStart - 8; 932 933 save->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) 934 | ((hsync_wid & 0x3f) << 16) 935 | ((mode->Flags & V_NHSYNC) 936 ? RADEON_CRTC_H_SYNC_POL 937 : 0)); 938 939 /* This works for double scan mode. */ 940 save->crtc_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff) 941 | ((mode->CrtcVDisplay - 1) << 16)); 942 943 vsync_wid = mode->CrtcVSyncEnd - mode->CrtcVSyncStart; 944 if (!vsync_wid) vsync_wid = 1; 945 946 save->crtc_v_sync_strt_wid = (((mode->CrtcVSyncStart - 1) & 0xfff) 947 | ((vsync_wid & 0x1f) << 16) 948 | ((mode->Flags & V_NVSYNC) 949 ? RADEON_CRTC_V_SYNC_POL 950 : 0)); 951 952 save->crtc_pitch = (((pScrn->displayWidth * pScrn->bitsPerPixel) + 953 ((pScrn->bitsPerPixel * 8) -1)) / 954 (pScrn->bitsPerPixel * 8)); 955 save->crtc_pitch |= save->crtc_pitch << 16; 956 957 if (info->IsDellServer) { 958 save->dac2_cntl = info->SavedReg->dac2_cntl; 959 save->tv_dac_cntl = info->SavedReg->tv_dac_cntl; 960 save->crtc2_gen_cntl = info->SavedReg->crtc2_gen_cntl; 961 save->disp_hw_debug = info->SavedReg->disp_hw_debug; 962 963 save->dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; 964 save->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; 965 966 /* For CRT on DAC2, don't turn it on if BIOS didn't 967 enable it, even it's detected. 968 */ 969 save->disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 970 save->tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16)); 971 save->tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16)); 972 } 973 974 return TRUE; 975} 976 977 978void 979RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save, 980 int x, int y) 981{ 982 ScrnInfoPtr pScrn = crtc->scrn; 983 RADEONInfoPtr info = RADEONPTR(pScrn); 984 int Base; 985#ifdef XF86DRI 986 drm_radeon_sarea_t *pSAREAPriv; 987 XF86DRISAREAPtr pSAREA; 988#endif 989 990 /* It seems all fancy options apart from pflip can be safely disabled 991 */ 992 save->crtc2_offset = pScrn->fbOffset; 993#ifdef XF86DRI 994 if (info->dri && info->dri->allowPageFlip) 995 save->crtc2_offset_cntl = RADEON_CRTC_OFFSET_FLIP_CNTL; 996 else 997#endif 998 save->crtc2_offset_cntl = 0; 999 1000 if (info->tilingEnabled && (crtc->rotatedData == NULL)) { 1001 if (IS_R300_VARIANT) 1002 save->crtc2_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | 1003 R300_CRTC_MICRO_TILE_BUFFER_DIS | 1004 R300_CRTC_MACRO_TILE_EN); 1005 else 1006 save->crtc2_offset_cntl |= RADEON_CRTC_TILE_EN; 1007 } 1008 else { 1009 if (IS_R300_VARIANT) 1010 save->crtc2_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | 1011 R300_CRTC_MICRO_TILE_BUFFER_DIS | 1012 R300_CRTC_MACRO_TILE_EN); 1013 else 1014 save->crtc2_offset_cntl &= ~RADEON_CRTC_TILE_EN; 1015 } 1016 1017 Base = pScrn->fbOffset; 1018 1019 if (info->tilingEnabled && (crtc->rotatedData == NULL)) { 1020 if (IS_R300_VARIANT) { 1021 /* On r300/r400 when tiling is enabled crtc_offset is set to the address of 1022 * the surface. the x/y offsets are handled by the X_Y tile reg for each crtc 1023 * Makes tiling MUCH easier. 1024 */ 1025 save->crtc2_tile_x0_y0 = x | (y << 16); 1026 Base &= ~0x7ff; 1027 } else { 1028 /* note we cannot really simply use the info->ModeReg.crtc_offset_cntl value, since the 1029 drm might have set FLIP_CNTL since we wrote that. Unfortunately FLIP_CNTL causes 1030 flickering when scrolling vertically in a virtual screen, possibly because crtc will 1031 pick up the new offset value at the end of each scanline, but the new offset_cntl value 1032 only after a vsync. We'd probably need to wait (in drm) for vsync and only then update 1033 OFFSET and OFFSET_CNTL, if the y coord has changed. Seems hard to fix. */ 1034 /*save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL) & ~0xf;*/ 1035#if 0 1036 /* try to get rid of flickering when scrolling at least for 2d */ 1037#ifdef XF86DRI 1038 if (!info->have3DWindows) 1039#endif 1040 save->crtc2_offset_cntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL; 1041#endif 1042 1043 int byteshift = info->CurrentLayout.bitsPerPixel >> 4; 1044 /* crtc uses 256(bytes)x8 "half-tile" start addresses? */ 1045 int tile_addr = (((y >> 3) * info->CurrentLayout.displayWidth + x) >> (8 - byteshift)) << 11; 1046 Base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); 1047 save->crtc2_offset_cntl = save->crtc_offset_cntl | (y % 16); 1048 } 1049 } 1050 else { 1051 int offset = y * info->CurrentLayout.displayWidth + x; 1052 switch (info->CurrentLayout.pixel_code) { 1053 case 15: 1054 case 16: offset *= 2; break; 1055 case 24: offset *= 3; break; 1056 case 32: offset *= 4; break; 1057 } 1058 Base += offset; 1059 } 1060 1061 if (crtc->rotatedData != NULL) { 1062 Base = pScrn->fbOffset + (char *)crtc->rotatedData - (char *)info->FB; 1063 } 1064 1065 Base &= ~7; /* 3 lower bits are always 0 */ 1066 1067#ifdef XF86DRI 1068 if (info->directRenderingInited) { 1069 /* note cannot use pScrn->pScreen since this is unitialized when called from 1070 RADEONScreenInit, and we need to call from there to get mergedfb + pageflip working */ 1071 /*** NOTE: r3/4xx will need sarea and drm pageflip updates to handle the xytile regs for 1072 *** pageflipping! 1073 ***/ 1074 pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]); 1075 /* can't get at sarea in a semi-sane way? */ 1076 pSAREA = (void *)((char*)pSAREAPriv - sizeof(XF86DRISAREARec)); 1077 1078 pSAREAPriv->crtc2_base = Base; 1079 1080 if (pSAREAPriv->pfCurrentPage == 1) { 1081 Base += info->dri->backOffset - info->dri->frontOffset; 1082 } 1083 } 1084#endif 1085 save->crtc2_offset = Base; 1086 1087} 1088 1089 1090/* Define CRTC2 registers for requested video mode */ 1091static Bool 1092RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save, 1093 DisplayModePtr mode) 1094{ 1095 ScrnInfoPtr pScrn = crtc->scrn; 1096 RADEONInfoPtr info = RADEONPTR(pScrn); 1097 int format; 1098 int hsync_start; 1099 int hsync_wid; 1100 int vsync_wid; 1101 1102 switch (info->CurrentLayout.pixel_code) { 1103 case 4: format = 1; break; 1104 case 8: format = 2; break; 1105 case 15: format = 3; break; /* 555 */ 1106 case 16: format = 4; break; /* 565 */ 1107 case 24: format = 5; break; /* RGB */ 1108 case 32: format = 6; break; /* xRGB */ 1109 default: 1110 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1111 "Unsupported pixel depth (%d)\n", 1112 info->CurrentLayout.bitsPerPixel); 1113 return FALSE; 1114 } 1115 1116 save->crtc2_h_total_disp = 1117 ((((mode->CrtcHTotal / 8) - 1) & 0x3ff) 1118 | ((((mode->CrtcHDisplay / 8) - 1) & 0x1ff) << 16)); 1119 1120 hsync_wid = (mode->CrtcHSyncEnd - mode->CrtcHSyncStart) / 8; 1121 if (!hsync_wid) hsync_wid = 1; 1122 hsync_start = mode->CrtcHSyncStart - 8; 1123 1124 save->crtc2_h_sync_strt_wid = ((hsync_start & 0x1fff) 1125 | ((hsync_wid & 0x3f) << 16) 1126 | ((mode->Flags & V_NHSYNC) 1127 ? RADEON_CRTC_H_SYNC_POL 1128 : 0)); 1129 1130 /* This works for double scan mode. */ 1131 save->crtc2_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff) 1132 | ((mode->CrtcVDisplay - 1) << 16)); 1133 1134 vsync_wid = mode->CrtcVSyncEnd - mode->CrtcVSyncStart; 1135 if (!vsync_wid) vsync_wid = 1; 1136 1137 save->crtc2_v_sync_strt_wid = (((mode->CrtcVSyncStart - 1) & 0xfff) 1138 | ((vsync_wid & 0x1f) << 16) 1139 | ((mode->Flags & V_NVSYNC) 1140 ? RADEON_CRTC2_V_SYNC_POL 1141 : 0)); 1142 1143 save->crtc2_pitch = ((pScrn->displayWidth * pScrn->bitsPerPixel) + 1144 ((pScrn->bitsPerPixel * 8) -1)) / (pScrn->bitsPerPixel * 8); 1145 save->crtc2_pitch |= save->crtc2_pitch << 16; 1146 1147 /* check to see if TV DAC is enabled for another crtc and keep it enabled */ 1148 if (save->crtc2_gen_cntl & RADEON_CRTC2_CRT2_ON) 1149 save->crtc2_gen_cntl = RADEON_CRTC2_CRT2_ON; 1150 else 1151 save->crtc2_gen_cntl = 0; 1152 1153 save->crtc2_gen_cntl |= ((format << 8) 1154 | RADEON_CRTC2_VSYNC_DIS 1155 | RADEON_CRTC2_HSYNC_DIS 1156 | RADEON_CRTC2_DISP_DIS 1157 | ((mode->Flags & V_DBLSCAN) 1158 ? RADEON_CRTC2_DBL_SCAN_EN 1159 : 0) 1160 | ((mode->Flags & V_CSYNC) 1161 ? RADEON_CRTC2_CSYNC_EN 1162 : 0) 1163 | ((mode->Flags & V_INTERLACE) 1164 ? RADEON_CRTC2_INTERLACE_EN 1165 : 0)); 1166 1167 save->disp2_merge_cntl = info->SavedReg->disp2_merge_cntl; 1168 save->disp2_merge_cntl &= ~(RADEON_DISP2_RGB_OFFSET_EN); 1169 1170 save->fp_h2_sync_strt_wid = save->crtc2_h_sync_strt_wid; 1171 save->fp_v2_sync_strt_wid = save->crtc2_v_sync_strt_wid; 1172 1173 return TRUE; 1174} 1175 1176 1177/* Define PLL registers for requested video mode */ 1178static void 1179RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, 1180 RADEONPLLPtr pll, DisplayModePtr mode, 1181 int flags) 1182{ 1183 RADEONInfoPtr info = RADEONPTR(pScrn); 1184 uint32_t feedback_div = 0; 1185 uint32_t reference_div = 0; 1186 uint32_t post_divider = 0; 1187 uint32_t freq = 0; 1188 1189 struct { 1190 int divider; 1191 int bitvalue; 1192 } *post_div, post_divs[] = { 1193 /* From RAGE 128 VR/RAGE 128 GL Register 1194 * Reference Manual (Technical Reference 1195 * Manual P/N RRG-G04100-C Rev. 0.04), page 1196 * 3-17 (PLL_DIV_[3:0]). 1197 */ 1198 { 1, 0 }, /* VCLK_SRC */ 1199 { 2, 1 }, /* VCLK_SRC/2 */ 1200 { 4, 2 }, /* VCLK_SRC/4 */ 1201 { 8, 3 }, /* VCLK_SRC/8 */ 1202 { 3, 4 }, /* VCLK_SRC/3 */ 1203 { 16, 5 }, /* VCLK_SRC/16 */ 1204 { 6, 6 }, /* VCLK_SRC/6 */ 1205 { 12, 7 }, /* VCLK_SRC/12 */ 1206 { 0, 0 } 1207 }; 1208 1209 1210 if ((flags & RADEON_PLL_USE_BIOS_DIVS) && info->UseBiosDividers) { 1211 save->ppll_ref_div = info->RefDivider; 1212 save->ppll_div_3 = info->FeedbackDivider | (info->PostDivider << 16); 1213 save->htotal_cntl = 0; 1214 return; 1215 } 1216 1217 RADEONComputePLL(pll, mode->Clock, &freq, &feedback_div, &reference_div, &post_divider, flags); 1218 1219 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { 1220 if (post_div->divider == post_divider) 1221 break; 1222 } 1223 1224 if (!post_div->divider) { 1225 save->pll_output_freq = freq; 1226 post_div = &post_divs[0]; 1227 } 1228 1229 save->dot_clock_freq = freq; 1230 save->feedback_div = feedback_div; 1231 save->reference_div = reference_div; 1232 save->post_div = post_divider; 1233 1234 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1235 "dc=%u, of=%u, fd=%d, rd=%d, pd=%d\n", 1236 (unsigned)save->dot_clock_freq, 1237 (unsigned)save->pll_output_freq, 1238 save->feedback_div, 1239 save->reference_div, 1240 save->post_div); 1241 1242 save->ppll_ref_div = save->reference_div; 1243 1244#if defined(__powerpc__) 1245 /* apparently programming this otherwise causes a hang??? */ 1246 if ((info->MacModel == RADEON_MAC_IBOOK) || 1247 (info->MacModel == RADEON_MAC_MINI_INTERNAL)) 1248 save->ppll_div_3 = 0x000600ad; 1249 else 1250#endif 1251 save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16)); 1252 1253 save->htotal_cntl = mode->HTotal & 0x7; 1254 1255 save->vclk_ecp_cntl = (info->SavedReg->vclk_ecp_cntl & 1256 ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK; 1257} 1258 1259/* Define PLL2 registers for requested video mode */ 1260static void 1261RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, 1262 RADEONPLLPtr pll, DisplayModePtr mode, 1263 int flags) 1264{ 1265 RADEONInfoPtr info = RADEONPTR(pScrn); 1266 uint32_t feedback_div = 0; 1267 uint32_t reference_div = 0; 1268 uint32_t post_divider = 0; 1269 uint32_t freq = 0; 1270 1271 struct { 1272 int divider; 1273 int bitvalue; 1274 } *post_div, post_divs[] = { 1275 /* From RAGE 128 VR/RAGE 128 GL Register 1276 * Reference Manual (Technical Reference 1277 * Manual P/N RRG-G04100-C Rev. 0.04), page 1278 * 3-17 (PLL_DIV_[3:0]). 1279 */ 1280 { 1, 0 }, /* VCLK_SRC */ 1281 { 2, 1 }, /* VCLK_SRC/2 */ 1282 { 4, 2 }, /* VCLK_SRC/4 */ 1283 { 8, 3 }, /* VCLK_SRC/8 */ 1284 { 3, 4 }, /* VCLK_SRC/3 */ 1285 { 6, 6 }, /* VCLK_SRC/6 */ 1286 { 12, 7 }, /* VCLK_SRC/12 */ 1287 { 0, 0 } 1288 }; 1289 1290 if ((flags & RADEON_PLL_USE_BIOS_DIVS) && info->UseBiosDividers) { 1291 save->p2pll_ref_div = info->RefDivider; 1292 save->p2pll_div_0 = info->FeedbackDivider | (info->PostDivider << 16); 1293 save->htotal_cntl2 = 0; 1294 return; 1295 } 1296 1297 RADEONComputePLL(pll, mode->Clock, &freq, &feedback_div, &reference_div, &post_divider, flags); 1298 1299 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { 1300 if (post_div->divider == post_divider) 1301 break; 1302 } 1303 1304 if (!post_div->divider) { 1305 save->pll_output_freq_2 = freq; 1306 post_div = &post_divs[0]; 1307 } 1308 1309 save->dot_clock_freq_2 = freq; 1310 save->feedback_div_2 = feedback_div; 1311 save->reference_div_2 = reference_div; 1312 save->post_div_2 = post_divider; 1313 1314 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1315 "dc=%u, of=%u, fd=%d, rd=%d, pd=%d\n", 1316 (unsigned)save->dot_clock_freq_2, 1317 (unsigned)save->pll_output_freq_2, 1318 save->feedback_div_2, 1319 save->reference_div_2, 1320 save->post_div_2); 1321 1322 save->p2pll_ref_div = save->reference_div_2; 1323 1324 save->p2pll_div_0 = (save->feedback_div_2 | 1325 (post_div->bitvalue << 16)); 1326 1327 save->htotal_cntl2 = mode->HTotal & 0x7; 1328 1329 save->pixclks_cntl = ((info->SavedReg->pixclks_cntl & 1330 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | 1331 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); 1332} 1333 1334static void 1335radeon_update_tv_routing(ScrnInfoPtr pScrn, RADEONSavePtr restore) 1336{ 1337 /* pixclks_cntl controls tv clock routing */ 1338 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, restore->pixclks_cntl); 1339} 1340 1341/* Calculate display buffer watermark to prevent buffer underflow */ 1342void 1343RADEONInitDispBandwidthLegacy(ScrnInfoPtr pScrn, 1344 DisplayModePtr mode1, int pixel_bytes1, 1345 DisplayModePtr mode2, int pixel_bytes2) 1346{ 1347 RADEONInfoPtr info = RADEONPTR(pScrn); 1348 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1349 unsigned char *RADEONMMIO = info->MMIO; 1350 1351 uint32_t temp, data, mem_trcd, mem_trp, mem_tras, mem_trbs=0; 1352 float mem_tcas; 1353 int k1, c; 1354 uint32_t MemTrcdExtMemCntl[4] = {1, 2, 3, 4}; 1355 uint32_t MemTrpExtMemCntl[4] = {1, 2, 3, 4}; 1356 uint32_t MemTrasExtMemCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8}; 1357 1358 uint32_t MemTrcdMemTimingCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8}; 1359 uint32_t MemTrpMemTimingCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8}; 1360 uint32_t MemTrasMemTimingCntl[16] = {4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19}; 1361 1362 float MemTcas[8] = {0, 1, 2, 3, 0, 1.5, 2.5, 0}; 1363 float MemTcas2[8] = {0, 1, 2, 3, 4, 5, 6, 7}; 1364 float MemTrbs[8] = {1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5}; 1365 1366 float mem_bw, peak_disp_bw; 1367 float min_mem_eff = 0.8; 1368 float sclk_eff, sclk_delay; 1369 float mc_latency_mclk, mc_latency_sclk, cur_latency_mclk, cur_latency_sclk; 1370 float disp_latency, disp_latency_overhead, disp_drain_rate = 0, disp_drain_rate2; 1371 float pix_clk, pix_clk2; /* in MHz */ 1372 int cur_size = 16; /* in octawords */ 1373 int critical_point = 0, critical_point2; 1374 int stop_req, max_stop_req; 1375 float read_return_rate, time_disp1_drop_priority; 1376 1377 /* 1378 * Set display0/1 priority up on r3/4xx in the memory controller for 1379 * high res modes if the user specifies HIGH for displaypriority 1380 * option. 1381 */ 1382 if ((info->DispPriority == 2) && IS_R300_VARIANT) { 1383 uint32_t mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER); 1384 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT); 1385 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT); 1386 if (pRADEONEnt->pCrtc[1]->enabled) 1387 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); /* display 1 */ 1388 if (pRADEONEnt->pCrtc[0]->enabled) 1389 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); /* display 0 */ 1390 OUTREG(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); 1391 } 1392 1393 /* R420 and RV410 family not supported yet */ 1394 if (info->ChipFamily == CHIP_FAMILY_R420 || info->ChipFamily == CHIP_FAMILY_RV410) return; 1395 1396 /* 1397 * Determine if there is enough bandwidth for current display mode 1398 */ 1399 mem_bw = info->mclk * (info->RamWidth / 8) * (info->IsDDR ? 2 : 1); 1400 1401 pix_clk = 0; 1402 pix_clk2 = 0; 1403 peak_disp_bw = 0; 1404 if (mode1) { 1405 pix_clk = mode1->Clock/1000.0; 1406 peak_disp_bw += (pix_clk * pixel_bytes1); 1407 } 1408 if (mode2) { 1409 pix_clk2 = mode2->Clock/1000.0; 1410 peak_disp_bw += (pix_clk2 * pixel_bytes2); 1411 } 1412 1413 if (peak_disp_bw >= mem_bw * min_mem_eff) { 1414 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1415 "You may not have enough display bandwidth for current mode\n" 1416 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); 1417 } 1418 1419 /* Get values from the EXT_MEM_CNTL register...converting its contents. */ 1420 temp = INREG(RADEON_MEM_TIMING_CNTL); 1421 if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */ 1422 mem_trcd = MemTrcdExtMemCntl[(temp & 0x0c) >> 2]; 1423 mem_trp = MemTrpExtMemCntl[ (temp & 0x03) >> 0]; 1424 mem_tras = MemTrasExtMemCntl[(temp & 0x70) >> 4]; 1425 } else { /* RV200 and later */ 1426 mem_trcd = MemTrcdMemTimingCntl[(temp & 0x07) >> 0]; 1427 mem_trp = MemTrpMemTimingCntl[ (temp & 0x700) >> 8]; 1428 mem_tras = MemTrasMemTimingCntl[(temp & 0xf000) >> 12]; 1429 } 1430 1431 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ 1432 temp = INREG(RADEON_MEM_SDRAM_MODE_REG); 1433 data = (temp & (7<<20)) >> 20; 1434 if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */ 1435 mem_tcas = MemTcas [data]; 1436 } else { 1437 mem_tcas = MemTcas2 [data]; 1438 } 1439 1440 if (IS_R300_VARIANT) { 1441 /* on the R300, Tcas is included in Trbs. 1442 */ 1443 temp = INREG(RADEON_MEM_CNTL); 1444 data = (R300_MEM_NUM_CHANNELS_MASK & temp); 1445 if (data == 1) { 1446 if (R300_MEM_USE_CD_CH_ONLY & temp) { 1447 temp = INREG(R300_MC_IND_INDEX); 1448 temp &= ~R300_MC_IND_ADDR_MASK; 1449 temp |= R300_MC_READ_CNTL_CD_mcind; 1450 OUTREG(R300_MC_IND_INDEX, temp); 1451 temp = INREG(R300_MC_IND_DATA); 1452 data = (R300_MEM_RBS_POSITION_C_MASK & temp); 1453 } else { 1454 temp = INREG(R300_MC_READ_CNTL_AB); 1455 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 1456 } 1457 } else { 1458 temp = INREG(R300_MC_READ_CNTL_AB); 1459 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 1460 } 1461 1462 mem_trbs = MemTrbs[data]; 1463 mem_tcas += mem_trbs; 1464 } 1465 1466 if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */ 1467 /* DDR64 SCLK_EFF = SCLK for analysis */ 1468 sclk_eff = info->sclk; 1469 } else { 1470#ifdef XF86DRI 1471 if (info->directRenderingEnabled) 1472 sclk_eff = info->sclk - (info->dri->agpMode * 50.0 / 3.0); 1473 else 1474#endif 1475 sclk_eff = info->sclk; 1476 } 1477 1478 /* 1479 Find the memory controller latency for the display client. 1480 */ 1481 if (IS_R300_VARIANT) { 1482 /*not enough for R350 ???*/ 1483 /* 1484 if (!mode2) sclk_delay = 150; 1485 else { 1486 if (info->RamWidth == 256) sclk_delay = 87; 1487 else sclk_delay = 97; 1488 } 1489 */ 1490 sclk_delay = 250; 1491 } else { 1492 if ((info->ChipFamily == CHIP_FAMILY_RV100) || 1493 info->IsIGP) { 1494 if (info->IsDDR) sclk_delay = 41; 1495 else sclk_delay = 33; 1496 } else { 1497 if (info->RamWidth == 128) sclk_delay = 57; 1498 else sclk_delay = 41; 1499 } 1500 } 1501 1502 mc_latency_sclk = sclk_delay / sclk_eff; 1503 1504 if (info->IsDDR) { 1505 if (info->RamWidth == 32) { 1506 k1 = 40; 1507 c = 3; 1508 } else { 1509 k1 = 20; 1510 c = 1; 1511 } 1512 } else { 1513 k1 = 40; 1514 c = 3; 1515 } 1516 mc_latency_mclk = ((2.0*mem_trcd + mem_tcas*c + 4.0*mem_tras + 4.0*mem_trp + k1) / 1517 info->mclk) + (4.0 / sclk_eff); 1518 1519 /* 1520 HW cursor time assuming worst case of full size colour cursor. 1521 */ 1522 cur_latency_mclk = (mem_trp + MAX(mem_tras, (mem_trcd + 2*(cur_size - (info->IsDDR+1))))) / info->mclk; 1523 cur_latency_sclk = cur_size / sclk_eff; 1524 1525 /* 1526 Find the total latency for the display data. 1527 */ 1528 disp_latency_overhead = 8.0 / info->sclk; 1529 mc_latency_mclk = mc_latency_mclk + disp_latency_overhead + cur_latency_mclk; 1530 mc_latency_sclk = mc_latency_sclk + disp_latency_overhead + cur_latency_sclk; 1531 disp_latency = MAX(mc_latency_mclk, mc_latency_sclk); 1532 1533 /* setup Max GRPH_STOP_REQ default value */ 1534 if (IS_RV100_VARIANT) 1535 max_stop_req = 0x5c; 1536 else 1537 max_stop_req = 0x7c; 1538 1539 if (mode1) { 1540 /* CRTC1 1541 Set GRPH_BUFFER_CNTL register using h/w defined optimal values. 1542 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] 1543 */ 1544 stop_req = mode1->HDisplay * pixel_bytes1 / 16; 1545 1546 if (stop_req > max_stop_req) 1547 stop_req = max_stop_req; 1548 1549 /* 1550 Find the drain rate of the display buffer. 1551 */ 1552 disp_drain_rate = pix_clk / (16.0/pixel_bytes1); 1553 1554 /* 1555 Find the critical point of the display buffer. 1556 */ 1557 critical_point= (uint32_t)(disp_drain_rate * disp_latency + 0.5); 1558 1559 /* ???? */ 1560 /* 1561 temp = (info->SavedReg.grph_buffer_cntl & RADEON_GRPH_CRITICAL_POINT_MASK) >> RADEON_GRPH_CRITICAL_POINT_SHIFT; 1562 if (critical_point < temp) critical_point = temp; 1563 */ 1564 if (info->DispPriority == 2) { 1565 critical_point = 0; 1566 } 1567 1568 /* 1569 The critical point should never be above max_stop_req-4. Setting 1570 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. 1571 */ 1572 if (max_stop_req - critical_point < 4) critical_point = 0; 1573 1574 if (critical_point == 0 && mode2 && info->ChipFamily == CHIP_FAMILY_R300) { 1575 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ 1576 critical_point = 0x10; 1577 } 1578 1579 temp = info->SavedReg->grph_buffer_cntl; 1580 temp &= ~(RADEON_GRPH_STOP_REQ_MASK); 1581 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 1582 temp &= ~(RADEON_GRPH_START_REQ_MASK); 1583 if ((info->ChipFamily == CHIP_FAMILY_R350) && 1584 (stop_req > 0x15)) { 1585 stop_req -= 0x10; 1586 } 1587 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 1588 1589 temp |= RADEON_GRPH_BUFFER_SIZE; 1590 temp &= ~(RADEON_GRPH_CRITICAL_CNTL | 1591 RADEON_GRPH_CRITICAL_AT_SOF | 1592 RADEON_GRPH_STOP_CNTL); 1593 /* 1594 Write the result into the register. 1595 */ 1596 OUTREG(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 1597 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 1598 1599#if 0 1600 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 1601 (info->ChipFamily == CHIP_FAMILY_RS480)) { 1602 /* attempt to program RS400 disp regs correctly ??? */ 1603 temp = info->SavedReg->disp1_req_cntl1; 1604 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | 1605 RS400_DISP1_STOP_REQ_LEVEL_MASK); 1606 OUTREG(RS400_DISP1_REQ_CNTL1, (temp | 1607 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 1608 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 1609 temp = info->SavedReg->dmif_mem_cntl1; 1610 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | 1611 RS400_DISP1_CRITICAL_POINT_STOP_MASK); 1612 OUTREG(RS400_DMIF_MEM_CNTL1, (temp | 1613 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | 1614 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); 1615 } 1616#endif 1617 1618 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1619 "GRPH_BUFFER_CNTL from %x to %x\n", 1620 (unsigned int)info->SavedReg->grph_buffer_cntl, 1621 (unsigned int)INREG(RADEON_GRPH_BUFFER_CNTL)); 1622 } 1623 1624 if (mode2) { 1625 stop_req = mode2->HDisplay * pixel_bytes2 / 16; 1626 1627 if (stop_req > max_stop_req) stop_req = max_stop_req; 1628 1629 /* 1630 Find the drain rate of the display buffer. 1631 */ 1632 disp_drain_rate2 = pix_clk2 / (16.0/pixel_bytes2); 1633 1634 temp = info->SavedReg->grph2_buffer_cntl; 1635 temp &= ~(RADEON_GRPH_STOP_REQ_MASK); 1636 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 1637 temp &= ~(RADEON_GRPH_START_REQ_MASK); 1638 if ((info->ChipFamily == CHIP_FAMILY_R350) && 1639 (stop_req > 0x15)) { 1640 stop_req -= 0x10; 1641 } 1642 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 1643 temp |= RADEON_GRPH_BUFFER_SIZE; 1644 temp &= ~(RADEON_GRPH_CRITICAL_CNTL | 1645 RADEON_GRPH_CRITICAL_AT_SOF | 1646 RADEON_GRPH_STOP_CNTL); 1647 1648 if ((info->ChipFamily == CHIP_FAMILY_RS100) || 1649 (info->ChipFamily == CHIP_FAMILY_RS200)) 1650 critical_point2 = 0; 1651 else { 1652 read_return_rate = MIN(info->sclk, info->mclk*(info->RamWidth*(info->IsDDR+1)/128)); 1653 if (mode1) 1654 time_disp1_drop_priority = critical_point / (read_return_rate - disp_drain_rate); 1655 else 1656 time_disp1_drop_priority = 0; 1657 1658 critical_point2 = (uint32_t)((disp_latency + time_disp1_drop_priority + 1659 disp_latency) * disp_drain_rate2 + 0.5); 1660 1661 if (info->DispPriority == 2) { 1662 critical_point2 = 0; 1663 } 1664 1665 if (max_stop_req - critical_point2 < 4) critical_point2 = 0; 1666 1667 } 1668 1669 if (critical_point2 == 0 && info->ChipFamily == CHIP_FAMILY_R300) { 1670 /* some R300 cards have problem with this set to 0 */ 1671 critical_point2 = 0x10; 1672 } 1673 1674 OUTREG(RADEON_GRPH2_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 1675 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 1676 1677 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 1678 (info->ChipFamily == CHIP_FAMILY_RS480)) { 1679#if 0 1680 /* attempt to program RS400 disp2 regs correctly ??? */ 1681 temp = info->SavedReg->disp2_req_cntl1; 1682 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | 1683 RS400_DISP2_STOP_REQ_LEVEL_MASK); 1684 OUTREG(RS400_DISP2_REQ_CNTL1, (temp | 1685 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 1686 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 1687 temp = info->SavedReg->disp2_req_cntl2; 1688 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | 1689 RS400_DISP2_CRITICAL_POINT_STOP_MASK); 1690 OUTREG(RS400_DISP2_REQ_CNTL2, (temp | 1691 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | 1692 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); 1693#endif 1694 OUTREG(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); 1695 OUTREG(RS400_DISP2_REQ_CNTL2, 0x2749D000); 1696 OUTREG(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); 1697 OUTREG(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); 1698 } 1699 1700 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1701 "GRPH2_BUFFER_CNTL from %x to %x\n", 1702 (unsigned int)info->SavedReg->grph2_buffer_cntl, 1703 (unsigned int)INREG(RADEON_GRPH2_BUFFER_CNTL)); 1704 } 1705} 1706 1707void 1708legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, 1709 DisplayModePtr adjusted_mode, int x, int y) 1710{ 1711 ScrnInfoPtr pScrn = crtc->scrn; 1712 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 1713 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 1714 RADEONInfoPtr info = RADEONPTR(pScrn); 1715 int i = 0; 1716 double dot_clock = 0; 1717 int pll_flags = RADEON_PLL_LEGACY; 1718 Bool update_tv_routing = FALSE; 1719 Bool tilingChanged = FALSE; 1720 1721 if (adjusted_mode->Clock > 200000) /* range limits??? */ 1722 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 1723 else 1724 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 1725 1726 if (info->allowColorTiling) { 1727 radeon_crtc->can_tile = (adjusted_mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; 1728 tilingChanged = RADEONSetTiling(pScrn); 1729 } 1730 1731 for (i = 0; i < xf86_config->num_output; i++) { 1732 xf86OutputPtr output = xf86_config->output[i]; 1733 RADEONOutputPrivatePtr radeon_output = output->driver_private; 1734 1735 if (output->crtc == crtc) { 1736 if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT | 1737 ATOM_DEVICE_DFP_SUPPORT)) 1738 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; 1739 if (radeon_output->active_device & (ATOM_DEVICE_LCD_SUPPORT)) 1740 pll_flags |= (RADEON_PLL_USE_BIOS_DIVS | RADEON_PLL_USE_REF_DIV); 1741 } 1742 } 1743 1744 1745 ErrorF("init memmap\n"); 1746 RADEONInitMemMapRegisters(pScrn, info->ModeReg, info); 1747 ErrorF("init common\n"); 1748 RADEONInitCommonRegisters(info->ModeReg, info); 1749 1750 RADEONInitSurfaceCntl(crtc, info->ModeReg); 1751 1752 switch (radeon_crtc->crtc_id) { 1753 case 0: 1754 ErrorF("init crtc1\n"); 1755 RADEONInitCrtcRegisters(crtc, info->ModeReg, adjusted_mode); 1756 RADEONInitCrtcBase(crtc, info->ModeReg, x, y); 1757 dot_clock = adjusted_mode->Clock / 1000.0; 1758 if (dot_clock) { 1759 ErrorF("init pll1\n"); 1760 RADEONInitPLLRegisters(pScrn, info->ModeReg, &info->pll, adjusted_mode, pll_flags); 1761 } else { 1762 info->ModeReg->ppll_ref_div = info->SavedReg->ppll_ref_div; 1763 info->ModeReg->ppll_div_3 = info->SavedReg->ppll_div_3; 1764 info->ModeReg->htotal_cntl = info->SavedReg->htotal_cntl; 1765 } 1766 break; 1767 case 1: 1768 ErrorF("init crtc2\n"); 1769 RADEONInitCrtc2Registers(crtc, info->ModeReg, adjusted_mode); 1770 RADEONInitCrtc2Base(crtc, info->ModeReg, x, y); 1771 dot_clock = adjusted_mode->Clock / 1000.0; 1772 if (dot_clock) { 1773 ErrorF("init pll2\n"); 1774 RADEONInitPLL2Registers(pScrn, info->ModeReg, &info->pll, adjusted_mode, pll_flags); 1775 } 1776 break; 1777 } 1778 1779 for (i = 0; i < xf86_config->num_output; i++) { 1780 xf86OutputPtr output = xf86_config->output[i]; 1781 RADEONOutputPrivatePtr radeon_output = output->driver_private; 1782 1783 if (output->crtc == crtc) { 1784 if (radeon_output->active_device & (ATOM_DEVICE_TV_SUPPORT)) { 1785 switch (radeon_crtc->crtc_id) { 1786 case 0: 1787 RADEONAdjustCrtcRegistersForTV(pScrn, info->ModeReg, adjusted_mode, output); 1788 RADEONAdjustPLLRegistersForTV(pScrn, info->ModeReg, adjusted_mode, output); 1789 update_tv_routing = TRUE; 1790 break; 1791 case 1: 1792 RADEONAdjustCrtc2RegistersForTV(pScrn, info->ModeReg, adjusted_mode, output); 1793 RADEONAdjustPLL2RegistersForTV(pScrn, info->ModeReg, adjusted_mode, output); 1794 break; 1795 } 1796 } 1797 } 1798 } 1799 1800 ErrorF("restore memmap\n"); 1801 RADEONRestoreMemMapRegisters(pScrn, info->ModeReg); 1802 ErrorF("restore common\n"); 1803 RADEONRestoreCommonRegisters(pScrn, info->ModeReg); 1804 1805 switch (radeon_crtc->crtc_id) { 1806 case 0: 1807 ErrorF("restore crtc1\n"); 1808 RADEONRestoreCrtcRegisters(pScrn, info->ModeReg); 1809 ErrorF("restore pll1\n"); 1810 RADEONRestorePLLRegisters(pScrn, info->ModeReg); 1811 break; 1812 case 1: 1813 ErrorF("restore crtc2\n"); 1814 RADEONRestoreCrtc2Registers(pScrn, info->ModeReg); 1815 ErrorF("restore pll2\n"); 1816 RADEONRestorePLL2Registers(pScrn, info->ModeReg); 1817 break; 1818 } 1819 1820 /* pixclks_cntl handles tv-out clock routing */ 1821 if (update_tv_routing) 1822 radeon_update_tv_routing(pScrn, info->ModeReg); 1823 1824 if (info->DispPriority) 1825 RADEONInitDispBandwidth(pScrn); 1826 1827 radeon_crtc->initialized = TRUE; 1828 1829 if (tilingChanged) { 1830 /* need to redraw front buffer, I guess this can be considered a hack ? */ 1831 /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */ 1832 if (pScrn->pScreen) 1833 xf86EnableDisableFBAccess(pScrn->scrnIndex, FALSE); 1834 RADEONChangeSurfaces(pScrn); 1835 if (pScrn->pScreen) 1836 xf86EnableDisableFBAccess(pScrn->scrnIndex, TRUE); 1837 /* xf86SetRootClip would do, but can't access that here */ 1838 } 1839 1840 /* reset ecp_div for Xv */ 1841 info->ecp_div = -1; 1842 1843} 1844 1845