legacy_crtc.c revision 209ff23f
1/* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining 8 * a copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation on the rights to use, copy, modify, merge, 11 * publish, distribute, sublicense, and/or sell copies of the Software, 12 * and to permit persons to whom the Software is furnished to do so, 13 * subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 */ 28 29#ifdef HAVE_CONFIG_H 30#include "config.h" 31#endif 32 33#include <string.h> 34#include <stdio.h> 35 36/* X and server generic header files */ 37#include "xf86.h" 38#include "xf86_OSproc.h" 39#include "vgaHW.h" 40#include "xf86Modes.h" 41 42/* Driver data structures */ 43#include "radeon.h" 44#include "radeon_reg.h" 45#include "radeon_macros.h" 46#include "radeon_probe.h" 47#include "radeon_version.h" 48 49#ifdef XF86DRI 50#define _XF86DRI_SERVER_ 51#include "radeon_dri.h" 52#include "radeon_sarea.h" 53#include "sarea.h" 54#ifdef DRM_IOCTL_MODESET_CTL 55#include <sys/ioctl.h> 56#endif 57#endif 58 59/* Write common registers */ 60void 61RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, 62 RADEONSavePtr restore) 63{ 64 RADEONInfoPtr info = RADEONPTR(pScrn); 65 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 66 unsigned char *RADEONMMIO = info->MMIO; 67 68 if (info->IsSecondary) 69 return; 70 71 OUTREG(RADEON_OVR_CLR, restore->ovr_clr); 72 OUTREG(RADEON_OVR_WID_LEFT_RIGHT, restore->ovr_wid_left_right); 73 OUTREG(RADEON_OVR_WID_TOP_BOTTOM, restore->ovr_wid_top_bottom); 74 OUTREG(RADEON_OV0_SCALE_CNTL, restore->ov0_scale_cntl); 75 OUTREG(RADEON_SUBPIC_CNTL, restore->subpic_cntl); 76 OUTREG(RADEON_VIPH_CONTROL, restore->viph_control); 77 OUTREG(RADEON_I2C_CNTL_1, restore->i2c_cntl_1); 78 OUTREG(RADEON_GEN_INT_CNTL, restore->gen_int_cntl); 79 OUTREG(RADEON_CAP0_TRIG_CNTL, restore->cap0_trig_cntl); 80 OUTREG(RADEON_CAP1_TRIG_CNTL, restore->cap1_trig_cntl); 81 OUTREG(RADEON_BUS_CNTL, restore->bus_cntl); 82 OUTREG(RADEON_SURFACE_CNTL, restore->surface_cntl); 83 84 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 85 (info->ChipFamily == CHIP_FAMILY_RS480)) { 86 OUTREG(RS400_DISP2_REQ_CNTL1, restore->disp2_req_cntl1); 87 OUTREG(RS400_DISP2_REQ_CNTL2, restore->disp2_req_cntl2); 88 OUTREG(RS400_DMIF_MEM_CNTL1, restore->dmif_mem_cntl1); 89 OUTREG(RS400_DISP1_REQ_CNTL1, restore->disp1_req_cntl1); 90 } 91 92 /* Workaround for the VT switching problem in dual-head mode. This 93 * problem only occurs on RV style chips, typically when a FP and 94 * CRT are connected. 95 */ 96 if (pRADEONEnt->HasCRTC2 && 97 info->ChipFamily != CHIP_FAMILY_R200 && 98 !IS_R300_VARIANT) { 99 uint32_t tmp; 100 101 tmp = INREG(RADEON_DAC_CNTL2); 102 OUTREG(RADEON_DAC_CNTL2, tmp & ~RADEON_DAC2_DAC_CLK_SEL); 103 usleep(100000); 104 } 105} 106 107 108/* Write CRTC registers */ 109void 110RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn, 111 RADEONSavePtr restore) 112{ 113 RADEONInfoPtr info = RADEONPTR(pScrn); 114 unsigned char *RADEONMMIO = info->MMIO; 115 116 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 117 "Programming CRTC1, offset: 0x%08x\n", 118 (unsigned)restore->crtc_offset); 119 120 /* We prevent the CRTC from hitting the memory controller until 121 * fully programmed 122 */ 123 OUTREG(RADEON_CRTC_GEN_CNTL, restore->crtc_gen_cntl | 124 RADEON_CRTC_DISP_REQ_EN_B); 125 126 OUTREGP(RADEON_CRTC_EXT_CNTL, 127 restore->crtc_ext_cntl, 128 RADEON_CRTC_VSYNC_DIS | 129 RADEON_CRTC_HSYNC_DIS | 130 RADEON_CRTC_DISPLAY_DIS); 131 132 OUTREG(RADEON_CRTC_H_TOTAL_DISP, restore->crtc_h_total_disp); 133 OUTREG(RADEON_CRTC_H_SYNC_STRT_WID, restore->crtc_h_sync_strt_wid); 134 OUTREG(RADEON_CRTC_V_TOTAL_DISP, restore->crtc_v_total_disp); 135 OUTREG(RADEON_CRTC_V_SYNC_STRT_WID, restore->crtc_v_sync_strt_wid); 136 137 if (IS_R300_VARIANT) 138 OUTREG(R300_CRTC_TILE_X0_Y0, restore->crtc_tile_x0_y0); 139 OUTREG(RADEON_CRTC_OFFSET_CNTL, restore->crtc_offset_cntl); 140 OUTREG(RADEON_CRTC_OFFSET, restore->crtc_offset); 141 142 OUTREG(RADEON_CRTC_PITCH, restore->crtc_pitch); 143 OUTREG(RADEON_DISP_MERGE_CNTL, restore->disp_merge_cntl); 144 145 if (info->IsDellServer) { 146 OUTREG(RADEON_TV_DAC_CNTL, restore->tv_dac_cntl); 147 OUTREG(RADEON_DISP_HW_DEBUG, restore->disp_hw_debug); 148 OUTREG(RADEON_DAC_CNTL2, restore->dac2_cntl); 149 OUTREG(RADEON_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl); 150 } 151 152 OUTREG(RADEON_CRTC_GEN_CNTL, restore->crtc_gen_cntl); 153} 154 155/* Write CRTC2 registers */ 156void 157RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, 158 RADEONSavePtr restore) 159{ 160 RADEONInfoPtr info = RADEONPTR(pScrn); 161 unsigned char *RADEONMMIO = info->MMIO; 162 /* uint32_t crtc2_gen_cntl;*/ 163 164 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 165 "Programming CRTC2, offset: 0x%08x\n", 166 (unsigned)restore->crtc2_offset); 167 168 /* We prevent the CRTC from hitting the memory controller until 169 * fully programmed 170 */ 171 OUTREG(RADEON_CRTC2_GEN_CNTL, 172 restore->crtc2_gen_cntl | RADEON_CRTC2_VSYNC_DIS | 173 RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_DIS | 174 RADEON_CRTC2_DISP_REQ_EN_B); 175 176 OUTREG(RADEON_CRTC2_H_TOTAL_DISP, restore->crtc2_h_total_disp); 177 OUTREG(RADEON_CRTC2_H_SYNC_STRT_WID, restore->crtc2_h_sync_strt_wid); 178 OUTREG(RADEON_CRTC2_V_TOTAL_DISP, restore->crtc2_v_total_disp); 179 OUTREG(RADEON_CRTC2_V_SYNC_STRT_WID, restore->crtc2_v_sync_strt_wid); 180 181 OUTREG(RADEON_FP_H2_SYNC_STRT_WID, restore->fp_h2_sync_strt_wid); 182 OUTREG(RADEON_FP_V2_SYNC_STRT_WID, restore->fp_v2_sync_strt_wid); 183 184 if (IS_R300_VARIANT) 185 OUTREG(R300_CRTC2_TILE_X0_Y0, restore->crtc2_tile_x0_y0); 186 OUTREG(RADEON_CRTC2_OFFSET_CNTL, restore->crtc2_offset_cntl); 187 OUTREG(RADEON_CRTC2_OFFSET, restore->crtc2_offset); 188 189 OUTREG(RADEON_CRTC2_PITCH, restore->crtc2_pitch); 190 OUTREG(RADEON_DISP2_MERGE_CNTL, restore->disp2_merge_cntl); 191 192 OUTREG(RADEON_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl); 193 194} 195 196static void 197RADEONPLLWaitForReadUpdateComplete(ScrnInfoPtr pScrn) 198{ 199 int i = 0; 200 201 /* FIXME: Certain revisions of R300 can't recover here. Not sure of 202 the cause yet, but this workaround will mask the problem for now. 203 Other chips usually will pass at the very first test, so the 204 workaround shouldn't have any effect on them. */ 205 for (i = 0; 206 (i < 10000 && 207 INPLL(pScrn, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); 208 i++); 209} 210 211static void 212RADEONPLLWriteUpdate(ScrnInfoPtr pScrn) 213{ 214 while (INPLL(pScrn, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R); 215 216 OUTPLLP(pScrn, RADEON_PPLL_REF_DIV, 217 RADEON_PPLL_ATOMIC_UPDATE_W, 218 ~(RADEON_PPLL_ATOMIC_UPDATE_W)); 219} 220 221static void 222RADEONPLL2WaitForReadUpdateComplete(ScrnInfoPtr pScrn) 223{ 224 int i = 0; 225 226 /* FIXME: Certain revisions of R300 can't recover here. Not sure of 227 the cause yet, but this workaround will mask the problem for now. 228 Other chips usually will pass at the very first test, so the 229 workaround shouldn't have any effect on them. */ 230 for (i = 0; 231 (i < 10000 && 232 INPLL(pScrn, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); 233 i++); 234} 235 236static void 237RADEONPLL2WriteUpdate(ScrnInfoPtr pScrn) 238{ 239 while (INPLL(pScrn, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R); 240 241 OUTPLLP(pScrn, RADEON_P2PLL_REF_DIV, 242 RADEON_P2PLL_ATOMIC_UPDATE_W, 243 ~(RADEON_P2PLL_ATOMIC_UPDATE_W)); 244} 245 246static uint8_t 247RADEONComputePLLGain(uint16_t reference_freq, uint16_t ref_div, 248 uint16_t fb_div) 249{ 250 unsigned vcoFreq; 251 252 if (!ref_div) 253 return 1; 254 255 vcoFreq = ((unsigned)reference_freq * fb_div) / ref_div; 256 257 /* 258 * This is horribly crude: the VCO frequency range is divided into 259 * 3 parts, each part having a fixed PLL gain value. 260 */ 261 if (vcoFreq >= 30000) 262 /* 263 * [300..max] MHz : 7 264 */ 265 return 7; 266 else if (vcoFreq >= 18000) 267 /* 268 * [180..300) MHz : 4 269 */ 270 return 4; 271 else 272 /* 273 * [0..180) MHz : 1 274 */ 275 return 1; 276} 277 278/* Write PLL registers */ 279void 280RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, 281 RADEONSavePtr restore) 282{ 283 RADEONInfoPtr info = RADEONPTR(pScrn); 284 unsigned char *RADEONMMIO = info->MMIO; 285 uint8_t pllGain; 286 287#if defined(__powerpc__) 288 /* apparently restoring the pll causes a hang??? */ 289 if (info->MacModel == RADEON_MAC_IBOOK) 290 return; 291#endif 292 293 pllGain = RADEONComputePLLGain(info->pll.reference_freq, 294 restore->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK, 295 restore->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK); 296 297 if (info->IsMobility) { 298 /* A temporal workaround for the occational blanking on certain laptop panels. 299 This appears to related to the PLL divider registers (fail to lock?). 300 It occurs even when all dividers are the same with their old settings. 301 In this case we really don't need to fiddle with PLL registers. 302 By doing this we can avoid the blanking problem with some panels. 303 */ 304 if ((restore->ppll_ref_div == (INPLL(pScrn, RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && 305 (restore->ppll_div_3 == (INPLL(pScrn, RADEON_PPLL_DIV_3) & 306 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) { 307 OUTREGP(RADEON_CLOCK_CNTL_INDEX, 308 RADEON_PLL_DIV_SEL, 309 ~(RADEON_PLL_DIV_SEL)); 310 RADEONPllErrataAfterIndex(info); 311 return; 312 } 313 } 314 315 OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL, 316 RADEON_VCLK_SRC_SEL_CPUCLK, 317 ~(RADEON_VCLK_SRC_SEL_MASK)); 318 319 OUTPLLP(pScrn, 320 RADEON_PPLL_CNTL, 321 RADEON_PPLL_RESET 322 | RADEON_PPLL_ATOMIC_UPDATE_EN 323 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN 324 | ((uint32_t)pllGain << RADEON_PPLL_PVG_SHIFT), 325 ~(RADEON_PPLL_RESET 326 | RADEON_PPLL_ATOMIC_UPDATE_EN 327 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN 328 | RADEON_PPLL_PVG_MASK)); 329 330 OUTREGP(RADEON_CLOCK_CNTL_INDEX, 331 RADEON_PLL_DIV_SEL, 332 ~(RADEON_PLL_DIV_SEL)); 333 RADEONPllErrataAfterIndex(info); 334 335 if (IS_R300_VARIANT || 336 (info->ChipFamily == CHIP_FAMILY_RS300) || 337 (info->ChipFamily == CHIP_FAMILY_RS400) || 338 (info->ChipFamily == CHIP_FAMILY_RS480)) { 339 if (restore->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { 340 /* When restoring console mode, use saved PPLL_REF_DIV 341 * setting. 342 */ 343 OUTPLLP(pScrn, RADEON_PPLL_REF_DIV, 344 restore->ppll_ref_div, 345 0); 346 } else { 347 /* R300 uses ref_div_acc field as real ref divider */ 348 OUTPLLP(pScrn, RADEON_PPLL_REF_DIV, 349 (restore->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), 350 ~R300_PPLL_REF_DIV_ACC_MASK); 351 } 352 } else { 353 OUTPLLP(pScrn, RADEON_PPLL_REF_DIV, 354 restore->ppll_ref_div, 355 ~RADEON_PPLL_REF_DIV_MASK); 356 } 357 358 OUTPLLP(pScrn, RADEON_PPLL_DIV_3, 359 restore->ppll_div_3, 360 ~RADEON_PPLL_FB3_DIV_MASK); 361 362 OUTPLLP(pScrn, RADEON_PPLL_DIV_3, 363 restore->ppll_div_3, 364 ~RADEON_PPLL_POST3_DIV_MASK); 365 366 RADEONPLLWriteUpdate(pScrn); 367 RADEONPLLWaitForReadUpdateComplete(pScrn); 368 369 OUTPLL(pScrn, RADEON_HTOTAL_CNTL, restore->htotal_cntl); 370 371 OUTPLLP(pScrn, RADEON_PPLL_CNTL, 372 0, 373 ~(RADEON_PPLL_RESET 374 | RADEON_PPLL_SLEEP 375 | RADEON_PPLL_ATOMIC_UPDATE_EN 376 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN)); 377 378 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 379 "Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n", 380 restore->ppll_ref_div, 381 restore->ppll_div_3, 382 (unsigned)restore->htotal_cntl, 383 INPLL(pScrn, RADEON_PPLL_CNTL)); 384 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 385 "Wrote: rd=%d, fd=%d, pd=%d\n", 386 restore->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK, 387 restore->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK, 388 (restore->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16); 389 390 usleep(50000); /* Let the clock to lock */ 391 392 OUTPLLP(pScrn, RADEON_VCLK_ECP_CNTL, 393 RADEON_VCLK_SRC_SEL_PPLLCLK, 394 ~(RADEON_VCLK_SRC_SEL_MASK)); 395 396 /*OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, restore->vclk_ecp_cntl);*/ 397 398 ErrorF("finished PLL1\n"); 399 400} 401 402/* Write PLL2 registers */ 403void 404RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, 405 RADEONSavePtr restore) 406{ 407 RADEONInfoPtr info = RADEONPTR(pScrn); 408 uint8_t pllGain; 409 410 pllGain = RADEONComputePLLGain(info->pll.reference_freq, 411 restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, 412 restore->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK); 413 414 415 OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 416 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 417 ~(RADEON_PIX2CLK_SRC_SEL_MASK)); 418 419 OUTPLLP(pScrn, 420 RADEON_P2PLL_CNTL, 421 RADEON_P2PLL_RESET 422 | RADEON_P2PLL_ATOMIC_UPDATE_EN 423 | ((uint32_t)pllGain << RADEON_P2PLL_PVG_SHIFT), 424 ~(RADEON_P2PLL_RESET 425 | RADEON_P2PLL_ATOMIC_UPDATE_EN 426 | RADEON_P2PLL_PVG_MASK)); 427 428 429 OUTPLLP(pScrn, RADEON_P2PLL_REF_DIV, 430 restore->p2pll_ref_div, 431 ~RADEON_P2PLL_REF_DIV_MASK); 432 433 OUTPLLP(pScrn, RADEON_P2PLL_DIV_0, 434 restore->p2pll_div_0, 435 ~RADEON_P2PLL_FB0_DIV_MASK); 436 437 OUTPLLP(pScrn, RADEON_P2PLL_DIV_0, 438 restore->p2pll_div_0, 439 ~RADEON_P2PLL_POST0_DIV_MASK); 440 441 RADEONPLL2WriteUpdate(pScrn); 442 RADEONPLL2WaitForReadUpdateComplete(pScrn); 443 444 OUTPLL(pScrn, RADEON_HTOTAL2_CNTL, restore->htotal_cntl2); 445 446 OUTPLLP(pScrn, RADEON_P2PLL_CNTL, 447 0, 448 ~(RADEON_P2PLL_RESET 449 | RADEON_P2PLL_SLEEP 450 | RADEON_P2PLL_ATOMIC_UPDATE_EN)); 451 452 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 453 "Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n", 454 (unsigned)restore->p2pll_ref_div, 455 (unsigned)restore->p2pll_div_0, 456 (unsigned)restore->htotal_cntl2, 457 INPLL(pScrn, RADEON_P2PLL_CNTL)); 458 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 459 "Wrote2: rd=%u, fd=%u, pd=%u\n", 460 (unsigned)restore->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, 461 (unsigned)restore->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK, 462 (unsigned)((restore->p2pll_div_0 & 463 RADEON_P2PLL_POST0_DIV_MASK) >>16)); 464 465 usleep(5000); /* Let the clock to lock */ 466 467 OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 468 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 469 ~(RADEON_PIX2CLK_SRC_SEL_MASK)); 470 471 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, restore->pixclks_cntl); 472 473 ErrorF("finished PLL2\n"); 474 475} 476 477/* Read common registers */ 478void 479RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) 480{ 481 RADEONInfoPtr info = RADEONPTR(pScrn); 482 unsigned char *RADEONMMIO = info->MMIO; 483 484 save->ovr_clr = INREG(RADEON_OVR_CLR); 485 save->ovr_wid_left_right = INREG(RADEON_OVR_WID_LEFT_RIGHT); 486 save->ovr_wid_top_bottom = INREG(RADEON_OVR_WID_TOP_BOTTOM); 487 save->ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL); 488 save->subpic_cntl = INREG(RADEON_SUBPIC_CNTL); 489 save->viph_control = INREG(RADEON_VIPH_CONTROL); 490 save->i2c_cntl_1 = INREG(RADEON_I2C_CNTL_1); 491 save->gen_int_cntl = INREG(RADEON_GEN_INT_CNTL); 492 save->cap0_trig_cntl = INREG(RADEON_CAP0_TRIG_CNTL); 493 save->cap1_trig_cntl = INREG(RADEON_CAP1_TRIG_CNTL); 494 save->bus_cntl = INREG(RADEON_BUS_CNTL); 495 save->surface_cntl = INREG(RADEON_SURFACE_CNTL); 496 save->grph_buffer_cntl = INREG(RADEON_GRPH_BUFFER_CNTL); 497 save->grph2_buffer_cntl = INREG(RADEON_GRPH2_BUFFER_CNTL); 498 499 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 500 (info->ChipFamily == CHIP_FAMILY_RS480)) { 501 save->disp2_req_cntl1 = INREG(RS400_DISP2_REQ_CNTL1); 502 save->disp2_req_cntl2 = INREG(RS400_DISP2_REQ_CNTL2); 503 save->dmif_mem_cntl1 = INREG(RS400_DMIF_MEM_CNTL1); 504 save->disp1_req_cntl1 = INREG(RS400_DISP1_REQ_CNTL1); 505 } 506} 507 508/* Read CRTC registers */ 509void 510RADEONSaveCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) 511{ 512 RADEONInfoPtr info = RADEONPTR(pScrn); 513 unsigned char *RADEONMMIO = info->MMIO; 514 515 save->crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); 516 save->crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL); 517 save->crtc_h_total_disp = INREG(RADEON_CRTC_H_TOTAL_DISP); 518 save->crtc_h_sync_strt_wid = INREG(RADEON_CRTC_H_SYNC_STRT_WID); 519 save->crtc_v_total_disp = INREG(RADEON_CRTC_V_TOTAL_DISP); 520 save->crtc_v_sync_strt_wid = INREG(RADEON_CRTC_V_SYNC_STRT_WID); 521 522 save->crtc_offset = INREG(RADEON_CRTC_OFFSET); 523 save->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL); 524 save->crtc_pitch = INREG(RADEON_CRTC_PITCH); 525 save->disp_merge_cntl = INREG(RADEON_DISP_MERGE_CNTL); 526 527 if (IS_R300_VARIANT) 528 save->crtc_tile_x0_y0 = INREG(R300_CRTC_TILE_X0_Y0); 529 530 if (info->IsDellServer) { 531 save->tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL); 532 save->dac2_cntl = INREG(RADEON_DAC_CNTL2); 533 save->disp_hw_debug = INREG (RADEON_DISP_HW_DEBUG); 534 save->crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); 535 } 536 537 /* track if the crtc is enabled for text restore */ 538 if (save->crtc_ext_cntl & RADEON_CRTC_DISPLAY_DIS) 539 info->crtc_on = FALSE; 540 else 541 info->crtc_on = TRUE; 542 543} 544 545/* Read CRTC2 registers */ 546void 547RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save) 548{ 549 RADEONInfoPtr info = RADEONPTR(pScrn); 550 unsigned char *RADEONMMIO = info->MMIO; 551 552 save->crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); 553 save->crtc2_h_total_disp = INREG(RADEON_CRTC2_H_TOTAL_DISP); 554 save->crtc2_h_sync_strt_wid = INREG(RADEON_CRTC2_H_SYNC_STRT_WID); 555 save->crtc2_v_total_disp = INREG(RADEON_CRTC2_V_TOTAL_DISP); 556 save->crtc2_v_sync_strt_wid = INREG(RADEON_CRTC2_V_SYNC_STRT_WID); 557 save->crtc2_offset = INREG(RADEON_CRTC2_OFFSET); 558 save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL); 559 save->crtc2_pitch = INREG(RADEON_CRTC2_PITCH); 560 561 if (IS_R300_VARIANT) 562 save->crtc2_tile_x0_y0 = INREG(R300_CRTC2_TILE_X0_Y0); 563 564 save->fp_h2_sync_strt_wid = INREG (RADEON_FP_H2_SYNC_STRT_WID); 565 save->fp_v2_sync_strt_wid = INREG (RADEON_FP_V2_SYNC_STRT_WID); 566 567 save->disp2_merge_cntl = INREG(RADEON_DISP2_MERGE_CNTL); 568 569 /* track if the crtc is enabled for text restore */ 570 if (save->crtc2_gen_cntl & RADEON_CRTC2_DISP_DIS) 571 info->crtc2_on = FALSE; 572 else 573 info->crtc2_on = TRUE; 574 575} 576 577/* Read PLL registers */ 578void 579RADEONSavePLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) 580{ 581 save->ppll_ref_div = INPLL(pScrn, RADEON_PPLL_REF_DIV); 582 save->ppll_div_3 = INPLL(pScrn, RADEON_PPLL_DIV_3); 583 save->htotal_cntl = INPLL(pScrn, RADEON_HTOTAL_CNTL); 584 save->vclk_ecp_cntl = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); 585 586 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 587 "Read: 0x%08x 0x%08x 0x%08x\n", 588 save->ppll_ref_div, 589 save->ppll_div_3, 590 (unsigned)save->htotal_cntl); 591 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 592 "Read: rd=%d, fd=%d, pd=%d\n", 593 save->ppll_ref_div & RADEON_PPLL_REF_DIV_MASK, 594 save->ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK, 595 (save->ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16); 596} 597 598/* Read PLL registers */ 599void 600RADEONSavePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save) 601{ 602 save->p2pll_ref_div = INPLL(pScrn, RADEON_P2PLL_REF_DIV); 603 save->p2pll_div_0 = INPLL(pScrn, RADEON_P2PLL_DIV_0); 604 save->htotal_cntl2 = INPLL(pScrn, RADEON_HTOTAL2_CNTL); 605 save->pixclks_cntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL); 606 607 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 608 "Read: 0x%08x 0x%08x 0x%08x\n", 609 (unsigned)save->p2pll_ref_div, 610 (unsigned)save->p2pll_div_0, 611 (unsigned)save->htotal_cntl2); 612 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 613 "Read: rd=%u, fd=%u, pd=%u\n", 614 (unsigned)(save->p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK), 615 (unsigned)(save->p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK), 616 (unsigned)((save->p2pll_div_0 & RADEON_P2PLL_POST0_DIV_MASK) 617 >> 16)); 618} 619 620void 621radeon_crtc_modeset_ioctl(xf86CrtcPtr crtc, Bool post) 622{ 623#if defined(XF86DRI) && defined(DRM_IOCTL_MODESET_CTL) 624 RADEONInfoPtr info = RADEONPTR(crtc->scrn); 625 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 626 struct drm_modeset_ctl modeset; 627 628 modeset.crtc = radeon_crtc->crtc_id; 629 modeset.cmd = post ? _DRM_POST_MODESET : _DRM_PRE_MODESET; 630 631 ioctl(info->drmFD, DRM_IOCTL_MODESET_CTL, &modeset); 632#endif 633} 634 635void 636legacy_crtc_dpms(xf86CrtcPtr crtc, int mode) 637{ 638 int mask; 639 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 640 RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn); 641 unsigned char *RADEONMMIO = pRADEONEnt->MMIO; 642 643 mask = radeon_crtc->crtc_id ? (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_REQ_EN_B) : (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS | RADEON_CRTC_VSYNC_DIS); 644 645 if (mode == DPMSModeOff) 646 radeon_crtc_modeset_ioctl(crtc, FALSE); 647 648 switch(mode) { 649 case DPMSModeOn: 650 if (radeon_crtc->crtc_id) { 651 OUTREGP(RADEON_CRTC2_GEN_CNTL, 0, ~mask); 652 } else { 653 OUTREGP(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B); 654 OUTREGP(RADEON_CRTC_EXT_CNTL, 0, ~mask); 655 } 656 break; 657 case DPMSModeStandby: 658 if (radeon_crtc->crtc_id) { 659 OUTREGP(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS), ~mask); 660 } else { 661 OUTREGP(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B); 662 OUTREGP(RADEON_CRTC_EXT_CNTL, (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS), ~mask); 663 } 664 break; 665 case DPMSModeSuspend: 666 if (radeon_crtc->crtc_id) { 667 OUTREGP(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS), ~mask); 668 } else { 669 OUTREGP(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B); 670 OUTREGP(RADEON_CRTC_EXT_CNTL, (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS), ~mask); 671 } 672 break; 673 case DPMSModeOff: 674 if (radeon_crtc->crtc_id) { 675 OUTREGP(RADEON_CRTC2_GEN_CNTL, mask, ~mask); 676 } else { 677 OUTREGP(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~RADEON_CRTC_DISP_REQ_EN_B); 678 OUTREGP(RADEON_CRTC_EXT_CNTL, mask, ~mask); 679 } 680 break; 681 } 682 683 if (mode != DPMSModeOff) { 684 radeon_crtc_modeset_ioctl(crtc, TRUE); 685 radeon_crtc_load_lut(crtc); 686 } 687} 688 689 690/* Define common registers for requested video mode */ 691static void 692RADEONInitCommonRegisters(RADEONSavePtr save, RADEONInfoPtr info) 693{ 694 save->ovr_clr = 0; 695 save->ovr_wid_left_right = 0; 696 save->ovr_wid_top_bottom = 0; 697 save->ov0_scale_cntl = 0; 698 save->subpic_cntl = 0; 699 save->viph_control = 0; 700 save->i2c_cntl_1 = 0; 701 save->rbbm_soft_reset = 0; 702 save->cap0_trig_cntl = 0; 703 save->cap1_trig_cntl = 0; 704 save->bus_cntl = info->BusCntl; 705 706 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 707 (info->ChipFamily == CHIP_FAMILY_RS480)) { 708 save->disp2_req_cntl1 = info->SavedReg->disp2_req_cntl1; 709 save->disp2_req_cntl2 = info->SavedReg->disp2_req_cntl2; 710 save->dmif_mem_cntl1 = info->SavedReg->dmif_mem_cntl1; 711 save->disp1_req_cntl1 = info->SavedReg->disp1_req_cntl1; 712 } 713 714 /* 715 * If bursts are enabled, turn on discards 716 * Radeon doesn't have write bursts 717 */ 718 if (save->bus_cntl & (RADEON_BUS_READ_BURST)) 719 save->bus_cntl |= RADEON_BUS_RD_DISCARD_EN; 720} 721 722static void 723RADEONInitSurfaceCntl(xf86CrtcPtr crtc, RADEONSavePtr save) 724{ 725 save->surface_cntl = 0; 726 727#if X_BYTE_ORDER == X_BIG_ENDIAN 728 /* We must set both apertures as they can be both used to map the entire 729 * video memory. -BenH. 730 */ 731 switch (crtc->scrn->bitsPerPixel) { 732 case 16: 733 save->surface_cntl |= RADEON_NONSURF_AP0_SWP_16BPP; 734 save->surface_cntl |= RADEON_NONSURF_AP1_SWP_16BPP; 735 break; 736 737 case 32: 738 save->surface_cntl |= RADEON_NONSURF_AP0_SWP_32BPP; 739 save->surface_cntl |= RADEON_NONSURF_AP1_SWP_32BPP; 740 break; 741 } 742#endif 743 744} 745 746 747static Bool 748RADEONInitCrtcBase(xf86CrtcPtr crtc, RADEONSavePtr save, 749 int x, int y) 750{ 751 ScrnInfoPtr pScrn = crtc->scrn; 752 RADEONInfoPtr info = RADEONPTR(pScrn); 753 int Base; 754#ifdef XF86DRI 755 RADEONSAREAPrivPtr pSAREAPriv; 756 XF86DRISAREAPtr pSAREA; 757#endif 758 759 save->crtc_offset = pScrn->fbOffset; 760#ifdef XF86DRI 761 if (info->allowPageFlip) 762 save->crtc_offset_cntl = RADEON_CRTC_OFFSET_FLIP_CNTL; 763 else 764#endif 765 save->crtc_offset_cntl = 0; 766 767 if (info->tilingEnabled && (crtc->rotatedData == NULL)) { 768 if (IS_R300_VARIANT) 769 save->crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | 770 R300_CRTC_MICRO_TILE_BUFFER_DIS | 771 R300_CRTC_MACRO_TILE_EN); 772 else 773 save->crtc_offset_cntl |= RADEON_CRTC_TILE_EN; 774 } 775 else { 776 if (IS_R300_VARIANT) 777 save->crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | 778 R300_CRTC_MICRO_TILE_BUFFER_DIS | 779 R300_CRTC_MACRO_TILE_EN); 780 else 781 save->crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN; 782 } 783 784 Base = pScrn->fbOffset; 785 786 if (info->tilingEnabled && (crtc->rotatedData == NULL)) { 787 if (IS_R300_VARIANT) { 788 /* On r300/r400 when tiling is enabled crtc_offset is set to the address of 789 * the surface. the x/y offsets are handled by the X_Y tile reg for each crtc 790 * Makes tiling MUCH easier. 791 */ 792 save->crtc_tile_x0_y0 = x | (y << 16); 793 Base &= ~0x7ff; 794 } else { 795 /* note we cannot really simply use the info->ModeReg.crtc_offset_cntl value, since the 796 drm might have set FLIP_CNTL since we wrote that. Unfortunately FLIP_CNTL causes 797 flickering when scrolling vertically in a virtual screen, possibly because crtc will 798 pick up the new offset value at the end of each scanline, but the new offset_cntl value 799 only after a vsync. We'd probably need to wait (in drm) for vsync and only then update 800 OFFSET and OFFSET_CNTL, if the y coord has changed. Seems hard to fix. */ 801 /*save->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL) & ~0xf;*/ 802#if 0 803 /* try to get rid of flickering when scrolling at least for 2d */ 804#ifdef XF86DRI 805 if (!info->have3DWindows) 806#endif 807 save->crtc_offset_cntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL; 808#endif 809 810 int byteshift = info->CurrentLayout.bitsPerPixel >> 4; 811 /* crtc uses 256(bytes)x8 "half-tile" start addresses? */ 812 int tile_addr = (((y >> 3) * info->CurrentLayout.displayWidth + x) >> (8 - byteshift)) << 11; 813 Base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); 814 save->crtc_offset_cntl = save->crtc_offset_cntl | (y % 16); 815 } 816 } 817 else { 818 int offset = y * info->CurrentLayout.displayWidth + x; 819 switch (info->CurrentLayout.pixel_code) { 820 case 15: 821 case 16: offset *= 2; break; 822 case 24: offset *= 3; break; 823 case 32: offset *= 4; break; 824 } 825 Base += offset; 826 } 827 828 if (crtc->rotatedData != NULL) { 829 Base = pScrn->fbOffset + (char *)crtc->rotatedData - (char *)info->FB; 830 } 831 832 Base &= ~7; /* 3 lower bits are always 0 */ 833 834 835#ifdef XF86DRI 836 if (info->directRenderingInited) { 837 /* note cannot use pScrn->pScreen since this is unitialized when called from 838 RADEONScreenInit, and we need to call from there to get mergedfb + pageflip working */ 839 /*** NOTE: r3/4xx will need sarea and drm pageflip updates to handle the xytile regs for 840 *** pageflipping! 841 ***/ 842 pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]); 843 /* can't get at sarea in a semi-sane way? */ 844 pSAREA = (void *)((char*)pSAREAPriv - sizeof(XF86DRISAREARec)); 845 846 pSAREA->frame.x = (Base / info->CurrentLayout.pixel_bytes) 847 % info->CurrentLayout.displayWidth; 848 pSAREA->frame.y = (Base / info->CurrentLayout.pixel_bytes) 849 / info->CurrentLayout.displayWidth; 850 pSAREA->frame.width = pScrn->frameX1 - x + 1; 851 pSAREA->frame.height = pScrn->frameY1 - y + 1; 852 853 if (pSAREAPriv->pfCurrentPage == 1) { 854 Base += info->backOffset - info->frontOffset; 855 } 856 } 857#endif 858 save->crtc_offset = Base; 859 860 return TRUE; 861 862} 863 864/* Define CRTC registers for requested video mode */ 865static Bool 866RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr save, 867 DisplayModePtr mode) 868{ 869 ScrnInfoPtr pScrn = crtc->scrn; 870 RADEONInfoPtr info = RADEONPTR(pScrn); 871 int format; 872 int hsync_start; 873 int hsync_wid; 874 int vsync_wid; 875 876 switch (info->CurrentLayout.pixel_code) { 877 case 4: format = 1; break; 878 case 8: format = 2; break; 879 case 15: format = 3; break; /* 555 */ 880 case 16: format = 4; break; /* 565 */ 881 case 24: format = 5; break; /* RGB */ 882 case 32: format = 6; break; /* xRGB */ 883 default: 884 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 885 "Unsupported pixel depth (%d)\n", 886 info->CurrentLayout.bitsPerPixel); 887 return FALSE; 888 } 889 890 /*save->bios_4_scratch = info->SavedReg->bios_4_scratch;*/ 891 save->crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN 892 | RADEON_CRTC_EN 893 | (format << 8) 894 | ((mode->Flags & V_DBLSCAN) 895 ? RADEON_CRTC_DBL_SCAN_EN 896 : 0) 897 | ((mode->Flags & V_CSYNC) 898 ? RADEON_CRTC_CSYNC_EN 899 : 0) 900 | ((mode->Flags & V_INTERLACE) 901 ? RADEON_CRTC_INTERLACE_EN 902 : 0)); 903 904 save->crtc_ext_cntl |= (RADEON_XCRT_CNT_EN| 905 RADEON_CRTC_VSYNC_DIS | 906 RADEON_CRTC_HSYNC_DIS | 907 RADEON_CRTC_DISPLAY_DIS); 908 909 save->disp_merge_cntl = info->SavedReg->disp_merge_cntl; 910 save->disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 911 912 save->crtc_h_total_disp = ((((mode->CrtcHTotal / 8) - 1) & 0x3ff) 913 | ((((mode->CrtcHDisplay / 8) - 1) & 0x1ff) 914 << 16)); 915 916 hsync_wid = (mode->CrtcHSyncEnd - mode->CrtcHSyncStart) / 8; 917 if (!hsync_wid) hsync_wid = 1; 918 hsync_start = mode->CrtcHSyncStart - 8; 919 920 save->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) 921 | ((hsync_wid & 0x3f) << 16) 922 | ((mode->Flags & V_NHSYNC) 923 ? RADEON_CRTC_H_SYNC_POL 924 : 0)); 925 926 /* This works for double scan mode. */ 927 save->crtc_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff) 928 | ((mode->CrtcVDisplay - 1) << 16)); 929 930 vsync_wid = mode->CrtcVSyncEnd - mode->CrtcVSyncStart; 931 if (!vsync_wid) vsync_wid = 1; 932 933 save->crtc_v_sync_strt_wid = (((mode->CrtcVSyncStart - 1) & 0xfff) 934 | ((vsync_wid & 0x1f) << 16) 935 | ((mode->Flags & V_NVSYNC) 936 ? RADEON_CRTC_V_SYNC_POL 937 : 0)); 938 939 save->crtc_pitch = (((pScrn->displayWidth * pScrn->bitsPerPixel) + 940 ((pScrn->bitsPerPixel * 8) -1)) / 941 (pScrn->bitsPerPixel * 8)); 942 save->crtc_pitch |= save->crtc_pitch << 16; 943 944 if (info->IsDellServer) { 945 save->dac2_cntl = info->SavedReg->dac2_cntl; 946 save->tv_dac_cntl = info->SavedReg->tv_dac_cntl; 947 save->crtc2_gen_cntl = info->SavedReg->crtc2_gen_cntl; 948 save->disp_hw_debug = info->SavedReg->disp_hw_debug; 949 950 save->dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL; 951 save->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL; 952 953 /* For CRT on DAC2, don't turn it on if BIOS didn't 954 enable it, even it's detected. 955 */ 956 save->disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 957 save->tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16)); 958 save->tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16)); 959 } 960 961 return TRUE; 962} 963 964 965static Bool 966RADEONInitCrtc2Base(xf86CrtcPtr crtc, RADEONSavePtr save, 967 int x, int y) 968{ 969 ScrnInfoPtr pScrn = crtc->scrn; 970 RADEONInfoPtr info = RADEONPTR(pScrn); 971 int Base; 972#ifdef XF86DRI 973 RADEONSAREAPrivPtr pSAREAPriv; 974 XF86DRISAREAPtr pSAREA; 975#endif 976 977 /* It seems all fancy options apart from pflip can be safely disabled 978 */ 979 save->crtc2_offset = pScrn->fbOffset; 980#ifdef XF86DRI 981 if (info->allowPageFlip) 982 save->crtc2_offset_cntl = RADEON_CRTC_OFFSET_FLIP_CNTL; 983 else 984#endif 985 save->crtc2_offset_cntl = 0; 986 987 if (info->tilingEnabled && (crtc->rotatedData == NULL)) { 988 if (IS_R300_VARIANT) 989 save->crtc2_offset_cntl |= (R300_CRTC_X_Y_MODE_EN | 990 R300_CRTC_MICRO_TILE_BUFFER_DIS | 991 R300_CRTC_MACRO_TILE_EN); 992 else 993 save->crtc2_offset_cntl |= RADEON_CRTC_TILE_EN; 994 } 995 else { 996 if (IS_R300_VARIANT) 997 save->crtc2_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN | 998 R300_CRTC_MICRO_TILE_BUFFER_DIS | 999 R300_CRTC_MACRO_TILE_EN); 1000 else 1001 save->crtc2_offset_cntl &= ~RADEON_CRTC_TILE_EN; 1002 } 1003 1004 Base = pScrn->fbOffset; 1005 1006 if (info->tilingEnabled && (crtc->rotatedData == NULL)) { 1007 if (IS_R300_VARIANT) { 1008 /* On r300/r400 when tiling is enabled crtc_offset is set to the address of 1009 * the surface. the x/y offsets are handled by the X_Y tile reg for each crtc 1010 * Makes tiling MUCH easier. 1011 */ 1012 save->crtc2_tile_x0_y0 = x | (y << 16); 1013 Base &= ~0x7ff; 1014 } else { 1015 /* note we cannot really simply use the info->ModeReg.crtc_offset_cntl value, since the 1016 drm might have set FLIP_CNTL since we wrote that. Unfortunately FLIP_CNTL causes 1017 flickering when scrolling vertically in a virtual screen, possibly because crtc will 1018 pick up the new offset value at the end of each scanline, but the new offset_cntl value 1019 only after a vsync. We'd probably need to wait (in drm) for vsync and only then update 1020 OFFSET and OFFSET_CNTL, if the y coord has changed. Seems hard to fix. */ 1021 /*save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL) & ~0xf;*/ 1022#if 0 1023 /* try to get rid of flickering when scrolling at least for 2d */ 1024#ifdef XF86DRI 1025 if (!info->have3DWindows) 1026#endif 1027 save->crtc2_offset_cntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL; 1028#endif 1029 1030 int byteshift = info->CurrentLayout.bitsPerPixel >> 4; 1031 /* crtc uses 256(bytes)x8 "half-tile" start addresses? */ 1032 int tile_addr = (((y >> 3) * info->CurrentLayout.displayWidth + x) >> (8 - byteshift)) << 11; 1033 Base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); 1034 save->crtc2_offset_cntl = save->crtc_offset_cntl | (y % 16); 1035 } 1036 } 1037 else { 1038 int offset = y * info->CurrentLayout.displayWidth + x; 1039 switch (info->CurrentLayout.pixel_code) { 1040 case 15: 1041 case 16: offset *= 2; break; 1042 case 24: offset *= 3; break; 1043 case 32: offset *= 4; break; 1044 } 1045 Base += offset; 1046 } 1047 1048 if (crtc->rotatedData != NULL) { 1049 Base = pScrn->fbOffset + (char *)crtc->rotatedData - (char *)info->FB; 1050 } 1051 1052 Base &= ~7; /* 3 lower bits are always 0 */ 1053 1054#ifdef XF86DRI 1055 if (info->directRenderingInited) { 1056 /* note cannot use pScrn->pScreen since this is unitialized when called from 1057 RADEONScreenInit, and we need to call from there to get mergedfb + pageflip working */ 1058 /*** NOTE: r3/4xx will need sarea and drm pageflip updates to handle the xytile regs for 1059 *** pageflipping! 1060 ***/ 1061 pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]); 1062 /* can't get at sarea in a semi-sane way? */ 1063 pSAREA = (void *)((char*)pSAREAPriv - sizeof(XF86DRISAREARec)); 1064 1065 pSAREAPriv->crtc2_base = Base; 1066 1067 if (pSAREAPriv->pfCurrentPage == 1) { 1068 Base += info->backOffset - info->frontOffset; 1069 } 1070 } 1071#endif 1072 save->crtc2_offset = Base; 1073 1074 return TRUE; 1075} 1076 1077 1078/* Define CRTC2 registers for requested video mode */ 1079static Bool 1080RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr save, 1081 DisplayModePtr mode) 1082{ 1083 ScrnInfoPtr pScrn = crtc->scrn; 1084 RADEONInfoPtr info = RADEONPTR(pScrn); 1085 int format; 1086 int hsync_start; 1087 int hsync_wid; 1088 int vsync_wid; 1089 1090 switch (info->CurrentLayout.pixel_code) { 1091 case 4: format = 1; break; 1092 case 8: format = 2; break; 1093 case 15: format = 3; break; /* 555 */ 1094 case 16: format = 4; break; /* 565 */ 1095 case 24: format = 5; break; /* RGB */ 1096 case 32: format = 6; break; /* xRGB */ 1097 default: 1098 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1099 "Unsupported pixel depth (%d)\n", 1100 info->CurrentLayout.bitsPerPixel); 1101 return FALSE; 1102 } 1103 1104 save->crtc2_h_total_disp = 1105 ((((mode->CrtcHTotal / 8) - 1) & 0x3ff) 1106 | ((((mode->CrtcHDisplay / 8) - 1) & 0x1ff) << 16)); 1107 1108 hsync_wid = (mode->CrtcHSyncEnd - mode->CrtcHSyncStart) / 8; 1109 if (!hsync_wid) hsync_wid = 1; 1110 hsync_start = mode->CrtcHSyncStart - 8; 1111 1112 save->crtc2_h_sync_strt_wid = ((hsync_start & 0x1fff) 1113 | ((hsync_wid & 0x3f) << 16) 1114 | ((mode->Flags & V_NHSYNC) 1115 ? RADEON_CRTC_H_SYNC_POL 1116 : 0)); 1117 1118 /* This works for double scan mode. */ 1119 save->crtc2_v_total_disp = (((mode->CrtcVTotal - 1) & 0xffff) 1120 | ((mode->CrtcVDisplay - 1) << 16)); 1121 1122 vsync_wid = mode->CrtcVSyncEnd - mode->CrtcVSyncStart; 1123 if (!vsync_wid) vsync_wid = 1; 1124 1125 save->crtc2_v_sync_strt_wid = (((mode->CrtcVSyncStart - 1) & 0xfff) 1126 | ((vsync_wid & 0x1f) << 16) 1127 | ((mode->Flags & V_NVSYNC) 1128 ? RADEON_CRTC2_V_SYNC_POL 1129 : 0)); 1130 1131 save->crtc2_pitch = ((pScrn->displayWidth * pScrn->bitsPerPixel) + 1132 ((pScrn->bitsPerPixel * 8) -1)) / (pScrn->bitsPerPixel * 8); 1133 save->crtc2_pitch |= save->crtc2_pitch << 16; 1134 1135 /* check to see if TV DAC is enabled for another crtc and keep it enabled */ 1136 if (save->crtc2_gen_cntl & RADEON_CRTC2_CRT2_ON) 1137 save->crtc2_gen_cntl = RADEON_CRTC2_CRT2_ON; 1138 else 1139 save->crtc2_gen_cntl = 0; 1140 1141 save->crtc2_gen_cntl |= (RADEON_CRTC2_EN 1142 | (format << 8) 1143 | RADEON_CRTC2_VSYNC_DIS 1144 | RADEON_CRTC2_HSYNC_DIS 1145 | RADEON_CRTC2_DISP_DIS 1146 | ((mode->Flags & V_DBLSCAN) 1147 ? RADEON_CRTC2_DBL_SCAN_EN 1148 : 0) 1149 | ((mode->Flags & V_CSYNC) 1150 ? RADEON_CRTC2_CSYNC_EN 1151 : 0) 1152 | ((mode->Flags & V_INTERLACE) 1153 ? RADEON_CRTC2_INTERLACE_EN 1154 : 0)); 1155 1156 save->disp2_merge_cntl = info->SavedReg->disp2_merge_cntl; 1157 save->disp2_merge_cntl &= ~(RADEON_DISP2_RGB_OFFSET_EN); 1158 1159 save->fp_h2_sync_strt_wid = save->crtc2_h_sync_strt_wid; 1160 save->fp_v2_sync_strt_wid = save->crtc2_v_sync_strt_wid; 1161 1162 return TRUE; 1163} 1164 1165 1166/* Define PLL registers for requested video mode */ 1167static void 1168RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, 1169 RADEONPLLPtr pll, DisplayModePtr mode, 1170 int flags) 1171{ 1172 RADEONInfoPtr info = RADEONPTR(pScrn); 1173 uint32_t feedback_div = 0; 1174 uint32_t reference_div = 0; 1175 uint32_t post_divider = 0; 1176 uint32_t freq = 0; 1177 1178 struct { 1179 int divider; 1180 int bitvalue; 1181 } *post_div, post_divs[] = { 1182 /* From RAGE 128 VR/RAGE 128 GL Register 1183 * Reference Manual (Technical Reference 1184 * Manual P/N RRG-G04100-C Rev. 0.04), page 1185 * 3-17 (PLL_DIV_[3:0]). 1186 */ 1187 { 1, 0 }, /* VCLK_SRC */ 1188 { 2, 1 }, /* VCLK_SRC/2 */ 1189 { 4, 2 }, /* VCLK_SRC/4 */ 1190 { 8, 3 }, /* VCLK_SRC/8 */ 1191 { 3, 4 }, /* VCLK_SRC/3 */ 1192 { 16, 5 }, /* VCLK_SRC/16 */ 1193 { 6, 6 }, /* VCLK_SRC/6 */ 1194 { 12, 7 }, /* VCLK_SRC/12 */ 1195 { 0, 0 } 1196 }; 1197 1198 1199 if ((flags & RADEON_PLL_USE_BIOS_DIVS) && info->UseBiosDividers) { 1200 save->ppll_ref_div = info->RefDivider; 1201 save->ppll_div_3 = info->FeedbackDivider | (info->PostDivider << 16); 1202 save->htotal_cntl = 0; 1203 return; 1204 } 1205 1206 RADEONComputePLL(pll, mode->Clock, &freq, &feedback_div, &reference_div, &post_divider, flags); 1207 1208 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { 1209 if (post_div->divider == post_divider) 1210 break; 1211 } 1212 1213 if (!post_div->divider) { 1214 save->pll_output_freq = freq; 1215 post_div = &post_divs[0]; 1216 } 1217 1218 save->dot_clock_freq = freq; 1219 save->feedback_div = feedback_div; 1220 save->reference_div = reference_div; 1221 save->post_div = post_divider; 1222 1223 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1224 "dc=%u, of=%u, fd=%d, rd=%d, pd=%d\n", 1225 (unsigned)save->dot_clock_freq, 1226 (unsigned)save->pll_output_freq, 1227 save->feedback_div, 1228 save->reference_div, 1229 save->post_div); 1230 1231 save->ppll_ref_div = save->reference_div; 1232 1233#if defined(__powerpc__) 1234 /* apparently programming this otherwise causes a hang??? */ 1235 if (info->MacModel == RADEON_MAC_IBOOK) 1236 save->ppll_div_3 = 0x000600ad; 1237 else 1238#endif 1239 save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16)); 1240 1241 save->htotal_cntl = mode->HTotal & 0x7; 1242 1243 save->vclk_ecp_cntl = (info->SavedReg->vclk_ecp_cntl & 1244 ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK; 1245} 1246 1247/* Define PLL2 registers for requested video mode */ 1248static void 1249RADEONInitPLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save, 1250 RADEONPLLPtr pll, DisplayModePtr mode, 1251 int flags) 1252{ 1253 RADEONInfoPtr info = RADEONPTR(pScrn); 1254 uint32_t feedback_div = 0; 1255 uint32_t reference_div = 0; 1256 uint32_t post_divider = 0; 1257 uint32_t freq = 0; 1258 1259 struct { 1260 int divider; 1261 int bitvalue; 1262 } *post_div, post_divs[] = { 1263 /* From RAGE 128 VR/RAGE 128 GL Register 1264 * Reference Manual (Technical Reference 1265 * Manual P/N RRG-G04100-C Rev. 0.04), page 1266 * 3-17 (PLL_DIV_[3:0]). 1267 */ 1268 { 1, 0 }, /* VCLK_SRC */ 1269 { 2, 1 }, /* VCLK_SRC/2 */ 1270 { 4, 2 }, /* VCLK_SRC/4 */ 1271 { 8, 3 }, /* VCLK_SRC/8 */ 1272 { 3, 4 }, /* VCLK_SRC/3 */ 1273 { 6, 6 }, /* VCLK_SRC/6 */ 1274 { 12, 7 }, /* VCLK_SRC/12 */ 1275 { 0, 0 } 1276 }; 1277 1278 if ((flags & RADEON_PLL_USE_BIOS_DIVS) && info->UseBiosDividers) { 1279 save->p2pll_ref_div = info->RefDivider; 1280 save->p2pll_div_0 = info->FeedbackDivider | (info->PostDivider << 16); 1281 save->htotal_cntl2 = 0; 1282 return; 1283 } 1284 1285 RADEONComputePLL(pll, mode->Clock, &freq, &feedback_div, &reference_div, &post_divider, flags); 1286 1287 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { 1288 if (post_div->divider == post_divider) 1289 break; 1290 } 1291 1292 if (!post_div->divider) { 1293 save->pll_output_freq_2 = freq; 1294 post_div = &post_divs[0]; 1295 } 1296 1297 save->dot_clock_freq_2 = freq; 1298 save->feedback_div_2 = feedback_div; 1299 save->reference_div_2 = reference_div; 1300 save->post_div_2 = post_divider; 1301 1302 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1303 "dc=%u, of=%u, fd=%d, rd=%d, pd=%d\n", 1304 (unsigned)save->dot_clock_freq_2, 1305 (unsigned)save->pll_output_freq_2, 1306 save->feedback_div_2, 1307 save->reference_div_2, 1308 save->post_div_2); 1309 1310 save->p2pll_ref_div = save->reference_div_2; 1311 1312 save->p2pll_div_0 = (save->feedback_div_2 | 1313 (post_div->bitvalue << 16)); 1314 1315 save->htotal_cntl2 = mode->HTotal & 0x7; 1316 1317 save->pixclks_cntl = ((info->SavedReg->pixclks_cntl & 1318 ~(RADEON_PIX2CLK_SRC_SEL_MASK)) | 1319 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK); 1320} 1321 1322static void 1323radeon_update_tv_routing(ScrnInfoPtr pScrn, RADEONSavePtr restore) 1324{ 1325 /* pixclks_cntl controls tv clock routing */ 1326 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, restore->pixclks_cntl); 1327} 1328 1329/* Calculate display buffer watermark to prevent buffer underflow */ 1330static void 1331RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int pixel_bytes2, DisplayModePtr mode1, DisplayModePtr mode2) 1332{ 1333 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1334 unsigned char *RADEONMMIO = info->MMIO; 1335 1336 uint32_t temp, data, mem_trcd, mem_trp, mem_tras, mem_trbs=0; 1337 float mem_tcas; 1338 int k1, c; 1339 uint32_t MemTrcdExtMemCntl[4] = {1, 2, 3, 4}; 1340 uint32_t MemTrpExtMemCntl[4] = {1, 2, 3, 4}; 1341 uint32_t MemTrasExtMemCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8}; 1342 1343 uint32_t MemTrcdMemTimingCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8}; 1344 uint32_t MemTrpMemTimingCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8}; 1345 uint32_t MemTrasMemTimingCntl[16] = {4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19}; 1346 1347 float MemTcas[8] = {0, 1, 2, 3, 0, 1.5, 2.5, 0}; 1348 float MemTcas2[8] = {0, 1, 2, 3, 4, 5, 6, 7}; 1349 float MemTrbs[8] = {1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5}; 1350 1351 float mem_bw, peak_disp_bw; 1352 float min_mem_eff = 0.8; 1353 float sclk_eff, sclk_delay; 1354 float mc_latency_mclk, mc_latency_sclk, cur_latency_mclk, cur_latency_sclk; 1355 float disp_latency, disp_latency_overhead, disp_drain_rate, disp_drain_rate2; 1356 float pix_clk, pix_clk2; /* in MHz */ 1357 int cur_size = 16; /* in octawords */ 1358 int critical_point, critical_point2; 1359 int stop_req, max_stop_req; 1360 float read_return_rate, time_disp1_drop_priority; 1361 1362 /* 1363 * Set display0/1 priority up on r3/4xx in the memory controller for 1364 * high res modes if the user specifies HIGH for displaypriority 1365 * option. 1366 */ 1367 if ((info->DispPriority == 2) && IS_R300_VARIANT) { 1368 uint32_t mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER); 1369 if (pRADEONEnt->pCrtc[1]->enabled) { 1370 mc_init_misc_lat_timer |= 0x1100; /* display 0 and 1 */ 1371 } else { 1372 mc_init_misc_lat_timer |= 0x0100; /* display 0 only */ 1373 } 1374 OUTREG(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer); 1375 } 1376 1377 1378 /* R420 and RV410 family not supported yet */ 1379 if (info->ChipFamily == CHIP_FAMILY_R420 || info->ChipFamily == CHIP_FAMILY_RV410) return; 1380 1381 /* 1382 * Determine if there is enough bandwidth for current display mode 1383 */ 1384 mem_bw = info->mclk * (info->RamWidth / 8) * (info->IsDDR ? 2 : 1); 1385 1386 pix_clk = mode1->Clock/1000.0; 1387 if (mode2) 1388 pix_clk2 = mode2->Clock/1000.0; 1389 else 1390 pix_clk2 = 0; 1391 1392 peak_disp_bw = (pix_clk * info->CurrentLayout.pixel_bytes); 1393 if (pixel_bytes2) 1394 peak_disp_bw += (pix_clk2 * pixel_bytes2); 1395 1396 if (peak_disp_bw >= mem_bw * min_mem_eff) { 1397 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1398 "You may not have enough display bandwidth for current mode\n" 1399 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"); 1400 } 1401 1402 /* CRTC1 1403 Set GRPH_BUFFER_CNTL register using h/w defined optimal values. 1404 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ] 1405 */ 1406 stop_req = mode1->HDisplay * info->CurrentLayout.pixel_bytes / 16; 1407 1408 /* setup Max GRPH_STOP_REQ default value */ 1409 if (IS_RV100_VARIANT) 1410 max_stop_req = 0x5c; 1411 else 1412 max_stop_req = 0x7c; 1413 if (stop_req > max_stop_req) 1414 stop_req = max_stop_req; 1415 1416 /* Get values from the EXT_MEM_CNTL register...converting its contents. */ 1417 temp = INREG(RADEON_MEM_TIMING_CNTL); 1418 if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */ 1419 mem_trcd = MemTrcdExtMemCntl[(temp & 0x0c) >> 2]; 1420 mem_trp = MemTrpExtMemCntl[ (temp & 0x03) >> 0]; 1421 mem_tras = MemTrasExtMemCntl[(temp & 0x70) >> 4]; 1422 } else { /* RV200 and later */ 1423 mem_trcd = MemTrcdMemTimingCntl[(temp & 0x07) >> 0]; 1424 mem_trp = MemTrpMemTimingCntl[ (temp & 0x700) >> 8]; 1425 mem_tras = MemTrasMemTimingCntl[(temp & 0xf000) >> 12]; 1426 } 1427 1428 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */ 1429 temp = INREG(RADEON_MEM_SDRAM_MODE_REG); 1430 data = (temp & (7<<20)) >> 20; 1431 if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */ 1432 mem_tcas = MemTcas [data]; 1433 } else { 1434 mem_tcas = MemTcas2 [data]; 1435 } 1436 1437 if (IS_R300_VARIANT) { 1438 1439 /* on the R300, Tcas is included in Trbs. 1440 */ 1441 temp = INREG(RADEON_MEM_CNTL); 1442 data = (R300_MEM_NUM_CHANNELS_MASK & temp); 1443 if (data == 1) { 1444 if (R300_MEM_USE_CD_CH_ONLY & temp) { 1445 temp = INREG(R300_MC_IND_INDEX); 1446 temp &= ~R300_MC_IND_ADDR_MASK; 1447 temp |= R300_MC_READ_CNTL_CD_mcind; 1448 OUTREG(R300_MC_IND_INDEX, temp); 1449 temp = INREG(R300_MC_IND_DATA); 1450 data = (R300_MEM_RBS_POSITION_C_MASK & temp); 1451 } else { 1452 temp = INREG(R300_MC_READ_CNTL_AB); 1453 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 1454 } 1455 } else { 1456 temp = INREG(R300_MC_READ_CNTL_AB); 1457 data = (R300_MEM_RBS_POSITION_A_MASK & temp); 1458 } 1459 1460 mem_trbs = MemTrbs[data]; 1461 mem_tcas += mem_trbs; 1462 } 1463 1464 if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100, M6, IGPs */ 1465 /* DDR64 SCLK_EFF = SCLK for analysis */ 1466 sclk_eff = info->sclk; 1467 } else { 1468#ifdef XF86DRI 1469 if (info->directRenderingEnabled) 1470 sclk_eff = info->sclk - (info->agpMode * 50.0 / 3.0); 1471 else 1472#endif 1473 sclk_eff = info->sclk; 1474 } 1475 1476 /* Find the memory controller latency for the display client. 1477 */ 1478 if (IS_R300_VARIANT) { 1479 /*not enough for R350 ???*/ 1480 /* 1481 if (!mode2) sclk_delay = 150; 1482 else { 1483 if (info->RamWidth == 256) sclk_delay = 87; 1484 else sclk_delay = 97; 1485 } 1486 */ 1487 sclk_delay = 250; 1488 } else { 1489 if ((info->ChipFamily == CHIP_FAMILY_RV100) || 1490 info->IsIGP) { 1491 if (info->IsDDR) sclk_delay = 41; 1492 else sclk_delay = 33; 1493 } else { 1494 if (info->RamWidth == 128) sclk_delay = 57; 1495 else sclk_delay = 41; 1496 } 1497 } 1498 1499 mc_latency_sclk = sclk_delay / sclk_eff; 1500 1501 if (info->IsDDR) { 1502 if (info->RamWidth == 32) { 1503 k1 = 40; 1504 c = 3; 1505 } else { 1506 k1 = 20; 1507 c = 1; 1508 } 1509 } else { 1510 k1 = 40; 1511 c = 3; 1512 } 1513 mc_latency_mclk = ((2.0*mem_trcd + mem_tcas*c + 4.0*mem_tras + 4.0*mem_trp + k1) / 1514 info->mclk) + (4.0 / sclk_eff); 1515 1516 /* 1517 HW cursor time assuming worst case of full size colour cursor. 1518 */ 1519 cur_latency_mclk = (mem_trp + MAX(mem_tras, (mem_trcd + 2*(cur_size - (info->IsDDR+1))))) / info->mclk; 1520 cur_latency_sclk = cur_size / sclk_eff; 1521 1522 /* 1523 Find the total latency for the display data. 1524 */ 1525 disp_latency_overhead = 8.0 / info->sclk; 1526 mc_latency_mclk = mc_latency_mclk + disp_latency_overhead + cur_latency_mclk; 1527 mc_latency_sclk = mc_latency_sclk + disp_latency_overhead + cur_latency_sclk; 1528 disp_latency = MAX(mc_latency_mclk, mc_latency_sclk); 1529 1530 /* 1531 Find the drain rate of the display buffer. 1532 */ 1533 disp_drain_rate = pix_clk / (16.0/info->CurrentLayout.pixel_bytes); 1534 if (pixel_bytes2) 1535 disp_drain_rate2 = pix_clk2 / (16.0/pixel_bytes2); 1536 else 1537 disp_drain_rate2 = 0; 1538 1539 /* 1540 Find the critical point of the display buffer. 1541 */ 1542 critical_point= (uint32_t)(disp_drain_rate * disp_latency + 0.5); 1543 1544 /* ???? */ 1545 /* 1546 temp = (info->SavedReg.grph_buffer_cntl & RADEON_GRPH_CRITICAL_POINT_MASK) >> RADEON_GRPH_CRITICAL_POINT_SHIFT; 1547 if (critical_point < temp) critical_point = temp; 1548 */ 1549 if (info->DispPriority == 2) { 1550 critical_point = 0; 1551 } 1552 1553 /* 1554 The critical point should never be above max_stop_req-4. Setting 1555 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time. 1556 */ 1557 if (max_stop_req - critical_point < 4) critical_point = 0; 1558 1559 if (critical_point == 0 && mode2 && info->ChipFamily == CHIP_FAMILY_R300) { 1560 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/ 1561 critical_point = 0x10; 1562 } 1563 1564 temp = info->SavedReg->grph_buffer_cntl; 1565 temp &= ~(RADEON_GRPH_STOP_REQ_MASK); 1566 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 1567 temp &= ~(RADEON_GRPH_START_REQ_MASK); 1568 if ((info->ChipFamily == CHIP_FAMILY_R350) && 1569 (stop_req > 0x15)) { 1570 stop_req -= 0x10; 1571 } 1572 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 1573 1574 temp |= RADEON_GRPH_BUFFER_SIZE; 1575 temp &= ~(RADEON_GRPH_CRITICAL_CNTL | 1576 RADEON_GRPH_CRITICAL_AT_SOF | 1577 RADEON_GRPH_STOP_CNTL); 1578 /* 1579 Write the result into the register. 1580 */ 1581 OUTREG(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 1582 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 1583 1584#if 0 1585 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 1586 (info->ChipFamily == CHIP_FAMILY_RS480)) { 1587 /* attempt to program RS400 disp regs correctly ??? */ 1588 temp = info->SavedReg->disp1_req_cntl1; 1589 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK | 1590 RS400_DISP1_STOP_REQ_LEVEL_MASK); 1591 OUTREG(RS400_DISP1_REQ_CNTL1, (temp | 1592 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 1593 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 1594 temp = info->SavedReg->dmif_mem_cntl1; 1595 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK | 1596 RS400_DISP1_CRITICAL_POINT_STOP_MASK); 1597 OUTREG(RS400_DMIF_MEM_CNTL1, (temp | 1598 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) | 1599 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT))); 1600 } 1601#endif 1602 1603 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1604 "GRPH_BUFFER_CNTL from %x to %x\n", 1605 (unsigned int)info->SavedReg->grph_buffer_cntl, 1606 (unsigned int)INREG(RADEON_GRPH_BUFFER_CNTL)); 1607 1608 if (mode2) { 1609 stop_req = mode2->HDisplay * pixel_bytes2 / 16; 1610 1611 if (stop_req > max_stop_req) stop_req = max_stop_req; 1612 1613 temp = info->SavedReg->grph2_buffer_cntl; 1614 temp &= ~(RADEON_GRPH_STOP_REQ_MASK); 1615 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT); 1616 temp &= ~(RADEON_GRPH_START_REQ_MASK); 1617 if ((info->ChipFamily == CHIP_FAMILY_R350) && 1618 (stop_req > 0x15)) { 1619 stop_req -= 0x10; 1620 } 1621 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT); 1622 temp |= RADEON_GRPH_BUFFER_SIZE; 1623 temp &= ~(RADEON_GRPH_CRITICAL_CNTL | 1624 RADEON_GRPH_CRITICAL_AT_SOF | 1625 RADEON_GRPH_STOP_CNTL); 1626 1627 if ((info->ChipFamily == CHIP_FAMILY_RS100) || 1628 (info->ChipFamily == CHIP_FAMILY_RS200)) 1629 critical_point2 = 0; 1630 else { 1631 read_return_rate = MIN(info->sclk, info->mclk*(info->RamWidth*(info->IsDDR+1)/128)); 1632 time_disp1_drop_priority = critical_point / (read_return_rate - disp_drain_rate); 1633 1634 critical_point2 = (uint32_t)((disp_latency + time_disp1_drop_priority + 1635 disp_latency) * disp_drain_rate2 + 0.5); 1636 1637 if (info->DispPriority == 2) { 1638 critical_point2 = 0; 1639 } 1640 1641 if (max_stop_req - critical_point2 < 4) critical_point2 = 0; 1642 1643 } 1644 1645 if (critical_point2 == 0 && info->ChipFamily == CHIP_FAMILY_R300) { 1646 /* some R300 cards have problem with this set to 0 */ 1647 critical_point2 = 0x10; 1648 } 1649 1650 OUTREG(RADEON_GRPH2_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) | 1651 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT))); 1652 1653 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 1654 (info->ChipFamily == CHIP_FAMILY_RS480)) { 1655#if 0 1656 /* attempt to program RS400 disp2 regs correctly ??? */ 1657 temp = info->SavedReg->disp2_req_cntl1; 1658 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK | 1659 RS400_DISP2_STOP_REQ_LEVEL_MASK); 1660 OUTREG(RS400_DISP2_REQ_CNTL1, (temp | 1661 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) | 1662 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT))); 1663 temp = info->SavedReg->disp2_req_cntl2; 1664 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK | 1665 RS400_DISP2_CRITICAL_POINT_STOP_MASK); 1666 OUTREG(RS400_DISP2_REQ_CNTL2, (temp | 1667 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) | 1668 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT))); 1669#endif 1670 OUTREG(RS400_DISP2_REQ_CNTL1, 0x105DC1CC); 1671 OUTREG(RS400_DISP2_REQ_CNTL2, 0x2749D000); 1672 OUTREG(RS400_DMIF_MEM_CNTL1, 0x29CA71DC); 1673 OUTREG(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC); 1674 } 1675 1676 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1677 "GRPH2_BUFFER_CNTL from %x to %x\n", 1678 (unsigned int)info->SavedReg->grph2_buffer_cntl, 1679 (unsigned int)INREG(RADEON_GRPH2_BUFFER_CNTL)); 1680 } 1681} 1682 1683void 1684RADEONInitDispBandwidth(ScrnInfoPtr pScrn) 1685{ 1686 RADEONInfoPtr info = RADEONPTR(pScrn); 1687 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 1688 DisplayModePtr mode1, mode2; 1689 int pixel_bytes2 = 0; 1690 1691 if (info->IsPrimary || info->IsSecondary) 1692 mode1 = &xf86_config->crtc[0]->mode; 1693 else 1694 mode1 = info->CurrentLayout.mode; 1695 mode2 = NULL; 1696 pixel_bytes2 = info->CurrentLayout.pixel_bytes; 1697 1698 if (xf86_config->num_crtc == 2) { 1699 pixel_bytes2 = 0; 1700 mode2 = NULL; 1701 1702 if (xf86_config->crtc[1]->enabled && xf86_config->crtc[0]->enabled) { 1703 pixel_bytes2 = info->CurrentLayout.pixel_bytes; 1704 mode1 = &xf86_config->crtc[0]->mode; 1705 mode2 = &xf86_config->crtc[1]->mode; 1706 } else if (xf86_config->crtc[0]->enabled) { 1707 mode1 = &xf86_config->crtc[0]->mode; 1708 } else if (xf86_config->crtc[1]->enabled) { 1709 mode1 = &xf86_config->crtc[1]->mode; 1710 } else 1711 return; 1712 } else { 1713 if (xf86_config->crtc[0]->enabled) 1714 mode1 = &xf86_config->crtc[0]->mode; 1715 else 1716 return; 1717 } 1718 1719 RADEONInitDispBandwidth2(pScrn, info, pixel_bytes2, mode1, mode2); 1720} 1721 1722void 1723legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, 1724 DisplayModePtr adjusted_mode, int x, int y) 1725{ 1726 ScrnInfoPtr pScrn = crtc->scrn; 1727 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 1728 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 1729 RADEONInfoPtr info = RADEONPTR(pScrn); 1730 int i = 0; 1731 double dot_clock = 0; 1732 int pll_flags = RADEON_PLL_LEGACY | RADEON_PLL_PREFER_LOW_REF_DIV; 1733 Bool update_tv_routing = FALSE; 1734 Bool tilingChanged = FALSE; 1735 1736 if (info->allowColorTiling) { 1737 radeon_crtc->can_tile = (adjusted_mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; 1738 tilingChanged = RADEONSetTiling(pScrn); 1739 } 1740 1741 for (i = 0; i < xf86_config->num_output; i++) { 1742 xf86OutputPtr output = xf86_config->output[i]; 1743 RADEONOutputPrivatePtr radeon_output = output->driver_private; 1744 1745 if (output->crtc == crtc) { 1746 if (radeon_output->MonType != MT_CRT) 1747 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; 1748 if (radeon_output->MonType == MT_LCD) 1749 pll_flags |= (RADEON_PLL_USE_BIOS_DIVS | RADEON_PLL_USE_REF_DIV); 1750 } 1751 } 1752 1753 1754 ErrorF("init memmap\n"); 1755 RADEONInitMemMapRegisters(pScrn, info->ModeReg, info); 1756 ErrorF("init common\n"); 1757 RADEONInitCommonRegisters(info->ModeReg, info); 1758 1759 RADEONInitSurfaceCntl(crtc, info->ModeReg); 1760 1761 switch (radeon_crtc->crtc_id) { 1762 case 0: 1763 ErrorF("init crtc1\n"); 1764 RADEONInitCrtcRegisters(crtc, info->ModeReg, adjusted_mode); 1765 RADEONInitCrtcBase(crtc, info->ModeReg, x, y); 1766 dot_clock = adjusted_mode->Clock / 1000.0; 1767 if (dot_clock) { 1768 ErrorF("init pll1\n"); 1769 RADEONInitPLLRegisters(pScrn, info->ModeReg, &info->pll, adjusted_mode, pll_flags); 1770 } else { 1771 info->ModeReg->ppll_ref_div = info->SavedReg->ppll_ref_div; 1772 info->ModeReg->ppll_div_3 = info->SavedReg->ppll_div_3; 1773 info->ModeReg->htotal_cntl = info->SavedReg->htotal_cntl; 1774 } 1775 break; 1776 case 1: 1777 ErrorF("init crtc2\n"); 1778 RADEONInitCrtc2Registers(crtc, info->ModeReg, adjusted_mode); 1779 RADEONInitCrtc2Base(crtc, info->ModeReg, x, y); 1780 dot_clock = adjusted_mode->Clock / 1000.0; 1781 if (dot_clock) { 1782 ErrorF("init pll2\n"); 1783 RADEONInitPLL2Registers(pScrn, info->ModeReg, &info->pll, adjusted_mode, pll_flags); 1784 } 1785 break; 1786 } 1787 1788 for (i = 0; i < xf86_config->num_output; i++) { 1789 xf86OutputPtr output = xf86_config->output[i]; 1790 RADEONOutputPrivatePtr radeon_output = output->driver_private; 1791 1792 if (output->crtc == crtc) { 1793 if (radeon_output->MonType == MT_STV || radeon_output->MonType == MT_CTV) { 1794 switch (radeon_crtc->crtc_id) { 1795 case 0: 1796 RADEONAdjustCrtcRegistersForTV(pScrn, info->ModeReg, adjusted_mode, output); 1797 RADEONAdjustPLLRegistersForTV(pScrn, info->ModeReg, adjusted_mode, output); 1798 update_tv_routing = TRUE; 1799 break; 1800 case 1: 1801 RADEONAdjustCrtc2RegistersForTV(pScrn, info->ModeReg, adjusted_mode, output); 1802 RADEONAdjustPLL2RegistersForTV(pScrn, info->ModeReg, adjusted_mode, output); 1803 break; 1804 } 1805 } 1806 } 1807 } 1808 1809 ErrorF("restore memmap\n"); 1810 RADEONRestoreMemMapRegisters(pScrn, info->ModeReg); 1811 ErrorF("restore common\n"); 1812 RADEONRestoreCommonRegisters(pScrn, info->ModeReg); 1813 1814 switch (radeon_crtc->crtc_id) { 1815 case 0: 1816 ErrorF("restore crtc1\n"); 1817 RADEONRestoreCrtcRegisters(pScrn, info->ModeReg); 1818 ErrorF("restore pll1\n"); 1819 RADEONRestorePLLRegisters(pScrn, info->ModeReg); 1820 break; 1821 case 1: 1822 ErrorF("restore crtc2\n"); 1823 RADEONRestoreCrtc2Registers(pScrn, info->ModeReg); 1824 ErrorF("restore pll2\n"); 1825 RADEONRestorePLL2Registers(pScrn, info->ModeReg); 1826 break; 1827 } 1828 1829 /* pixclks_cntl handles tv-out clock routing */ 1830 if (update_tv_routing) 1831 radeon_update_tv_routing(pScrn, info->ModeReg); 1832 1833 if (info->DispPriority) 1834 RADEONInitDispBandwidth(pScrn); 1835 1836 if (tilingChanged) { 1837 /* need to redraw front buffer, I guess this can be considered a hack ? */ 1838 /* if this is called during ScreenInit() we don't have pScrn->pScreen yet */ 1839 if (pScrn->pScreen) 1840 xf86EnableDisableFBAccess(pScrn->scrnIndex, FALSE); 1841 RADEONChangeSurfaces(pScrn); 1842 if (pScrn->pScreen) 1843 xf86EnableDisableFBAccess(pScrn->scrnIndex, TRUE); 1844 /* xf86SetRootClip would do, but can't access that here */ 1845 } 1846 1847 /* reset ecp_div for Xv */ 1848 info->ecp_div = -1; 1849 1850} 1851 1852