1b7e1c893Smrg/* 2b7e1c893Smrg * RadeonHD R6xx, R7xx Register documentation 3b7e1c893Smrg * 4b7e1c893Smrg * Copyright (C) 2008-2009 Advanced Micro Devices, Inc. 5b7e1c893Smrg * Copyright (C) 2008-2009 Matthias Hopf 6b7e1c893Smrg * 7b7e1c893Smrg * Permission is hereby granted, free of charge, to any person obtaining a 8b7e1c893Smrg * copy of this software and associated documentation files (the "Software"), 9b7e1c893Smrg * to deal in the Software without restriction, including without limitation 10b7e1c893Smrg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11b7e1c893Smrg * and/or sell copies of the Software, and to permit persons to whom the 12b7e1c893Smrg * Software is furnished to do so, subject to the following conditions: 13b7e1c893Smrg * 14b7e1c893Smrg * The above copyright notice and this permission notice shall be included 15b7e1c893Smrg * in all copies or substantial portions of the Software. 16b7e1c893Smrg * 17b7e1c893Smrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18b7e1c893Smrg * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19b7e1c893Smrg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20b7e1c893Smrg * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 21b7e1c893Smrg * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 22b7e1c893Smrg * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23b7e1c893Smrg */ 24b7e1c893Smrg 25b7e1c893Smrg#ifndef _R600_REG_R6xx_H_ 26b7e1c893Smrg#define _R600_REG_R6xx_H_ 27b7e1c893Smrg 28b7e1c893Smrg/* 29b7e1c893Smrg * Registers for R6xx chips that are not documented yet 30b7e1c893Smrg */ 31b7e1c893Smrg 32b7e1c893Smrgenum { 33b7e1c893Smrg 34b7e1c893Smrg MM_INDEX = 0x0000, 35b7e1c893Smrg MM_DATA = 0x0004, 36b7e1c893Smrg 37b7e1c893Smrg SRBM_STATUS = 0x0e50, 38b7e1c893Smrg RLC_RQ_PENDING_bit = 1 << 3, 39b7e1c893Smrg RCU_RQ_PENDING_bit = 1 << 4, 40b7e1c893Smrg GRBM_RQ_PENDING_bit = 1 << 5, 41b7e1c893Smrg HI_RQ_PENDING_bit = 1 << 6, 42b7e1c893Smrg IO_EXTERN_SIGNAL_bit = 1 << 7, 43b7e1c893Smrg VMC_BUSY_bit = 1 << 8, 44b7e1c893Smrg MCB_BUSY_bit = 1 << 9, 45b7e1c893Smrg MCDZ_BUSY_bit = 1 << 10, 46b7e1c893Smrg MCDY_BUSY_bit = 1 << 11, 47b7e1c893Smrg MCDX_BUSY_bit = 1 << 12, 48b7e1c893Smrg MCDW_BUSY_bit = 1 << 13, 49b7e1c893Smrg SEM_BUSY_bit = 1 << 14, 50b7e1c893Smrg SRBM_STATUS__RLC_BUSY_bit = 1 << 15, 51b7e1c893Smrg PDMA_BUSY_bit = 1 << 16, 52b7e1c893Smrg IH_BUSY_bit = 1 << 17, 53b7e1c893Smrg CSC_BUSY_bit = 1 << 20, 54b7e1c893Smrg CMC7_BUSY_bit = 1 << 21, 55b7e1c893Smrg CMC6_BUSY_bit = 1 << 22, 56b7e1c893Smrg CMC5_BUSY_bit = 1 << 23, 57b7e1c893Smrg CMC4_BUSY_bit = 1 << 24, 58b7e1c893Smrg CMC3_BUSY_bit = 1 << 25, 59b7e1c893Smrg CMC2_BUSY_bit = 1 << 26, 60b7e1c893Smrg CMC1_BUSY_bit = 1 << 27, 61b7e1c893Smrg CMC0_BUSY_bit = 1 << 28, 62b7e1c893Smrg BIF_BUSY_bit = 1 << 29, 63b7e1c893Smrg IDCT_BUSY_bit = 1 << 30, 64b7e1c893Smrg 65b7e1c893Smrg SRBM_READ_ERROR = 0x0e98, 66b7e1c893Smrg READ_ADDRESS_mask = 0xffff << 2, 67b7e1c893Smrg READ_ADDRESS_shift = 2, 68b7e1c893Smrg READ_REQUESTER_HI_bit = 1 << 24, 69b7e1c893Smrg READ_REQUESTER_GRBM_bit = 1 << 25, 70b7e1c893Smrg READ_REQUESTER_RCU_bit = 1 << 26, 71b7e1c893Smrg READ_REQUESTER_RLC_bit = 1 << 27, 72b7e1c893Smrg READ_ERROR_bit = 1 << 31, 73b7e1c893Smrg 74b7e1c893Smrg SRBM_INT_STATUS = 0x0ea4, 75b7e1c893Smrg RDERR_INT_STAT_bit = 1 << 0, 76b7e1c893Smrg GFX_CNTX_SWITCH_INT_STAT_bit = 1 << 1, 77b7e1c893Smrg SRBM_INT_ACK = 0x0ea8, 78b7e1c893Smrg RDERR_INT_ACK_bit = 1 << 0, 79b7e1c893Smrg GFX_CNTX_SWITCH_INT_ACK_bit = 1 << 1, 80b7e1c893Smrg 81b7e1c893Smrg R6XX_MC_VM_FB_LOCATION = 0x2180, 82b7e1c893Smrg 83b7e1c893Smrg VENDOR_DEVICE_ID = 0x4000, 84b7e1c893Smrg 85b7e1c893Smrg HDP_MEM_COHERENCY_FLUSH_CNTL = 0x5480, 86b7e1c893Smrg 87b7e1c893Smrg D1GRPH_PRIMARY_SURFACE_ADDRESS = 0x6110, 88b7e1c893Smrg D1GRPH_PITCH = 0x6120, 89b7e1c893Smrg D1GRPH_Y_END = 0x6138, 90b7e1c893Smrg 91b7e1c893Smrg GRBM_STATUS = 0x8010, 92b7e1c893Smrg CMDFIFO_AVAIL_mask = 0x1f << 0, 93b7e1c893Smrg CMDFIFO_AVAIL_shift = 0, 94b7e1c893Smrg SRBM_RQ_PENDING_bit = 1 << 5, 95b7e1c893Smrg CP_RQ_PENDING_bit = 1 << 6, 96b7e1c893Smrg CF_RQ_PENDING_bit = 1 << 7, 97b7e1c893Smrg PF_RQ_PENDING_bit = 1 << 8, 98b7e1c893Smrg GRBM_EE_BUSY_bit = 1 << 10, 99b7e1c893Smrg GRBM_STATUS__VC_BUSY_bit = 1 << 11, 100b7e1c893Smrg DB03_CLEAN_bit = 1 << 12, 101b7e1c893Smrg CB03_CLEAN_bit = 1 << 13, 102b7e1c893Smrg VGT_BUSY_NO_DMA_bit = 1 << 16, 103b7e1c893Smrg GRBM_STATUS__VGT_BUSY_bit = 1 << 17, 104b7e1c893Smrg TA03_BUSY_bit = 1 << 18, 105b7e1c893Smrg GRBM_STATUS__TC_BUSY_bit = 1 << 19, 106b7e1c893Smrg SX_BUSY_bit = 1 << 20, 107b7e1c893Smrg SH_BUSY_bit = 1 << 21, 108b7e1c893Smrg SPI03_BUSY_bit = 1 << 22, 109b7e1c893Smrg SMX_BUSY_bit = 1 << 23, 110b7e1c893Smrg SC_BUSY_bit = 1 << 24, 111b7e1c893Smrg PA_BUSY_bit = 1 << 25, 112b7e1c893Smrg DB03_BUSY_bit = 1 << 26, 113b7e1c893Smrg CR_BUSY_bit = 1 << 27, 114b7e1c893Smrg CP_COHERENCY_BUSY_bit = 1 << 28, 115b7e1c893Smrg GRBM_STATUS__CP_BUSY_bit = 1 << 29, 116b7e1c893Smrg CB03_BUSY_bit = 1 << 30, 117b7e1c893Smrg GUI_ACTIVE_bit = 1 << 31, 118b7e1c893Smrg GRBM_STATUS2 = 0x8014, 119b7e1c893Smrg CR_CLEAN_bit = 1 << 0, 120b7e1c893Smrg SMX_CLEAN_bit = 1 << 1, 121b7e1c893Smrg SPI0_BUSY_bit = 1 << 8, 122b7e1c893Smrg SPI1_BUSY_bit = 1 << 9, 123b7e1c893Smrg SPI2_BUSY_bit = 1 << 10, 124b7e1c893Smrg SPI3_BUSY_bit = 1 << 11, 125b7e1c893Smrg TA0_BUSY_bit = 1 << 12, 126b7e1c893Smrg TA1_BUSY_bit = 1 << 13, 127b7e1c893Smrg TA2_BUSY_bit = 1 << 14, 128b7e1c893Smrg TA3_BUSY_bit = 1 << 15, 129b7e1c893Smrg DB0_BUSY_bit = 1 << 16, 130b7e1c893Smrg DB1_BUSY_bit = 1 << 17, 131b7e1c893Smrg DB2_BUSY_bit = 1 << 18, 132b7e1c893Smrg DB3_BUSY_bit = 1 << 19, 133b7e1c893Smrg CB0_BUSY_bit = 1 << 20, 134b7e1c893Smrg CB1_BUSY_bit = 1 << 21, 135b7e1c893Smrg CB2_BUSY_bit = 1 << 22, 136b7e1c893Smrg CB3_BUSY_bit = 1 << 23, 137b7e1c893Smrg GRBM_SOFT_RESET = 0x8020, 138b7e1c893Smrg SOFT_RESET_CP_bit = 1 << 0, 139b7e1c893Smrg SOFT_RESET_CB_bit = 1 << 1, 140b7e1c893Smrg SOFT_RESET_CR_bit = 1 << 2, 141b7e1c893Smrg SOFT_RESET_DB_bit = 1 << 3, 142b7e1c893Smrg SOFT_RESET_PA_bit = 1 << 5, 143b7e1c893Smrg SOFT_RESET_SC_bit = 1 << 6, 144b7e1c893Smrg SOFT_RESET_SMX_bit = 1 << 7, 145b7e1c893Smrg SOFT_RESET_SPI_bit = 1 << 8, 146b7e1c893Smrg SOFT_RESET_SH_bit = 1 << 9, 147b7e1c893Smrg SOFT_RESET_SX_bit = 1 << 10, 148b7e1c893Smrg SOFT_RESET_TC_bit = 1 << 11, 149b7e1c893Smrg SOFT_RESET_TA_bit = 1 << 12, 150b7e1c893Smrg SOFT_RESET_VC_bit = 1 << 13, 151b7e1c893Smrg SOFT_RESET_VGT_bit = 1 << 14, 152b7e1c893Smrg SOFT_RESET_GRBM_GCA_bit = 1 << 15, 153b7e1c893Smrg 154b7e1c893Smrg WAIT_UNTIL = 0x8040, 155b7e1c893Smrg WAIT_CP_DMA_IDLE_bit = 1 << 8, 156b7e1c893Smrg WAIT_CMDFIFO_bit = 1 << 10, 157b7e1c893Smrg WAIT_2D_IDLE_bit = 1 << 14, 158b7e1c893Smrg WAIT_3D_IDLE_bit = 1 << 15, 159b7e1c893Smrg WAIT_2D_IDLECLEAN_bit = 1 << 16, 160b7e1c893Smrg WAIT_3D_IDLECLEAN_bit = 1 << 17, 161b7e1c893Smrg WAIT_EXTERN_SIG_bit = 1 << 19, 162b7e1c893Smrg CMDFIFO_ENTRIES_mask = 0x1f << 20, 163b7e1c893Smrg CMDFIFO_ENTRIES_shift = 20, 164b7e1c893Smrg 165b7e1c893Smrg GRBM_READ_ERROR = 0x8058, 166b7e1c893Smrg/* READ_ADDRESS_mask = 0xffff << 2, */ 167b7e1c893Smrg/* READ_ADDRESS_shift = 2, */ 168b7e1c893Smrg READ_REQUESTER_SRBM_bit = 1 << 28, 169b7e1c893Smrg READ_REQUESTER_CP_bit = 1 << 29, 170b7e1c893Smrg READ_REQUESTER_WU_POLL_bit = 1 << 30, 171b7e1c893Smrg/* READ_ERROR_bit = 1 << 31, */ 172b7e1c893Smrg 173b7e1c893Smrg SCRATCH_REG0 = 0x8500, 174b7e1c893Smrg SCRATCH_REG1 = 0x8504, 175b7e1c893Smrg SCRATCH_REG2 = 0x8508, 176b7e1c893Smrg SCRATCH_REG3 = 0x850c, 177b7e1c893Smrg SCRATCH_REG4 = 0x8510, 178b7e1c893Smrg SCRATCH_REG5 = 0x8514, 179b7e1c893Smrg SCRATCH_REG6 = 0x8518, 180b7e1c893Smrg SCRATCH_REG7 = 0x851c, 181b7e1c893Smrg SCRATCH_UMSK = 0x8540, 182b7e1c893Smrg SCRATCH_ADDR = 0x8544, 183b7e1c893Smrg 184b7e1c893Smrg CP_COHER_CNTL = 0x85f0, 185b7e1c893Smrg DEST_BASE_0_ENA_bit = 1 << 0, 186b7e1c893Smrg DEST_BASE_1_ENA_bit = 1 << 1, 187b7e1c893Smrg SO0_DEST_BASE_ENA_bit = 1 << 2, 188b7e1c893Smrg SO1_DEST_BASE_ENA_bit = 1 << 3, 189b7e1c893Smrg SO2_DEST_BASE_ENA_bit = 1 << 4, 190b7e1c893Smrg SO3_DEST_BASE_ENA_bit = 1 << 5, 191b7e1c893Smrg CB0_DEST_BASE_ENA_bit = 1 << 6, 192b7e1c893Smrg CB1_DEST_BASE_ENA_bit = 1 << 7, 193b7e1c893Smrg CB2_DEST_BASE_ENA_bit = 1 << 8, 194b7e1c893Smrg CB3_DEST_BASE_ENA_bit = 1 << 9, 195b7e1c893Smrg CB4_DEST_BASE_ENA_bit = 1 << 10, 196b7e1c893Smrg CB5_DEST_BASE_ENA_bit = 1 << 11, 197b7e1c893Smrg CB6_DEST_BASE_ENA_bit = 1 << 12, 198b7e1c893Smrg CB7_DEST_BASE_ENA_bit = 1 << 13, 199b7e1c893Smrg DB_DEST_BASE_ENA_bit = 1 << 14, 200b7e1c893Smrg CR_DEST_BASE_ENA_bit = 1 << 15, 201b7e1c893Smrg TC_ACTION_ENA_bit = 1 << 23, 202b7e1c893Smrg VC_ACTION_ENA_bit = 1 << 24, 203b7e1c893Smrg CB_ACTION_ENA_bit = 1 << 25, 204b7e1c893Smrg DB_ACTION_ENA_bit = 1 << 26, 205b7e1c893Smrg SH_ACTION_ENA_bit = 1 << 27, 206b7e1c893Smrg SMX_ACTION_ENA_bit = 1 << 28, 207b7e1c893Smrg CR0_ACTION_ENA_bit = 1 << 29, 208b7e1c893Smrg CR1_ACTION_ENA_bit = 1 << 30, 209b7e1c893Smrg CR2_ACTION_ENA_bit = 1 << 31, 210b7e1c893Smrg CP_COHER_SIZE = 0x85f4, 211b7e1c893Smrg CP_COHER_BASE = 0x85f8, 212b7e1c893Smrg CP_COHER_STATUS = 0x85fc, 213b7e1c893Smrg MATCHING_GFX_CNTX_mask = 0xff << 0, 214b7e1c893Smrg MATCHING_GFX_CNTX_shift = 0, 215b7e1c893Smrg MATCHING_CR_CNTX_mask = 0xffff << 8, 216b7e1c893Smrg MATCHING_CR_CNTX_shift = 8, 217b7e1c893Smrg STATUS_bit = 1 << 31, 218b7e1c893Smrg 219b7e1c893Smrg CP_STALLED_STAT1 = 0x8674, 220b7e1c893Smrg RBIU_TO_DMA_NOT_RDY_TO_RCV_bit = 1 << 0, 221b7e1c893Smrg RBIU_TO_IBS_NOT_RDY_TO_RCV_bit = 1 << 1, 222b7e1c893Smrg RBIU_TO_SEM_NOT_RDY_TO_RCV_bit = 1 << 2, 223b7e1c893Smrg RBIU_TO_2DREGS_NOT_RDY_TO_RCV_bit = 1 << 3, 224b7e1c893Smrg RBIU_TO_MEMWR_NOT_RDY_TO_RCV_bit = 1 << 4, 225b7e1c893Smrg RBIU_TO_MEMRD_NOT_RDY_TO_RCV_bit = 1 << 5, 226b7e1c893Smrg RBIU_TO_EOPD_NOT_RDY_TO_RCV_bit = 1 << 6, 227b7e1c893Smrg RBIU_TO_RECT_NOT_RDY_TO_RCV_bit = 1 << 7, 228b7e1c893Smrg RBIU_TO_STRMO_NOT_RDY_TO_RCV_bit = 1 << 8, 229b7e1c893Smrg RBIU_TO_PSTAT_NOT_RDY_TO_RCV_bit = 1 << 9, 230b7e1c893Smrg MIU_WAITING_ON_RDREQ_FREE_bit = 1 << 16, 231b7e1c893Smrg MIU_WAITING_ON_WRREQ_FREE_bit = 1 << 17, 232b7e1c893Smrg MIU_NEEDS_AVAIL_WRREQ_PHASE_bit = 1 << 18, 233b7e1c893Smrg RCIU_WAITING_ON_GRBM_FREE_bit = 1 << 24, 234b7e1c893Smrg RCIU_WAITING_ON_VGT_FREE_bit = 1 << 25, 235b7e1c893Smrg RCIU_STALLED_ON_ME_READ_bit = 1 << 26, 236b7e1c893Smrg RCIU_STALLED_ON_DMA_READ_bit = 1 << 27, 237b7e1c893Smrg RCIU_HALTED_BY_REG_VIOLATION_bit = 1 << 28, 238b7e1c893Smrg CP_STALLED_STAT2 = 0x8678, 239b7e1c893Smrg PFP_TO_CSF_NOT_RDY_TO_RCV_bit = 1 << 0, 240b7e1c893Smrg PFP_TO_MEQ_NOT_RDY_TO_RCV_bit = 1 << 1, 241b7e1c893Smrg PFP_TO_VGT_NOT_RDY_TO_RCV_bit = 1 << 2, 242b7e1c893Smrg PFP_HALTED_BY_INSTR_VIOLATION_bit = 1 << 3, 243b7e1c893Smrg MULTIPASS_IB_PENDING_IN_PFP_bit = 1 << 4, 244b7e1c893Smrg ME_BRUSH_WC_NOT_RDY_TO_RCV_bit = 1 << 8, 245b7e1c893Smrg ME_STALLED_ON_BRUSH_LOGIC_bit = 1 << 9, 246b7e1c893Smrg CR_CNTX_NOT_AVAIL_TO_ME_bit = 1 << 10, 247b7e1c893Smrg GFX_CNTX_NOT_AVAIL_TO_ME_bit = 1 << 11, 248b7e1c893Smrg ME_RCIU_NOT_RDY_TO_RCV_bit = 1 << 12, 249b7e1c893Smrg ME_TO_CONST_NOT_RDY_TO_RCV_bit = 1 << 13, 250b7e1c893Smrg ME_WAITING_DATA_FROM_PFP_bit = 1 << 14, 251b7e1c893Smrg ME_WAITING_ON_PARTIAL_FLUSH_bit = 1 << 15, 252b7e1c893Smrg RECT_FIFO_NEEDS_CR_RECT_DONE_bit = 1 << 16, 253b7e1c893Smrg RECT_FIFO_NEEDS_WR_CONFIRM_bit = 1 << 17, 254b7e1c893Smrg EOPD_FIFO_NEEDS_SC_EOP_DONE_bit = 1 << 18, 255b7e1c893Smrg EOPD_FIFO_NEEDS_SMX_EOP_DONE_bit = 1 << 19, 256b7e1c893Smrg EOPD_FIFO_NEEDS_WR_CONFIRM_bit = 1 << 20, 257b7e1c893Smrg EOPD_FIFO_NEEDS_SIGNAL_SEM_bit = 1 << 21, 258b7e1c893Smrg SO_NUMPRIM_FIFO_NEEDS_SOADDR_bit = 1 << 22, 259b7e1c893Smrg SO_NUMPRIM_FIFO_NEEDS_NUMPRIM_bit = 1 << 23, 260b7e1c893Smrg PIPE_STATS_FIFO_NEEDS_SAMPLE_bit = 1 << 24, 261b7e1c893Smrg SURF_SYNC_NEEDS_IDLE_CNTXS_bit = 1 << 30, 262b7e1c893Smrg SURF_SYNC_NEEDS_ALL_CLEAN_bit = 1 << 31, 263b7e1c893Smrg CP_BUSY_STAT = 0x867c, 264b7e1c893Smrg REG_BUS_FIFO_BUSY_bit = 1 << 0, 265b7e1c893Smrg RING_FETCHING_DATA_bit = 1 << 1, 266b7e1c893Smrg INDR1_FETCHING_DATA_bit = 1 << 2, 267b7e1c893Smrg INDR2_FETCHING_DATA_bit = 1 << 3, 268b7e1c893Smrg STATE_FETCHING_DATA_bit = 1 << 4, 269b7e1c893Smrg PRED_FETCHING_DATA_bit = 1 << 5, 270b7e1c893Smrg COHER_CNTR_NEQ_ZERO_bit = 1 << 6, 271b7e1c893Smrg PFP_PARSING_PACKETS_bit = 1 << 7, 272b7e1c893Smrg ME_PARSING_PACKETS_bit = 1 << 8, 273b7e1c893Smrg RCIU_PFP_BUSY_bit = 1 << 9, 274b7e1c893Smrg RCIU_ME_BUSY_bit = 1 << 10, 275b7e1c893Smrg OUTSTANDING_READ_TAGS_bit = 1 << 11, 276b7e1c893Smrg SEM_CMDFIFO_NOT_EMPTY_bit = 1 << 12, 277b7e1c893Smrg SEM_FAILED_AND_HOLDING_bit = 1 << 13, 278b7e1c893Smrg SEM_POLLING_FOR_PASS_bit = 1 << 14, 279b7e1c893Smrg _3D_BUSY_bit = 1 << 15, 280b7e1c893Smrg _2D_BUSY_bit = 1 << 16, 281b7e1c893Smrg CP_STAT = 0x8680, 282b7e1c893Smrg CSF_RING_BUSY_bit = 1 << 0, 283b7e1c893Smrg CSF_WPTR_POLL_BUSY_bit = 1 << 1, 284b7e1c893Smrg CSF_INDIRECT1_BUSY_bit = 1 << 2, 285b7e1c893Smrg CSF_INDIRECT2_BUSY_bit = 1 << 3, 286b7e1c893Smrg CSF_STATE_BUSY_bit = 1 << 4, 287b7e1c893Smrg CSF_PREDICATE_BUSY_bit = 1 << 5, 288b7e1c893Smrg CSF_BUSY_bit = 1 << 6, 289b7e1c893Smrg MIU_RDREQ_BUSY_bit = 1 << 7, 290b7e1c893Smrg MIU_WRREQ_BUSY_bit = 1 << 8, 291b7e1c893Smrg ROQ_RING_BUSY_bit = 1 << 9, 292b7e1c893Smrg ROQ_INDIRECT1_BUSY_bit = 1 << 10, 293b7e1c893Smrg ROQ_INDIRECT2_BUSY_bit = 1 << 11, 294b7e1c893Smrg ROQ_STATE_BUSY_bit = 1 << 12, 295b7e1c893Smrg ROQ_PREDICATE_BUSY_bit = 1 << 13, 296b7e1c893Smrg ROQ_ALIGN_BUSY_bit = 1 << 14, 297b7e1c893Smrg PFP_BUSY_bit = 1 << 15, 298b7e1c893Smrg MEQ_BUSY_bit = 1 << 16, 299b7e1c893Smrg ME_BUSY_bit = 1 << 17, 300b7e1c893Smrg QUERY_BUSY_bit = 1 << 18, 301b7e1c893Smrg SEMAPHORE_BUSY_bit = 1 << 19, 302b7e1c893Smrg INTERRUPT_BUSY_bit = 1 << 20, 303b7e1c893Smrg SURFACE_SYNC_BUSY_bit = 1 << 21, 304b7e1c893Smrg DMA_BUSY_bit = 1 << 22, 305b7e1c893Smrg RCIU_BUSY_bit = 1 << 23, 306b7e1c893Smrg CP_STAT__CP_BUSY_bit = 1 << 31, 307b7e1c893Smrg 308b7e1c893Smrg CP_ME_CNTL = 0x86d8, 309b7e1c893Smrg ME_STATMUX_mask = 0xff << 0, 310b7e1c893Smrg ME_STATMUX_shift = 0, 311b7e1c893Smrg ME_HALT_bit = 1 << 28, 312b7e1c893Smrg CP_ME_STATUS = 0x86dc, 313b7e1c893Smrg 314b7e1c893Smrg CP_RB_RPTR = 0x8700, 315b7e1c893Smrg RB_RPTR_mask = 0xfffff << 0, 316b7e1c893Smrg RB_RPTR_shift = 0, 317b7e1c893Smrg CP_RB_WPTR_DELAY = 0x8704, 318b7e1c893Smrg PRE_WRITE_TIMER_mask = 0xfffffff << 0, 319b7e1c893Smrg PRE_WRITE_TIMER_shift = 0, 320b7e1c893Smrg PRE_WRITE_LIMIT_mask = 0x0f << 28, 321b7e1c893Smrg PRE_WRITE_LIMIT_shift = 28, 322b7e1c893Smrg 323b7e1c893Smrg CP_ROQ_RB_STAT = 0x8780, 324b7e1c893Smrg ROQ_RPTR_PRIMARY_mask = 0x3ff << 0, 325b7e1c893Smrg ROQ_RPTR_PRIMARY_shift = 0, 326b7e1c893Smrg ROQ_WPTR_PRIMARY_mask = 0x3ff << 16, 327b7e1c893Smrg ROQ_WPTR_PRIMARY_shift = 16, 328b7e1c893Smrg CP_ROQ_IB1_STAT = 0x8784, 329b7e1c893Smrg ROQ_RPTR_INDIRECT1_mask = 0x3ff << 0, 330b7e1c893Smrg ROQ_RPTR_INDIRECT1_shift = 0, 331b7e1c893Smrg ROQ_WPTR_INDIRECT1_mask = 0x3ff << 16, 332b7e1c893Smrg ROQ_WPTR_INDIRECT1_shift = 16, 333b7e1c893Smrg CP_ROQ_IB2_STAT = 0x8788, 334b7e1c893Smrg ROQ_RPTR_INDIRECT2_mask = 0x3ff << 0, 335b7e1c893Smrg ROQ_RPTR_INDIRECT2_shift = 0, 336b7e1c893Smrg ROQ_WPTR_INDIRECT2_mask = 0x3ff << 16, 337b7e1c893Smrg ROQ_WPTR_INDIRECT2_shift = 16, 338b7e1c893Smrg 339b7e1c893Smrg CP_MEQ_STAT = 0x8794, 340b7e1c893Smrg MEQ_RPTR_mask = 0x3ff << 0, 341b7e1c893Smrg MEQ_RPTR_shift = 0, 342b7e1c893Smrg MEQ_WPTR_mask = 0x3ff << 16, 343b7e1c893Smrg MEQ_WPTR_shift = 16, 344b7e1c893Smrg 345b7e1c893Smrg CC_GC_SHADER_PIPE_CONFIG = 0x8950, 346b7e1c893Smrg INACTIVE_QD_PIPES_mask = 0xff << 8, 347b7e1c893Smrg INACTIVE_QD_PIPES_shift = 8, 348b7e1c893Smrg R6XX_MAX_QD_PIPES = 8, 349b7e1c893Smrg INACTIVE_SIMDS_mask = 0xff << 16, 350b7e1c893Smrg INACTIVE_SIMDS_shift = 16, 351b7e1c893Smrg R6XX_MAX_SIMDS = 8, 352b7e1c893Smrg GC_USER_SHADER_PIPE_CONFIG = 0x8954, 353b7e1c893Smrg 354b7e1c893Smrg VC_ENHANCE = 0x9714, 355b7e1c893Smrg DB_DEBUG = 0x9830, 356b7e1c893Smrg PREZ_MUST_WAIT_FOR_POSTZ_DONE = 1 << 31, 357b7e1c893Smrg 358b7e1c893Smrg DB_WATERMARKS = 0x00009838, 359b7e1c893Smrg DEPTH_FREE_mask = 0x1f << 0, 360b7e1c893Smrg DEPTH_FREE_shift = 0, 361b7e1c893Smrg DEPTH_FLUSH_mask = 0x3f << 5, 362b7e1c893Smrg DEPTH_FLUSH_shift = 5, 363b7e1c893Smrg FORCE_SUMMARIZE_mask = 0x0f << 11, 364b7e1c893Smrg FORCE_SUMMARIZE_shift = 11, 365b7e1c893Smrg DEPTH_PENDING_FREE_mask = 0x1f << 15, 366b7e1c893Smrg DEPTH_PENDING_FREE_shift = 15, 367b7e1c893Smrg DEPTH_CACHELINE_FREE_mask = 0x1f << 20, 368b7e1c893Smrg DEPTH_CACHELINE_FREE_shift = 20, 369b7e1c893Smrg EARLY_Z_PANIC_DISABLE_bit = 1 << 25, 370b7e1c893Smrg LATE_Z_PANIC_DISABLE_bit = 1 << 26, 371b7e1c893Smrg RE_Z_PANIC_DISABLE_bit = 1 << 27, 372b7e1c893Smrg DB_EXTRA_DEBUG_mask = 0x0f << 28, 373b7e1c893Smrg DB_EXTRA_DEBUG_shift = 28, 374b7e1c893Smrg 375b7e1c893Smrg CP_RB_BASE = 0xc100, 376b7e1c893Smrg CP_RB_CNTL = 0xc104, 377b7e1c893Smrg RB_BUFSZ_mask = 0x3f << 0, 378b7e1c893Smrg CP_RB_WPTR = 0xc114, 379b7e1c893Smrg RB_WPTR_mask = 0xfffff << 0, 380b7e1c893Smrg RB_WPTR_shift = 0, 381b7e1c893Smrg CP_RB_RPTR_WR = 0xc108, 382b7e1c893Smrg RB_RPTR_WR_mask = 0xfffff << 0, 383b7e1c893Smrg RB_RPTR_WR_shift = 0, 384b7e1c893Smrg 385b7e1c893Smrg CP_INT_STATUS = 0xc128, 386b7e1c893Smrg DISABLE_CNTX_SWITCH_INT_STAT_bit = 1 << 0, 387b7e1c893Smrg ENABLE_CNTX_SWITCH_INT_STAT_bit = 1 << 1, 388b7e1c893Smrg SEM_SIGNAL_INT_STAT_bit = 1 << 18, 389b7e1c893Smrg CNTX_BUSY_INT_STAT_bit = 1 << 19, 390b7e1c893Smrg CNTX_EMPTY_INT_STAT_bit = 1 << 20, 391b7e1c893Smrg WAITMEM_SEM_INT_STAT_bit = 1 << 21, 392b7e1c893Smrg PRIV_INSTR_INT_STAT_bit = 1 << 22, 393b7e1c893Smrg PRIV_REG_INT_STAT_bit = 1 << 23, 394b7e1c893Smrg OPCODE_ERROR_INT_STAT_bit = 1 << 24, 395b7e1c893Smrg SCRATCH_INT_STAT_bit = 1 << 25, 396b7e1c893Smrg TIME_STAMP_INT_STAT_bit = 1 << 26, 397b7e1c893Smrg RESERVED_BIT_ERROR_INT_STAT_bit = 1 << 27, 398b7e1c893Smrg DMA_INT_STAT_bit = 1 << 28, 399b7e1c893Smrg IB2_INT_STAT_bit = 1 << 29, 400b7e1c893Smrg IB1_INT_STAT_bit = 1 << 30, 401b7e1c893Smrg RB_INT_STAT_bit = 1 << 31, 402b7e1c893Smrg 403b7e1c893Smrg// SX_ALPHA_TEST_CONTROL = 0x00028410, 404b7e1c893Smrg ALPHA_FUNC__REF_NEVER = 0, 405b7e1c893Smrg ALPHA_FUNC__REF_ALWAYS = 7, 406b7e1c893Smrg// DB_SHADER_CONTROL = 0x0002880c, 407b7e1c893Smrg Z_ORDER__EARLY_Z_THEN_LATE_Z = 2, 408b7e1c893Smrg// PA_SU_SC_MODE_CNTL = 0x00028814, 409b7e1c893Smrg// POLY_MODE_mask = 0x03 << 3, 410b7e1c893Smrg POLY_MODE__TRIANGLES = 0, POLY_MODE__DUAL_MODE, 411b7e1c893Smrg// POLYMODE_FRONT_PTYPE_mask = 0x07 << 5, 412b7e1c893Smrg POLYMODE_PTYPE__POINTS = 0, POLYMODE_PTYPE__LINES, POLYMODE_PTYPE__TRIANGLES, 413b7e1c893Smrg PA_SC_AA_SAMPLE_LOCS_8S_WD1_M = 0x00028c20, 414b7e1c893Smrg DB_SRESULTS_COMPARE_STATE0 = 0x00028d28, /* See autoregs: DB_SRESULTS_COMPARE_STATE1 */ 415b7e1c893Smrg// DB_SRESULTS_COMPARE_STATE1 = 0x00028d2c, 416b7e1c893Smrg DB_ALPHA_TO_MASK = 0x00028d44, 417b7e1c893Smrg ALPHA_TO_MASK_ENABLE = 1 << 0, 418b7e1c893Smrg ALPHA_TO_MASK_OFFSET0_mask = 0x03 << 8, 419b7e1c893Smrg ALPHA_TO_MASK_OFFSET0_shift = 8, 420ad43ddacSmrg ALPHA_TO_MASK_OFFSET1_mask = 0x03 << 10, 421b7e1c893Smrg ALPHA_TO_MASK_OFFSET1_shift = 10, 422ad43ddacSmrg ALPHA_TO_MASK_OFFSET2_mask = 0x03 << 12, 423b7e1c893Smrg ALPHA_TO_MASK_OFFSET2_shift = 12, 424ad43ddacSmrg ALPHA_TO_MASK_OFFSET3_mask = 0x03 << 14, 425b7e1c893Smrg ALPHA_TO_MASK_OFFSET3_shift = 14, 426b7e1c893Smrg 427b7e1c893Smrg// SQ_VTX_CONSTANT_WORD2_0 = 0x00038008, 428b7e1c893Smrg// SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask = 0x3f << 20, 429b7e1c893Smrg FMT_INVALID=0, FMT_8, FMT_4_4, FMT_3_3_2, 430b7e1c893Smrg FMT_16=5, FMT_16_FLOAT, FMT_8_8, 431b7e1c893Smrg FMT_5_6_5, FMT_6_5_5, FMT_1_5_5_5, FMT_4_4_4_4, 432b7e1c893Smrg FMT_5_5_5_1, FMT_32, FMT_32_FLOAT, FMT_16_16, 433b7e1c893Smrg FMT_16_16_FLOAT=16, FMT_8_24, FMT_8_24_FLOAT, FMT_24_8, 434b7e1c893Smrg FMT_24_8_FLOAT, FMT_10_11_11, FMT_10_11_11_FLOAT, FMT_11_11_10, 435b7e1c893Smrg FMT_11_11_10_FLOAT, FMT_2_10_10_10, FMT_8_8_8_8, FMT_10_10_10_2, 436b7e1c893Smrg FMT_X24_8_32_FLOAT, FMT_32_32, FMT_32_32_FLOAT, FMT_16_16_16_16, 437b7e1c893Smrg FMT_16_16_16_16_FLOAT=32, FMT_32_32_32_32=34, FMT_32_32_32_32_FLOAT, 438b7e1c893Smrg FMT_1 = 37, FMT_GB_GR=39, 439b7e1c893Smrg FMT_BG_RG, FMT_32_AS_8, FMT_32_AS_8_8, FMT_5_9_9_9_SHAREDEXP, 440b7e1c893Smrg FMT_8_8_8, FMT_16_16_16, FMT_16_16_16_FLOAT, FMT_32_32_32, 441b7e1c893Smrg FMT_32_32_32_FLOAT=48, 442b7e1c893Smrg 443b7e1c893Smrg// High level register file lengths 444b7e1c893Smrg SQ_ALU_CONSTANT = SQ_ALU_CONSTANT0_0, /* 256 PS, 256 VS */ 445b7e1c893Smrg SQ_ALU_CONSTANT_ps_num = 256, 446b7e1c893Smrg SQ_ALU_CONSTANT_vs_num = 256, 447b7e1c893Smrg SQ_ALU_CONSTANT_all_num = 512, 448b7e1c893Smrg SQ_ALU_CONSTANT_offset = 16, 449b7e1c893Smrg SQ_ALU_CONSTANT_ps = 0, 450b7e1c893Smrg SQ_ALU_CONSTANT_vs = SQ_ALU_CONSTANT_ps + SQ_ALU_CONSTANT_ps_num, 451b7e1c893Smrg SQ_TEX_RESOURCE = SQ_TEX_RESOURCE_WORD0_0, /* 160 PS, 160 VS, 16 FS, 160 GS */ 452b7e1c893Smrg SQ_TEX_RESOURCE_ps_num = 160, 453b7e1c893Smrg SQ_TEX_RESOURCE_vs_num = 160, 454b7e1c893Smrg SQ_TEX_RESOURCE_fs_num = 16, 455b7e1c893Smrg SQ_TEX_RESOURCE_gs_num = 160, 456b7e1c893Smrg SQ_TEX_RESOURCE_all_num = 496, 457b7e1c893Smrg SQ_TEX_RESOURCE_offset = 28, 458b7e1c893Smrg SQ_TEX_RESOURCE_ps = 0, 459b7e1c893Smrg SQ_TEX_RESOURCE_vs = SQ_TEX_RESOURCE_ps + SQ_TEX_RESOURCE_ps_num, 460b7e1c893Smrg SQ_TEX_RESOURCE_fs = SQ_TEX_RESOURCE_vs + SQ_TEX_RESOURCE_vs_num, 461b7e1c893Smrg SQ_TEX_RESOURCE_gs = SQ_TEX_RESOURCE_fs + SQ_TEX_RESOURCE_fs_num, 462b7e1c893Smrg SQ_VTX_RESOURCE = SQ_VTX_CONSTANT_WORD0_0, /* 160 PS, 160 VS, 16 FS, 160 GS */ 463b7e1c893Smrg SQ_VTX_RESOURCE_ps_num = 160, 464b7e1c893Smrg SQ_VTX_RESOURCE_vs_num = 160, 465b7e1c893Smrg SQ_VTX_RESOURCE_fs_num = 16, 466b7e1c893Smrg SQ_VTX_RESOURCE_gs_num = 160, 467b7e1c893Smrg SQ_VTX_RESOURCE_all_num = 496, 468b7e1c893Smrg SQ_VTX_RESOURCE_offset = 28, 469b7e1c893Smrg SQ_VTX_RESOURCE_ps = 0, 470b7e1c893Smrg SQ_VTX_RESOURCE_vs = SQ_VTX_RESOURCE_ps + SQ_VTX_RESOURCE_ps_num, 471b7e1c893Smrg SQ_VTX_RESOURCE_fs = SQ_VTX_RESOURCE_vs + SQ_VTX_RESOURCE_vs_num, 472b7e1c893Smrg SQ_VTX_RESOURCE_gs = SQ_VTX_RESOURCE_fs + SQ_VTX_RESOURCE_fs_num, 473b7e1c893Smrg SQ_TEX_SAMPLER_WORD = SQ_TEX_SAMPLER_WORD0_0, /* 18 per PS, VS, GS */ 474b7e1c893Smrg SQ_TEX_SAMPLER_WORD_ps_num = 18, 475b7e1c893Smrg SQ_TEX_SAMPLER_WORD_vs_num = 18, 476b7e1c893Smrg SQ_TEX_SAMPLER_WORD_gs_num = 18, 477b7e1c893Smrg SQ_TEX_SAMPLER_WORD_all_num = 54, 478b7e1c893Smrg SQ_TEX_SAMPLER_WORD_offset = 12, 479b7e1c893Smrg SQ_TEX_SAMPLER_WORD_ps = 0, 480b7e1c893Smrg SQ_TEX_SAMPLER_WORD_vs = SQ_TEX_SAMPLER_WORD_ps + SQ_TEX_SAMPLER_WORD_ps_num, 481b7e1c893Smrg SQ_TEX_SAMPLER_WORD_gs = SQ_TEX_SAMPLER_WORD_vs + SQ_TEX_SAMPLER_WORD_vs_num, 482b7e1c893Smrg SQ_LOOP_CONST = SQ_LOOP_CONST_0, /* 32 per PS, VS, GS */ 483b7e1c893Smrg SQ_LOOP_CONST_ps_num = 32, 484b7e1c893Smrg SQ_LOOP_CONST_vs_num = 32, 485b7e1c893Smrg SQ_LOOP_CONST_gs_num = 32, 486b7e1c893Smrg SQ_LOOP_CONST_all_num = 96, 487b7e1c893Smrg SQ_LOOP_CONST_offset = 4, 488b7e1c893Smrg SQ_LOOP_CONST_ps = 0, 489b7e1c893Smrg SQ_LOOP_CONST_vs = SQ_LOOP_CONST_ps + SQ_LOOP_CONST_ps_num, 490b7e1c893Smrg SQ_LOOP_CONST_gs = SQ_LOOP_CONST_vs + SQ_LOOP_CONST_vs_num, 491b7e1c893Smrg SQ_BOOL_CONST = SQ_BOOL_CONST_0, /* 32 bits per PS, VS, GS */ 492b7e1c893Smrg SQ_BOOL_CONST_ps_num = 1, 493b7e1c893Smrg SQ_BOOL_CONST_vs_num = 1, 494b7e1c893Smrg SQ_BOOL_CONST_gs_num = 1, 495b7e1c893Smrg SQ_BOOL_CONST_all_num = 3, 496b7e1c893Smrg SQ_BOOL_CONST_offset = 4, 497b7e1c893Smrg SQ_BOOL_CONST_ps = 0, 498b7e1c893Smrg SQ_BOOL_CONST_vs = SQ_BOOL_CONST_ps + SQ_BOOL_CONST_ps_num, 499b7e1c893Smrg SQ_BOOL_CONST_gs = SQ_BOOL_CONST_vs + SQ_BOOL_CONST_vs_num, 500b7e1c893Smrg}; 501b7e1c893Smrg 502b7e1c893Smrg 503b7e1c893Smrg#endif 504