1#ifndef __R600_STATE_H__
2#define __R600_STATE_H__
3
4
5#include "xf86drm.h"
6
7typedef int bool_t;
8
9#define CLEAR(x) memset (&x, 0, sizeof(x))
10
11/* Sequencer / thread handling */
12typedef struct {
13    int ps_prio;
14    int vs_prio;
15    int gs_prio;
16    int es_prio;
17    int num_ps_gprs;
18    int num_vs_gprs;
19    int num_gs_gprs;
20    int num_es_gprs;
21    int num_temp_gprs;
22    int num_ps_threads;
23    int num_vs_threads;
24    int num_gs_threads;
25    int num_es_threads;
26    int num_ps_stack_entries;
27    int num_vs_stack_entries;
28    int num_gs_stack_entries;
29    int num_es_stack_entries;
30} sq_config_t;
31
32/* Color buffer / render target */
33typedef struct {
34    int id;
35    int w;
36    int h;
37    uint64_t base;
38    int format;
39    int endian;
40    int array_mode;						// tiling
41    int number_type;
42    int read_size;
43    int comp_swap;
44    int tile_mode;
45    int blend_clamp;
46    int clear_color;
47    int blend_bypass;
48    int blend_float32;
49    int simple_float;
50    int round_mode;
51    int tile_compact;
52    int source_format;
53    /* 2D related CB state */
54    uint32_t pmask;
55    int rop;
56    int blend_enable;
57    uint32_t blendcntl;
58    struct radeon_bo *bo;
59#ifdef XF86DRM_MODE
60    struct radeon_surface *surface;
61#endif
62} cb_config_t;
63
64/* Depth buffer */
65typedef struct {
66    int w;
67    int h;
68    uint64_t base;
69    int format;
70    int read_size;
71    int array_mode;						// tiling
72    int tile_surface_en;
73    int tile_compact;
74    int zrange_precision;
75    struct radeon_bo *bo;
76} db_config_t;
77
78/* Shader */
79typedef struct {
80    uint64_t shader_addr;
81    uint32_t shader_size;
82    int num_gprs;
83    int stack_size;
84    int dx10_clamp;
85    int prime_cache_pgm_en;
86    int prime_cache_on_draw;
87    int fetch_cache_lines;
88    int prime_cache_en;
89    int prime_cache_on_const;
90    int clamp_consts;
91    int export_mode;
92    int uncached_first_inst;
93    struct radeon_bo *bo;
94} shader_config_t;
95
96/* Vertex buffer / vtx resource */
97typedef struct {
98    int id;
99    uint64_t vb_addr;
100    uint32_t vtx_num_entries;
101    uint32_t vtx_size_dw;
102    int clamp_x;
103    int format;
104    int num_format_all;
105    int format_comp_all;
106    int srf_mode_all;
107    int endian;
108    int mem_req_size;
109    struct radeon_bo *bo;
110} vtx_resource_t;
111
112/* Texture resource */
113typedef struct {
114    int id;
115    int w;
116    int h;
117    int pitch;
118    int depth;
119    int dim;
120    int tile_mode;
121    int tile_type;
122    int format;
123    uint64_t base;
124    uint64_t mip_base;
125    uint32_t size;
126    int format_comp_x;
127    int format_comp_y;
128    int format_comp_z;
129    int format_comp_w;
130    int num_format_all;
131    int srf_mode_all;
132    int force_degamma;
133    int endian;
134    int request_size;
135    int dst_sel_x;
136    int dst_sel_y;
137    int dst_sel_z;
138    int dst_sel_w;
139    int base_level;
140    int last_level;
141    int base_array;
142    int last_array;
143    int mpeg_clamp;
144    int perf_modulation;
145    int interlaced;
146    struct radeon_bo *bo;
147    struct radeon_bo *mip_bo;
148#ifdef XF86DRM_MODE
149    struct radeon_surface *surface;
150#endif
151} tex_resource_t;
152
153/* Texture sampler */
154typedef struct {
155    int				id;
156    /* Clamping */
157    int				clamp_x, clamp_y, clamp_z;
158    int		       		border_color;
159    /* Filtering */
160    int				xy_mag_filter, xy_min_filter;
161    int				z_filter;
162    int				mip_filter;
163    bool_t			high_precision_filter;	/* ? */
164    int				perf_mip;		/* ? 0-7 */
165    int				perf_z;			/* ? 3 */
166    /* LoD selection */
167    int				min_lod, max_lod;	/* 0-0x3ff */
168    int                         lod_bias;		/* 0-0xfff (signed?) */
169    int                         lod_bias2;		/* ? 0-0xfff (signed?) */
170    bool_t			lod_uses_minor_axis;	/* ? */
171    /* Other stuff */
172    bool_t			point_sampling_clamp;	/* ? */
173    bool_t			tex_array_override;	/* ? */
174    bool_t                      mc_coord_truncate;	/* ? */
175    bool_t			force_degamma;		/* ? */
176    bool_t			fetch_4;		/* ? */
177    bool_t			sample_is_pcf;		/* ? */
178    bool_t			type;			/* ? */
179    int				depth_compare;		/* only depth textures? */
180    int				chroma_key;
181} tex_sampler_t;
182
183/* Draw command */
184typedef struct {
185    uint32_t prim_type;
186    uint32_t vgt_draw_initiator;
187    uint32_t index_type;
188    uint32_t num_instances;
189    uint32_t num_indices;
190} draw_config_t;
191
192#if defined(XF86DRM_MODE)
193#define BEGIN_BATCH(n)				\
194do {					\
195    if (info->cs)			\
196	radeon_ddx_cs_start(pScrn, (n), __FILE__, __func__, __LINE__);	\
197} while(0)
198#define END_BATCH()				\
199do {					\
200    if (info->cs)			\
201	radeon_cs_end(info->cs, __FILE__, __func__, __LINE__);	\
202} while(0)
203#define RELOC_BATCH(bo, rd, wd)					\
204do {							\
205    if (info->cs) {							\
206	int _ret;							\
207	_ret = radeon_cs_write_reloc(info->cs, (bo), (rd), (wd), 0);	\
208	if (_ret) ErrorF("reloc emit failure %d (%s %d)\n", _ret, __func__, __LINE__); \
209    }									\
210} while(0)
211#define E32(ib, dword)                                                  \
212do {                                                                    \
213    if (info->cs)							\
214	radeon_cs_write_dword(info->cs, (dword));			\
215    else {								\
216	uint32_t *ib_head = (pointer)(char*)(ib)->address;		\
217	ib_head[(ib)->used >> 2] = (dword);				\
218	(ib)->used += 4;						\
219    }									\
220} while (0)
221#else
222#define BEGIN_BATCH(n) do {(void)info;} while(0)
223#define END_BATCH() do {} while(0)
224#define RELOC_BATCH(bo, wd, rd) do {} while(0)
225#define E32(ib, dword)                                                  \
226do {                                                                    \
227    uint32_t *ib_head = (pointer)(char*)(ib)->address;			\
228    ib_head[(ib)->used >> 2] = (dword);					\
229    (ib)->used += 4;							\
230} while (0)
231#endif
232
233#define EFLOAT(ib, val)							\
234do {								        \
235    union { float f; uint32_t d; } a;                                   \
236    a.f = (val);								\
237    E32((ib), a.d);							\
238} while (0)
239
240#define PACK3(ib, cmd, num)	       					\
241do {                                                                    \
242    E32((ib), RADEON_CP_PACKET3 | ((cmd) << 8) | ((((num) - 1) & 0x3fff) << 16)); \
243} while (0)
244
245/* write num registers, start at reg */
246/* If register falls in a special area, special commands are issued */
247#define PACK0(ib, reg, num)                                             \
248do {                                                                    \
249    if ((reg) >= SET_CONFIG_REG_offset && (reg) < SET_CONFIG_REG_end) {	\
250	PACK3((ib), IT_SET_CONFIG_REG, (num) + 1);			\
251	E32((ib), ((reg) - SET_CONFIG_REG_offset) >> 2);		\
252    } else if ((reg) >= SET_CONTEXT_REG_offset && (reg) < SET_CONTEXT_REG_end) { \
253	PACK3((ib), IT_SET_CONTEXT_REG, (num) + 1);			\
254	E32((ib), ((reg) - SET_CONTEXT_REG_offset) >> 2);		\
255    } else if ((reg) >= SET_ALU_CONST_offset && (reg) < SET_ALU_CONST_end) { \
256	PACK3((ib), IT_SET_ALU_CONST, (num) + 1);			\
257	E32((ib), ((reg) - SET_ALU_CONST_offset) >> 2);			\
258    } else if ((reg) >= SET_RESOURCE_offset && (reg) < SET_RESOURCE_end) { \
259	PACK3((ib), IT_SET_RESOURCE, num + 1);				\
260	E32((ib), ((reg) - SET_RESOURCE_offset) >> 2);			\
261    } else if ((reg) >= SET_SAMPLER_offset && (reg) < SET_SAMPLER_end) { \
262	PACK3((ib), IT_SET_SAMPLER, (num) + 1);				\
263	E32((ib), (reg - SET_SAMPLER_offset) >> 2);			\
264    } else if ((reg) >= SET_CTL_CONST_offset && (reg) < SET_CTL_CONST_end) { \
265	PACK3((ib), IT_SET_CTL_CONST, (num) + 1);			\
266	E32((ib), ((reg) - SET_CTL_CONST_offset) >> 2);		\
267    } else if ((reg) >= SET_LOOP_CONST_offset && (reg) < SET_LOOP_CONST_end) { \
268	PACK3((ib), IT_SET_LOOP_CONST, (num) + 1);			\
269	E32((ib), ((reg) - SET_LOOP_CONST_offset) >> 2);		\
270    } else if ((reg) >= SET_BOOL_CONST_offset && (reg) < SET_BOOL_CONST_end) { \
271	PACK3((ib), IT_SET_BOOL_CONST, (num) + 1);			\
272	E32((ib), ((reg) - SET_BOOL_CONST_offset) >> 2);		\
273    } else {								\
274	E32((ib), CP_PACKET0 ((reg), (num) - 1));			\
275    }									\
276} while (0)
277
278/* write a single register */
279#define EREG(ib, reg, val)                                              \
280do {								        \
281    PACK0((ib), (reg), 1);						\
282    E32((ib), (val));							\
283} while (0)
284
285void R600CPFlushIndirect(ScrnInfoPtr pScrn, drmBufPtr ib);
286void R600IBDiscard(ScrnInfoPtr pScrn, drmBufPtr ib);
287
288void
289r600_wait_3d_idle_clean(ScrnInfoPtr pScrn, drmBufPtr ib);
290void
291r600_wait_3d_idle(ScrnInfoPtr pScrn, drmBufPtr ib);
292void
293r600_start_3d(ScrnInfoPtr pScrn, drmBufPtr ib);
294void
295r600_set_render_target(ScrnInfoPtr pScrn, drmBufPtr ib, cb_config_t *cb_conf, uint32_t domain);
296void
297r600_cp_wait_vline_sync(ScrnInfoPtr pScrn, drmBufPtr ib, PixmapPtr pPix, xf86CrtcPtr crtc, int start, int stop);
298void
299r600_set_spi(ScrnInfoPtr pScrn, drmBufPtr ib, int vs_export_count, int num_interp);
300void
301r600_fs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *fs_conf, uint32_t domain);
302void
303r600_vs_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *vs_conf, uint32_t domain);
304void
305r600_ps_setup(ScrnInfoPtr pScrn, drmBufPtr ib, shader_config_t *ps_conf, uint32_t domain);
306void
307r600_set_alu_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, int count, float *const_buf);
308void
309r600_set_bool_consts(ScrnInfoPtr pScrn, drmBufPtr ib, int offset, uint32_t val);
310void
311r600_set_tex_resource(ScrnInfoPtr pScrn, drmBufPtr ib, tex_resource_t *tex_res, uint32_t domain);
312void
313r600_set_tex_sampler (ScrnInfoPtr pScrn, drmBufPtr ib, tex_sampler_t *s);
314void
315r600_set_screen_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2);
316void
317r600_set_vport_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2);
318void
319r600_set_generic_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2);
320void
321r600_set_window_scissor(ScrnInfoPtr pScrn, drmBufPtr ib, int x1, int y1, int x2, int y2);
322void
323r600_set_clip_rect(ScrnInfoPtr pScrn, drmBufPtr ib, int id, int x1, int y1, int x2, int y2);
324void
325r600_set_default_state(ScrnInfoPtr pScrn, drmBufPtr ib);
326void
327r600_draw_immd(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf, uint32_t *indices);
328void
329r600_draw_auto(ScrnInfoPtr pScrn, drmBufPtr ib, draw_config_t *draw_conf);
330
331void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size);
332
333Bool
334R600SetAccelState(ScrnInfoPtr pScrn,
335		  struct r600_accel_object *src0,
336		  struct r600_accel_object *src1,
337		  struct r600_accel_object *dst,
338		  uint32_t vs_offset, uint32_t ps_offset,
339		  int rop, Pixel planemask);
340
341extern Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index);
342extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index);
343extern void *RADEONEXACreatePixmap(ScreenPtr pScreen, int size, int align);
344extern void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
345				    int depth, int usage_hint, int bitsPerPixel,
346				    int *new_pitch);
347extern void RADEONEXADestroyPixmap(ScreenPtr pScreen, void *driverPriv);
348extern struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix);
349extern Bool RADEONEXAPixmapIsOffscreen(PixmapPtr pPix);
350
351
352#endif
353