radeon.h revision 40732134
1/* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining 8 * a copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation on the rights to use, copy, modify, merge, 11 * publish, distribute, sublicense, and/or sell copies of the Software, 12 * and to permit persons to whom the Software is furnished to do so, 13 * subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 */ 28 29/* 30 * Authors: 31 * Kevin E. Martin <martin@xfree86.org> 32 * Rickard E. Faith <faith@valinux.com> 33 * Alan Hourihane <alanh@fairlite.demon.co.uk> 34 * 35 */ 36 37#ifndef _RADEON_H_ 38#define _RADEON_H_ 39 40#include <stdlib.h> /* For abs() */ 41#include <unistd.h> /* For usleep() */ 42#include <sys/time.h> /* For gettimeofday() */ 43 44#include "config.h" 45#include "xf86str.h" 46#include "compiler.h" 47#include "xf86fbman.h" 48 49 /* PCI support */ 50#include "xf86Pci.h" 51 52#ifdef USE_EXA 53#include "exa.h" 54#endif 55#ifdef USE_XAA 56#include "xaa.h" 57#endif 58 59 /* Exa and Cursor Support */ 60#include "vbe.h" 61#include "xf86Cursor.h" 62 63 /* DDC support */ 64#include "xf86DDC.h" 65 66 /* Xv support */ 67#include "xf86xv.h" 68 69#include "radeon_probe.h" 70#include "radeon_tv.h" 71 72 /* DRI support */ 73#ifdef XF86DRI 74#define _XF86DRI_SERVER_ 75#include "dri.h" 76#include "GL/glxint.h" 77#include "xf86drm.h" 78#include "radeon_drm.h" 79 80#ifdef DAMAGE 81#include "damage.h" 82#include "globals.h" 83#endif 84#endif 85 86#include "xf86Crtc.h" 87#include "X11/Xatom.h" 88 89#ifdef XF86DRM_MODE 90#include "radeon_bo.h" 91#include "radeon_cs.h" 92#include "radeon_dri2.h" 93#include "drmmode_display.h" 94#include "radeon_surface.h" 95#else 96#include "radeon_dummy_bufmgr.h" 97#endif 98 99 /* Render support */ 100#ifdef RENDER 101#include "picturestr.h" 102#endif 103 104#include "simple_list.h" 105#include "atipcirename.h" 106 107#ifndef MAX 108#define MAX(a,b) ((a)>(b)?(a):(b)) 109#endif 110#ifndef MIN 111#define MIN(a,b) ((a)>(b)?(b):(a)) 112#endif 113 114#if HAVE_BYTESWAP_H 115#include <byteswap.h> 116#elif defined(USE_SYS_ENDIAN_H) 117#include <sys/endian.h> 118#else 119#define bswap_16(value) \ 120 ((((value) & 0xff) << 8) | ((value) >> 8)) 121 122#define bswap_32(value) \ 123 (((uint32_t)bswap_16((uint16_t)((value) & 0xffff)) << 16) | \ 124 (uint32_t)bswap_16((uint16_t)((value) >> 16))) 125 126#define bswap_64(value) \ 127 (((uint64_t)bswap_32((uint32_t)((value) & 0xffffffff)) \ 128 << 32) | \ 129 (uint64_t)bswap_32((uint32_t)((value) >> 32))) 130#endif 131 132#if X_BYTE_ORDER == X_BIG_ENDIAN 133#define le32_to_cpu(x) bswap_32(x) 134#define le16_to_cpu(x) bswap_16(x) 135#define cpu_to_le32(x) bswap_32(x) 136#define cpu_to_le16(x) bswap_16(x) 137#else 138#define le32_to_cpu(x) (x) 139#define le16_to_cpu(x) (x) 140#define cpu_to_le32(x) (x) 141#define cpu_to_le16(x) (x) 142#endif 143 144/* Provide substitutes for gcc's __FUNCTION__ on other compilers */ 145#if !defined(__GNUC__) && !defined(__FUNCTION__) 146# define __FUNCTION__ __func__ /* C99 */ 147#endif 148 149#ifndef HAVE_XF86MODEBANDWIDTH 150extern unsigned int xf86ModeBandwidth(DisplayModePtr mode, int depth); 151#define MODE_BANDWIDTH MODE_BAD 152#endif 153 154typedef enum { 155 OPTION_NOACCEL, 156 OPTION_SW_CURSOR, 157 OPTION_DAC_6BIT, 158 OPTION_DAC_8BIT, 159#ifdef XF86DRI 160 OPTION_BUS_TYPE, 161 OPTION_CP_PIO, 162 OPTION_USEC_TIMEOUT, 163 OPTION_AGP_MODE, 164 OPTION_AGP_FW, 165 OPTION_GART_SIZE, 166 OPTION_GART_SIZE_OLD, 167 OPTION_RING_SIZE, 168 OPTION_BUFFER_SIZE, 169 OPTION_DEPTH_MOVE, 170 OPTION_PAGE_FLIP, 171 OPTION_NO_BACKBUFFER, 172 OPTION_XV_DMA, 173 OPTION_FBTEX_PERCENT, 174 OPTION_DEPTH_BITS, 175 OPTION_PCIAPER_SIZE, 176#ifdef USE_EXA 177 OPTION_ACCEL_DFS, 178 OPTION_EXA_PIXMAPS, 179#endif 180#endif 181 OPTION_IGNORE_EDID, 182 OPTION_CUSTOM_EDID, 183 OPTION_DISP_PRIORITY, 184 OPTION_PANEL_SIZE, 185 OPTION_MIN_DOTCLOCK, 186 OPTION_COLOR_TILING, 187 OPTION_COLOR_TILING_2D, 188#ifdef XvExtension 189 OPTION_VIDEO_KEY, 190 OPTION_RAGE_THEATRE_CRYSTAL, 191 OPTION_RAGE_THEATRE_TUNER_PORT, 192 OPTION_RAGE_THEATRE_COMPOSITE_PORT, 193 OPTION_RAGE_THEATRE_SVIDEO_PORT, 194 OPTION_TUNER_TYPE, 195 OPTION_RAGE_THEATRE_MICROC_PATH, 196 OPTION_RAGE_THEATRE_MICROC_TYPE, 197 OPTION_SCALER_WIDTH, 198#endif 199#ifdef RENDER 200 OPTION_RENDER_ACCEL, 201 OPTION_SUBPIXEL_ORDER, 202#endif 203 OPTION_SHOWCACHE, 204 OPTION_CLOCK_GATING, 205 OPTION_BIOS_HOTKEYS, 206 OPTION_VGA_ACCESS, 207 OPTION_REVERSE_DDC, 208 OPTION_LVDS_PROBE_PLL, 209 OPTION_ACCELMETHOD, 210 OPTION_CONNECTORTABLE, 211 OPTION_DRI, 212 OPTION_DEFAULT_CONNECTOR_TABLE, 213#if defined(__powerpc__) 214 OPTION_MAC_MODEL, 215#endif 216 OPTION_DEFAULT_TMDS_PLL, 217 OPTION_TVDAC_LOAD_DETECT, 218 OPTION_FORCE_TVOUT, 219 OPTION_TVSTD, 220 OPTION_IGNORE_LID_STATUS, 221 OPTION_DEFAULT_TVDAC_ADJ, 222 OPTION_INT10, 223 OPTION_EXA_VSYNC, 224 OPTION_ATOM_TVOUT, 225 OPTION_R4XX_ATOM, 226 OPTION_FORCE_LOW_POWER, 227 OPTION_DYNAMIC_PM, 228 OPTION_NEW_PLL, 229 OPTION_ZAPHOD_HEADS, 230 OPTION_SWAPBUFFERS_WAIT 231} RADEONOpts; 232 233 234#define RADEON_IDLE_RETRY 16 /* Fall out of idle loops after this count */ 235#define RADEON_TIMEOUT 2000000 /* Fall out of wait loops after this count */ 236 237#define RADEON_VSYNC_TIMEOUT 20000 /* Maximum wait for VSYNC (in usecs) */ 238 239/* Buffer are aligned on 4096 byte boundaries */ 240#define RADEON_GPU_PAGE_SIZE 4096 241#define RADEON_BUFFER_ALIGN (RADEON_GPU_PAGE_SIZE - 1) 242#define RADEON_VBIOS_SIZE 0x00010000 243#define RADEON_USE_RMX 0x80000000 /* mode flag for using RMX 244 * Need to comfirm this is not used 245 * for something else. 246 */ 247 248#define xFixedToFloat(f) (((float) (f)) / 65536) 249 250#define RADEON_LOGLEVEL_DEBUG 4 251 252/* for Xv, outputs */ 253#define MAKE_ATOM(a) MakeAtom(a, sizeof(a) - 1, TRUE) 254 255/* Other macros */ 256#define RADEON_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) 257#define RADEON_ALIGN(x,bytes) (((x) + ((bytes) - 1)) & ~((bytes) - 1)) 258#define RADEONPTR(pScrn) ((RADEONInfoPtr)(pScrn)->driverPrivate) 259 260typedef struct { 261 int revision; 262 uint16_t rr1_offset; 263 uint16_t rr2_offset; 264 uint16_t dyn_clk_offset; 265 uint16_t pll_offset; 266 uint16_t mem_config_offset; 267 uint16_t mem_reset_offset; 268 uint16_t short_mem_offset; 269 uint16_t rr3_offset; 270 uint16_t rr4_offset; 271} RADEONBIOSInitTable; 272 273#define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 274#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 275#define RADEON_PLL_USE_REF_DIV (1 << 2) 276#define RADEON_PLL_LEGACY (1 << 3) 277#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 278#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 279#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 280#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 281#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 282#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 283#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 284#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 285#define RADEON_PLL_USE_POST_DIV (1 << 12) 286 287typedef struct { 288 uint32_t reference_freq; 289 uint32_t reference_div; 290 uint32_t post_div; 291 uint32_t pll_in_min; 292 uint32_t pll_in_max; 293 uint32_t pll_out_min; 294 uint32_t pll_out_max; 295 uint16_t xclk; 296 297 uint32_t min_ref_div; 298 uint32_t max_ref_div; 299 uint32_t min_post_div; 300 uint32_t max_post_div; 301 uint32_t min_feedback_div; 302 uint32_t max_feedback_div; 303 uint32_t min_frac_feedback_div; 304 uint32_t max_frac_feedback_div; 305 uint32_t best_vco; 306} RADEONPLLRec, *RADEONPLLPtr; 307 308typedef struct { 309 int bitsPerPixel; 310 int depth; 311 int displayWidth; 312 int displayHeight; 313 int pixel_code; 314 int pixel_bytes; 315 DisplayModePtr mode; 316} RADEONFBLayout; 317 318#define IS_RV100_VARIANT ((info->ChipFamily == CHIP_FAMILY_RV100) || \ 319 (info->ChipFamily == CHIP_FAMILY_RV200) || \ 320 (info->ChipFamily == CHIP_FAMILY_RS100) || \ 321 (info->ChipFamily == CHIP_FAMILY_RS200) || \ 322 (info->ChipFamily == CHIP_FAMILY_RV250) || \ 323 (info->ChipFamily == CHIP_FAMILY_RV280) || \ 324 (info->ChipFamily == CHIP_FAMILY_RS300)) 325 326 327#define IS_R300_VARIANT ((info->ChipFamily == CHIP_FAMILY_R300) || \ 328 (info->ChipFamily == CHIP_FAMILY_RV350) || \ 329 (info->ChipFamily == CHIP_FAMILY_R350) || \ 330 (info->ChipFamily == CHIP_FAMILY_RV380) || \ 331 (info->ChipFamily == CHIP_FAMILY_R420) || \ 332 (info->ChipFamily == CHIP_FAMILY_RV410) || \ 333 (info->ChipFamily == CHIP_FAMILY_RS400) || \ 334 (info->ChipFamily == CHIP_FAMILY_RS480)) 335 336#define IS_AVIVO_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV515)) 337 338#define IS_DCE3_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV620)) 339 340#define IS_DCE32_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV730)) 341 342#define IS_DCE4_VARIANT ((info->ChipFamily >= CHIP_FAMILY_CEDAR)) 343 344#define IS_DCE41_VARIANT ((info->ChipFamily >= CHIP_FAMILY_PALM)) 345 346#define IS_DCE5_VARIANT ((info->ChipFamily >= CHIP_FAMILY_BARTS)) 347 348#define IS_EVERGREEN_3D (info->ChipFamily >= CHIP_FAMILY_CEDAR) 349 350#define IS_R600_3D (info->ChipFamily >= CHIP_FAMILY_R600) 351 352#define IS_R500_3D ((info->ChipFamily == CHIP_FAMILY_RV515) || \ 353 (info->ChipFamily == CHIP_FAMILY_R520) || \ 354 (info->ChipFamily == CHIP_FAMILY_RV530) || \ 355 (info->ChipFamily == CHIP_FAMILY_R580) || \ 356 (info->ChipFamily == CHIP_FAMILY_RV560) || \ 357 (info->ChipFamily == CHIP_FAMILY_RV570)) 358 359#define IS_R400_3D ((info->ChipFamily == CHIP_FAMILY_R420) || \ 360 (info->ChipFamily == CHIP_FAMILY_RV410) || \ 361 (info->ChipFamily == CHIP_FAMILY_RS690) || \ 362 (info->ChipFamily == CHIP_FAMILY_RS600) || \ 363 (info->ChipFamily == CHIP_FAMILY_RS740)) 364 365#define IS_R300_3D ((info->ChipFamily == CHIP_FAMILY_R300) || \ 366 (info->ChipFamily == CHIP_FAMILY_RV350) || \ 367 (info->ChipFamily == CHIP_FAMILY_R350) || \ 368 (info->ChipFamily == CHIP_FAMILY_RV380) || \ 369 (info->ChipFamily == CHIP_FAMILY_R420) || \ 370 (info->ChipFamily == CHIP_FAMILY_RV410) || \ 371 (info->ChipFamily == CHIP_FAMILY_RS690) || \ 372 (info->ChipFamily == CHIP_FAMILY_RS600) || \ 373 (info->ChipFamily == CHIP_FAMILY_RS740) || \ 374 (info->ChipFamily == CHIP_FAMILY_RS400) || \ 375 (info->ChipFamily == CHIP_FAMILY_RS480)) 376 377#define IS_R200_3D ((info->ChipFamily == CHIP_FAMILY_RV250) || \ 378 (info->ChipFamily == CHIP_FAMILY_RV280) || \ 379 (info->ChipFamily == CHIP_FAMILY_RS300) || \ 380 (info->ChipFamily == CHIP_FAMILY_R200)) 381 382/* 383 * Errata workarounds 384 */ 385typedef enum { 386 CHIP_ERRATA_R300_CG = 0x00000001, 387 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 388 CHIP_ERRATA_PLL_DELAY = 0x00000004 389} RADEONErrata; 390 391typedef enum { 392 RADEON_DVOCHIP_NONE, 393 RADEON_SIL_164, 394 RADEON_SIL_1178 395} RADEONExtTMDSChip; 396 397#if defined(__powerpc__) 398typedef enum { 399 RADEON_MAC_NONE, 400 RADEON_MAC_IBOOK, 401 RADEON_MAC_POWERBOOK_EXTERNAL, 402 RADEON_MAC_POWERBOOK_INTERNAL, 403 RADEON_MAC_POWERBOOK_VGA, 404 RADEON_MAC_MINI_EXTERNAL, 405 RADEON_MAC_MINI_INTERNAL, 406 RADEON_MAC_IMAC_G5_ISIGHT, 407 RADEON_MAC_EMAC 408} RADEONMacModel; 409#endif 410 411typedef enum { 412 CARD_PCI, 413 CARD_AGP, 414 CARD_PCIE 415} RADEONCardType; 416 417typedef enum { 418 POWER_DEFAULT, 419 POWER_LOW, 420 POWER_HIGH 421} RADEONPMType; 422 423typedef struct { 424 RADEONPMType type; 425 uint32_t sclk; 426 uint32_t mclk; 427 uint32_t pcie_lanes; 428 uint32_t flags; 429} RADEONPowerMode; 430 431typedef struct { 432 /* power modes */ 433 int num_modes; 434 int current_mode; 435 RADEONPowerMode mode[3]; 436 437 Bool clock_gating_enabled; 438 Bool dynamic_mode_enabled; 439 Bool force_low_power_enabled; 440} RADEONPowerManagement; 441 442typedef struct _atomBiosHandle *atomBiosHandlePtr; 443 444struct radeon_exa_pixmap_priv { 445 struct radeon_bo *bo; 446 uint32_t tiling_flags; 447#ifdef XF86DRM_MODE 448 struct radeon_surface surface; 449#endif 450 Bool bo_mapped; 451}; 452 453#define RADEON_2D_EXA_COPY 1 454#define RADEON_2D_EXA_SOLID 2 455 456struct radeon_2d_state { 457 int op; // 458 uint32_t dst_pitch_offset; 459 uint32_t src_pitch_offset; 460 uint32_t dp_gui_master_cntl; 461 uint32_t dp_cntl; 462 uint32_t dp_write_mask; 463 uint32_t dp_brush_frgd_clr; 464 uint32_t dp_brush_bkgd_clr; 465 uint32_t dp_src_frgd_clr; 466 uint32_t dp_src_bkgd_clr; 467 uint32_t default_sc_bottom_right; 468 struct radeon_bo *dst_bo; 469 struct radeon_bo *src_bo; 470}; 471 472#ifdef XF86DRI 473struct radeon_cp { 474 Bool CPRuns; /* CP is running */ 475 Bool CPInUse; /* CP has been used by X server */ 476 Bool CPStarted; /* CP has started */ 477 int CPMode; /* CP mode that server/clients use */ 478 int CPFifoSize; /* Size of the CP command FIFO */ 479 int CPusecTimeout; /* CP timeout in usecs */ 480 Bool needCacheFlush; 481 482 /* CP accleration */ 483 drmBufPtr indirectBuffer; 484 int indirectStart; 485 486 /* Debugging info for BEGIN_RING/ADVANCE_RING pairs. */ 487 int dma_begin_count; 488 char *dma_debug_func; 489 int dma_debug_lineno; 490 491 }; 492 493typedef struct { 494 /* Nothing here yet */ 495 int dummy; 496} RADEONConfigPrivRec, *RADEONConfigPrivPtr; 497 498typedef struct { 499 /* Nothing here yet */ 500 int dummy; 501} RADEONDRIContextRec, *RADEONDRIContextPtr; 502 503struct radeon_dri { 504 Bool noBackBuffer; 505 506 Bool newMemoryMap; 507 drmVersionPtr pLibDRMVersion; 508 drmVersionPtr pKernelDRMVersion; 509 DRIInfoPtr pDRIInfo; 510 int drmFD; 511 int numVisualConfigs; 512 __GLXvisualConfig *pVisualConfigs; 513 RADEONConfigPrivPtr pVisualConfigsPriv; 514 Bool (*DRICloseScreen)(int, ScreenPtr); 515 516 drm_handle_t fbHandle; 517 518 drmSize registerSize; 519 drm_handle_t registerHandle; 520 521 drmSize pciSize; 522 drm_handle_t pciMemHandle; 523 unsigned char *PCI; /* Map */ 524 525 Bool depthMoves; /* Enable depth moves -- slow! */ 526 Bool allowPageFlip; /* Enable 3d page flipping */ 527#ifdef DAMAGE 528 DamagePtr pDamage; 529 RegionRec driRegion; 530#endif 531 Bool have3DWindows; /* Are there any 3d clients? */ 532 533 int pciAperSize; 534 drmSize gartSize; 535 drm_handle_t agpMemHandle; /* Handle from drmAgpAlloc */ 536 unsigned long gartOffset; 537 unsigned char *AGP; /* Map */ 538 int agpMode; 539 540 uint32_t pciCommand; 541 542 /* CP ring buffer data */ 543 unsigned long ringStart; /* Offset into GART space */ 544 drm_handle_t ringHandle; /* Handle from drmAddMap */ 545 drmSize ringMapSize; /* Size of map */ 546 int ringSize; /* Size of ring (in MB) */ 547 drmAddress ring; /* Map */ 548 int ringSizeLog2QW; 549 550 unsigned long ringReadOffset; /* Offset into GART space */ 551 drm_handle_t ringReadPtrHandle; /* Handle from drmAddMap */ 552 drmSize ringReadMapSize; /* Size of map */ 553 drmAddress ringReadPtr; /* Map */ 554 555 /* CP vertex/indirect buffer data */ 556 unsigned long bufStart; /* Offset into GART space */ 557 drm_handle_t bufHandle; /* Handle from drmAddMap */ 558 drmSize bufMapSize; /* Size of map */ 559 int bufSize; /* Size of buffers (in MB) */ 560 drmAddress buf; /* Map */ 561 int bufNumBufs; /* Number of buffers */ 562 drmBufMapPtr buffers; /* Buffer map */ 563 564 /* CP GART Texture data */ 565 unsigned long gartTexStart; /* Offset into GART space */ 566 drm_handle_t gartTexHandle; /* Handle from drmAddMap */ 567 drmSize gartTexMapSize; /* Size of map */ 568 int gartTexSize; /* Size of GART tex space (in MB) */ 569 drmAddress gartTex; /* Map */ 570 int log2GARTTexGran; 571 572 /* DRI screen private data */ 573 int fbX; 574 int fbY; 575 int backX; 576 int backY; 577 int depthX; 578 int depthY; 579 580 int frontOffset; 581 int frontPitch; 582 int backOffset; 583 int backPitch; 584 int depthOffset; 585 int depthPitch; 586 int depthBits; 587 int textureOffset; 588 int textureSize; 589 int log2TexGran; 590 591 int pciGartSize; 592 uint32_t pciGartOffset; 593 void *pciGartBackup; 594 595 int irq; 596 597#ifdef USE_XAA 598 uint32_t frontPitchOffset; 599 uint32_t backPitchOffset; 600 uint32_t depthPitchOffset; 601 602 /* offscreen memory management */ 603 int backLines; 604 FBAreaPtr backArea; 605 int depthTexLines; 606 FBAreaPtr depthTexArea; 607#endif 608 609}; 610#endif 611 612#define DMA_BO_FREE_TIME 1000 613 614struct radeon_dma_bo { 615 struct radeon_dma_bo *next, *prev; 616 struct radeon_bo *bo; 617 int expire_counter; 618}; 619 620struct r600_accel_object { 621 uint32_t pitch; 622 uint32_t width; 623 uint32_t height; 624 uint32_t offset; 625 int bpp; 626 uint32_t domain; 627 struct radeon_bo *bo; 628 uint32_t tiling_flags; 629#if defined(XF86DRM_MODE) 630 struct radeon_surface *surface; 631#endif 632}; 633 634struct radeon_vbo_object { 635 int vb_offset; 636 uint64_t vb_mc_addr; 637 int vb_total; 638 void *vb_ptr; 639 uint32_t vb_size; 640 uint32_t vb_op_vert_size; 641 int32_t vb_start_op; 642 struct radeon_bo *vb_bo; 643 unsigned verts_per_op; 644}; 645 646struct radeon_accel_state { 647 /* common accel data */ 648 int fifo_slots; /* Free slots in the FIFO (64 max) */ 649 /* Computed values for Radeon */ 650 uint32_t dp_gui_master_cntl; 651 uint32_t dp_gui_master_cntl_clip; 652 uint32_t trans_color; 653 /* Saved values for ScreenToScreenCopy */ 654 int xdir; 655 int ydir; 656 uint32_t dst_pitch_offset; 657 658 /* render accel */ 659 unsigned short texW[2]; 660 unsigned short texH[2]; 661 Bool XInited3D; /* X itself has the 3D context */ 662 int num_gb_pipes; 663 Bool has_tcl; 664 Bool allowHWDFS; 665 666#ifdef USE_EXA 667 /* EXA */ 668 ExaDriverPtr exa; 669 int exaSyncMarker; 670 int exaMarkerSynced; 671 int engineMode; 672#define EXA_ENGINEMODE_UNKNOWN 0 673#define EXA_ENGINEMODE_2D 1 674#define EXA_ENGINEMODE_3D 2 675 676 int composite_op; 677 PicturePtr dst_pic; 678 PicturePtr msk_pic; 679 PicturePtr src_pic; 680 PixmapPtr dst_pix; 681 PixmapPtr msk_pix; 682 PixmapPtr src_pix; 683 Bool is_transform[2]; 684 PictTransform *transform[2]; 685 /* Whether we are tiling horizontally and vertically */ 686 Bool need_src_tile_x; 687 Bool need_src_tile_y; 688 /* Size of tiles ... set to 65536x65536 if not tiling in that direction */ 689 Bool src_tile_width; 690 Bool src_tile_height; 691 uint32_t *draw_header; 692 unsigned vtx_count; 693 unsigned num_vtx; 694 Bool vsync; 695 696 drmBufPtr ib; 697 698 struct radeon_vbo_object vbo; 699 struct radeon_vbo_object cbuf; 700 701 /* where to discard IB from if we cancel operation */ 702 uint32_t ib_reset_op; 703#ifdef XF86DRM_MODE 704 struct radeon_dma_bo bo_free; 705 struct radeon_dma_bo bo_wait; 706 struct radeon_dma_bo bo_reserved; 707 Bool use_vbos; 708#endif 709 void (*finish_op)(ScrnInfoPtr, int); 710 // shader storage 711 ExaOffscreenArea *shaders; 712 struct radeon_bo *shaders_bo; 713 uint32_t solid_vs_offset; 714 uint32_t solid_ps_offset; 715 uint32_t copy_vs_offset; 716 uint32_t copy_ps_offset; 717 uint32_t comp_vs_offset; 718 uint32_t comp_ps_offset; 719 uint32_t xv_vs_offset; 720 uint32_t xv_ps_offset; 721 // shader consts 722 uint32_t solid_vs_const_offset; 723 uint32_t solid_ps_const_offset; 724 uint32_t copy_vs_const_offset; 725 uint32_t copy_ps_const_offset; 726 uint32_t comp_vs_const_offset; 727 uint32_t comp_ps_const_offset; 728 uint32_t comp_mask_ps_const_offset; 729 uint32_t xv_vs_const_offset; 730 uint32_t xv_ps_const_offset; 731 732 //size/addr stuff 733 struct r600_accel_object src_obj[2]; 734 struct r600_accel_object dst_obj; 735 uint32_t src_size[2]; 736 uint32_t dst_size; 737 738 uint32_t vs_size; 739 uint64_t vs_mc_addr; 740 uint32_t ps_size; 741 uint64_t ps_mc_addr; 742 743 // UTS/DFS 744 drmBufPtr scratch; 745 746 // solid/copy 747 ExaOffscreenArea *copy_area; 748 struct radeon_bo *copy_area_bo; 749 Bool same_surface; 750 int rop; 751 uint32_t planemask; 752 uint32_t fg; 753 754 // composite 755 Bool component_alpha; 756 Bool src_alpha; 757 // vline 758 xf86CrtcPtr vline_crtc; 759 int vline_y1; 760 int vline_y2; 761#endif 762 763#ifdef USE_XAA 764 /* XAA */ 765 XAAInfoRecPtr accel; 766 /* ScanlineScreenToScreenColorExpand support */ 767 unsigned char *scratch_buffer[1]; 768 unsigned char *scratch_save; 769 int scanline_x; 770 int scanline_y; 771 int scanline_w; 772 int scanline_h; 773 int scanline_h_w; 774 int scanline_words; 775 int scanline_direct; 776 int scanline_bpp; /* Only used for ImageWrite */ 777 int scanline_fg; 778 int scanline_bg; 779 int scanline_hpass; 780 int scanline_x1clip; 781 int scanline_x2clip; 782 /* Saved values for DashedTwoPointLine */ 783 int dashLen; 784 uint32_t dashPattern; 785 int dash_fg; 786 int dash_bg; 787 788 FBLinearPtr RenderTex; 789 void (*RenderCallback)(ScrnInfoPtr); 790 Time RenderTimeout; 791 /* 792 * XAAForceTransBlit is used to change the behavior of the XAA 793 * SetupForScreenToScreenCopy function, to make it DGA-friendly. 794 */ 795 Bool XAAForceTransBlit; 796#endif 797 798}; 799 800typedef struct { 801 EntityInfoPtr pEnt; 802 pciVideoPtr PciInfo; 803#ifndef XSERVER_LIBPCIACCESS 804 PCITAG PciTag; 805#endif 806 int Chipset; 807 RADEONChipFamily ChipFamily; 808 RADEONErrata ChipErrata; 809 810 unsigned long long LinearAddr; /* Frame buffer physical address */ 811 unsigned long long MMIOAddr; /* MMIO region physical address */ 812 unsigned long long BIOSAddr; /* BIOS physical address */ 813 uint64_t fbLocation; 814 uint32_t gartLocation; 815 uint32_t mc_fb_location; 816 uint32_t mc_agp_location; 817 uint32_t mc_agp_location_hi; 818 819 void *MMIO; /* Map of MMIO region */ 820 void *FB; /* Map of frame buffer */ 821 uint8_t *VBIOS; /* Video BIOS pointer */ 822 823 Bool IsAtomBios; /* New BIOS used in R420 etc. */ 824 int ROMHeaderStart; /* Start of the ROM Info Table */ 825 int MasterDataStart; /* Offset for Master Data Table for ATOM BIOS */ 826 827 uint32_t MemCntl; 828 uint32_t BusCntl; 829 unsigned long MMIOSize; /* MMIO region physical address */ 830 unsigned long FbMapSize; /* Size of frame buffer, in bytes */ 831 unsigned long FbSecureSize; /* Size of secured fb area at end of 832 framebuffer */ 833 834 Bool IsMobility; /* Mobile chips for laptops */ 835 Bool IsIGP; /* IGP chips */ 836 Bool HasSingleDAC; /* only TVDAC on chip */ 837 Bool ddc_mode; /* Validate mode by matching exactly 838 * the modes supported in DDC data 839 */ 840 Bool R300CGWorkaround; 841 842 /* EDID or BIOS values for FPs */ 843 int RefDivider; 844 int FeedbackDivider; 845 int PostDivider; 846 Bool UseBiosDividers; 847 /* EDID data using DDC interface */ 848 Bool ddc_bios; 849 Bool ddc1; 850 Bool ddc2; 851 852 RADEONPLLRec pll; 853 int default_dispclk; 854 int dp_extclk; 855 856 int RamWidth; 857 float sclk; /* in MHz */ 858 float mclk; /* in MHz */ 859 Bool IsDDR; 860 int DispPriority; 861 862 RADEONSavePtr SavedReg; /* Original (text) mode */ 863 RADEONSavePtr ModeReg; /* Current mode */ 864 Bool (*CloseScreen)(int, ScreenPtr); 865 866 void (*BlockHandler)(int, pointer, pointer, pointer); 867 868 Bool PaletteSavedOnVT; /* Palette saved on last VT switch */ 869 870 xf86CursorInfoPtr cursor; 871#ifdef ARGB_CURSOR 872 Bool cursor_argb; 873#endif 874 int cursor_fg; 875 int cursor_bg; 876 877 int pix24bpp; /* Depth of pixmap for 24bpp fb */ 878 Bool dac6bits; /* Use 6 bit DAC? */ 879 880 RADEONFBLayout CurrentLayout; 881 882#ifdef XF86DRI 883 Bool directRenderingEnabled; 884 Bool directRenderingInited; 885 RADEONCardType cardType; /* Current card is a PCI card */ 886 struct radeon_cp *cp; 887 struct radeon_dri *dri; 888#ifdef XF86DRM_MODE 889 struct radeon_dri2 dri2; 890#endif 891#ifdef USE_EXA 892 Bool accelDFS; 893#endif 894 Bool DMAForXv; 895#endif /* XF86DRI */ 896 897 /* accel */ 898 Bool RenderAccel; /* Render */ 899 Bool allowColorTiling; 900 Bool allowColorTiling2D; 901 Bool tilingEnabled; /* mirror of sarea->tiling_enabled */ 902 struct radeon_accel_state *accel_state; 903 Bool accelOn; 904 Bool useEXA; 905#ifdef USE_EXA 906 Bool exa_pixmaps; 907 Bool exa_force_create; 908 XF86ModReqInfo exaReq; 909#endif 910#ifdef USE_XAA 911 XF86ModReqInfo xaaReq; 912#endif 913 914 /* XVideo */ 915 XF86VideoAdaptorPtr adaptor; 916 void (*VideoTimerCallback)(ScrnInfoPtr, Time); 917 int videoKey; 918 int RageTheatreCrystal; 919 int RageTheatreTunerPort; 920 int RageTheatreCompositePort; 921 int RageTheatreSVideoPort; 922 int tunerType; 923 char* RageTheatreMicrocPath; 924 char* RageTheatreMicrocType; 925 Bool MM_TABLE_valid; 926 struct { 927 uint8_t table_revision; 928 uint8_t table_size; 929 uint8_t tuner_type; 930 uint8_t audio_chip; 931 uint8_t product_id; 932 uint8_t tuner_voltage_teletext_fm; 933 uint8_t i2s_config; /* configuration of the sound chip */ 934 uint8_t video_decoder_type; 935 uint8_t video_decoder_host_config; 936 uint8_t input[5]; 937 } MM_TABLE; 938 uint16_t video_decoder_type; 939 int overlay_scaler_buffer_width; 940 int ecp_div; 941 unsigned int xv_max_width; 942 unsigned int xv_max_height; 943 944 /* general */ 945 OptionInfoPtr Options; 946 947 DisplayModePtr currentMode, savedCurrentMode; 948 949 /* special handlings for DELL triple-head server */ 950 Bool IsDellServer; 951 952 Bool VGAAccess; 953 954 int MaxSurfaceWidth; 955 int MaxLines; 956 957 Bool want_vblank_interrupts; 958 RADEONBIOSConnector BiosConnector[RADEON_MAX_BIOS_CONNECTOR]; 959 radeon_encoder_ptr encoders[RADEON_MAX_BIOS_CONNECTOR]; 960 RADEONBIOSInitTable BiosTable; 961 962 /* save crtc state for console restore */ 963 Bool crtc_on; 964 Bool crtc2_on; 965 966 Bool InternalTVOut; 967 968#if defined(__powerpc__) 969 RADEONMacModel MacModel; 970#endif 971 RADEONExtTMDSChip ext_tmds_chip; 972 973 atomBiosHandlePtr atomBIOS; 974 unsigned long FbFreeStart, FbFreeSize; 975 unsigned char* BIOSCopy; 976 977 CreateScreenResourcesProcPtr CreateScreenResources; 978 979 /* if no devices are connected at server startup */ 980 Bool first_load_no_devices; 981 982 Bool IsSecondary; 983 Bool IsPrimary; 984 985 Bool r600_shadow_fb; 986 void *fb_shadow; 987 988 /* some server chips have a hardcoded edid in the bios so that they work with KVMs */ 989 Bool get_hardcoded_edid_from_bios; 990 991 int virtualX; 992 int virtualY; 993 994 Bool r4xx_atom; 995 996 /* pm */ 997 RADEONPowerManagement pm; 998 999 /* igp info */ 1000 float igp_sideport_mclk; 1001 float igp_system_mclk; 1002 float igp_ht_link_clk; 1003 float igp_ht_link_width; 1004 1005 int can_resize; 1006 void (*reemit_current2d)(ScrnInfoPtr pScrn, int op); // emit the current 2D state into the IB 1007 struct radeon_2d_state state_2d; 1008 Bool kms_enabled; 1009 struct radeon_bo *front_bo; 1010#ifdef XF86DRM_MODE 1011 struct radeon_bo_manager *bufmgr; 1012 struct radeon_cs_manager *csm; 1013 struct radeon_cs *cs; 1014 1015 struct radeon_bo *cursor_bo[32]; 1016 uint64_t vram_size; 1017 uint64_t gart_size; 1018 drmmode_rec drmmode; 1019 /* r6xx+ tile config */ 1020 Bool have_tiling_info; 1021 uint32_t tile_config; 1022 int group_bytes; 1023 int num_channels; 1024 int num_banks; 1025 int r7xx_bank_op; 1026 struct radeon_surface_manager *surf_man; 1027 struct radeon_surface front_surface; 1028#else 1029 /* fake bool */ 1030 Bool cs; 1031#endif 1032 1033 /* Xv bicubic filtering */ 1034 struct radeon_bo *bicubic_bo; 1035 void *bicubic_memory; 1036 int bicubic_offset; 1037 /* kms pageflipping */ 1038 Bool allowPageFlip; 1039 1040 /* Perform vsync'ed SwapBuffers? */ 1041 Bool swapBuffersWait; 1042} RADEONInfoRec, *RADEONInfoPtr; 1043 1044#define RADEONWaitForFifo(pScrn, entries) \ 1045do { \ 1046 if (info->accel_state->fifo_slots < entries) \ 1047 RADEONWaitForFifoFunction(pScrn, entries); \ 1048 info->accel_state->fifo_slots -= entries; \ 1049} while (0) 1050 1051/* legacy_crtc.c */ 1052extern void legacy_crtc_dpms(xf86CrtcPtr crtc, int mode); 1053extern void legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, 1054 DisplayModePtr adjusted_mode, int x, int y); 1055extern void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, 1056 RADEONSavePtr restore); 1057extern void RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn, 1058 RADEONSavePtr restore); 1059extern void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, 1060 RADEONSavePtr restore); 1061extern void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, 1062 RADEONSavePtr restore); 1063extern void RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, 1064 RADEONSavePtr restore); 1065extern void RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1066extern void RADEONSaveCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1067extern void RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save); 1068extern void RADEONSavePLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1069extern void RADEONSavePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save); 1070 1071/* legacy_output.c */ 1072extern RADEONMonitorType legacy_dac_detect(xf86OutputPtr output); 1073extern void legacy_output_dpms(xf86OutputPtr output, int mode); 1074extern void legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, 1075 DisplayModePtr adjusted_mode); 1076extern I2CDevPtr RADEONDVODeviceInit(I2CBusPtr b, I2CSlaveAddr addr); 1077extern Bool RADEONDVOReadByte(I2CDevPtr dvo, int addr, uint8_t *ch); 1078extern Bool RADEONDVOWriteByte(I2CDevPtr dvo, int addr, uint8_t ch); 1079extern void RADEONRestoreDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1080extern void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1081extern void RADEONRestoreFP2Registers(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1082extern void RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1083extern void RADEONRestoreRMXRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1084extern void RADEONSaveDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1085extern void RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1086extern void radeon_save_palette_on_demand(ScrnInfoPtr pScrn, int palID); 1087 1088extern void RADEONGetTVDacAdjInfo(ScrnInfoPtr pScrn, radeon_tvdac_ptr tvdac); 1089extern void RADEONGetTMDSInfoFromTable(ScrnInfoPtr pScrn, radeon_tmds_ptr tmds); 1090extern void RADEONGetTMDSInfo(ScrnInfoPtr pScrn, radeon_tmds_ptr tmds); 1091extern void RADEONGetExtTMDSInfo(ScrnInfoPtr pScrn, radeon_dvo_ptr dvo); 1092extern void RADEONGetLVDSInfo(ScrnInfoPtr pScrn, radeon_lvds_ptr lvds); 1093 1094/* radeon_accel.c */ 1095extern Bool RADEONAccelInit(ScreenPtr pScreen); 1096extern void RADEONEngineFlush(ScrnInfoPtr pScrn); 1097extern void RADEONEngineInit(ScrnInfoPtr pScrn); 1098extern void RADEONEngineReset(ScrnInfoPtr pScrn); 1099extern void RADEONEngineRestore(ScrnInfoPtr pScrn); 1100extern uint8_t *RADEONHostDataBlit(ScrnInfoPtr pScrn, unsigned int cpp, 1101 unsigned int w, uint32_t dstPitchOff, 1102 uint32_t *bufPitch, int x, int *y, 1103 unsigned int *h, unsigned int *hpass); 1104extern void RADEONHostDataBlitCopyPass(ScrnInfoPtr pScrn, 1105 unsigned int bpp, 1106 uint8_t *dst, uint8_t *src, 1107 unsigned int hpass, 1108 unsigned int dstPitch, 1109 unsigned int srcPitch); 1110extern void RADEONCopySwap(uint8_t *dst, uint8_t *src, unsigned int size, int swap); 1111extern void RADEONHostDataParams(ScrnInfoPtr pScrn, uint8_t *dst, 1112 uint32_t pitch, int cpp, 1113 uint32_t *dstPitchOffset, int *x, int *y); 1114extern void RADEONInit3DEngine(ScrnInfoPtr pScrn); 1115extern void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries); 1116#ifdef XF86DRI 1117extern drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn); 1118extern void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard); 1119extern void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn); 1120extern int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info); 1121# ifdef USE_XAA 1122extern Bool RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen); 1123# endif 1124uint32_t radeonGetPixmapOffset(PixmapPtr pPix); 1125#endif 1126extern int radeon_cs_space_remaining(ScrnInfoPtr pScrn); 1127 1128#ifdef USE_XAA 1129/* radeon_accelfuncs.c */ 1130extern void RADEONAccelInitMMIO(ScreenPtr pScreen, XAAInfoRecPtr a); 1131extern Bool RADEONSetupMemXAA(int scrnIndex, ScreenPtr pScreen); 1132#endif 1133 1134/* radeon_bios.c */ 1135extern Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10); 1136extern Bool RADEONGetClockInfoFromBIOS(ScrnInfoPtr pScrn); 1137extern Bool RADEONGetConnectorInfoFromBIOS(ScrnInfoPtr pScrn); 1138extern Bool RADEONGetDAC2InfoFromBIOS(ScrnInfoPtr pScrn, radeon_tvdac_ptr tvdac); 1139extern Bool RADEONGetExtTMDSInfoFromBIOS (ScrnInfoPtr pScrn, radeon_dvo_ptr dvo); 1140extern xf86MonPtr RADEONGetHardCodedEDIDFromBIOS(xf86OutputPtr output); 1141extern Bool RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn); 1142extern Bool RADEONGetLVDSInfoFromBIOS(ScrnInfoPtr pScrn, radeon_lvds_ptr lvds); 1143extern Bool RADEONGetTMDSInfoFromBIOS(ScrnInfoPtr pScrn, radeon_tmds_ptr tmds); 1144extern Bool RADEONGetTVInfoFromBIOS(xf86OutputPtr output); 1145extern Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output); 1146extern Bool RADEONPostCardFromBIOSTables(ScrnInfoPtr pScrn); 1147extern Bool radeon_card_posted(ScrnInfoPtr pScrn); 1148 1149/* radeon_commonfuncs.c */ 1150#ifdef XF86DRI 1151extern void RADEONWaitForIdleCP(ScrnInfoPtr pScrn); 1152extern void RADEONWaitForVLineCP(ScrnInfoPtr pScrn, PixmapPtr pPix, 1153 xf86CrtcPtr crtc, int start, int stop); 1154#endif 1155extern void RADEONWaitForIdleMMIO(ScrnInfoPtr pScrn); 1156extern void RADEONWaitForVLineMMIO(ScrnInfoPtr pScrn, PixmapPtr pPix, 1157 xf86CrtcPtr crtc, int start, int stop); 1158 1159/* radeon_crtc.c */ 1160extern void radeon_crtc_dpms(xf86CrtcPtr crtc, int mode); 1161extern void radeon_do_crtc_dpms(xf86CrtcPtr crtc, int mode); 1162extern void radeon_crtc_load_lut(xf86CrtcPtr crtc); 1163extern void radeon_crtc_modeset_ioctl(xf86CrtcPtr crtc, Bool post); 1164extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask); 1165extern void RADEONBlank(ScrnInfoPtr pScrn); 1166extern void RADEONComputePLL(xf86CrtcPtr crtc, 1167 RADEONPLLPtr pll, unsigned long freq, 1168 uint32_t *chosen_dot_clock_freq, 1169 uint32_t *chosen_feedback_div, 1170 uint32_t *chosen_frac_feedback_div, 1171 uint32_t *chosen_reference_div, 1172 uint32_t *chosen_post_div, int flags); 1173extern DisplayModePtr RADEONCrtcFindClosestMode(xf86CrtcPtr crtc, 1174 DisplayModePtr pMode); 1175extern void RADEONUnblank(ScrnInfoPtr pScrn); 1176extern Bool RADEONSetTiling(ScrnInfoPtr pScrn); 1177extern void RADEONInitDispBandwidth(ScrnInfoPtr pScrn); 1178 1179/* radeon_cursor.c */ 1180extern Bool RADEONCursorInit(ScreenPtr pScreen); 1181extern void radeon_crtc_hide_cursor(xf86CrtcPtr crtc); 1182extern void radeon_crtc_load_cursor_argb(xf86CrtcPtr crtc, CARD32 *image); 1183extern void radeon_crtc_set_cursor_colors(xf86CrtcPtr crtc, int bg, int fg); 1184extern void radeon_crtc_set_cursor_position(xf86CrtcPtr crtc, int x, int y); 1185extern void radeon_crtc_show_cursor(xf86CrtcPtr crtc); 1186 1187#ifdef XF86DRI 1188/* radeon_dri.c */ 1189extern void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen); 1190extern void RADEONDRICloseScreen(ScreenPtr pScreen); 1191extern Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen); 1192extern int RADEONDRIGetPciAperTableSize(ScrnInfoPtr pScrn); 1193extern Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn); 1194extern void RADEONDRIResume(ScreenPtr pScreen); 1195extern Bool RADEONDRIScreenInit(ScreenPtr pScreen); 1196extern int RADEONDRISetParam(ScrnInfoPtr pScrn, 1197 unsigned int param, int64_t value); 1198extern Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on); 1199extern void RADEONDRIStop(ScreenPtr pScreen); 1200#endif 1201 1202/* radeon_driver.c */ 1203extern void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool clone); 1204extern void RADEONChangeSurfaces(ScrnInfoPtr pScrn); 1205extern RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn); 1206extern int RADEONMinBits(int val); 1207extern unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr); 1208extern unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr); 1209extern unsigned RADEONINPCIE(ScrnInfoPtr pScrn, int addr); 1210extern unsigned R600INPCIE_PORT(ScrnInfoPtr pScrn, int addr); 1211extern void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, uint32_t data); 1212extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, uint32_t data); 1213extern void RADEONOUTPCIE(ScrnInfoPtr pScrn, int addr, uint32_t data); 1214extern void R600OUTPCIE_PORT(ScrnInfoPtr pScrn, int addr, uint32_t data); 1215extern void RADEONPllErrataAfterData(RADEONInfoPtr info); 1216extern void RADEONPllErrataAfterIndex(RADEONInfoPtr info); 1217extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn); 1218extern void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn); 1219extern void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, 1220 RADEONInfoPtr info); 1221extern void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, 1222 RADEONSavePtr restore); 1223extern Bool 1224RADEONZaphodStringMatches(ScrnInfoPtr pScrn, const char *s, char *output_name); 1225 1226Bool RADEONGetRec(ScrnInfoPtr pScrn); 1227void RADEONFreeRec(ScrnInfoPtr pScrn); 1228Bool RADEONPreInitVisual(ScrnInfoPtr pScrn); 1229Bool RADEONPreInitWeight(ScrnInfoPtr pScrn); 1230 1231extern Bool RADEON_DP_I2CInit(ScrnInfoPtr pScrn, I2CBusPtr *bus_ptr, 1232 char *name, xf86OutputPtr output); 1233extern void RADEON_DP_GetDPCD(xf86OutputPtr output); 1234extern int RADEON_DP_GetSinkType(xf86OutputPtr output); 1235 1236/* radeon_pm.c */ 1237extern void RADEONPMInit(ScrnInfoPtr pScrn); 1238extern void RADEONPMBlockHandler(ScrnInfoPtr pScrn); 1239extern void RADEONPMEnterVT(ScrnInfoPtr pScrn); 1240extern void RADEONPMLeaveVT(ScrnInfoPtr pScrn); 1241extern void RADEONPMFini(ScrnInfoPtr pScrn); 1242 1243#ifdef USE_EXA 1244/* radeon_exa.c */ 1245extern unsigned eg_tile_split(unsigned tile_split); 1246extern Bool RADEONSetupMemEXA(ScreenPtr pScreen); 1247extern Bool radeon_transform_is_affine_or_scaled(PictTransformPtr t); 1248 1249/* radeon_exa_funcs.c */ 1250extern void RADEONCopyCP(PixmapPtr pDst, int srcX, int srcY, int dstX, 1251 int dstY, int w, int h); 1252extern void RADEONCopyMMIO(PixmapPtr pDst, int srcX, int srcY, int dstX, 1253 int dstY, int w, int h); 1254extern Bool RADEONDrawInitCP(ScreenPtr pScreen); 1255extern Bool RADEONDrawInitMMIO(ScreenPtr pScreen); 1256extern void RADEONDoPrepareCopyCP(ScrnInfoPtr pScrn, 1257 uint32_t src_pitch_offset, 1258 uint32_t dst_pitch_offset, 1259 uint32_t datatype, int rop, 1260 Pixel planemask); 1261extern void RADEONDoPrepareCopyMMIO(ScrnInfoPtr pScrn, 1262 uint32_t src_pitch_offset, 1263 uint32_t dst_pitch_offset, 1264 uint32_t datatype, int rop, 1265 Pixel planemask); 1266extern Bool R600DrawInit(ScreenPtr pScreen); 1267extern Bool R600LoadShaders(ScrnInfoPtr pScrn); 1268#ifdef XF86DRM_MODE 1269extern Bool EVERGREENDrawInit(ScreenPtr pScreen); 1270#endif 1271#endif 1272 1273#if defined(XF86DRI) && defined(USE_EXA) 1274/* radeon_exa.c */ 1275extern Bool RADEONGetDatatypeBpp(int bpp, uint32_t *type); 1276extern Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, 1277 uint32_t *pitch_offset); 1278extern unsigned long long RADEONTexOffsetStart(PixmapPtr pPix); 1279#endif 1280 1281/* radeon_modes.c */ 1282extern void RADEONSetPitch(ScrnInfoPtr pScrn); 1283extern DisplayModePtr RADEONProbeOutputModes(xf86OutputPtr output); 1284 1285/* radeon_output.c */ 1286extern RADEONI2CBusRec atom_setup_i2c_bus(int ddc_line); 1287extern RADEONI2CBusRec legacy_setup_i2c_bus(int ddc_line); 1288extern void RADEONGetPanelInfo(ScrnInfoPtr pScrn); 1289extern void RADEONInitConnector(xf86OutputPtr output); 1290extern void RADEONPrintPortMap(ScrnInfoPtr pScrn); 1291extern void RADEONSetOutputType(ScrnInfoPtr pScrn, 1292 RADEONOutputPrivatePtr radeon_output); 1293extern Bool RADEONSetupConnectors(ScrnInfoPtr pScrn); 1294extern Bool RADEONI2CDoLock(xf86OutputPtr output, I2CBusPtr b, Bool lock_state); 1295 1296extern Bool radeon_dp_mode_fixup(xf86OutputPtr output, DisplayModePtr mode, DisplayModePtr adjusted_mode); 1297 1298/* radeon_tv.c */ 1299extern void RADEONSaveTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1300extern void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, 1301 DisplayModePtr mode, xf86OutputPtr output); 1302extern void RADEONAdjustPLLRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, 1303 DisplayModePtr mode, xf86OutputPtr output); 1304extern void RADEONAdjustCrtc2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, 1305 DisplayModePtr mode, xf86OutputPtr output); 1306extern void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, 1307 DisplayModePtr mode, xf86OutputPtr output); 1308extern void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save, 1309 DisplayModePtr mode, BOOL IsPrimary); 1310extern void RADEONRestoreTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1311extern void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode); 1312 1313/* radeon_video.c */ 1314extern void RADEONInitVideo(ScreenPtr pScreen); 1315extern void RADEONResetVideo(ScrnInfoPtr pScrn); 1316extern Bool radeon_load_bicubic_texture(ScrnInfoPtr pScrn); 1317extern xf86CrtcPtr radeon_pick_best_crtc(ScrnInfoPtr pScrn, 1318 int x1, int x2, int y1, int y2); 1319 1320/* radeon_legacy_memory.c */ 1321extern uint32_t 1322radeon_legacy_allocate_memory(ScrnInfoPtr pScrn, 1323 void **mem_struct, 1324 int size, 1325 int align, 1326 int domain); 1327extern void 1328radeon_legacy_free_memory(ScrnInfoPtr pScrn, 1329 void *mem_struct); 1330 1331#ifdef XF86DRM_MODE 1332extern void radeon_cs_flush_indirect(ScrnInfoPtr pScrn); 1333extern void radeon_ddx_cs_start(ScrnInfoPtr pScrn, 1334 int num, const char *file, 1335 const char *func, int line); 1336void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, int new_fb_size); 1337struct radeon_surface *radeon_get_pixmap_surface(PixmapPtr pPix); 1338#endif 1339struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix); 1340void radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_bo *bo); 1341uint32_t radeon_get_pixmap_tiling(PixmapPtr pPix); 1342 1343#ifdef XF86DRI 1344# ifdef USE_XAA 1345/* radeon_accelfuncs.c */ 1346extern void RADEONAccelInitCP(ScreenPtr pScreen, XAAInfoRecPtr a); 1347# endif 1348 1349#define RADEONCP_START(pScrn, info) \ 1350do { \ 1351 int _ret = drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_START); \ 1352 if (_ret) { \ 1353 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1354 "%s: CP start %d\n", __FUNCTION__, _ret); \ 1355 } \ 1356 info->cp->CPStarted = TRUE; \ 1357} while (0) 1358 1359#define RADEONCP_RELEASE(pScrn, info) \ 1360do { \ 1361 if (info->cs) { \ 1362 radeon_cs_flush_indirect(pScrn); \ 1363 } else if (info->cp->CPInUse) { \ 1364 RADEON_PURGE_CACHE(); \ 1365 RADEON_WAIT_UNTIL_IDLE(); \ 1366 RADEONCPReleaseIndirect(pScrn); \ 1367 info->cp->CPInUse = FALSE; \ 1368 } \ 1369} while (0) 1370 1371#define RADEONCP_STOP(pScrn, info) \ 1372do { \ 1373 int _ret; \ 1374 if (info->cp->CPStarted) { \ 1375 _ret = RADEONCPStop(pScrn, info); \ 1376 if (_ret) { \ 1377 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1378 "%s: CP stop %d\n", __FUNCTION__, _ret); \ 1379 } \ 1380 info->cp->CPStarted = FALSE; \ 1381 } \ 1382 if (info->ChipFamily < CHIP_FAMILY_R600) \ 1383 RADEONEngineRestore(pScrn); \ 1384 info->cp->CPRuns = FALSE; \ 1385} while (0) 1386 1387#define RADEONCP_RESET(pScrn, info) \ 1388do { \ 1389 int _ret = drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_RESET); \ 1390 if (_ret) { \ 1391 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1392 "%s: CP reset %d\n", __FUNCTION__, _ret); \ 1393 } \ 1394} while (0) 1395 1396#define RADEONCP_REFRESH(pScrn, info) \ 1397do { \ 1398 if (!info->cp->CPInUse && !info->cs) { \ 1399 if (info->cp->needCacheFlush) { \ 1400 RADEON_PURGE_CACHE(); \ 1401 RADEON_PURGE_ZCACHE(); \ 1402 info->cp->needCacheFlush = FALSE; \ 1403 } \ 1404 RADEON_WAIT_UNTIL_IDLE(); \ 1405 info->cp->CPInUse = TRUE; \ 1406 } \ 1407} while (0) 1408 1409 1410#define CP_PACKET0(reg, n) \ 1411 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 1412#define CP_PACKET1(reg0, reg1) \ 1413 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2)) 1414#define CP_PACKET2() \ 1415 (RADEON_CP_PACKET2) 1416#define CP_PACKET3(pkt, n) \ 1417 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 1418 1419 1420#define RADEON_VERBOSE 0 1421 1422#define RING_LOCALS uint32_t *__head = NULL; int __expected; int __count = 0 1423 1424#define BEGIN_RING(n) do { \ 1425 if (RADEON_VERBOSE) { \ 1426 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ 1427 "BEGIN_RING(%d) in %s\n", (unsigned int)n, __FUNCTION__);\ 1428 } \ 1429 if (info->cs) { radeon_ddx_cs_start(pScrn, n, __FILE__, __func__, __LINE__); } else { \ 1430 if (++info->cp->dma_begin_count != 1) { \ 1431 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1432 "BEGIN_RING without end at %s:%d\n", \ 1433 info->cp->dma_debug_func, info->cp->dma_debug_lineno); \ 1434 info->cp->dma_begin_count = 1; \ 1435 } \ 1436 info->cp->dma_debug_func = __FILE__; \ 1437 info->cp->dma_debug_lineno = __LINE__; \ 1438 if (!info->cp->indirectBuffer) { \ 1439 info->cp->indirectBuffer = RADEONCPGetBuffer(pScrn); \ 1440 info->cp->indirectStart = 0; \ 1441 } else if (info->cp->indirectBuffer->used + (n) * (int)sizeof(uint32_t) > \ 1442 info->cp->indirectBuffer->total) { \ 1443 RADEONCPFlushIndirect(pScrn, 1); \ 1444 } \ 1445 __expected = n; \ 1446 __head = (pointer)((char *)info->cp->indirectBuffer->address + \ 1447 info->cp->indirectBuffer->used); \ 1448 __count = 0; \ 1449 } \ 1450} while (0) 1451 1452#define ADVANCE_RING() do { \ 1453 if (info->cs) radeon_cs_end(info->cs, __FILE__, __func__, __LINE__); else { \ 1454 if (info->cp->dma_begin_count-- != 1) { \ 1455 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1456 "ADVANCE_RING without begin at %s:%d\n", \ 1457 __FILE__, __LINE__); \ 1458 info->cp->dma_begin_count = 0; \ 1459 } \ 1460 if (__count != __expected) { \ 1461 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1462 "ADVANCE_RING count != expected (%d vs %d) at %s:%d\n", \ 1463 __count, __expected, __FILE__, __LINE__); \ 1464 } \ 1465 if (RADEON_VERBOSE) { \ 1466 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ 1467 "ADVANCE_RING() start: %d used: %d count: %d\n", \ 1468 info->cp->indirectStart, \ 1469 info->cp->indirectBuffer->used, \ 1470 __count * (int)sizeof(uint32_t)); \ 1471 } \ 1472 info->cp->indirectBuffer->used += __count * (int)sizeof(uint32_t); \ 1473 } \ 1474 } while (0) 1475 1476#define OUT_RING(x) do { \ 1477 if (RADEON_VERBOSE) { \ 1478 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ 1479 " OUT_RING(0x%08x)\n", (unsigned int)(x)); \ 1480 } \ 1481 if (info->cs) radeon_cs_write_dword(info->cs, (x)); else \ 1482 __head[__count++] = (x); \ 1483} while (0) 1484 1485#define OUT_RING_REG(reg, val) \ 1486do { \ 1487 OUT_RING(CP_PACKET0(reg, 0)); \ 1488 OUT_RING(val); \ 1489} while (0) 1490 1491#define OUT_RING_RELOC(x, read_domains, write_domain) \ 1492 do { \ 1493 int _ret; \ 1494 _ret = radeon_cs_write_reloc(info->cs, x, read_domains, write_domain, 0); \ 1495 if (_ret) ErrorF("reloc emit failure %d\n", _ret); \ 1496 } while(0) 1497 1498 1499#define FLUSH_RING() \ 1500do { \ 1501 if (RADEON_VERBOSE) \ 1502 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ 1503 "FLUSH_RING in %s\n", __FUNCTION__); \ 1504 if (info->cs) \ 1505 radeon_cs_flush_indirect(pScrn); \ 1506 else if (info->cp->indirectBuffer) \ 1507 RADEONCPFlushIndirect(pScrn, 0); \ 1508} while (0) 1509 1510 1511#define RADEON_WAIT_UNTIL_2D_IDLE() \ 1512do { \ 1513 if (info->ChipFamily < CHIP_FAMILY_R600) { \ 1514 BEGIN_RING(2); \ 1515 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \ 1516 OUT_RING((RADEON_WAIT_2D_IDLECLEAN | \ 1517 RADEON_WAIT_HOST_IDLECLEAN)); \ 1518 ADVANCE_RING(); \ 1519 } \ 1520} while (0) 1521 1522#define RADEON_WAIT_UNTIL_3D_IDLE() \ 1523do { \ 1524 if (info->ChipFamily < CHIP_FAMILY_R600) { \ 1525 BEGIN_RING(2); \ 1526 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \ 1527 OUT_RING((RADEON_WAIT_3D_IDLECLEAN | \ 1528 RADEON_WAIT_HOST_IDLECLEAN)); \ 1529 ADVANCE_RING(); \ 1530 } \ 1531} while (0) 1532 1533#define RADEON_WAIT_UNTIL_IDLE() \ 1534do { \ 1535 if (RADEON_VERBOSE) { \ 1536 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ 1537 "WAIT_UNTIL_IDLE() in %s\n", __FUNCTION__); \ 1538 } \ 1539 if (info->ChipFamily < CHIP_FAMILY_R600) { \ 1540 BEGIN_RING(2); \ 1541 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \ 1542 OUT_RING((RADEON_WAIT_2D_IDLECLEAN | \ 1543 RADEON_WAIT_3D_IDLECLEAN | \ 1544 RADEON_WAIT_HOST_IDLECLEAN)); \ 1545 ADVANCE_RING(); \ 1546 } \ 1547} while (0) 1548 1549#define RADEON_PURGE_CACHE() \ 1550do { \ 1551 if (info->ChipFamily < CHIP_FAMILY_R600) { \ 1552 BEGIN_RING(2); \ 1553 if (info->ChipFamily <= CHIP_FAMILY_RV280) { \ 1554 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1555 OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \ 1556 } else { \ 1557 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1558 OUT_RING(R300_RB3D_DC_FLUSH_ALL); \ 1559 } \ 1560 ADVANCE_RING(); \ 1561 } \ 1562} while (0) 1563 1564#define RADEON_PURGE_ZCACHE() \ 1565do { \ 1566 if (info->ChipFamily < CHIP_FAMILY_R600) { \ 1567 BEGIN_RING(2); \ 1568 if (info->ChipFamily <= CHIP_FAMILY_RV280) { \ 1569 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1570 OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL); \ 1571 } else { \ 1572 OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); \ 1573 OUT_RING(R300_ZC_FLUSH_ALL); \ 1574 } \ 1575 ADVANCE_RING(); \ 1576 } \ 1577} while (0) 1578 1579#endif /* XF86DRI */ 1580 1581#if defined(XF86DRI) && defined(USE_EXA) 1582 1583#ifdef XF86DRM_MODE 1584#define CS_FULL(cs) ((cs)->cdw > 15 * 1024) 1585#else 1586#define CS_FULL(cs) FALSE 1587#endif 1588 1589#define RADEON_SWITCH_TO_2D() \ 1590do { \ 1591 uint32_t flush = 0; \ 1592 switch (info->accel_state->engineMode) { \ 1593 case EXA_ENGINEMODE_UNKNOWN: \ 1594 flush = 1; \ 1595 break; \ 1596 case EXA_ENGINEMODE_3D: \ 1597 flush = !info->cs || CS_FULL(info->cs); \ 1598 break; \ 1599 case EXA_ENGINEMODE_2D: \ 1600 flush = info->cs && CS_FULL(info->cs); \ 1601 break; \ 1602 } \ 1603 if (flush) { \ 1604 if (info->cs) \ 1605 radeon_cs_flush_indirect(pScrn); \ 1606 else if (info->directRenderingEnabled) \ 1607 RADEONCPFlushIndirect(pScrn, 1); \ 1608 } \ 1609 info->accel_state->engineMode = EXA_ENGINEMODE_2D; \ 1610} while (0); 1611 1612#define RADEON_SWITCH_TO_3D() \ 1613do { \ 1614 uint32_t flush = 0; \ 1615 switch (info->accel_state->engineMode) { \ 1616 case EXA_ENGINEMODE_UNKNOWN: \ 1617 flush = 1; \ 1618 break; \ 1619 case EXA_ENGINEMODE_2D: \ 1620 flush = !info->cs || CS_FULL(info->cs); \ 1621 break; \ 1622 case EXA_ENGINEMODE_3D: \ 1623 flush = info->cs && CS_FULL(info->cs); \ 1624 break; \ 1625 } \ 1626 if (flush) { \ 1627 if (info->cs) \ 1628 radeon_cs_flush_indirect(pScrn); \ 1629 else if (info->directRenderingEnabled) \ 1630 RADEONCPFlushIndirect(pScrn, 1); \ 1631 } \ 1632 if (!info->accel_state->XInited3D) \ 1633 RADEONInit3DEngine(pScrn); \ 1634 info->accel_state->engineMode = EXA_ENGINEMODE_3D; \ 1635} while (0); 1636#else 1637#define RADEON_SWITCH_TO_2D() 1638#define RADEON_SWITCH_TO_3D() 1639#endif 1640 1641static __inline__ void RADEON_MARK_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn) 1642{ 1643#ifdef USE_EXA 1644 if (info->useEXA) 1645 exaMarkSync(pScrn->pScreen); 1646#endif 1647#ifdef USE_XAA 1648 if (!info->useEXA) 1649 SET_SYNC_FLAG(info->accel_state->accel); 1650#endif 1651} 1652 1653static __inline__ void RADEON_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn) 1654{ 1655#ifdef USE_EXA 1656 if (info->useEXA && pScrn->pScreen) 1657 exaWaitSync(pScrn->pScreen); 1658#endif 1659#ifdef USE_XAA 1660 if (!info->useEXA && info->accel_state->accel) 1661 info->accel_state->accel->Sync(pScrn); 1662#endif 1663} 1664 1665static __inline__ void radeon_init_timeout(struct timeval *endtime, 1666 unsigned int timeout) 1667{ 1668 gettimeofday(endtime, NULL); 1669 endtime->tv_usec += timeout; 1670 endtime->tv_sec += endtime->tv_usec / 1000000; 1671 endtime->tv_usec %= 1000000; 1672} 1673 1674static __inline__ int radeon_timedout(const struct timeval *endtime) 1675{ 1676 struct timeval now; 1677 gettimeofday(&now, NULL); 1678 return now.tv_sec == endtime->tv_sec ? 1679 now.tv_usec > endtime->tv_usec : now.tv_sec > endtime->tv_sec; 1680} 1681 1682enum { 1683 RADEON_CREATE_PIXMAP_TILING_MACRO = 0x10000000, 1684 RADEON_CREATE_PIXMAP_TILING_MICRO = 0x20000000, 1685 RADEON_CREATE_PIXMAP_DEPTH = 0x40000000, /* for r200 */ 1686 RADEON_CREATE_PIXMAP_SZBUFFER = 0x80000000, /* for eg */ 1687}; 1688 1689#endif /* _RADEON_H_ */ 1690