radeon.h revision b13dfe66
1/* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining 8 * a copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation on the rights to use, copy, modify, merge, 11 * publish, distribute, sublicense, and/or sell copies of the Software, 12 * and to permit persons to whom the Software is furnished to do so, 13 * subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 */ 28 29/* 30 * Authors: 31 * Kevin E. Martin <martin@xfree86.org> 32 * Rickard E. Faith <faith@valinux.com> 33 * Alan Hourihane <alanh@fairlite.demon.co.uk> 34 * 35 */ 36 37#ifndef _RADEON_H_ 38#define _RADEON_H_ 39 40#include <stdlib.h> /* For abs() */ 41#include <unistd.h> /* For usleep() */ 42#include <sys/time.h> /* For gettimeofday() */ 43 44#include "config.h" 45#include "xf86str.h" 46#include "compiler.h" 47#include "xf86fbman.h" 48 49 /* PCI support */ 50#include "xf86Pci.h" 51 52#ifdef USE_EXA 53#include "exa.h" 54#endif 55#ifdef USE_XAA 56#include "xaa.h" 57#endif 58 59 /* Exa and Cursor Support */ 60#include "vbe.h" 61#include "xf86Cursor.h" 62 63 /* DDC support */ 64#include "xf86DDC.h" 65 66 /* Xv support */ 67#include "xf86xv.h" 68 69#include "radeon_probe.h" 70#include "radeon_tv.h" 71 72 /* DRI support */ 73#ifdef XF86DRI 74#define _XF86DRI_SERVER_ 75#include "dri.h" 76#include "GL/glxint.h" 77#include "xf86drm.h" 78#include "radeon_drm.h" 79 80#ifdef DAMAGE 81#include "damage.h" 82#include "globals.h" 83#endif 84#endif 85 86#include "xf86Crtc.h" 87#include "X11/Xatom.h" 88 89#ifdef XF86DRM_MODE 90#include "radeon_bo.h" 91#include "radeon_cs.h" 92#include "radeon_dri2.h" 93#include "drmmode_display.h" 94#else 95#include "radeon_dummy_bufmgr.h" 96#endif 97 98 /* Render support */ 99#ifdef RENDER 100#include "picturestr.h" 101#endif 102 103#include "simple_list.h" 104#include "atipcirename.h" 105 106#ifndef MAX 107#define MAX(a,b) ((a)>(b)?(a):(b)) 108#endif 109#ifndef MIN 110#define MIN(a,b) ((a)>(b)?(b):(a)) 111#endif 112 113#if HAVE_BYTESWAP_H 114#include <byteswap.h> 115#elif defined(USE_SYS_ENDIAN_H) 116#include <sys/endian.h> 117#else 118#define bswap_16(value) \ 119 ((((value) & 0xff) << 8) | ((value) >> 8)) 120 121#define bswap_32(value) \ 122 (((uint32_t)bswap_16((uint16_t)((value) & 0xffff)) << 16) | \ 123 (uint32_t)bswap_16((uint16_t)((value) >> 16))) 124 125#define bswap_64(value) \ 126 (((uint64_t)bswap_32((uint32_t)((value) & 0xffffffff)) \ 127 << 32) | \ 128 (uint64_t)bswap_32((uint32_t)((value) >> 32))) 129#endif 130 131#if X_BYTE_ORDER == X_BIG_ENDIAN 132#define le32_to_cpu(x) bswap_32(x) 133#define le16_to_cpu(x) bswap_16(x) 134#define cpu_to_le32(x) bswap_32(x) 135#define cpu_to_le16(x) bswap_16(x) 136#else 137#define le32_to_cpu(x) (x) 138#define le16_to_cpu(x) (x) 139#define cpu_to_le32(x) (x) 140#define cpu_to_le16(x) (x) 141#endif 142 143/* Provide substitutes for gcc's __FUNCTION__ on other compilers */ 144#if !defined(__GNUC__) && !defined(__FUNCTION__) 145# define __FUNCTION__ __func__ /* C99 */ 146#endif 147 148#ifndef HAVE_XF86MODEBANDWIDTH 149extern unsigned int xf86ModeBandwidth(DisplayModePtr mode, int depth); 150#define MODE_BANDWIDTH MODE_BAD 151#endif 152 153typedef enum { 154 OPTION_NOACCEL, 155 OPTION_SW_CURSOR, 156 OPTION_DAC_6BIT, 157 OPTION_DAC_8BIT, 158#ifdef XF86DRI 159 OPTION_BUS_TYPE, 160 OPTION_CP_PIO, 161 OPTION_USEC_TIMEOUT, 162 OPTION_AGP_MODE, 163 OPTION_AGP_FW, 164 OPTION_GART_SIZE, 165 OPTION_GART_SIZE_OLD, 166 OPTION_RING_SIZE, 167 OPTION_BUFFER_SIZE, 168 OPTION_DEPTH_MOVE, 169 OPTION_PAGE_FLIP, 170 OPTION_NO_BACKBUFFER, 171 OPTION_XV_DMA, 172 OPTION_FBTEX_PERCENT, 173 OPTION_DEPTH_BITS, 174 OPTION_PCIAPER_SIZE, 175#ifdef USE_EXA 176 OPTION_ACCEL_DFS, 177 OPTION_EXA_PIXMAPS, 178#endif 179#endif 180 OPTION_IGNORE_EDID, 181 OPTION_CUSTOM_EDID, 182 OPTION_DISP_PRIORITY, 183 OPTION_PANEL_SIZE, 184 OPTION_MIN_DOTCLOCK, 185 OPTION_COLOR_TILING, 186#ifdef XvExtension 187 OPTION_VIDEO_KEY, 188 OPTION_RAGE_THEATRE_CRYSTAL, 189 OPTION_RAGE_THEATRE_TUNER_PORT, 190 OPTION_RAGE_THEATRE_COMPOSITE_PORT, 191 OPTION_RAGE_THEATRE_SVIDEO_PORT, 192 OPTION_TUNER_TYPE, 193 OPTION_RAGE_THEATRE_MICROC_PATH, 194 OPTION_RAGE_THEATRE_MICROC_TYPE, 195 OPTION_SCALER_WIDTH, 196#endif 197#ifdef RENDER 198 OPTION_RENDER_ACCEL, 199 OPTION_SUBPIXEL_ORDER, 200#endif 201 OPTION_SHOWCACHE, 202 OPTION_CLOCK_GATING, 203 OPTION_BIOS_HOTKEYS, 204 OPTION_VGA_ACCESS, 205 OPTION_REVERSE_DDC, 206 OPTION_LVDS_PROBE_PLL, 207 OPTION_ACCELMETHOD, 208 OPTION_CONNECTORTABLE, 209 OPTION_DRI, 210 OPTION_DEFAULT_CONNECTOR_TABLE, 211#if defined(__powerpc__) 212 OPTION_MAC_MODEL, 213#endif 214 OPTION_DEFAULT_TMDS_PLL, 215 OPTION_TVDAC_LOAD_DETECT, 216 OPTION_FORCE_TVOUT, 217 OPTION_TVSTD, 218 OPTION_IGNORE_LID_STATUS, 219 OPTION_DEFAULT_TVDAC_ADJ, 220 OPTION_INT10, 221 OPTION_EXA_VSYNC, 222 OPTION_ATOM_TVOUT, 223 OPTION_R4XX_ATOM, 224 OPTION_FORCE_LOW_POWER, 225 OPTION_DYNAMIC_PM, 226 OPTION_NEW_PLL, 227 OPTION_ZAPHOD_HEADS, 228 OPTION_SWAPBUFFERS_WAIT 229} RADEONOpts; 230 231 232#define RADEON_IDLE_RETRY 16 /* Fall out of idle loops after this count */ 233#define RADEON_TIMEOUT 2000000 /* Fall out of wait loops after this count */ 234 235#define RADEON_VSYNC_TIMEOUT 20000 /* Maximum wait for VSYNC (in usecs) */ 236 237/* Buffer are aligned on 4096 byte boundaries */ 238#define RADEON_GPU_PAGE_SIZE 4096 239#define RADEON_BUFFER_ALIGN (RADEON_GPU_PAGE_SIZE - 1) 240#define RADEON_VBIOS_SIZE 0x00010000 241#define RADEON_USE_RMX 0x80000000 /* mode flag for using RMX 242 * Need to comfirm this is not used 243 * for something else. 244 */ 245 246#define xFixedToFloat(f) (((float) (f)) / 65536) 247 248#define RADEON_LOGLEVEL_DEBUG 4 249 250/* for Xv, outputs */ 251#define MAKE_ATOM(a) MakeAtom(a, sizeof(a) - 1, TRUE) 252 253/* Other macros */ 254#define RADEON_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) 255#define RADEON_ALIGN(x,bytes) (((x) + ((bytes) - 1)) & ~((bytes) - 1)) 256#define RADEONPTR(pScrn) ((RADEONInfoPtr)(pScrn)->driverPrivate) 257 258typedef struct { 259 int revision; 260 uint16_t rr1_offset; 261 uint16_t rr2_offset; 262 uint16_t dyn_clk_offset; 263 uint16_t pll_offset; 264 uint16_t mem_config_offset; 265 uint16_t mem_reset_offset; 266 uint16_t short_mem_offset; 267 uint16_t rr3_offset; 268 uint16_t rr4_offset; 269} RADEONBIOSInitTable; 270 271#define RADEON_PLL_USE_BIOS_DIVS (1 << 0) 272#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1) 273#define RADEON_PLL_USE_REF_DIV (1 << 2) 274#define RADEON_PLL_LEGACY (1 << 3) 275#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4) 276#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5) 277#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6) 278#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7) 279#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8) 280#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 281#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 282#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 283#define RADEON_PLL_USE_POST_DIV (1 << 12) 284 285typedef struct { 286 uint32_t reference_freq; 287 uint32_t reference_div; 288 uint32_t post_div; 289 uint32_t pll_in_min; 290 uint32_t pll_in_max; 291 uint32_t pll_out_min; 292 uint32_t pll_out_max; 293 uint16_t xclk; 294 295 uint32_t min_ref_div; 296 uint32_t max_ref_div; 297 uint32_t min_post_div; 298 uint32_t max_post_div; 299 uint32_t min_feedback_div; 300 uint32_t max_feedback_div; 301 uint32_t min_frac_feedback_div; 302 uint32_t max_frac_feedback_div; 303 uint32_t best_vco; 304} RADEONPLLRec, *RADEONPLLPtr; 305 306typedef struct { 307 int bitsPerPixel; 308 int depth; 309 int displayWidth; 310 int displayHeight; 311 int pixel_code; 312 int pixel_bytes; 313 DisplayModePtr mode; 314} RADEONFBLayout; 315 316typedef enum { 317 CHIP_FAMILY_UNKNOW, 318 CHIP_FAMILY_LEGACY, 319 CHIP_FAMILY_RADEON, 320 CHIP_FAMILY_RV100, 321 CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/ 322 CHIP_FAMILY_RV200, 323 CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */ 324 CHIP_FAMILY_R200, 325 CHIP_FAMILY_RV250, 326 CHIP_FAMILY_RS300, /* RS300/RS350 */ 327 CHIP_FAMILY_RV280, 328 CHIP_FAMILY_R300, 329 CHIP_FAMILY_R350, 330 CHIP_FAMILY_RV350, 331 CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ 332 CHIP_FAMILY_R420, /* R420/R423/M18 */ 333 CHIP_FAMILY_RV410, /* RV410, M26 */ 334 CHIP_FAMILY_RS400, /* xpress 200, 200m (RS400) Intel */ 335 CHIP_FAMILY_RS480, /* xpress 200, 200m (RS410/480/482/485) AMD */ 336 CHIP_FAMILY_RV515, /* rv515 */ 337 CHIP_FAMILY_R520, /* r520 */ 338 CHIP_FAMILY_RV530, /* rv530 */ 339 CHIP_FAMILY_R580, /* r580 */ 340 CHIP_FAMILY_RV560, /* rv560 */ 341 CHIP_FAMILY_RV570, /* rv570 */ 342 CHIP_FAMILY_RS600, 343 CHIP_FAMILY_RS690, 344 CHIP_FAMILY_RS740, 345 CHIP_FAMILY_R600, /* r600 */ 346 CHIP_FAMILY_RV610, 347 CHIP_FAMILY_RV630, 348 CHIP_FAMILY_RV670, 349 CHIP_FAMILY_RV620, 350 CHIP_FAMILY_RV635, 351 CHIP_FAMILY_RS780, 352 CHIP_FAMILY_RS880, 353 CHIP_FAMILY_RV770, /* r700 */ 354 CHIP_FAMILY_RV730, 355 CHIP_FAMILY_RV710, 356 CHIP_FAMILY_RV740, 357 CHIP_FAMILY_CEDAR, /* evergreen */ 358 CHIP_FAMILY_REDWOOD, 359 CHIP_FAMILY_JUNIPER, 360 CHIP_FAMILY_CYPRESS, 361 CHIP_FAMILY_HEMLOCK, 362 CHIP_FAMILY_PALM, 363 CHIP_FAMILY_BARTS, 364 CHIP_FAMILY_TURKS, 365 CHIP_FAMILY_CAICOS, 366 CHIP_FAMILY_CAYMAN, 367 CHIP_FAMILY_LAST 368} RADEONChipFamily; 369 370#define IS_RV100_VARIANT ((info->ChipFamily == CHIP_FAMILY_RV100) || \ 371 (info->ChipFamily == CHIP_FAMILY_RV200) || \ 372 (info->ChipFamily == CHIP_FAMILY_RS100) || \ 373 (info->ChipFamily == CHIP_FAMILY_RS200) || \ 374 (info->ChipFamily == CHIP_FAMILY_RV250) || \ 375 (info->ChipFamily == CHIP_FAMILY_RV280) || \ 376 (info->ChipFamily == CHIP_FAMILY_RS300)) 377 378 379#define IS_R300_VARIANT ((info->ChipFamily == CHIP_FAMILY_R300) || \ 380 (info->ChipFamily == CHIP_FAMILY_RV350) || \ 381 (info->ChipFamily == CHIP_FAMILY_R350) || \ 382 (info->ChipFamily == CHIP_FAMILY_RV380) || \ 383 (info->ChipFamily == CHIP_FAMILY_R420) || \ 384 (info->ChipFamily == CHIP_FAMILY_RV410) || \ 385 (info->ChipFamily == CHIP_FAMILY_RS400) || \ 386 (info->ChipFamily == CHIP_FAMILY_RS480)) 387 388#define IS_AVIVO_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV515)) 389 390#define IS_DCE3_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV620)) 391 392#define IS_DCE32_VARIANT ((info->ChipFamily >= CHIP_FAMILY_RV730)) 393 394#define IS_DCE4_VARIANT ((info->ChipFamily >= CHIP_FAMILY_CEDAR)) 395 396#define IS_DCE41_VARIANT ((info->ChipFamily >= CHIP_FAMILY_PALM)) 397 398#define IS_DCE5_VARIANT ((info->ChipFamily >= CHIP_FAMILY_BARTS)) 399 400#define IS_EVERGREEN_3D (info->ChipFamily >= CHIP_FAMILY_CEDAR) 401 402#define IS_R600_3D (info->ChipFamily >= CHIP_FAMILY_R600) 403 404#define IS_R500_3D ((info->ChipFamily == CHIP_FAMILY_RV515) || \ 405 (info->ChipFamily == CHIP_FAMILY_R520) || \ 406 (info->ChipFamily == CHIP_FAMILY_RV530) || \ 407 (info->ChipFamily == CHIP_FAMILY_R580) || \ 408 (info->ChipFamily == CHIP_FAMILY_RV560) || \ 409 (info->ChipFamily == CHIP_FAMILY_RV570)) 410 411#define IS_R400_3D ((info->ChipFamily == CHIP_FAMILY_R420) || \ 412 (info->ChipFamily == CHIP_FAMILY_RV410) || \ 413 (info->ChipFamily == CHIP_FAMILY_RS690) || \ 414 (info->ChipFamily == CHIP_FAMILY_RS600) || \ 415 (info->ChipFamily == CHIP_FAMILY_RS740)) 416 417#define IS_R300_3D ((info->ChipFamily == CHIP_FAMILY_R300) || \ 418 (info->ChipFamily == CHIP_FAMILY_RV350) || \ 419 (info->ChipFamily == CHIP_FAMILY_R350) || \ 420 (info->ChipFamily == CHIP_FAMILY_RV380) || \ 421 (info->ChipFamily == CHIP_FAMILY_R420) || \ 422 (info->ChipFamily == CHIP_FAMILY_RV410) || \ 423 (info->ChipFamily == CHIP_FAMILY_RS690) || \ 424 (info->ChipFamily == CHIP_FAMILY_RS600) || \ 425 (info->ChipFamily == CHIP_FAMILY_RS740) || \ 426 (info->ChipFamily == CHIP_FAMILY_RS400) || \ 427 (info->ChipFamily == CHIP_FAMILY_RS480)) 428 429#define IS_R200_3D ((info->ChipFamily == CHIP_FAMILY_RV250) || \ 430 (info->ChipFamily == CHIP_FAMILY_RV280) || \ 431 (info->ChipFamily == CHIP_FAMILY_RS300) || \ 432 (info->ChipFamily == CHIP_FAMILY_R200)) 433 434/* 435 * Errata workarounds 436 */ 437typedef enum { 438 CHIP_ERRATA_R300_CG = 0x00000001, 439 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 440 CHIP_ERRATA_PLL_DELAY = 0x00000004 441} RADEONErrata; 442 443typedef enum { 444 RADEON_DVOCHIP_NONE, 445 RADEON_SIL_164, 446 RADEON_SIL_1178 447} RADEONExtTMDSChip; 448 449#if defined(__powerpc__) 450typedef enum { 451 RADEON_MAC_NONE, 452 RADEON_MAC_IBOOK, 453 RADEON_MAC_POWERBOOK_EXTERNAL, 454 RADEON_MAC_POWERBOOK_INTERNAL, 455 RADEON_MAC_POWERBOOK_VGA, 456 RADEON_MAC_MINI_EXTERNAL, 457 RADEON_MAC_MINI_INTERNAL, 458 RADEON_MAC_IMAC_G5_ISIGHT, 459 RADEON_MAC_EMAC 460} RADEONMacModel; 461#endif 462 463typedef enum { 464 CARD_PCI, 465 CARD_AGP, 466 CARD_PCIE 467} RADEONCardType; 468 469typedef enum { 470 POWER_DEFAULT, 471 POWER_LOW, 472 POWER_HIGH 473} RADEONPMType; 474 475typedef struct { 476 RADEONPMType type; 477 uint32_t sclk; 478 uint32_t mclk; 479 uint32_t pcie_lanes; 480 uint32_t flags; 481} RADEONPowerMode; 482 483typedef struct { 484 /* power modes */ 485 int num_modes; 486 int current_mode; 487 RADEONPowerMode mode[3]; 488 489 Bool clock_gating_enabled; 490 Bool dynamic_mode_enabled; 491 Bool force_low_power_enabled; 492} RADEONPowerManagement; 493 494typedef struct _atomBiosHandle *atomBiosHandlePtr; 495 496struct radeon_exa_pixmap_priv { 497 struct radeon_bo *bo; 498 int flags; 499 Bool bo_mapped; 500}; 501 502typedef struct { 503 uint32_t pci_device_id; 504 RADEONChipFamily chip_family; 505 int mobility; 506 int igp; 507 int nocrtc2; 508 int nointtvout; 509 int singledac; 510} RADEONCardInfo; 511 512#define RADEON_2D_EXA_COPY 1 513#define RADEON_2D_EXA_SOLID 2 514 515struct radeon_2d_state { 516 int op; // 517 uint32_t dst_pitch_offset; 518 uint32_t src_pitch_offset; 519 uint32_t dp_gui_master_cntl; 520 uint32_t dp_cntl; 521 uint32_t dp_write_mask; 522 uint32_t dp_brush_frgd_clr; 523 uint32_t dp_brush_bkgd_clr; 524 uint32_t dp_src_frgd_clr; 525 uint32_t dp_src_bkgd_clr; 526 uint32_t default_sc_bottom_right; 527 struct radeon_bo *dst_bo; 528 struct radeon_bo *src_bo; 529}; 530 531#ifdef XF86DRI 532struct radeon_cp { 533 Bool CPRuns; /* CP is running */ 534 Bool CPInUse; /* CP has been used by X server */ 535 Bool CPStarted; /* CP has started */ 536 int CPMode; /* CP mode that server/clients use */ 537 int CPFifoSize; /* Size of the CP command FIFO */ 538 int CPusecTimeout; /* CP timeout in usecs */ 539 Bool needCacheFlush; 540 541 /* CP accleration */ 542 drmBufPtr indirectBuffer; 543 int indirectStart; 544 545 /* Debugging info for BEGIN_RING/ADVANCE_RING pairs. */ 546 int dma_begin_count; 547 char *dma_debug_func; 548 int dma_debug_lineno; 549 550 }; 551 552typedef struct { 553 /* Nothing here yet */ 554 int dummy; 555} RADEONConfigPrivRec, *RADEONConfigPrivPtr; 556 557typedef struct { 558 /* Nothing here yet */ 559 int dummy; 560} RADEONDRIContextRec, *RADEONDRIContextPtr; 561 562struct radeon_dri { 563 Bool noBackBuffer; 564 565 Bool newMemoryMap; 566 drmVersionPtr pLibDRMVersion; 567 drmVersionPtr pKernelDRMVersion; 568 DRIInfoPtr pDRIInfo; 569 int drmFD; 570 int numVisualConfigs; 571 __GLXvisualConfig *pVisualConfigs; 572 RADEONConfigPrivPtr pVisualConfigsPriv; 573 Bool (*DRICloseScreen)(int, ScreenPtr); 574 575 drm_handle_t fbHandle; 576 577 drmSize registerSize; 578 drm_handle_t registerHandle; 579 580 drmSize pciSize; 581 drm_handle_t pciMemHandle; 582 unsigned char *PCI; /* Map */ 583 584 Bool depthMoves; /* Enable depth moves -- slow! */ 585 Bool allowPageFlip; /* Enable 3d page flipping */ 586#ifdef DAMAGE 587 DamagePtr pDamage; 588 RegionRec driRegion; 589#endif 590 Bool have3DWindows; /* Are there any 3d clients? */ 591 592 int pciAperSize; 593 drmSize gartSize; 594 drm_handle_t agpMemHandle; /* Handle from drmAgpAlloc */ 595 unsigned long gartOffset; 596 unsigned char *AGP; /* Map */ 597 int agpMode; 598 599 uint32_t pciCommand; 600 601 /* CP ring buffer data */ 602 unsigned long ringStart; /* Offset into GART space */ 603 drm_handle_t ringHandle; /* Handle from drmAddMap */ 604 drmSize ringMapSize; /* Size of map */ 605 int ringSize; /* Size of ring (in MB) */ 606 drmAddress ring; /* Map */ 607 int ringSizeLog2QW; 608 609 unsigned long ringReadOffset; /* Offset into GART space */ 610 drm_handle_t ringReadPtrHandle; /* Handle from drmAddMap */ 611 drmSize ringReadMapSize; /* Size of map */ 612 drmAddress ringReadPtr; /* Map */ 613 614 /* CP vertex/indirect buffer data */ 615 unsigned long bufStart; /* Offset into GART space */ 616 drm_handle_t bufHandle; /* Handle from drmAddMap */ 617 drmSize bufMapSize; /* Size of map */ 618 int bufSize; /* Size of buffers (in MB) */ 619 drmAddress buf; /* Map */ 620 int bufNumBufs; /* Number of buffers */ 621 drmBufMapPtr buffers; /* Buffer map */ 622 623 /* CP GART Texture data */ 624 unsigned long gartTexStart; /* Offset into GART space */ 625 drm_handle_t gartTexHandle; /* Handle from drmAddMap */ 626 drmSize gartTexMapSize; /* Size of map */ 627 int gartTexSize; /* Size of GART tex space (in MB) */ 628 drmAddress gartTex; /* Map */ 629 int log2GARTTexGran; 630 631 /* DRI screen private data */ 632 int fbX; 633 int fbY; 634 int backX; 635 int backY; 636 int depthX; 637 int depthY; 638 639 int frontOffset; 640 int frontPitch; 641 int backOffset; 642 int backPitch; 643 int depthOffset; 644 int depthPitch; 645 int depthBits; 646 int textureOffset; 647 int textureSize; 648 int log2TexGran; 649 650 int pciGartSize; 651 uint32_t pciGartOffset; 652 void *pciGartBackup; 653 654 int irq; 655 656#ifdef USE_XAA 657 uint32_t frontPitchOffset; 658 uint32_t backPitchOffset; 659 uint32_t depthPitchOffset; 660 661 /* offscreen memory management */ 662 int backLines; 663 FBAreaPtr backArea; 664 int depthTexLines; 665 FBAreaPtr depthTexArea; 666#endif 667 668}; 669#endif 670 671#define DMA_BO_FREE_TIME 1000 672 673struct radeon_dma_bo { 674 struct radeon_dma_bo *next, *prev; 675 struct radeon_bo *bo; 676 int expire_counter; 677}; 678 679struct r600_accel_object { 680 uint32_t pitch; 681 uint32_t width; 682 uint32_t height; 683 uint32_t offset; 684 int bpp; 685 uint32_t domain; 686 struct radeon_bo *bo; 687 uint32_t tiling_flags; 688}; 689 690struct radeon_vbo_object { 691 int vb_offset; 692 uint64_t vb_mc_addr; 693 int vb_total; 694 void *vb_ptr; 695 uint32_t vb_size; 696 uint32_t vb_op_vert_size; 697 int32_t vb_start_op; 698 struct radeon_bo *vb_bo; 699 unsigned verts_per_op; 700}; 701 702struct radeon_accel_state { 703 /* common accel data */ 704 int fifo_slots; /* Free slots in the FIFO (64 max) */ 705 /* Computed values for Radeon */ 706 uint32_t dp_gui_master_cntl; 707 uint32_t dp_gui_master_cntl_clip; 708 uint32_t trans_color; 709 /* Saved values for ScreenToScreenCopy */ 710 int xdir; 711 int ydir; 712 uint32_t dst_pitch_offset; 713 714 /* render accel */ 715 unsigned short texW[2]; 716 unsigned short texH[2]; 717 Bool XInited3D; /* X itself has the 3D context */ 718 int num_gb_pipes; 719 Bool has_tcl; 720 721#ifdef USE_EXA 722 /* EXA */ 723 ExaDriverPtr exa; 724 int exaSyncMarker; 725 int exaMarkerSynced; 726 int engineMode; 727#define EXA_ENGINEMODE_UNKNOWN 0 728#define EXA_ENGINEMODE_2D 1 729#define EXA_ENGINEMODE_3D 2 730 731 int composite_op; 732 PicturePtr dst_pic; 733 PicturePtr msk_pic; 734 PicturePtr src_pic; 735 PixmapPtr dst_pix; 736 PixmapPtr msk_pix; 737 PixmapPtr src_pix; 738 Bool is_transform[2]; 739 PictTransform *transform[2]; 740 /* Whether we are tiling horizontally and vertically */ 741 Bool need_src_tile_x; 742 Bool need_src_tile_y; 743 /* Size of tiles ... set to 65536x65536 if not tiling in that direction */ 744 Bool src_tile_width; 745 Bool src_tile_height; 746 uint32_t *draw_header; 747 unsigned vtx_count; 748 unsigned num_vtx; 749 Bool vsync; 750 751 drmBufPtr ib; 752 753 struct radeon_vbo_object vbo; 754 struct radeon_vbo_object cbuf; 755 756 /* where to discard IB from if we cancel operation */ 757 uint32_t ib_reset_op; 758#ifdef XF86DRM_MODE 759 struct radeon_dma_bo bo_free; 760 struct radeon_dma_bo bo_wait; 761 struct radeon_dma_bo bo_reserved; 762 Bool use_vbos; 763#endif 764 void (*finish_op)(ScrnInfoPtr, int); 765 // shader storage 766 ExaOffscreenArea *shaders; 767 struct radeon_bo *shaders_bo; 768 uint32_t solid_vs_offset; 769 uint32_t solid_ps_offset; 770 uint32_t copy_vs_offset; 771 uint32_t copy_ps_offset; 772 uint32_t comp_vs_offset; 773 uint32_t comp_ps_offset; 774 uint32_t xv_vs_offset; 775 uint32_t xv_ps_offset; 776 // shader consts 777 uint32_t solid_vs_const_offset; 778 uint32_t solid_ps_const_offset; 779 uint32_t copy_vs_const_offset; 780 uint32_t copy_ps_const_offset; 781 uint32_t comp_vs_const_offset; 782 uint32_t comp_ps_const_offset; 783 uint32_t comp_mask_ps_const_offset; 784 uint32_t xv_vs_const_offset; 785 uint32_t xv_ps_const_offset; 786 787 //size/addr stuff 788 struct r600_accel_object src_obj[2]; 789 struct r600_accel_object dst_obj; 790 uint32_t src_size[2]; 791 uint32_t dst_size; 792 793 uint32_t vs_size; 794 uint64_t vs_mc_addr; 795 uint32_t ps_size; 796 uint64_t ps_mc_addr; 797 798 // UTS/DFS 799 drmBufPtr scratch; 800 801 // copy 802 ExaOffscreenArea *copy_area; 803 struct radeon_bo *copy_area_bo; 804 Bool same_surface; 805 int rop; 806 uint32_t planemask; 807 808 // composite 809 Bool component_alpha; 810 Bool src_alpha; 811 // vline 812 xf86CrtcPtr vline_crtc; 813 int vline_y1; 814 int vline_y2; 815#endif 816 817#ifdef USE_XAA 818 /* XAA */ 819 XAAInfoRecPtr accel; 820 /* ScanlineScreenToScreenColorExpand support */ 821 unsigned char *scratch_buffer[1]; 822 unsigned char *scratch_save; 823 int scanline_x; 824 int scanline_y; 825 int scanline_w; 826 int scanline_h; 827 int scanline_h_w; 828 int scanline_words; 829 int scanline_direct; 830 int scanline_bpp; /* Only used for ImageWrite */ 831 int scanline_fg; 832 int scanline_bg; 833 int scanline_hpass; 834 int scanline_x1clip; 835 int scanline_x2clip; 836 /* Saved values for DashedTwoPointLine */ 837 int dashLen; 838 uint32_t dashPattern; 839 int dash_fg; 840 int dash_bg; 841 842 FBLinearPtr RenderTex; 843 void (*RenderCallback)(ScrnInfoPtr); 844 Time RenderTimeout; 845 /* 846 * XAAForceTransBlit is used to change the behavior of the XAA 847 * SetupForScreenToScreenCopy function, to make it DGA-friendly. 848 */ 849 Bool XAAForceTransBlit; 850#endif 851 852}; 853 854typedef struct { 855 EntityInfoPtr pEnt; 856 pciVideoPtr PciInfo; 857 PCITAG PciTag; 858 int Chipset; 859 RADEONChipFamily ChipFamily; 860 RADEONErrata ChipErrata; 861 862 unsigned long long LinearAddr; /* Frame buffer physical address */ 863 unsigned long long MMIOAddr; /* MMIO region physical address */ 864 unsigned long long BIOSAddr; /* BIOS physical address */ 865 uint64_t fbLocation; 866 uint32_t gartLocation; 867 uint32_t mc_fb_location; 868 uint32_t mc_agp_location; 869 uint32_t mc_agp_location_hi; 870 871 void *MMIO; /* Map of MMIO region */ 872 void *FB; /* Map of frame buffer */ 873 uint8_t *VBIOS; /* Video BIOS pointer */ 874 875 Bool IsAtomBios; /* New BIOS used in R420 etc. */ 876 int ROMHeaderStart; /* Start of the ROM Info Table */ 877 int MasterDataStart; /* Offset for Master Data Table for ATOM BIOS */ 878 879 uint32_t MemCntl; 880 uint32_t BusCntl; 881 unsigned long MMIOSize; /* MMIO region physical address */ 882 unsigned long FbMapSize; /* Size of frame buffer, in bytes */ 883 unsigned long FbSecureSize; /* Size of secured fb area at end of 884 framebuffer */ 885 886 Bool IsMobility; /* Mobile chips for laptops */ 887 Bool IsIGP; /* IGP chips */ 888 Bool HasSingleDAC; /* only TVDAC on chip */ 889 Bool ddc_mode; /* Validate mode by matching exactly 890 * the modes supported in DDC data 891 */ 892 Bool R300CGWorkaround; 893 894 /* EDID or BIOS values for FPs */ 895 int RefDivider; 896 int FeedbackDivider; 897 int PostDivider; 898 Bool UseBiosDividers; 899 /* EDID data using DDC interface */ 900 Bool ddc_bios; 901 Bool ddc1; 902 Bool ddc2; 903 904 RADEONPLLRec pll; 905 int default_dispclk; 906 int dp_extclk; 907 908 int RamWidth; 909 float sclk; /* in MHz */ 910 float mclk; /* in MHz */ 911 Bool IsDDR; 912 int DispPriority; 913 914 RADEONSavePtr SavedReg; /* Original (text) mode */ 915 RADEONSavePtr ModeReg; /* Current mode */ 916 Bool (*CloseScreen)(int, ScreenPtr); 917 918 void (*BlockHandler)(int, pointer, pointer, pointer); 919 920 Bool PaletteSavedOnVT; /* Palette saved on last VT switch */ 921 922 xf86CursorInfoPtr cursor; 923#ifdef ARGB_CURSOR 924 Bool cursor_argb; 925#endif 926 int cursor_fg; 927 int cursor_bg; 928 929 int pix24bpp; /* Depth of pixmap for 24bpp fb */ 930 Bool dac6bits; /* Use 6 bit DAC? */ 931 932 RADEONFBLayout CurrentLayout; 933 934#ifdef XF86DRI 935 Bool directRenderingEnabled; 936 Bool directRenderingInited; 937 RADEONCardType cardType; /* Current card is a PCI card */ 938 struct radeon_cp *cp; 939 struct radeon_dri *dri; 940#ifdef XF86DRM_MODE 941 struct radeon_dri2 dri2; 942#endif 943#ifdef USE_EXA 944 Bool accelDFS; 945#endif 946 Bool DMAForXv; 947#endif /* XF86DRI */ 948 949 /* accel */ 950 Bool RenderAccel; /* Render */ 951 Bool allowColorTiling; 952 Bool tilingEnabled; /* mirror of sarea->tiling_enabled */ 953 struct radeon_accel_state *accel_state; 954 Bool accelOn; 955 Bool useEXA; 956#ifdef USE_EXA 957 Bool exa_pixmaps; 958 Bool exa_force_create; 959 XF86ModReqInfo exaReq; 960#endif 961#ifdef USE_XAA 962 XF86ModReqInfo xaaReq; 963#endif 964 965 /* XVideo */ 966 XF86VideoAdaptorPtr adaptor; 967 void (*VideoTimerCallback)(ScrnInfoPtr, Time); 968 int videoKey; 969 int RageTheatreCrystal; 970 int RageTheatreTunerPort; 971 int RageTheatreCompositePort; 972 int RageTheatreSVideoPort; 973 int tunerType; 974 char* RageTheatreMicrocPath; 975 char* RageTheatreMicrocType; 976 Bool MM_TABLE_valid; 977 struct { 978 uint8_t table_revision; 979 uint8_t table_size; 980 uint8_t tuner_type; 981 uint8_t audio_chip; 982 uint8_t product_id; 983 uint8_t tuner_voltage_teletext_fm; 984 uint8_t i2s_config; /* configuration of the sound chip */ 985 uint8_t video_decoder_type; 986 uint8_t video_decoder_host_config; 987 uint8_t input[5]; 988 } MM_TABLE; 989 uint16_t video_decoder_type; 990 int overlay_scaler_buffer_width; 991 int ecp_div; 992 unsigned int xv_max_width; 993 unsigned int xv_max_height; 994 995 /* general */ 996 OptionInfoPtr Options; 997 998 DisplayModePtr currentMode, savedCurrentMode; 999 1000 /* special handlings for DELL triple-head server */ 1001 Bool IsDellServer; 1002 1003 Bool VGAAccess; 1004 1005 int MaxSurfaceWidth; 1006 int MaxLines; 1007 1008 Bool want_vblank_interrupts; 1009 RADEONBIOSConnector BiosConnector[RADEON_MAX_BIOS_CONNECTOR]; 1010 radeon_encoder_ptr encoders[RADEON_MAX_BIOS_CONNECTOR]; 1011 RADEONBIOSInitTable BiosTable; 1012 1013 /* save crtc state for console restore */ 1014 Bool crtc_on; 1015 Bool crtc2_on; 1016 1017 Bool InternalTVOut; 1018 1019#if defined(__powerpc__) 1020 RADEONMacModel MacModel; 1021#endif 1022 RADEONExtTMDSChip ext_tmds_chip; 1023 1024 atomBiosHandlePtr atomBIOS; 1025 unsigned long FbFreeStart, FbFreeSize; 1026 unsigned char* BIOSCopy; 1027 1028 CreateScreenResourcesProcPtr CreateScreenResources; 1029 1030 /* if no devices are connected at server startup */ 1031 Bool first_load_no_devices; 1032 1033 Bool IsSecondary; 1034 Bool IsPrimary; 1035 1036 Bool r600_shadow_fb; 1037 void *fb_shadow; 1038 1039 /* some server chips have a hardcoded edid in the bios so that they work with KVMs */ 1040 Bool get_hardcoded_edid_from_bios; 1041 1042 int virtualX; 1043 int virtualY; 1044 1045 Bool r4xx_atom; 1046 1047 /* pm */ 1048 RADEONPowerManagement pm; 1049 1050 /* igp info */ 1051 float igp_sideport_mclk; 1052 float igp_system_mclk; 1053 float igp_ht_link_clk; 1054 float igp_ht_link_width; 1055 1056 int can_resize; 1057 void (*reemit_current2d)(ScrnInfoPtr pScrn, int op); // emit the current 2D state into the IB 1058 struct radeon_2d_state state_2d; 1059 Bool kms_enabled; 1060 struct radeon_bo *front_bo; 1061#ifdef XF86DRM_MODE 1062 struct radeon_bo_manager *bufmgr; 1063 struct radeon_cs_manager *csm; 1064 struct radeon_cs *cs; 1065 1066 struct radeon_bo *cursor_bo[6]; 1067 uint64_t vram_size; 1068 uint64_t gart_size; 1069 drmmode_rec drmmode; 1070 /* r6xx+ tile config */ 1071 Bool have_tiling_info; 1072 uint32_t tile_config; 1073 int group_bytes; 1074 int num_channels; 1075 int num_banks; 1076 int r7xx_bank_op; 1077#else 1078 /* fake bool */ 1079 Bool cs; 1080#endif 1081 1082 /* Xv bicubic filtering */ 1083 struct radeon_bo *bicubic_bo; 1084 void *bicubic_memory; 1085 int bicubic_offset; 1086 /* kms pageflipping */ 1087 Bool allowPageFlip; 1088 1089 /* Perform vsync'ed SwapBuffers? */ 1090 Bool swapBuffersWait; 1091} RADEONInfoRec, *RADEONInfoPtr; 1092 1093#define RADEONWaitForFifo(pScrn, entries) \ 1094do { \ 1095 if (info->accel_state->fifo_slots < entries) \ 1096 RADEONWaitForFifoFunction(pScrn, entries); \ 1097 info->accel_state->fifo_slots -= entries; \ 1098} while (0) 1099 1100/* legacy_crtc.c */ 1101extern void legacy_crtc_dpms(xf86CrtcPtr crtc, int mode); 1102extern void legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode, 1103 DisplayModePtr adjusted_mode, int x, int y); 1104extern void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn, 1105 RADEONSavePtr restore); 1106extern void RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn, 1107 RADEONSavePtr restore); 1108extern void RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn, 1109 RADEONSavePtr restore); 1110extern void RADEONRestorePLLRegisters(ScrnInfoPtr pScrn, 1111 RADEONSavePtr restore); 1112extern void RADEONRestorePLL2Registers(ScrnInfoPtr pScrn, 1113 RADEONSavePtr restore); 1114extern void RADEONSaveCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1115extern void RADEONSaveCrtcRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1116extern void RADEONSaveCrtc2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save); 1117extern void RADEONSavePLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1118extern void RADEONSavePLL2Registers(ScrnInfoPtr pScrn, RADEONSavePtr save); 1119 1120/* legacy_output.c */ 1121extern RADEONMonitorType legacy_dac_detect(xf86OutputPtr output); 1122extern void legacy_output_dpms(xf86OutputPtr output, int mode); 1123extern void legacy_output_mode_set(xf86OutputPtr output, DisplayModePtr mode, 1124 DisplayModePtr adjusted_mode); 1125extern I2CDevPtr RADEONDVODeviceInit(I2CBusPtr b, I2CSlaveAddr addr); 1126extern Bool RADEONDVOReadByte(I2CDevPtr dvo, int addr, uint8_t *ch); 1127extern Bool RADEONDVOWriteByte(I2CDevPtr dvo, int addr, uint8_t ch); 1128extern void RADEONRestoreDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1129extern void RADEONRestoreFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1130extern void RADEONRestoreFP2Registers(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1131extern void RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1132extern void RADEONRestoreRMXRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1133extern void RADEONSaveDACRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1134extern void RADEONSaveFPRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1135 1136extern void RADEONGetTVDacAdjInfo(ScrnInfoPtr pScrn, radeon_tvdac_ptr tvdac); 1137extern void RADEONGetTMDSInfoFromTable(ScrnInfoPtr pScrn, radeon_tmds_ptr tmds); 1138extern void RADEONGetTMDSInfo(ScrnInfoPtr pScrn, radeon_tmds_ptr tmds); 1139extern void RADEONGetExtTMDSInfo(ScrnInfoPtr pScrn, radeon_dvo_ptr dvo); 1140extern void RADEONGetLVDSInfo(ScrnInfoPtr pScrn, radeon_lvds_ptr lvds); 1141 1142/* radeon_accel.c */ 1143extern Bool RADEONAccelInit(ScreenPtr pScreen); 1144extern void RADEONEngineFlush(ScrnInfoPtr pScrn); 1145extern void RADEONEngineInit(ScrnInfoPtr pScrn); 1146extern void RADEONEngineReset(ScrnInfoPtr pScrn); 1147extern void RADEONEngineRestore(ScrnInfoPtr pScrn); 1148extern uint8_t *RADEONHostDataBlit(ScrnInfoPtr pScrn, unsigned int cpp, 1149 unsigned int w, uint32_t dstPitchOff, 1150 uint32_t *bufPitch, int x, int *y, 1151 unsigned int *h, unsigned int *hpass); 1152extern void RADEONHostDataBlitCopyPass(ScrnInfoPtr pScrn, 1153 unsigned int bpp, 1154 uint8_t *dst, uint8_t *src, 1155 unsigned int hpass, 1156 unsigned int dstPitch, 1157 unsigned int srcPitch); 1158extern void RADEONCopySwap(uint8_t *dst, uint8_t *src, unsigned int size, int swap); 1159extern void RADEONHostDataParams(ScrnInfoPtr pScrn, uint8_t *dst, 1160 uint32_t pitch, int cpp, 1161 uint32_t *dstPitchOffset, int *x, int *y); 1162extern void RADEONInit3DEngine(ScrnInfoPtr pScrn); 1163extern void RADEONWaitForFifoFunction(ScrnInfoPtr pScrn, int entries); 1164#ifdef XF86DRI 1165extern drmBufPtr RADEONCPGetBuffer(ScrnInfoPtr pScrn); 1166extern void RADEONCPFlushIndirect(ScrnInfoPtr pScrn, int discard); 1167extern void RADEONCPReleaseIndirect(ScrnInfoPtr pScrn); 1168extern int RADEONCPStop(ScrnInfoPtr pScrn, RADEONInfoPtr info); 1169# ifdef USE_XAA 1170extern Bool RADEONSetupMemXAA_DRI(int scrnIndex, ScreenPtr pScreen); 1171# endif 1172uint32_t radeonGetPixmapOffset(PixmapPtr pPix); 1173#endif 1174extern int radeon_cs_space_remaining(ScrnInfoPtr pScrn); 1175 1176#ifdef USE_XAA 1177/* radeon_accelfuncs.c */ 1178extern void RADEONAccelInitMMIO(ScreenPtr pScreen, XAAInfoRecPtr a); 1179extern Bool RADEONSetupMemXAA(int scrnIndex, ScreenPtr pScreen); 1180#endif 1181 1182/* radeon_bios.c */ 1183extern Bool RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10); 1184extern Bool RADEONGetClockInfoFromBIOS(ScrnInfoPtr pScrn); 1185extern Bool RADEONGetConnectorInfoFromBIOS(ScrnInfoPtr pScrn); 1186extern Bool RADEONGetDAC2InfoFromBIOS(ScrnInfoPtr pScrn, radeon_tvdac_ptr tvdac); 1187extern Bool RADEONGetExtTMDSInfoFromBIOS (ScrnInfoPtr pScrn, radeon_dvo_ptr dvo); 1188extern xf86MonPtr RADEONGetHardCodedEDIDFromBIOS(xf86OutputPtr output); 1189extern Bool RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn); 1190extern Bool RADEONGetLVDSInfoFromBIOS(ScrnInfoPtr pScrn, radeon_lvds_ptr lvds); 1191extern Bool RADEONGetTMDSInfoFromBIOS(ScrnInfoPtr pScrn, radeon_tmds_ptr tmds); 1192extern Bool RADEONGetTVInfoFromBIOS(xf86OutputPtr output); 1193extern Bool RADEONInitExtTMDSInfoFromBIOS (xf86OutputPtr output); 1194extern Bool RADEONPostCardFromBIOSTables(ScrnInfoPtr pScrn); 1195extern Bool radeon_card_posted(ScrnInfoPtr pScrn); 1196 1197/* radeon_commonfuncs.c */ 1198#ifdef XF86DRI 1199extern void RADEONWaitForIdleCP(ScrnInfoPtr pScrn); 1200extern void RADEONWaitForVLineCP(ScrnInfoPtr pScrn, PixmapPtr pPix, 1201 xf86CrtcPtr crtc, int start, int stop); 1202#endif 1203extern void RADEONWaitForIdleMMIO(ScrnInfoPtr pScrn); 1204extern void RADEONWaitForVLineMMIO(ScrnInfoPtr pScrn, PixmapPtr pPix, 1205 xf86CrtcPtr crtc, int start, int stop); 1206 1207/* radeon_crtc.c */ 1208extern void radeon_crtc_dpms(xf86CrtcPtr crtc, int mode); 1209extern void radeon_crtc_load_lut(xf86CrtcPtr crtc); 1210extern void radeon_crtc_modeset_ioctl(xf86CrtcPtr crtc, Bool post); 1211extern Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask); 1212extern void RADEONBlank(ScrnInfoPtr pScrn); 1213extern void RADEONComputePLL(xf86CrtcPtr crtc, 1214 RADEONPLLPtr pll, unsigned long freq, 1215 uint32_t *chosen_dot_clock_freq, 1216 uint32_t *chosen_feedback_div, 1217 uint32_t *chosen_frac_feedback_div, 1218 uint32_t *chosen_reference_div, 1219 uint32_t *chosen_post_div, int flags); 1220extern DisplayModePtr RADEONCrtcFindClosestMode(xf86CrtcPtr crtc, 1221 DisplayModePtr pMode); 1222extern void RADEONUnblank(ScrnInfoPtr pScrn); 1223extern Bool RADEONSetTiling(ScrnInfoPtr pScrn); 1224extern void RADEONInitDispBandwidth(ScrnInfoPtr pScrn); 1225 1226/* radeon_cursor.c */ 1227extern Bool RADEONCursorInit(ScreenPtr pScreen); 1228extern void radeon_crtc_hide_cursor(xf86CrtcPtr crtc); 1229extern void radeon_crtc_load_cursor_argb(xf86CrtcPtr crtc, CARD32 *image); 1230extern void radeon_crtc_set_cursor_colors(xf86CrtcPtr crtc, int bg, int fg); 1231extern void radeon_crtc_set_cursor_position(xf86CrtcPtr crtc, int x, int y); 1232extern void radeon_crtc_show_cursor(xf86CrtcPtr crtc); 1233 1234#ifdef XF86DRI 1235/* radeon_dri.c */ 1236extern void RADEONDRIAllocatePCIGARTTable(ScreenPtr pScreen); 1237extern void RADEONDRICloseScreen(ScreenPtr pScreen); 1238extern Bool RADEONDRIFinishScreenInit(ScreenPtr pScreen); 1239extern int RADEONDRIGetPciAperTableSize(ScrnInfoPtr pScrn); 1240extern Bool RADEONDRIGetVersion(ScrnInfoPtr pScrn); 1241extern void RADEONDRIResume(ScreenPtr pScreen); 1242extern Bool RADEONDRIScreenInit(ScreenPtr pScreen); 1243extern int RADEONDRISetParam(ScrnInfoPtr pScrn, 1244 unsigned int param, int64_t value); 1245extern Bool RADEONDRISetVBlankInterrupt(ScrnInfoPtr pScrn, Bool on); 1246extern void RADEONDRIStop(ScreenPtr pScreen); 1247#endif 1248 1249/* radeon_driver.c */ 1250extern void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool clone); 1251extern void RADEONChangeSurfaces(ScrnInfoPtr pScrn); 1252extern RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn); 1253extern int RADEONMinBits(int val); 1254extern unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr); 1255extern unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr); 1256extern unsigned RADEONINPCIE(ScrnInfoPtr pScrn, int addr); 1257extern unsigned R600INPCIE_PORT(ScrnInfoPtr pScrn, int addr); 1258extern void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, uint32_t data); 1259extern void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, uint32_t data); 1260extern void RADEONOUTPCIE(ScrnInfoPtr pScrn, int addr, uint32_t data); 1261extern void R600OUTPCIE_PORT(ScrnInfoPtr pScrn, int addr, uint32_t data); 1262extern void RADEONPllErrataAfterData(RADEONInfoPtr info); 1263extern void RADEONPllErrataAfterIndex(RADEONInfoPtr info); 1264extern void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn); 1265extern void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn); 1266extern void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, 1267 RADEONInfoPtr info); 1268extern void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, 1269 RADEONSavePtr restore); 1270extern Bool 1271RADEONZaphodStringMatches(ScrnInfoPtr pScrn, const char *s, char *output_name); 1272 1273Bool RADEONGetRec(ScrnInfoPtr pScrn); 1274void RADEONFreeRec(ScrnInfoPtr pScrn); 1275Bool RADEONPreInitVisual(ScrnInfoPtr pScrn); 1276Bool RADEONPreInitWeight(ScrnInfoPtr pScrn); 1277 1278extern Bool RADEON_DP_I2CInit(ScrnInfoPtr pScrn, I2CBusPtr *bus_ptr, 1279 char *name, xf86OutputPtr output); 1280extern void RADEON_DP_GetDPCD(xf86OutputPtr output); 1281extern int RADEON_DP_GetSinkType(xf86OutputPtr output); 1282 1283/* radeon_pm.c */ 1284extern void RADEONPMInit(ScrnInfoPtr pScrn); 1285extern void RADEONPMBlockHandler(ScrnInfoPtr pScrn); 1286extern void RADEONPMEnterVT(ScrnInfoPtr pScrn); 1287extern void RADEONPMLeaveVT(ScrnInfoPtr pScrn); 1288extern void RADEONPMFini(ScrnInfoPtr pScrn); 1289 1290#ifdef USE_EXA 1291/* radeon_exa.c */ 1292extern Bool RADEONSetupMemEXA(ScreenPtr pScreen); 1293extern Bool radeon_transform_is_affine_or_scaled(PictTransformPtr t); 1294 1295/* radeon_exa_funcs.c */ 1296extern void RADEONCopyCP(PixmapPtr pDst, int srcX, int srcY, int dstX, 1297 int dstY, int w, int h); 1298extern void RADEONCopyMMIO(PixmapPtr pDst, int srcX, int srcY, int dstX, 1299 int dstY, int w, int h); 1300extern Bool RADEONDrawInitCP(ScreenPtr pScreen); 1301extern Bool RADEONDrawInitMMIO(ScreenPtr pScreen); 1302extern void RADEONDoPrepareCopyCP(ScrnInfoPtr pScrn, 1303 uint32_t src_pitch_offset, 1304 uint32_t dst_pitch_offset, 1305 uint32_t datatype, int rop, 1306 Pixel planemask); 1307extern void RADEONDoPrepareCopyMMIO(ScrnInfoPtr pScrn, 1308 uint32_t src_pitch_offset, 1309 uint32_t dst_pitch_offset, 1310 uint32_t datatype, int rop, 1311 Pixel planemask); 1312extern Bool R600DrawInit(ScreenPtr pScreen); 1313extern Bool R600LoadShaders(ScrnInfoPtr pScrn); 1314#ifdef XF86DRM_MODE 1315extern Bool EVERGREENDrawInit(ScreenPtr pScreen); 1316extern Bool EVERGREENLoadShaders(ScrnInfoPtr pScrn); 1317#endif 1318#endif 1319 1320#if defined(XF86DRI) && defined(USE_EXA) 1321/* radeon_exa.c */ 1322extern Bool RADEONGetDatatypeBpp(int bpp, uint32_t *type); 1323extern Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, 1324 uint32_t *pitch_offset); 1325extern unsigned long long RADEONTexOffsetStart(PixmapPtr pPix); 1326#endif 1327 1328/* radeon_modes.c */ 1329extern void RADEONSetPitch(ScrnInfoPtr pScrn); 1330extern DisplayModePtr RADEONProbeOutputModes(xf86OutputPtr output); 1331 1332/* radeon_output.c */ 1333extern RADEONI2CBusRec atom_setup_i2c_bus(int ddc_line); 1334extern RADEONI2CBusRec legacy_setup_i2c_bus(int ddc_line); 1335extern void RADEONGetPanelInfo(ScrnInfoPtr pScrn); 1336extern void RADEONInitConnector(xf86OutputPtr output); 1337extern void RADEONPrintPortMap(ScrnInfoPtr pScrn); 1338extern void RADEONSetOutputType(ScrnInfoPtr pScrn, 1339 RADEONOutputPrivatePtr radeon_output); 1340extern Bool RADEONSetupConnectors(ScrnInfoPtr pScrn); 1341extern Bool RADEONI2CDoLock(xf86OutputPtr output, I2CBusPtr b, Bool lock_state); 1342 1343extern Bool radeon_dp_mode_fixup(xf86OutputPtr output, DisplayModePtr mode, DisplayModePtr adjusted_mode); 1344 1345/* radeon_tv.c */ 1346extern void RADEONSaveTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 1347extern void RADEONAdjustCrtcRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, 1348 DisplayModePtr mode, xf86OutputPtr output); 1349extern void RADEONAdjustPLLRegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, 1350 DisplayModePtr mode, xf86OutputPtr output); 1351extern void RADEONAdjustCrtc2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, 1352 DisplayModePtr mode, xf86OutputPtr output); 1353extern void RADEONAdjustPLL2RegistersForTV(ScrnInfoPtr pScrn, RADEONSavePtr save, 1354 DisplayModePtr mode, xf86OutputPtr output); 1355extern void RADEONInitTVRegisters(xf86OutputPtr output, RADEONSavePtr save, 1356 DisplayModePtr mode, BOOL IsPrimary); 1357extern void RADEONRestoreTVRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore); 1358extern void RADEONUpdateHVPosition(xf86OutputPtr output, DisplayModePtr mode); 1359 1360/* radeon_video.c */ 1361extern void RADEONInitVideo(ScreenPtr pScreen); 1362extern void RADEONResetVideo(ScrnInfoPtr pScrn); 1363extern Bool radeon_load_bicubic_texture(ScrnInfoPtr pScrn); 1364extern xf86CrtcPtr radeon_pick_best_crtc(ScrnInfoPtr pScrn, 1365 int x1, int x2, int y1, int y2); 1366 1367/* radeon_legacy_memory.c */ 1368extern uint32_t 1369radeon_legacy_allocate_memory(ScrnInfoPtr pScrn, 1370 void **mem_struct, 1371 int size, 1372 int align, 1373 int domain); 1374extern void 1375radeon_legacy_free_memory(ScrnInfoPtr pScrn, 1376 void *mem_struct); 1377 1378#ifdef XF86DRM_MODE 1379extern void radeon_cs_flush_indirect(ScrnInfoPtr pScrn); 1380extern void radeon_ddx_cs_start(ScrnInfoPtr pScrn, 1381 int num, const char *file, 1382 const char *func, int line); 1383void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, int new_fb_size); 1384#endif 1385struct radeon_bo *radeon_get_pixmap_bo(PixmapPtr pPix); 1386void radeon_set_pixmap_bo(PixmapPtr pPix, struct radeon_bo *bo); 1387 1388#ifdef XF86DRI 1389# ifdef USE_XAA 1390/* radeon_accelfuncs.c */ 1391extern void RADEONAccelInitCP(ScreenPtr pScreen, XAAInfoRecPtr a); 1392# endif 1393 1394#define RADEONCP_START(pScrn, info) \ 1395do { \ 1396 int _ret = drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_START); \ 1397 if (_ret) { \ 1398 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1399 "%s: CP start %d\n", __FUNCTION__, _ret); \ 1400 } \ 1401 info->cp->CPStarted = TRUE; \ 1402} while (0) 1403 1404#define RADEONCP_RELEASE(pScrn, info) \ 1405do { \ 1406 if (info->cs) { \ 1407 radeon_cs_flush_indirect(pScrn); \ 1408 } else if (info->cp->CPInUse) { \ 1409 RADEON_PURGE_CACHE(); \ 1410 RADEON_WAIT_UNTIL_IDLE(); \ 1411 RADEONCPReleaseIndirect(pScrn); \ 1412 info->cp->CPInUse = FALSE; \ 1413 } \ 1414} while (0) 1415 1416#define RADEONCP_STOP(pScrn, info) \ 1417do { \ 1418 int _ret; \ 1419 if (info->cp->CPStarted) { \ 1420 _ret = RADEONCPStop(pScrn, info); \ 1421 if (_ret) { \ 1422 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1423 "%s: CP stop %d\n", __FUNCTION__, _ret); \ 1424 } \ 1425 info->cp->CPStarted = FALSE; \ 1426 } \ 1427 if (info->ChipFamily < CHIP_FAMILY_R600) \ 1428 RADEONEngineRestore(pScrn); \ 1429 info->cp->CPRuns = FALSE; \ 1430} while (0) 1431 1432#define RADEONCP_RESET(pScrn, info) \ 1433do { \ 1434 int _ret = drmCommandNone(info->dri->drmFD, DRM_RADEON_CP_RESET); \ 1435 if (_ret) { \ 1436 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1437 "%s: CP reset %d\n", __FUNCTION__, _ret); \ 1438 } \ 1439} while (0) 1440 1441#define RADEONCP_REFRESH(pScrn, info) \ 1442do { \ 1443 if (!info->cp->CPInUse && !info->cs) { \ 1444 if (info->cp->needCacheFlush) { \ 1445 RADEON_PURGE_CACHE(); \ 1446 RADEON_PURGE_ZCACHE(); \ 1447 info->cp->needCacheFlush = FALSE; \ 1448 } \ 1449 RADEON_WAIT_UNTIL_IDLE(); \ 1450 info->cp->CPInUse = TRUE; \ 1451 } \ 1452} while (0) 1453 1454 1455#define CP_PACKET0(reg, n) \ 1456 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2)) 1457#define CP_PACKET1(reg0, reg1) \ 1458 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 11) | ((reg0) >> 2)) 1459#define CP_PACKET2() \ 1460 (RADEON_CP_PACKET2) 1461#define CP_PACKET3(pkt, n) \ 1462 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16)) 1463 1464 1465#define RADEON_VERBOSE 0 1466 1467#define RING_LOCALS uint32_t *__head = NULL; int __expected; int __count = 0 1468 1469#define BEGIN_RING(n) do { \ 1470 if (RADEON_VERBOSE) { \ 1471 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ 1472 "BEGIN_RING(%d) in %s\n", (unsigned int)n, __FUNCTION__);\ 1473 } \ 1474 if (info->cs) { radeon_ddx_cs_start(pScrn, n, __FILE__, __func__, __LINE__); } else { \ 1475 if (++info->cp->dma_begin_count != 1) { \ 1476 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1477 "BEGIN_RING without end at %s:%d\n", \ 1478 info->cp->dma_debug_func, info->cp->dma_debug_lineno); \ 1479 info->cp->dma_begin_count = 1; \ 1480 } \ 1481 info->cp->dma_debug_func = __FILE__; \ 1482 info->cp->dma_debug_lineno = __LINE__; \ 1483 if (!info->cp->indirectBuffer) { \ 1484 info->cp->indirectBuffer = RADEONCPGetBuffer(pScrn); \ 1485 info->cp->indirectStart = 0; \ 1486 } else if (info->cp->indirectBuffer->used + (n) * (int)sizeof(uint32_t) > \ 1487 info->cp->indirectBuffer->total) { \ 1488 RADEONCPFlushIndirect(pScrn, 1); \ 1489 } \ 1490 __expected = n; \ 1491 __head = (pointer)((char *)info->cp->indirectBuffer->address + \ 1492 info->cp->indirectBuffer->used); \ 1493 __count = 0; \ 1494 } \ 1495} while (0) 1496 1497#define ADVANCE_RING() do { \ 1498 if (info->cs) radeon_cs_end(info->cs, __FILE__, __func__, __LINE__); else { \ 1499 if (info->cp->dma_begin_count-- != 1) { \ 1500 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1501 "ADVANCE_RING without begin at %s:%d\n", \ 1502 __FILE__, __LINE__); \ 1503 info->cp->dma_begin_count = 0; \ 1504 } \ 1505 if (__count != __expected) { \ 1506 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, \ 1507 "ADVANCE_RING count != expected (%d vs %d) at %s:%d\n", \ 1508 __count, __expected, __FILE__, __LINE__); \ 1509 } \ 1510 if (RADEON_VERBOSE) { \ 1511 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ 1512 "ADVANCE_RING() start: %d used: %d count: %d\n", \ 1513 info->cp->indirectStart, \ 1514 info->cp->indirectBuffer->used, \ 1515 __count * (int)sizeof(uint32_t)); \ 1516 } \ 1517 info->cp->indirectBuffer->used += __count * (int)sizeof(uint32_t); \ 1518 } \ 1519 } while (0) 1520 1521#define OUT_RING(x) do { \ 1522 if (RADEON_VERBOSE) { \ 1523 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ 1524 " OUT_RING(0x%08x)\n", (unsigned int)(x)); \ 1525 } \ 1526 if (info->cs) radeon_cs_write_dword(info->cs, (x)); else \ 1527 __head[__count++] = (x); \ 1528} while (0) 1529 1530#define OUT_RING_REG(reg, val) \ 1531do { \ 1532 OUT_RING(CP_PACKET0(reg, 0)); \ 1533 OUT_RING(val); \ 1534} while (0) 1535 1536#define OUT_RING_RELOC(x, read_domains, write_domain) \ 1537 do { \ 1538 int _ret; \ 1539 _ret = radeon_cs_write_reloc(info->cs, x, read_domains, write_domain, 0); \ 1540 if (_ret) ErrorF("reloc emit failure %d\n", _ret); \ 1541 } while(0) 1542 1543 1544#define FLUSH_RING() \ 1545do { \ 1546 if (RADEON_VERBOSE) \ 1547 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ 1548 "FLUSH_RING in %s\n", __FUNCTION__); \ 1549 if (info->cs) \ 1550 radeon_cs_flush_indirect(pScrn); \ 1551 else if (info->cp->indirectBuffer) \ 1552 RADEONCPFlushIndirect(pScrn, 0); \ 1553} while (0) 1554 1555 1556#define RADEON_WAIT_UNTIL_2D_IDLE() \ 1557do { \ 1558 if (info->ChipFamily < CHIP_FAMILY_R600) { \ 1559 BEGIN_RING(2); \ 1560 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \ 1561 OUT_RING((RADEON_WAIT_2D_IDLECLEAN | \ 1562 RADEON_WAIT_HOST_IDLECLEAN)); \ 1563 ADVANCE_RING(); \ 1564 } \ 1565} while (0) 1566 1567#define RADEON_WAIT_UNTIL_3D_IDLE() \ 1568do { \ 1569 if (info->ChipFamily < CHIP_FAMILY_R600) { \ 1570 BEGIN_RING(2); \ 1571 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \ 1572 OUT_RING((RADEON_WAIT_3D_IDLECLEAN | \ 1573 RADEON_WAIT_HOST_IDLECLEAN)); \ 1574 ADVANCE_RING(); \ 1575 } \ 1576} while (0) 1577 1578#define RADEON_WAIT_UNTIL_IDLE() \ 1579do { \ 1580 if (RADEON_VERBOSE) { \ 1581 xf86DrvMsg(pScrn->scrnIndex, X_INFO, \ 1582 "WAIT_UNTIL_IDLE() in %s\n", __FUNCTION__); \ 1583 } \ 1584 if (info->ChipFamily < CHIP_FAMILY_R600) { \ 1585 BEGIN_RING(2); \ 1586 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0)); \ 1587 OUT_RING((RADEON_WAIT_2D_IDLECLEAN | \ 1588 RADEON_WAIT_3D_IDLECLEAN | \ 1589 RADEON_WAIT_HOST_IDLECLEAN)); \ 1590 ADVANCE_RING(); \ 1591 } \ 1592} while (0) 1593 1594#define RADEON_PURGE_CACHE() \ 1595do { \ 1596 if (info->ChipFamily < CHIP_FAMILY_R600) { \ 1597 BEGIN_RING(2); \ 1598 if (info->ChipFamily <= CHIP_FAMILY_RV280) { \ 1599 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1600 OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \ 1601 } else { \ 1602 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \ 1603 OUT_RING(R300_RB3D_DC_FLUSH_ALL); \ 1604 } \ 1605 ADVANCE_RING(); \ 1606 } \ 1607} while (0) 1608 1609#define RADEON_PURGE_ZCACHE() \ 1610do { \ 1611 if (info->ChipFamily < CHIP_FAMILY_R600) { \ 1612 BEGIN_RING(2); \ 1613 if (info->ChipFamily <= CHIP_FAMILY_RV280) { \ 1614 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \ 1615 OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL); \ 1616 } else { \ 1617 OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); \ 1618 OUT_RING(R300_ZC_FLUSH_ALL); \ 1619 } \ 1620 ADVANCE_RING(); \ 1621 } \ 1622} while (0) 1623 1624#endif /* XF86DRI */ 1625 1626#if defined(XF86DRI) && defined(USE_EXA) 1627 1628#ifdef XF86DRM_MODE 1629#define CS_FULL(cs) ((cs)->cdw > 15 * 1024) 1630#else 1631#define CS_FULL(cs) FALSE 1632#endif 1633 1634#define RADEON_SWITCH_TO_2D() \ 1635do { \ 1636 uint32_t flush = 0; \ 1637 switch (info->accel_state->engineMode) { \ 1638 case EXA_ENGINEMODE_UNKNOWN: \ 1639 flush = 1; \ 1640 break; \ 1641 case EXA_ENGINEMODE_3D: \ 1642 flush = !info->cs || CS_FULL(info->cs); \ 1643 break; \ 1644 case EXA_ENGINEMODE_2D: \ 1645 flush = info->cs && CS_FULL(info->cs); \ 1646 break; \ 1647 } \ 1648 if (flush) { \ 1649 if (info->cs) \ 1650 radeon_cs_flush_indirect(pScrn); \ 1651 else if (info->directRenderingEnabled) \ 1652 RADEONCPFlushIndirect(pScrn, 1); \ 1653 } \ 1654 info->accel_state->engineMode = EXA_ENGINEMODE_2D; \ 1655} while (0); 1656 1657#define RADEON_SWITCH_TO_3D() \ 1658do { \ 1659 uint32_t flush = 0; \ 1660 switch (info->accel_state->engineMode) { \ 1661 case EXA_ENGINEMODE_UNKNOWN: \ 1662 flush = 1; \ 1663 break; \ 1664 case EXA_ENGINEMODE_2D: \ 1665 flush = !info->cs || CS_FULL(info->cs); \ 1666 break; \ 1667 case EXA_ENGINEMODE_3D: \ 1668 flush = info->cs && CS_FULL(info->cs); \ 1669 break; \ 1670 } \ 1671 if (flush) { \ 1672 if (info->cs) \ 1673 radeon_cs_flush_indirect(pScrn); \ 1674 else if (info->directRenderingEnabled) \ 1675 RADEONCPFlushIndirect(pScrn, 1); \ 1676 } \ 1677 if (!info->accel_state->XInited3D) \ 1678 RADEONInit3DEngine(pScrn); \ 1679 info->accel_state->engineMode = EXA_ENGINEMODE_3D; \ 1680} while (0); 1681#else 1682#define RADEON_SWITCH_TO_2D() 1683#define RADEON_SWITCH_TO_3D() 1684#endif 1685 1686static __inline__ void RADEON_MARK_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn) 1687{ 1688#ifdef USE_EXA 1689 if (info->useEXA) 1690 exaMarkSync(pScrn->pScreen); 1691#endif 1692#ifdef USE_XAA 1693 if (!info->useEXA) 1694 SET_SYNC_FLAG(info->accel_state->accel); 1695#endif 1696} 1697 1698static __inline__ void RADEON_SYNC(RADEONInfoPtr info, ScrnInfoPtr pScrn) 1699{ 1700#ifdef USE_EXA 1701 if (info->useEXA && pScrn->pScreen) 1702 exaWaitSync(pScrn->pScreen); 1703#endif 1704#ifdef USE_XAA 1705 if (!info->useEXA && info->accel_state->accel) 1706 info->accel_state->accel->Sync(pScrn); 1707#endif 1708} 1709 1710static __inline__ void radeon_init_timeout(struct timeval *endtime, 1711 unsigned int timeout) 1712{ 1713 gettimeofday(endtime, NULL); 1714 endtime->tv_usec += timeout; 1715 endtime->tv_sec += endtime->tv_usec / 1000000; 1716 endtime->tv_usec %= 1000000; 1717} 1718 1719static __inline__ int radeon_timedout(const struct timeval *endtime) 1720{ 1721 struct timeval now; 1722 gettimeofday(&now, NULL); 1723 return now.tv_sec == endtime->tv_sec ? 1724 now.tv_usec > endtime->tv_usec : now.tv_sec > endtime->tv_sec; 1725} 1726 1727enum { 1728 RADEON_CREATE_PIXMAP_TILING_MACRO = 0x10000000, 1729 RADEON_CREATE_PIXMAP_TILING_MICRO = 0x20000000, 1730}; 1731 1732#endif /* _RADEON_H_ */ 1733