1209ff23fSmrg/*
2209ff23fSmrg * Copyright 2000 ATI Technologies Inc., Markham, Ontario,
3209ff23fSmrg *                VA Linux Systems Inc., Fremont, California.
4209ff23fSmrg *
5209ff23fSmrg * All Rights Reserved.
6209ff23fSmrg *
7209ff23fSmrg * Permission is hereby granted, free of charge, to any person obtaining
8209ff23fSmrg * a copy of this software and associated documentation files (the
9209ff23fSmrg * "Software"), to deal in the Software without restriction, including
10209ff23fSmrg * without limitation on the rights to use, copy, modify, merge,
11209ff23fSmrg * publish, distribute, sublicense, and/or sell copies of the Software,
12209ff23fSmrg * and to permit persons to whom the Software is furnished to do so,
13209ff23fSmrg * subject to the following conditions:
14209ff23fSmrg *
15209ff23fSmrg * The above copyright notice and this permission notice (including the
16209ff23fSmrg * next paragraph) shall be included in all copies or substantial
17209ff23fSmrg * portions of the Software.
18209ff23fSmrg *
19209ff23fSmrg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20209ff23fSmrg * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21209ff23fSmrg * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
22209ff23fSmrg * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
23209ff23fSmrg * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
24209ff23fSmrg * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25209ff23fSmrg * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26209ff23fSmrg * DEALINGS IN THE SOFTWARE.
27209ff23fSmrg */
28209ff23fSmrg
29209ff23fSmrg/*
30209ff23fSmrg * Authors:
31209ff23fSmrg *   Kevin E. Martin <martin@xfree86.org>
32209ff23fSmrg *   Rickard E. Faith <faith@valinux.com>
33209ff23fSmrg *
34209ff23fSmrg */
35209ff23fSmrg
36209ff23fSmrg#ifndef _RADEON_DRI_
37209ff23fSmrg#define _RADEON_DRI_
38209ff23fSmrg
39209ff23fSmrg#include "xf86drm.h"
40209ff23fSmrg
41209ff23fSmrg/* DRI Driver defaults */
42209ff23fSmrg#define RADEON_DEFAULT_GART_SIZE      8 /* MB (must be 2^n and > 4MB) */
43b7e1c893Smrg#define R300_DEFAULT_GART_SIZE        32 /* MB (for R300 and above) */
44209ff23fSmrg#define RADEON_DEFAULT_RING_SIZE      1 /* MB (must be page aligned) */
45209ff23fSmrg#define RADEON_DEFAULT_BUFFER_SIZE    2 /* MB (must be page aligned) */
46209ff23fSmrg#define RADEON_DEFAULT_GART_TEX_SIZE  1 /* MB (must be page aligned) */
47209ff23fSmrg
48209ff23fSmrg#define RADEON_DEFAULT_CP_TIMEOUT     100000  /* usecs */
49209ff23fSmrg
50209ff23fSmrg#define RADEON_DEFAULT_PCI_APER_SIZE 32 /* in MB */
51209ff23fSmrg
52209ff23fSmrg#define RADEON_CARD_TYPE_RADEON       1
53209ff23fSmrg
54209ff23fSmrgtypedef struct {
55209ff23fSmrg    /* DRI screen private data */
56209ff23fSmrg    int           deviceID;	/* PCI device ID */
57209ff23fSmrg    int           width;	/* Width in pixels of display */
58209ff23fSmrg    int           height;	/* Height in scanlines of display */
59209ff23fSmrg    int           depth;	/* Depth of display (8, 15, 16, 24) */
60209ff23fSmrg    int           bpp;		/* Bit depth of display (8, 16, 24, 32) */
61209ff23fSmrg
62209ff23fSmrg    int           IsPCI;	/* Current card is a PCI card */
63209ff23fSmrg    int           AGPMode;
64209ff23fSmrg
65209ff23fSmrg    int           frontOffset;  /* Start of front buffer */
66209ff23fSmrg    int           frontPitch;
67209ff23fSmrg    int           backOffset;   /* Start of shared back buffer */
68209ff23fSmrg    int           backPitch;
69209ff23fSmrg    int           depthOffset;  /* Start of shared depth buffer */
70209ff23fSmrg    int           depthPitch;
71209ff23fSmrg    int           textureOffset;/* Start of texture data in frame buffer */
72209ff23fSmrg    int           textureSize;
73209ff23fSmrg    int           log2TexGran;
74209ff23fSmrg
75209ff23fSmrg    /* MMIO register data */
76209ff23fSmrg    drm_handle_t     registerHandle;
77209ff23fSmrg    drmSize       registerSize;
78209ff23fSmrg
79209ff23fSmrg    /* CP in-memory status information */
80209ff23fSmrg    drm_handle_t     statusHandle;
81209ff23fSmrg    drmSize       statusSize;
82209ff23fSmrg
83209ff23fSmrg    /* CP GART Texture data */
84209ff23fSmrg    drm_handle_t     gartTexHandle;
85209ff23fSmrg    drmSize       gartTexMapSize;
86209ff23fSmrg    int           log2GARTTexGran;
87209ff23fSmrg    int           gartTexOffset;
88209ff23fSmrg    unsigned int  sarea_priv_offset;
89209ff23fSmrg} RADEONDRIRec, *RADEONDRIPtr;
90209ff23fSmrg
91209ff23fSmrg#endif
92