radeon_driver.c revision c8eabe9c
1/* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining 8 * a copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation on the rights to use, copy, modify, merge, 11 * publish, distribute, sublicense, and/or sell copies of the Software, 12 * and to permit persons to whom the Software is furnished to do so, 13 * subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 */ 28 29#ifdef HAVE_CONFIG_H 30#include "config.h" 31#endif 32 33/* 34 * Authors: 35 * Kevin E. Martin <martin@xfree86.org> 36 * Rickard E. Faith <faith@valinux.com> 37 * Alan Hourihane <alanh@fairlite.demon.co.uk> 38 * 39 * Credits: 40 * 41 * Thanks to Ani Joshi <ajoshi@shell.unixbox.com> for providing source 42 * code to his Radeon driver. Portions of this file are based on the 43 * initialization code for that driver. 44 * 45 * References: 46 * 47 * !!!! FIXME !!!! 48 * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical 49 * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April 50 * 1999. 51 * 52 * RAGE 128 Software Development Manual (Technical Reference Manual P/N 53 * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. 54 * 55 * This server does not yet support these XFree86 4.0 features: 56 * !!!! FIXME !!!! 57 * DDC1 & DDC2 58 * shadowfb 59 * overlay planes 60 * 61 * Modified by Marc Aurele La France (tsi@xfree86.org) for ATI driver merge. 62 * 63 * Mergedfb and pseudo xinerama support added by Alex Deucher (agd5f@yahoo.com) 64 * based on the sis driver by Thomas Winischhofer. 65 * 66 */ 67 68#include <string.h> 69#include <stdio.h> 70 71 /* Driver data structures */ 72#include "radeon.h" 73#include "radeon_reg.h" 74#include "radeon_macros.h" 75#include "radeon_probe.h" 76#include "radeon_version.h" 77#include "radeon_atombios.h" 78 79#ifdef XF86DRI 80#define _XF86DRI_SERVER_ 81#include "radeon_dri.h" 82#include "radeon_drm.h" 83#include "sarea.h" 84#endif 85 86#include "fb.h" 87 88 /* colormap initialization */ 89#include "micmap.h" 90#include "dixstruct.h" 91 92 /* X and server generic header files */ 93#include "xf86.h" 94#include "xf86_OSproc.h" 95#include "xf86RAC.h" 96#include "xf86RandR12.h" 97#include "xf86Resources.h" 98#include "xf86cmap.h" 99#include "vbe.h" 100 101#include "shadow.h" 102 /* vgaHW definitions */ 103#ifdef WITH_VGAHW 104#include "vgaHW.h" 105#endif 106 107#define DPMS_SERVER 108#include <X11/extensions/dpms.h> 109 110#include "atipciids.h" 111#include "radeon_chipset_gen.h" 112 113 114#include "radeon_chipinfo_gen.h" 115 116 /* Forward definitions for driver functions */ 117static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen); 118static Bool RADEONSaveScreen(ScreenPtr pScreen, int mode); 119static void RADEONSave(ScrnInfoPtr pScrn); 120 121static void RADEONSetDynamicClock(ScrnInfoPtr pScrn, int mode); 122static void RADEONForceSomeClocks(ScrnInfoPtr pScrn); 123static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 124 125static void 126RADEONSaveBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 127 128#ifdef XF86DRI 129static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 130#endif 131 132static const OptionInfoRec RADEONOptions[] = { 133 { OPTION_NOACCEL, "NoAccel", OPTV_BOOLEAN, {0}, FALSE }, 134 { OPTION_SW_CURSOR, "SWcursor", OPTV_BOOLEAN, {0}, FALSE }, 135 { OPTION_DAC_6BIT, "Dac6Bit", OPTV_BOOLEAN, {0}, FALSE }, 136 { OPTION_DAC_8BIT, "Dac8Bit", OPTV_BOOLEAN, {0}, TRUE }, 137#ifdef XF86DRI 138 { OPTION_BUS_TYPE, "BusType", OPTV_ANYSTR, {0}, FALSE }, 139 { OPTION_CP_PIO, "CPPIOMode", OPTV_BOOLEAN, {0}, FALSE }, 140 { OPTION_USEC_TIMEOUT, "CPusecTimeout", OPTV_INTEGER, {0}, FALSE }, 141 { OPTION_AGP_MODE, "AGPMode", OPTV_INTEGER, {0}, FALSE }, 142 { OPTION_AGP_FW, "AGPFastWrite", OPTV_BOOLEAN, {0}, FALSE }, 143 { OPTION_GART_SIZE_OLD, "AGPSize", OPTV_INTEGER, {0}, FALSE }, 144 { OPTION_GART_SIZE, "GARTSize", OPTV_INTEGER, {0}, FALSE }, 145 { OPTION_RING_SIZE, "RingSize", OPTV_INTEGER, {0}, FALSE }, 146 { OPTION_BUFFER_SIZE, "BufferSize", OPTV_INTEGER, {0}, FALSE }, 147 { OPTION_DEPTH_MOVE, "EnableDepthMoves", OPTV_BOOLEAN, {0}, FALSE }, 148 { OPTION_PAGE_FLIP, "EnablePageFlip", OPTV_BOOLEAN, {0}, FALSE }, 149 { OPTION_NO_BACKBUFFER, "NoBackBuffer", OPTV_BOOLEAN, {0}, FALSE }, 150 { OPTION_XV_DMA, "DMAForXv", OPTV_BOOLEAN, {0}, FALSE }, 151 { OPTION_FBTEX_PERCENT, "FBTexPercent", OPTV_INTEGER, {0}, FALSE }, 152 { OPTION_DEPTH_BITS, "DepthBits", OPTV_INTEGER, {0}, FALSE }, 153 { OPTION_PCIAPER_SIZE, "PCIAPERSize", OPTV_INTEGER, {0}, FALSE }, 154#ifdef USE_EXA 155 { OPTION_ACCEL_DFS, "AccelDFS", OPTV_BOOLEAN, {0}, FALSE }, 156#endif 157#endif 158 { OPTION_IGNORE_EDID, "IgnoreEDID", OPTV_BOOLEAN, {0}, FALSE }, 159 { OPTION_DISP_PRIORITY, "DisplayPriority", OPTV_ANYSTR, {0}, FALSE }, 160 { OPTION_PANEL_SIZE, "PanelSize", OPTV_ANYSTR, {0}, FALSE }, 161 { OPTION_MIN_DOTCLOCK, "ForceMinDotClock", OPTV_FREQ, {0}, FALSE }, 162 { OPTION_COLOR_TILING, "ColorTiling", OPTV_BOOLEAN, {0}, FALSE }, 163#ifdef XvExtension 164 { OPTION_VIDEO_KEY, "VideoKey", OPTV_INTEGER, {0}, FALSE }, 165 { OPTION_RAGE_THEATRE_CRYSTAL, "RageTheatreCrystal", OPTV_INTEGER, {0}, FALSE }, 166 { OPTION_RAGE_THEATRE_TUNER_PORT, "RageTheatreTunerPort", OPTV_INTEGER, {0}, FALSE }, 167 { OPTION_RAGE_THEATRE_COMPOSITE_PORT, "RageTheatreCompositePort", OPTV_INTEGER, {0}, FALSE }, 168 { OPTION_RAGE_THEATRE_SVIDEO_PORT, "RageTheatreSVideoPort", OPTV_INTEGER, {0}, FALSE }, 169 { OPTION_TUNER_TYPE, "TunerType", OPTV_INTEGER, {0}, FALSE }, 170 { OPTION_RAGE_THEATRE_MICROC_PATH, "RageTheatreMicrocPath", OPTV_STRING, {0}, FALSE }, 171 { OPTION_RAGE_THEATRE_MICROC_TYPE, "RageTheatreMicrocType", OPTV_STRING, {0}, FALSE }, 172 { OPTION_SCALER_WIDTH, "ScalerWidth", OPTV_INTEGER, {0}, FALSE }, 173#endif 174#ifdef RENDER 175 { OPTION_RENDER_ACCEL, "RenderAccel", OPTV_BOOLEAN, {0}, FALSE }, 176 { OPTION_SUBPIXEL_ORDER, "SubPixelOrder", OPTV_ANYSTR, {0}, FALSE }, 177#endif 178 { OPTION_SHOWCACHE, "ShowCache", OPTV_BOOLEAN, {0}, FALSE }, 179 { OPTION_DYNAMIC_CLOCKS, "DynamicClocks", OPTV_BOOLEAN, {0}, FALSE }, 180 { OPTION_VGA_ACCESS, "VGAAccess", OPTV_BOOLEAN, {0}, TRUE }, 181 { OPTION_REVERSE_DDC, "ReverseDDC", OPTV_BOOLEAN, {0}, FALSE }, 182 { OPTION_LVDS_PROBE_PLL, "LVDSProbePLL", OPTV_BOOLEAN, {0}, FALSE }, 183 { OPTION_ACCELMETHOD, "AccelMethod", OPTV_STRING, {0}, FALSE }, 184 { OPTION_DRI, "DRI", OPTV_BOOLEAN, {0}, FALSE }, 185 { OPTION_CONNECTORTABLE, "ConnectorTable", OPTV_STRING, {0}, FALSE }, 186 { OPTION_DEFAULT_CONNECTOR_TABLE, "DefaultConnectorTable", OPTV_BOOLEAN, {0}, FALSE }, 187 { OPTION_DEFAULT_TMDS_PLL, "DefaultTMDSPLL", OPTV_BOOLEAN, {0}, FALSE }, 188#if defined(__powerpc__) 189 { OPTION_MAC_MODEL, "MacModel", OPTV_STRING, {0}, FALSE }, 190#endif 191 { OPTION_TVDAC_LOAD_DETECT, "TVDACLoadDetect", OPTV_BOOLEAN, {0}, FALSE }, 192 { OPTION_FORCE_TVOUT, "ForceTVOut", OPTV_BOOLEAN, {0}, FALSE }, 193 { OPTION_TVSTD, "TVStandard", OPTV_STRING, {0}, FALSE }, 194 { OPTION_IGNORE_LID_STATUS, "IgnoreLidStatus", OPTV_BOOLEAN, {0}, FALSE }, 195 { OPTION_DEFAULT_TVDAC_ADJ, "DefaultTVDACAdj", OPTV_BOOLEAN, {0}, FALSE }, 196 { OPTION_INT10, "Int10", OPTV_BOOLEAN, {0}, FALSE }, 197 { OPTION_EXA_VSYNC, "EXAVSync", OPTV_BOOLEAN, {0}, FALSE }, 198 { OPTION_ATOM_TVOUT, "ATOMTVOut", OPTV_BOOLEAN, {0}, FALSE }, 199 { OPTION_R4XX_ATOM, "R4xxATOM", OPTV_BOOLEAN, {0}, FALSE }, 200 { -1, NULL, OPTV_NONE, {0}, FALSE } 201}; 202 203const OptionInfoRec *RADEONOptionsWeak(void) { return RADEONOptions; } 204 205extern _X_EXPORT int gRADEONEntityIndex; 206 207static int getRADEONEntityIndex(void) 208{ 209 return gRADEONEntityIndex; 210} 211 212struct RADEONInt10Save { 213 uint32_t MEM_CNTL; 214 uint32_t MEMSIZE; 215 uint32_t MPP_TB_CONFIG; 216}; 217 218static Bool RADEONMapMMIO(ScrnInfoPtr pScrn); 219static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn); 220 221static void * 222radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode, 223 CARD32 *size, void *closure) 224{ 225 ScrnInfoPtr pScrn = xf86Screens[screen->myNum]; 226 RADEONInfoPtr info = RADEONPTR(pScrn); 227 int stride; 228 229 stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8; 230 *size = stride; 231 232 return ((uint8_t *)info->FB + row * stride + offset); 233} 234static Bool 235RADEONCreateScreenResources (ScreenPtr pScreen) 236{ 237 ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; 238 RADEONInfoPtr info = RADEONPTR(pScrn); 239 PixmapPtr pixmap; 240 241 pScreen->CreateScreenResources = info->CreateScreenResources; 242 if (!(*pScreen->CreateScreenResources)(pScreen)) 243 return FALSE; 244 pScreen->CreateScreenResources = RADEONCreateScreenResources; 245 246 if (info->r600_shadow_fb) { 247 pixmap = pScreen->GetScreenPixmap(pScreen); 248 249 if (!shadowAdd(pScreen, pixmap, shadowUpdatePackedWeak(), 250 radeonShadowWindow, 0, NULL)) 251 return FALSE; 252 } 253 return TRUE; 254} 255 256RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn) 257{ 258 DevUnion *pPriv; 259 RADEONInfoPtr info = RADEONPTR(pScrn); 260 pPriv = xf86GetEntityPrivate(info->pEnt->index, 261 getRADEONEntityIndex()); 262 return pPriv->ptr; 263} 264 265static void 266RADEONPreInt10Save(ScrnInfoPtr pScrn, void **pPtr) 267{ 268 RADEONInfoPtr info = RADEONPTR(pScrn); 269 unsigned char *RADEONMMIO = info->MMIO; 270 uint32_t CardTmp; 271 static struct RADEONInt10Save SaveStruct = { 0, 0, 0 }; 272 273 if (!IS_AVIVO_VARIANT) { 274 /* Save the values and zap MEM_CNTL */ 275 SaveStruct.MEM_CNTL = INREG(RADEON_MEM_CNTL); 276 SaveStruct.MEMSIZE = INREG(RADEON_CONFIG_MEMSIZE); 277 SaveStruct.MPP_TB_CONFIG = INREG(RADEON_MPP_TB_CONFIG); 278 279 /* 280 * Zap MEM_CNTL and set MPP_TB_CONFIG<31:24> to 4 281 */ 282 OUTREG(RADEON_MEM_CNTL, 0); 283 CardTmp = SaveStruct.MPP_TB_CONFIG & 0x00ffffffu; 284 CardTmp |= 0x04 << 24; 285 OUTREG(RADEON_MPP_TB_CONFIG, CardTmp); 286 } 287 288 *pPtr = (void *)&SaveStruct; 289} 290 291static void 292RADEONPostInt10Check(ScrnInfoPtr pScrn, void *ptr) 293{ 294 RADEONInfoPtr info = RADEONPTR(pScrn); 295 unsigned char *RADEONMMIO = info->MMIO; 296 struct RADEONInt10Save *pSave = ptr; 297 uint32_t CardTmp; 298 299 /* If we don't have a valid (non-zero) saved MEM_CNTL, get out now */ 300 if (!pSave || !pSave->MEM_CNTL) 301 return; 302 303 if (IS_AVIVO_VARIANT) 304 return; 305 306 /* 307 * If either MEM_CNTL is currently zero or inconistent (configured for 308 * two channels with the two channels configured differently), restore 309 * the saved registers. 310 */ 311 CardTmp = INREG(RADEON_MEM_CNTL); 312 if (!CardTmp || 313 ((CardTmp & 1) && 314 (((CardTmp >> 8) & 0xff) != ((CardTmp >> 24) & 0xff)))) { 315 /* Restore the saved registers */ 316 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 317 "Restoring MEM_CNTL (%08lx), setting to %08lx\n", 318 (unsigned long)CardTmp, (unsigned long)pSave->MEM_CNTL); 319 OUTREG(RADEON_MEM_CNTL, pSave->MEM_CNTL); 320 321 CardTmp = INREG(RADEON_CONFIG_MEMSIZE); 322 if (CardTmp != pSave->MEMSIZE) { 323 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 324 "Restoring CONFIG_MEMSIZE (%08lx), setting to %08lx\n", 325 (unsigned long)CardTmp, (unsigned long)pSave->MEMSIZE); 326 OUTREG(RADEON_CONFIG_MEMSIZE, pSave->MEMSIZE); 327 } 328 } 329 330 CardTmp = INREG(RADEON_MPP_TB_CONFIG); 331 if ((CardTmp & 0xff000000u) != (pSave->MPP_TB_CONFIG & 0xff000000u)) { 332 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 333 "Restoring MPP_TB_CONFIG<31:24> (%02lx), setting to %02lx\n", 334 (unsigned long)CardTmp >> 24, 335 (unsigned long)pSave->MPP_TB_CONFIG >> 24); 336 CardTmp &= 0x00ffffffu; 337 CardTmp |= (pSave->MPP_TB_CONFIG & 0xff000000u); 338 OUTREG(RADEON_MPP_TB_CONFIG, CardTmp); 339 } 340} 341 342/* Allocate our private RADEONInfoRec */ 343static Bool RADEONGetRec(ScrnInfoPtr pScrn) 344{ 345 if (pScrn->driverPrivate) return TRUE; 346 347 pScrn->driverPrivate = xnfcalloc(sizeof(RADEONInfoRec), 1); 348 return TRUE; 349} 350 351/* Free our private RADEONInfoRec */ 352static void RADEONFreeRec(ScrnInfoPtr pScrn) 353{ 354 RADEONInfoPtr info; 355 int i; 356 357 if (!pScrn || !pScrn->driverPrivate) return; 358 359 info = RADEONPTR(pScrn); 360 361 if (info->cp) { 362 xfree(info->cp); 363 info->cp = NULL; 364 } 365 366 if (info->dri) { 367 xfree(info->dri); 368 info->dri = NULL; 369 } 370 371 if (info->accel_state) { 372 xfree(info->accel_state); 373 info->accel_state = NULL; 374 } 375 376 for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) { 377 if (info->encoders[i]) { 378 if (info->encoders[i]->dev_priv) { 379 xfree(info->encoders[i]->dev_priv); 380 info->encoders[i]->dev_priv = NULL; 381 } 382 xfree(info->encoders[i]); 383 info->encoders[i]= NULL; 384 } 385 } 386 387 xfree(pScrn->driverPrivate); 388 pScrn->driverPrivate = NULL; 389} 390 391/* Memory map the MMIO region. Used during pre-init and by RADEONMapMem, 392 * below 393 */ 394static Bool RADEONMapMMIO(ScrnInfoPtr pScrn) 395{ 396 RADEONInfoPtr info = RADEONPTR(pScrn); 397 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 398 399 if (pRADEONEnt->MMIO) { 400 info->MMIO = pRADEONEnt->MMIO; 401 return TRUE; 402 } 403 404#ifndef XSERVER_LIBPCIACCESS 405 406 info->MMIO = xf86MapPciMem(pScrn->scrnIndex, 407 VIDMEM_MMIO | VIDMEM_READSIDEEFFECT, 408 info->PciTag, 409 info->MMIOAddr, 410 info->MMIOSize); 411 412 if (!info->MMIO) return FALSE; 413#else 414 415 void** result = (void**)&info->MMIO; 416 int err = pci_device_map_range(info->PciInfo, 417 info->MMIOAddr, 418 info->MMIOSize, 419 PCI_DEV_MAP_FLAG_WRITABLE, 420 result); 421 422 if (err) { 423 xf86DrvMsg (pScrn->scrnIndex, X_ERROR, 424 "Unable to map MMIO aperture. %s (%d)\n", 425 strerror (err), err); 426 return FALSE; 427 } 428 429#endif 430 431 pRADEONEnt->MMIO = info->MMIO; 432 return TRUE; 433} 434 435/* Unmap the MMIO region. Used during pre-init and by RADEONUnmapMem, 436 * below 437 */ 438static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn) 439{ 440 RADEONInfoPtr info = RADEONPTR(pScrn); 441 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 442 443 if (info->IsPrimary || info->IsSecondary) { 444 /* never unmap on zaphod */ 445 info->MMIO = NULL; 446 return TRUE; 447 } 448 449#ifndef XSERVER_LIBPCIACCESS 450 xf86UnMapVidMem(pScrn->scrnIndex, info->MMIO, info->MMIOSize); 451#else 452 pci_device_unmap_range(info->PciInfo, info->MMIO, info->MMIOSize); 453#endif 454 455 pRADEONEnt->MMIO = NULL; 456 info->MMIO = NULL; 457 return TRUE; 458} 459 460/* Memory map the frame buffer. Used by RADEONMapMem, below. */ 461static Bool RADEONMapFB(ScrnInfoPtr pScrn) 462{ 463#ifdef XSERVER_LIBPCIACCESS 464 int err; 465#endif 466 RADEONInfoPtr info = RADEONPTR(pScrn); 467 468 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 469 "Map: 0x%016llx, 0x%08lx\n", info->LinearAddr, info->FbMapSize); 470 471#ifndef XSERVER_LIBPCIACCESS 472 473 info->FB = xf86MapPciMem(pScrn->scrnIndex, 474 VIDMEM_FRAMEBUFFER, 475 info->PciTag, 476 info->LinearAddr, 477 info->FbMapSize); 478 479 if (!info->FB) return FALSE; 480 481#else 482 483 err = pci_device_map_range(info->PciInfo, 484 info->LinearAddr, 485 info->FbMapSize, 486 PCI_DEV_MAP_FLAG_WRITABLE | 487 PCI_DEV_MAP_FLAG_WRITE_COMBINE, 488 &info->FB); 489 490 if (err) { 491 xf86DrvMsg (pScrn->scrnIndex, X_ERROR, 492 "Unable to map FB aperture. %s (%d)\n", 493 strerror (err), err); 494 return FALSE; 495 } 496 497#endif 498 499 return TRUE; 500} 501 502/* Unmap the frame buffer. Used by RADEONUnmapMem, below. */ 503static Bool RADEONUnmapFB(ScrnInfoPtr pScrn) 504{ 505 RADEONInfoPtr info = RADEONPTR(pScrn); 506 507#ifndef XSERVER_LIBPCIACCESS 508 xf86UnMapVidMem(pScrn->scrnIndex, info->FB, info->FbMapSize); 509#else 510 pci_device_unmap_range(info->PciInfo, info->FB, info->FbMapSize); 511#endif 512 513 info->FB = NULL; 514 return TRUE; 515} 516 517/* Memory map the MMIO region and the frame buffer */ 518static Bool RADEONMapMem(ScrnInfoPtr pScrn) 519{ 520 if (!RADEONMapMMIO(pScrn)) return FALSE; 521 if (!RADEONMapFB(pScrn)) { 522 RADEONUnmapMMIO(pScrn); 523 return FALSE; 524 } 525 return TRUE; 526} 527 528/* Unmap the MMIO region and the frame buffer */ 529static Bool RADEONUnmapMem(ScrnInfoPtr pScrn) 530{ 531 if (!RADEONUnmapMMIO(pScrn) || !RADEONUnmapFB(pScrn)) return FALSE; 532 return TRUE; 533} 534 535void RADEONPllErrataAfterIndex(RADEONInfoPtr info) 536{ 537 unsigned char *RADEONMMIO = info->MMIO; 538 539 if (!(info->ChipErrata & CHIP_ERRATA_PLL_DUMMYREADS)) 540 return; 541 542 /* This workaround is necessary on rv200 and RS200 or PLL 543 * reads may return garbage (among others...) 544 */ 545 (void)INREG(RADEON_CLOCK_CNTL_DATA); 546 (void)INREG(RADEON_CRTC_GEN_CNTL); 547} 548 549void RADEONPllErrataAfterData(RADEONInfoPtr info) 550{ 551 unsigned char *RADEONMMIO = info->MMIO; 552 553 /* This workarounds is necessary on RV100, RS100 and RS200 chips 554 * or the chip could hang on a subsequent access 555 */ 556 if (info->ChipErrata & CHIP_ERRATA_PLL_DELAY) { 557 /* we can't deal with posted writes here ... */ 558 usleep(5000); 559 } 560 561 /* This function is required to workaround a hardware bug in some (all?) 562 * revisions of the R300. This workaround should be called after every 563 * CLOCK_CNTL_INDEX register access. If not, register reads afterward 564 * may not be correct. 565 */ 566 if (info->ChipErrata & CHIP_ERRATA_R300_CG) { 567 uint32_t save, tmp; 568 569 save = INREG(RADEON_CLOCK_CNTL_INDEX); 570 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 571 OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp); 572 tmp = INREG(RADEON_CLOCK_CNTL_DATA); 573 OUTREG(RADEON_CLOCK_CNTL_INDEX, save); 574 } 575} 576 577/* Read PLL register */ 578unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr) 579{ 580 RADEONInfoPtr info = RADEONPTR(pScrn); 581 unsigned char *RADEONMMIO = info->MMIO; 582 uint32_t data; 583 584 OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f); 585 RADEONPllErrataAfterIndex(info); 586 data = INREG(RADEON_CLOCK_CNTL_DATA); 587 RADEONPllErrataAfterData(info); 588 589 return data; 590} 591 592/* Write PLL information */ 593void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, uint32_t data) 594{ 595 RADEONInfoPtr info = RADEONPTR(pScrn); 596 unsigned char *RADEONMMIO = info->MMIO; 597 598 OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) | 599 RADEON_PLL_WR_EN)); 600 RADEONPllErrataAfterIndex(info); 601 OUTREG(RADEON_CLOCK_CNTL_DATA, data); 602 RADEONPllErrataAfterData(info); 603} 604 605/* Read MC register */ 606unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr) 607{ 608 RADEONInfoPtr info = RADEONPTR(pScrn); 609 unsigned char *RADEONMMIO = info->MMIO; 610 uint32_t data; 611 612 if ((info->ChipFamily == CHIP_FAMILY_RS690) || 613 (info->ChipFamily == CHIP_FAMILY_RS740)) { 614 OUTREG(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); 615 data = INREG(RS690_MC_DATA); 616 } else if (info->ChipFamily == CHIP_FAMILY_RS600) { 617 OUTREG(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) | RS600_MC_IND_CITF_ARB0)); 618 data = INREG(RS600_MC_DATA); 619 } else if (IS_AVIVO_VARIANT) { 620 OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000); 621 (void)INREG(AVIVO_MC_INDEX); 622 data = INREG(AVIVO_MC_DATA); 623 624 OUTREG(AVIVO_MC_INDEX, 0); 625 (void)INREG(AVIVO_MC_INDEX); 626 } else { 627 OUTREG(R300_MC_IND_INDEX, addr & 0x3f); 628 (void)INREG(R300_MC_IND_INDEX); 629 data = INREG(R300_MC_IND_DATA); 630 631 OUTREG(R300_MC_IND_INDEX, 0); 632 (void)INREG(R300_MC_IND_INDEX); 633 } 634 635 return data; 636} 637 638/* Write MC information */ 639void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, uint32_t data) 640{ 641 RADEONInfoPtr info = RADEONPTR(pScrn); 642 unsigned char *RADEONMMIO = info->MMIO; 643 644 if ((info->ChipFamily == CHIP_FAMILY_RS690) || 645 (info->ChipFamily == CHIP_FAMILY_RS740)) { 646 OUTREG(RS690_MC_INDEX, ((addr & RS690_MC_INDEX_MASK) | 647 RS690_MC_INDEX_WR_EN)); 648 OUTREG(RS690_MC_DATA, data); 649 OUTREG(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); 650 } else if (info->ChipFamily == CHIP_FAMILY_RS600) { 651 OUTREG(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) | 652 RS600_MC_IND_CITF_ARB0 | 653 RS600_MC_IND_WR_EN)); 654 OUTREG(RS600_MC_DATA, data); 655 } else if (IS_AVIVO_VARIANT) { 656 OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0xff0000); 657 (void)INREG(AVIVO_MC_INDEX); 658 OUTREG(AVIVO_MC_DATA, data); 659 OUTREG(AVIVO_MC_INDEX, 0); 660 (void)INREG(AVIVO_MC_INDEX); 661 } else { 662 OUTREG(R300_MC_IND_INDEX, (((addr) & 0x3f) | 663 R300_MC_IND_WR_EN)); 664 (void)INREG(R300_MC_IND_INDEX); 665 OUTREG(R300_MC_IND_DATA, data); 666 OUTREG(R300_MC_IND_INDEX, 0); 667 (void)INREG(R300_MC_IND_INDEX); 668 } 669} 670 671/* Read PCIE register */ 672unsigned RADEONINPCIE(ScrnInfoPtr pScrn, int addr) 673{ 674 RADEONInfoPtr info = RADEONPTR(pScrn); 675 unsigned char *RADEONMMIO = info->MMIO; 676 CARD32 data; 677 678 OUTREG(RADEON_PCIE_INDEX, addr & 0xff); 679 data = INREG(RADEON_PCIE_DATA); 680 681 return data; 682} 683 684/* Write PCIE register */ 685void RADEONOUTPCIE(ScrnInfoPtr pScrn, int addr, uint32_t data) 686{ 687 RADEONInfoPtr info = RADEONPTR(pScrn); 688 unsigned char *RADEONMMIO = info->MMIO; 689 690 OUTREG(RADEON_PCIE_INDEX, ((addr) & 0xff)); 691 OUTREG(RADEON_PCIE_DATA, data); 692} 693 694static Bool radeon_get_mc_idle(ScrnInfoPtr pScrn) 695{ 696 RADEONInfoPtr info = RADEONPTR(pScrn); 697 unsigned char *RADEONMMIO = info->MMIO; 698 699 if (info->ChipFamily >= CHIP_FAMILY_R600) { 700 if (INREG(R600_SRBM_STATUS) & 0x3f00) 701 return FALSE; 702 else 703 return TRUE; 704 } else if (info->ChipFamily == CHIP_FAMILY_RV515) { 705 if (INMC(pScrn, RV515_MC_STATUS) & RV515_MC_STATUS_IDLE) 706 return TRUE; 707 else 708 return FALSE; 709 } else if (info->ChipFamily == CHIP_FAMILY_RS600) { 710 if (INMC(pScrn, RS600_MC_STATUS) & RS600_MC_IDLE) 711 return TRUE; 712 else 713 return FALSE; 714 } else if ((info->ChipFamily == CHIP_FAMILY_RS690) || 715 (info->ChipFamily == CHIP_FAMILY_RS740)) { 716 if (INMC(pScrn, RS690_MC_STATUS) & RS690_MC_STATUS_IDLE) 717 return TRUE; 718 else 719 return FALSE; 720 } else if (info->ChipFamily >= CHIP_FAMILY_R520) { 721 if (INMC(pScrn, R520_MC_STATUS) & R520_MC_STATUS_IDLE) 722 return TRUE; 723 else 724 return FALSE; 725 } else if (IS_R300_VARIANT) { 726 if (INREG(RADEON_MC_STATUS) & R300_MC_IDLE) 727 return TRUE; 728 else 729 return FALSE; 730 } else { 731 if (INREG(RADEON_MC_STATUS) & RADEON_MC_IDLE) 732 return TRUE; 733 else 734 return FALSE; 735 } 736} 737 738#define LOC_FB 0x1 739#define LOC_AGP 0x2 740static void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, uint32_t fb_loc, uint32_t agp_loc, uint32_t agp_loc_hi) 741{ 742 RADEONInfoPtr info = RADEONPTR(pScrn); 743 unsigned char *RADEONMMIO = info->MMIO; 744 745 if (info->ChipFamily >= CHIP_FAMILY_RV770) { 746 if (mask & LOC_FB) 747 OUTREG(R700_MC_VM_FB_LOCATION, fb_loc); 748 if (mask & LOC_AGP) { 749 OUTREG(R700_MC_VM_AGP_BOT, agp_loc); 750 OUTREG(R700_MC_VM_AGP_TOP, agp_loc_hi); 751 } 752 } else if (info->ChipFamily >= CHIP_FAMILY_R600) { 753 if (mask & LOC_FB) 754 OUTREG(R600_MC_VM_FB_LOCATION, fb_loc); 755 if (mask & LOC_AGP) { 756 OUTREG(R600_MC_VM_AGP_BOT, agp_loc); 757 OUTREG(R600_MC_VM_AGP_TOP, agp_loc_hi); 758 } 759 } else if (info->ChipFamily == CHIP_FAMILY_RV515) { 760 if (mask & LOC_FB) 761 OUTMC(pScrn, RV515_MC_FB_LOCATION, fb_loc); 762 if (mask & LOC_AGP) 763 OUTMC(pScrn, RV515_MC_AGP_LOCATION, agp_loc); 764 (void)INMC(pScrn, RV515_MC_AGP_LOCATION); 765 } else if (info->ChipFamily == CHIP_FAMILY_RS600) { 766 if (mask & LOC_FB) 767 OUTMC(pScrn, RS600_MC_FB_LOCATION, fb_loc); 768 if (mask & LOC_AGP) 769 OUTMC(pScrn, RS600_MC_AGP_LOCATION, agp_loc); 770 } else if ((info->ChipFamily == CHIP_FAMILY_RS690) || 771 (info->ChipFamily == CHIP_FAMILY_RS740)) { 772 if (mask & LOC_FB) 773 OUTMC(pScrn, RS690_MC_FB_LOCATION, fb_loc); 774 if (mask & LOC_AGP) 775 OUTMC(pScrn, RS690_MC_AGP_LOCATION, agp_loc); 776 } else if (info->ChipFamily >= CHIP_FAMILY_R520) { 777 if (mask & LOC_FB) 778 OUTMC(pScrn, R520_MC_FB_LOCATION, fb_loc); 779 if (mask & LOC_AGP) 780 OUTMC(pScrn, R520_MC_AGP_LOCATION, agp_loc); 781 (void)INMC(pScrn, R520_MC_FB_LOCATION); 782 } else { 783 if (mask & LOC_FB) 784 OUTREG(RADEON_MC_FB_LOCATION, fb_loc); 785 if (mask & LOC_AGP) 786 OUTREG(RADEON_MC_AGP_LOCATION, agp_loc); 787 } 788} 789 790static void radeon_read_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, uint32_t *fb_loc, uint32_t *agp_loc, uint32_t *agp_loc_hi) 791{ 792 RADEONInfoPtr info = RADEONPTR(pScrn); 793 unsigned char *RADEONMMIO = info->MMIO; 794 795 if (info->ChipFamily >= CHIP_FAMILY_RV770) { 796 if (mask & LOC_FB) 797 *fb_loc = INREG(R700_MC_VM_FB_LOCATION); 798 if (mask & LOC_AGP) { 799 *agp_loc = INREG(R700_MC_VM_AGP_BOT); 800 *agp_loc_hi = INREG(R700_MC_VM_AGP_TOP); 801 } 802 } else if (info->ChipFamily >= CHIP_FAMILY_R600) { 803 if (mask & LOC_FB) 804 *fb_loc = INREG(R600_MC_VM_FB_LOCATION); 805 if (mask & LOC_AGP) { 806 *agp_loc = INREG(R600_MC_VM_AGP_BOT); 807 *agp_loc_hi = INREG(R600_MC_VM_AGP_TOP); 808 } 809 } else if (info->ChipFamily == CHIP_FAMILY_RV515) { 810 if (mask & LOC_FB) 811 *fb_loc = INMC(pScrn, RV515_MC_FB_LOCATION); 812 if (mask & LOC_AGP) { 813 *agp_loc = INMC(pScrn, RV515_MC_AGP_LOCATION); 814 *agp_loc_hi = 0; 815 } 816 } else if (info->ChipFamily == CHIP_FAMILY_RS600) { 817 if (mask & LOC_FB) 818 *fb_loc = INMC(pScrn, RS600_MC_FB_LOCATION); 819 if (mask & LOC_AGP) { 820 *agp_loc = INMC(pScrn, RS600_MC_AGP_LOCATION); 821 *agp_loc_hi = 0; 822 } 823 } else if ((info->ChipFamily == CHIP_FAMILY_RS690) || 824 (info->ChipFamily == CHIP_FAMILY_RS740)) { 825 if (mask & LOC_FB) 826 *fb_loc = INMC(pScrn, RS690_MC_FB_LOCATION); 827 if (mask & LOC_AGP) { 828 *agp_loc = INMC(pScrn, RS690_MC_AGP_LOCATION); 829 *agp_loc_hi = 0; 830 } 831 } else if (info->ChipFamily >= CHIP_FAMILY_R520) { 832 if (mask & LOC_FB) 833 *fb_loc = INMC(pScrn, R520_MC_FB_LOCATION); 834 if (mask & LOC_AGP) { 835 *agp_loc = INMC(pScrn, R520_MC_AGP_LOCATION); 836 *agp_loc_hi = 0; 837 } 838 } else { 839 if (mask & LOC_FB) 840 *fb_loc = INREG(RADEON_MC_FB_LOCATION); 841 if (mask & LOC_AGP) 842 *agp_loc = INREG(RADEON_MC_AGP_LOCATION); 843 } 844} 845 846#if 0 847/* Read PAL information (only used for debugging) */ 848static int RADEONINPAL(int idx) 849{ 850 RADEONInfoPtr info = RADEONPTR(pScrn); 851 unsigned char *RADEONMMIO = info->MMIO; 852 853 OUTREG(RADEON_PALETTE_INDEX, idx << 16); 854 return INREG(RADEON_PALETTE_DATA); 855} 856#endif 857 858/* Wait for vertical sync on primary CRTC */ 859void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn) 860{ 861 RADEONInfoPtr info = RADEONPTR(pScrn); 862 unsigned char *RADEONMMIO = info->MMIO; 863 uint32_t crtc_gen_cntl; 864 struct timeval timeout; 865 866 crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); 867 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) || 868 !(crtc_gen_cntl & RADEON_CRTC_EN)) 869 return; 870 871 /* Clear the CRTC_VBLANK_SAVE bit */ 872 OUTREG(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR); 873 874 /* Wait for it to go back up */ 875 radeon_init_timeout(&timeout, RADEON_VSYNC_TIMEOUT); 876 while (!(INREG(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_SAVE) && 877 !radeon_timedout(&timeout)) 878 usleep(100); 879} 880 881/* Wait for vertical sync on secondary CRTC */ 882void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn) 883{ 884 RADEONInfoPtr info = RADEONPTR(pScrn); 885 unsigned char *RADEONMMIO = info->MMIO; 886 uint32_t crtc2_gen_cntl; 887 struct timeval timeout; 888 889 crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); 890 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) || 891 !(crtc2_gen_cntl & RADEON_CRTC2_EN)) 892 return; 893 894 /* Clear the CRTC2_VBLANK_SAVE bit */ 895 OUTREG(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR); 896 897 /* Wait for it to go back up */ 898 radeon_init_timeout(&timeout, RADEON_VSYNC_TIMEOUT); 899 while (!(INREG(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_SAVE) && 900 !radeon_timedout(&timeout)) 901 usleep(100); 902} 903 904 905/* Compute log base 2 of val */ 906int RADEONMinBits(int val) 907{ 908 int bits; 909 910 if (!val) return 1; 911 for (bits = 0; val; val >>= 1, ++bits); 912 return bits; 913} 914 915/* Compute n/d with rounding */ 916static int RADEONDiv(int n, int d) 917{ 918 return (n + (d / 2)) / d; 919} 920 921static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn) 922{ 923 RADEONInfoPtr info = RADEONPTR(pScrn); 924 RADEONPLLPtr pll = &info->pll; 925 unsigned char *RADEONMMIO = info->MMIO; 926 unsigned char ppll_div_sel; 927 unsigned mpll_fb_div, spll_fb_div, M; 928 unsigned xclk, tmp, ref_div; 929 int hTotal, vTotal, num, denom, m, n; 930 float hz, prev_xtal, vclk, xtal, mpll, spll; 931 long total_usecs; 932 struct timeval start, stop, to1, to2; 933 unsigned int f1, f2, f3; 934 int tries = 0; 935 936 prev_xtal = 0; 937 again: 938 xtal = 0; 939 if (++tries > 10) 940 goto failed; 941 942 gettimeofday(&to1, NULL); 943 f1 = INREG(RADEON_CRTC_CRNT_FRAME); 944 for (;;) { 945 f2 = INREG(RADEON_CRTC_CRNT_FRAME); 946 if (f1 != f2) 947 break; 948 gettimeofday(&to2, NULL); 949 if ((to2.tv_sec - to1.tv_sec) > 1) { 950 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Clock not counting...\n"); 951 goto failed; 952 } 953 } 954 gettimeofday(&start, NULL); 955 for(;;) { 956 f3 = INREG(RADEON_CRTC_CRNT_FRAME); 957 if (f3 != f2) 958 break; 959 gettimeofday(&to2, NULL); 960 if ((to2.tv_sec - start.tv_sec) > 1) 961 goto failed; 962 } 963 gettimeofday(&stop, NULL); 964 965 if ((stop.tv_sec - start.tv_sec) != 0) 966 goto again; 967 total_usecs = abs(stop.tv_usec - start.tv_usec); 968 if (total_usecs == 0) 969 goto again; 970 hz = 1000000.0/(float)total_usecs; 971 972 hTotal = ((INREG(RADEON_CRTC_H_TOTAL_DISP) & 0x3ff) + 1) * 8; 973 vTotal = ((INREG(RADEON_CRTC_V_TOTAL_DISP) & 0xfff) + 1); 974 vclk = (float)(hTotal * (float)(vTotal * hz)); 975 976 switch((INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x30000) >> 16) { 977 case 0: 978 default: 979 num = 1; 980 denom = 1; 981 break; 982 case 1: 983 n = ((INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) >> 16) & 0xff); 984 m = (INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) & 0xff); 985 num = 2*n; 986 denom = 2*m; 987 break; 988 case 2: 989 n = ((INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) >> 8) & 0xff); 990 m = (INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) & 0xff); 991 num = 2*n; 992 denom = 2*m; 993 break; 994 } 995 996 ppll_div_sel = INREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; 997 RADEONPllErrataAfterIndex(info); 998 999 n = (INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel) & 0x7ff); 1000 m = (INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x3ff); 1001 1002 num *= n; 1003 denom *= m; 1004 1005 switch ((INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) { 1006 case 1: 1007 denom *= 2; 1008 break; 1009 case 2: 1010 denom *= 4; 1011 break; 1012 case 3: 1013 denom *= 8; 1014 break; 1015 case 4: 1016 denom *= 3; 1017 break; 1018 case 6: 1019 denom *= 6; 1020 break; 1021 case 7: 1022 denom *= 12; 1023 break; 1024 } 1025 1026 xtal = (int)(vclk *(float)denom/(float)num); 1027 1028 if ((xtal > 26900000) && (xtal < 27100000)) 1029 xtal = 2700; 1030 else if ((xtal > 14200000) && (xtal < 14400000)) 1031 xtal = 1432; 1032 else if ((xtal > 29400000) && (xtal < 29600000)) 1033 xtal = 2950; 1034 else 1035 goto again; 1036 failed: 1037 if (xtal == 0) { 1038 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Failed to probe xtal value ! " 1039 "Using default 27Mhz\n"); 1040 xtal = 2700; 1041 } else { 1042 if (prev_xtal == 0) { 1043 prev_xtal = xtal; 1044 tries = 0; 1045 goto again; 1046 } else if (prev_xtal != xtal) { 1047 prev_xtal = 0; 1048 goto again; 1049 } 1050 } 1051 1052 tmp = INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV); 1053 ref_div = INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x3ff; 1054 1055 /* Some sanity check based on the BIOS code .... */ 1056 if (ref_div < 2) { 1057 uint32_t tmp; 1058 tmp = INPLL(pScrn, RADEON_PPLL_REF_DIV); 1059 if (IS_R300_VARIANT 1060 || (info->ChipFamily == CHIP_FAMILY_RS300) 1061 || (info->ChipFamily == CHIP_FAMILY_RS400) 1062 || (info->ChipFamily == CHIP_FAMILY_RS480)) 1063 ref_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> 1064 R300_PPLL_REF_DIV_ACC_SHIFT; 1065 else 1066 ref_div = tmp & RADEON_PPLL_REF_DIV_MASK; 1067 if (ref_div < 2) 1068 ref_div = 12; 1069 } 1070 1071 /* Calculate "base" xclk straight from MPLL, though that isn't 1072 * really useful (hopefully). This isn't called XCLK anymore on 1073 * radeon's... 1074 */ 1075 mpll_fb_div = (tmp & 0xff00) >> 8; 1076 spll_fb_div = (tmp & 0xff0000) >> 16; 1077 M = (tmp & 0xff); 1078 xclk = RADEONDiv((2 * mpll_fb_div * xtal), (M)); 1079 1080 /* 1081 * Calculate MCLK based on MCLK-A 1082 */ 1083 mpll = (2.0 * (float)mpll_fb_div * (xtal / 100.0)) / (float)M; 1084 spll = (2.0 * (float)spll_fb_div * (xtal / 100.0)) / (float)M; 1085 1086 tmp = INPLL(pScrn, RADEON_MCLK_CNTL) & 0x7; 1087 switch(tmp) { 1088 case 1: info->mclk = mpll; break; 1089 case 2: info->mclk = mpll / 2.0; break; 1090 case 3: info->mclk = mpll / 4.0; break; 1091 case 4: info->mclk = mpll / 8.0; break; 1092 case 7: info->mclk = spll; break; 1093 default: 1094 info->mclk = 200.00; 1095 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unsupported MCLKA source" 1096 " setting %d, can't probe MCLK value !\n", tmp); 1097 } 1098 1099 /* 1100 * Calculate SCLK 1101 */ 1102 tmp = INPLL(pScrn, RADEON_SCLK_CNTL) & 0x7; 1103 switch(tmp) { 1104 case 1: info->sclk = spll; break; 1105 case 2: info->sclk = spll / 2.0; break; 1106 case 3: info->sclk = spll / 4.0; break; 1107 case 4: info->sclk = spll / 8.0; break; 1108 case 7: info->sclk = mpll; break; 1109 default: 1110 info->sclk = 200.00; 1111 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unsupported SCLK source" 1112 " setting %d, can't probe SCLK value !\n", tmp); 1113 } 1114 1115 /* we're done, hopefully these are sane values */ 1116 pll->reference_div = ref_div; 1117 pll->xclk = xclk; 1118 pll->reference_freq = xtal; 1119 1120 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Probed PLL values: xtal: %f Mhz, " 1121 "sclk: %f Mhz, mclk: %f Mhz\n", xtal/100.0, info->sclk, info->mclk); 1122 1123 return TRUE; 1124} 1125 1126static void RADEONGetClockInfo(ScrnInfoPtr pScrn) 1127{ 1128 RADEONInfoPtr info = RADEONPTR (pScrn); 1129 RADEONPLLPtr pll = &info->pll; 1130 double min_dotclock; 1131 1132 if (RADEONGetClockInfoFromBIOS(pScrn)) { 1133 if (pll->reference_div < 2) { 1134 /* retrive it from register setting for fitting into current PLL algorithm. 1135 We'll probably need a new routine to calculate the best ref_div from BIOS 1136 provided min_input_pll and max_input_pll 1137 */ 1138 uint32_t tmp; 1139 tmp = INPLL(pScrn, RADEON_PPLL_REF_DIV); 1140 if (IS_R300_VARIANT || 1141 (info->ChipFamily == CHIP_FAMILY_RS300) || 1142 (info->ChipFamily == CHIP_FAMILY_RS400) || 1143 (info->ChipFamily == CHIP_FAMILY_RS480)) { 1144 pll->reference_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT; 1145 } else { 1146 pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; 1147 } 1148 1149 if (pll->reference_div < 2) pll->reference_div = 12; 1150 } 1151 } else { 1152 xf86DrvMsg (pScrn->scrnIndex, X_WARNING, 1153 "Video BIOS not detected, using default clock settings!\n"); 1154 1155 /* Default min/max PLL values */ 1156 if (info->ChipFamily == CHIP_FAMILY_R420 || info->ChipFamily == CHIP_FAMILY_RV410) { 1157 pll->pll_in_min = 100; 1158 pll->pll_in_max = 1350; 1159 pll->pll_out_min = 20000; 1160 pll->pll_out_max = 50000; 1161 } else { 1162 pll->pll_in_min = 40; 1163 pll->pll_in_max = 500; 1164 pll->pll_out_min = 12500; 1165 pll->pll_out_max = 35000; 1166 } 1167 1168 if (!RADEONProbePLLParameters(pScrn)) { 1169 if (info->IsIGP) 1170 pll->reference_freq = 1432; 1171 else 1172 pll->reference_freq = 2700; 1173 1174 pll->reference_div = 12; 1175 pll->xclk = 10300; 1176 1177 info->sclk = 200.00; 1178 info->mclk = 200.00; 1179 } 1180 } 1181 1182 /* card limits for computing PLLs */ 1183 if (IS_AVIVO_VARIANT) { 1184 pll->min_post_div = 2; 1185 pll->max_post_div = 0x7f; 1186 } else { 1187 pll->min_post_div = 1; 1188 pll->max_post_div = 12; //16 on crtc0 1189 } 1190 pll->min_ref_div = 2; 1191 pll->max_ref_div = 0x3ff; 1192 pll->min_feedback_div = 4; 1193 pll->max_feedback_div = 0x7ff; 1194 pll->best_vco = 0; 1195 1196 xf86DrvMsg (pScrn->scrnIndex, X_INFO, 1197 "PLL parameters: rf=%u rd=%u min=%u max=%u; xclk=%u\n", 1198 pll->reference_freq, 1199 pll->reference_div, 1200 (unsigned)pll->pll_out_min, (unsigned)pll->pll_out_max, 1201 pll->xclk); 1202 1203 /* (Some?) Radeon BIOSes seem too lie about their minimum dot 1204 * clocks. Allow users to override the detected minimum dot clock 1205 * value (e.g., and allow it to be suitable for TV sets). 1206 */ 1207 if (xf86GetOptValFreq(info->Options, OPTION_MIN_DOTCLOCK, 1208 OPTUNITS_MHZ, &min_dotclock)) { 1209 if (min_dotclock < 12 || min_dotclock*100 >= pll->pll_out_max) { 1210 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1211 "Illegal minimum dotclock specified %.2f MHz " 1212 "(option ignored)\n", 1213 min_dotclock); 1214 } else { 1215 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1216 "Forced minimum dotclock to %.2f MHz " 1217 "(instead of detected %.2f MHz)\n", 1218 min_dotclock, ((double)pll->pll_out_min/1000)); 1219 pll->pll_out_min = min_dotclock * 1000; 1220 } 1221 } 1222} 1223 1224 1225 1226/* This is called by RADEONPreInit to set up the default visual */ 1227static Bool RADEONPreInitVisual(ScrnInfoPtr pScrn) 1228{ 1229 RADEONInfoPtr info = RADEONPTR(pScrn); 1230 1231 if (!xf86SetDepthBpp(pScrn, 0, 0, 0, Support32bppFb)) 1232 return FALSE; 1233 1234 switch (pScrn->depth) { 1235 case 8: 1236 case 15: 1237 case 16: 1238 case 24: 1239 break; 1240 1241 default: 1242 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1243 "Given depth (%d) is not supported by %s driver\n", 1244 pScrn->depth, RADEON_DRIVER_NAME); 1245 return FALSE; 1246 } 1247 1248 xf86PrintDepthBpp(pScrn); 1249 1250 info->pix24bpp = xf86GetBppFromDepth(pScrn, 1251 pScrn->depth); 1252 info->CurrentLayout.bitsPerPixel = pScrn->bitsPerPixel; 1253 info->CurrentLayout.depth = pScrn->depth; 1254 info->CurrentLayout.pixel_bytes = pScrn->bitsPerPixel / 8; 1255 info->CurrentLayout.pixel_code = (pScrn->bitsPerPixel != 16 1256 ? pScrn->bitsPerPixel 1257 : pScrn->depth); 1258 1259 if (info->pix24bpp == 24) { 1260 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1261 "Radeon does NOT support 24bpp\n"); 1262 return FALSE; 1263 } 1264 1265 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1266 "Pixel depth = %d bits stored in %d byte%s (%d bpp pixmaps)\n", 1267 pScrn->depth, 1268 info->CurrentLayout.pixel_bytes, 1269 info->CurrentLayout.pixel_bytes > 1 ? "s" : "", 1270 info->pix24bpp); 1271 1272 if (!xf86SetDefaultVisual(pScrn, -1)) return FALSE; 1273 1274 if (pScrn->depth > 8 && pScrn->defaultVisual != TrueColor) { 1275 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1276 "Default visual (%s) is not supported at depth %d\n", 1277 xf86GetVisualName(pScrn->defaultVisual), pScrn->depth); 1278 return FALSE; 1279 } 1280 return TRUE; 1281} 1282 1283/* This is called by RADEONPreInit to handle all color weight issues */ 1284static Bool RADEONPreInitWeight(ScrnInfoPtr pScrn) 1285{ 1286 RADEONInfoPtr info = RADEONPTR(pScrn); 1287 1288 /* Save flag for 6 bit DAC to use for 1289 setting CRTC registers. Otherwise use 1290 an 8 bit DAC, even if xf86SetWeight sets 1291 pScrn->rgbBits to some value other than 1292 8. */ 1293 info->dac6bits = FALSE; 1294 1295 if (pScrn->depth > 8) { 1296 rgb defaultWeight = { 0, 0, 0 }; 1297 1298 if (!xf86SetWeight(pScrn, defaultWeight, defaultWeight)) return FALSE; 1299 } else { 1300 pScrn->rgbBits = 8; 1301 if (xf86ReturnOptValBool(info->Options, OPTION_DAC_6BIT, FALSE)) { 1302 pScrn->rgbBits = 6; 1303 info->dac6bits = TRUE; 1304 } 1305 } 1306 1307 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1308 "Using %d bits per RGB (%d bit DAC)\n", 1309 pScrn->rgbBits, info->dac6bits ? 6 : 8); 1310 1311 return TRUE; 1312} 1313 1314void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, 1315 RADEONInfoPtr info) 1316{ 1317 save->mc_fb_location = info->mc_fb_location; 1318 save->mc_agp_location = info->mc_agp_location; 1319 1320 if (IS_AVIVO_VARIANT) { 1321 save->mc_agp_location_hi = info->mc_agp_location_hi; 1322 } else { 1323 save->display_base_addr = info->fbLocation; 1324 save->display2_base_addr = info->fbLocation; 1325 save->ov0_base_addr = info->fbLocation; 1326 } 1327} 1328 1329static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) 1330{ 1331 RADEONInfoPtr info = RADEONPTR(pScrn); 1332 unsigned char *RADEONMMIO = info->MMIO; 1333 uint64_t mem_size; 1334 uint64_t aper_size; 1335 1336 radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &info->mc_fb_location, 1337 &info->mc_agp_location, &info->mc_agp_location_hi); 1338 1339 /* We shouldn't use info->videoRam here which might have been clipped 1340 * but the real video RAM instead 1341 */ 1342 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1343 mem_size = INREG(R600_CONFIG_MEMSIZE); 1344 aper_size = INREG(R600_CONFIG_APER_SIZE); 1345 } else { 1346 mem_size = INREG(RADEON_CONFIG_MEMSIZE); 1347 aper_size = INREG(RADEON_CONFIG_APER_SIZE); 1348 } 1349 1350 if (mem_size == 0) 1351 mem_size = 0x800000; 1352 1353 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 1354 Novell bug 204882 + along with lots of ubuntu ones */ 1355 if (aper_size > mem_size) 1356 mem_size = aper_size; 1357 1358#ifdef XF86DRI 1359 /* Apply memory map limitation if using an old DRI */ 1360 if (info->directRenderingEnabled && !info->dri->newMemoryMap) { 1361 if (aper_size < mem_size) 1362 mem_size = aper_size; 1363 } 1364#endif 1365 1366 if ((info->ChipFamily != CHIP_FAMILY_RS600) && 1367 (info->ChipFamily != CHIP_FAMILY_RS690) && 1368 (info->ChipFamily != CHIP_FAMILY_RS740) && 1369 (info->ChipFamily != CHIP_FAMILY_RS780) && 1370 (info->ChipFamily != CHIP_FAMILY_RS880)) { 1371 if (info->IsIGP) 1372 info->mc_fb_location = INREG(RADEON_NB_TOM); 1373 else 1374#ifdef XF86DRI 1375 /* Old DRI has restrictions on the memory map */ 1376 if ( info->directRenderingEnabled && 1377 info->dri->pKernelDRMVersion->version_minor < 10 ) 1378 info->mc_fb_location = (mem_size - 1) & 0xffff0000U; 1379 else 1380#endif 1381 { 1382 uint64_t aper0_base; 1383 1384 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1385 aper0_base = INREG(R600_CONFIG_F0_BASE); 1386 } else { 1387 aper0_base = INREG(RADEON_CONFIG_APER_0_BASE); 1388 } 1389 1390 /* Recent chips have an "issue" with the memory controller, the 1391 * location must be aligned to the size. We just align it down, 1392 * too bad if we walk over the top of system memory, we don't 1393 * use DMA without a remapped anyway. 1394 * Affected chips are rv280, all r3xx, and all r4xx, but not IGP 1395 */ 1396 if (info->ChipFamily == CHIP_FAMILY_RV280 || 1397 info->ChipFamily == CHIP_FAMILY_R300 || 1398 info->ChipFamily == CHIP_FAMILY_R350 || 1399 info->ChipFamily == CHIP_FAMILY_RV350 || 1400 info->ChipFamily == CHIP_FAMILY_RV380 || 1401 info->ChipFamily == CHIP_FAMILY_R420 || 1402 info->ChipFamily == CHIP_FAMILY_RV410) 1403 aper0_base &= ~(mem_size - 1); 1404 1405 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1406 uint64_t mc_fb = ((aper0_base >> 24) & 0xffff) | 1407 (((aper0_base + mem_size - 1) >> 8) & 0xffff0000); 1408 info->mc_fb_location = mc_fb & 0xffffffff; 1409 ErrorF("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location); 1410 } else { 1411 uint64_t mc_fb = ((aper0_base >> 16) & 0xffff) | 1412 ((aper0_base + mem_size - 1) & 0xffff0000U); 1413 info->mc_fb_location = mc_fb & 0xffffffff; 1414 } 1415 } 1416 } 1417 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1418 info->fbLocation = (info->mc_fb_location & 0xffff) << 24; 1419 } else { 1420 info->fbLocation = (info->mc_fb_location & 0xffff) << 16; 1421 } 1422 /* Just disable the damn AGP apertures for now, it may be 1423 * re-enabled later by the DRM 1424 */ 1425 if (IS_AVIVO_VARIANT) 1426 info->mc_agp_location = 0x003f0000; 1427 else 1428 info->mc_agp_location = 0xffffffc0; 1429 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1430 "RADEONInitMemoryMap() : \n"); 1431 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1432 " mem_size : 0x%08x\n", (unsigned)mem_size); 1433 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1434 " MC_FB_LOCATION : 0x%08x\n", (unsigned)info->mc_fb_location); 1435 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1436 " MC_AGP_LOCATION : 0x%08x\n", 1437 (unsigned)info->mc_agp_location); 1438} 1439 1440static void RADEONGetVRamType(ScrnInfoPtr pScrn) 1441{ 1442 RADEONInfoPtr info = RADEONPTR(pScrn); 1443 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1444 unsigned char *RADEONMMIO = info->MMIO; 1445 uint32_t tmp; 1446 1447 if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300)) 1448 info->IsDDR = TRUE; 1449 else if (INREG(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) 1450 info->IsDDR = TRUE; 1451 else 1452 info->IsDDR = FALSE; 1453 1454 if ((info->ChipFamily >= CHIP_FAMILY_R600) && 1455 (info->ChipFamily <= CHIP_FAMILY_RV635)) { 1456 int chansize; 1457 /* r6xx */ 1458 tmp = INREG(R600_RAMCFG); 1459 if (tmp & R600_CHANSIZE_OVERRIDE) 1460 chansize = 16; 1461 else if (tmp & R600_CHANSIZE) 1462 chansize = 64; 1463 else 1464 chansize = 32; 1465 if (info->ChipFamily == CHIP_FAMILY_R600) 1466 info->RamWidth = 8 * chansize; 1467 else if (info->ChipFamily == CHIP_FAMILY_RV670) 1468 info->RamWidth = 4 * chansize; 1469 else if ((info->ChipFamily == CHIP_FAMILY_RV610) || 1470 (info->ChipFamily == CHIP_FAMILY_RV620)) 1471 info->RamWidth = chansize; 1472 else if ((info->ChipFamily == CHIP_FAMILY_RV630) || 1473 (info->ChipFamily == CHIP_FAMILY_RV635)) 1474 info->RamWidth = 2 * chansize; 1475 } else if (info->ChipFamily == CHIP_FAMILY_RV515) { 1476 /* rv515/rv550 */ 1477 tmp = INMC(pScrn, RV515_MC_CNTL); 1478 tmp &= RV515_MEM_NUM_CHANNELS_MASK; 1479 switch (tmp) { 1480 case 0: info->RamWidth = 64; break; 1481 case 1: info->RamWidth = 128; break; 1482 default: info->RamWidth = 128; break; 1483 } 1484 } else if ((info->ChipFamily >= CHIP_FAMILY_R520) && 1485 (info->ChipFamily <= CHIP_FAMILY_RV570)){ 1486 /* r520/rv530/rv560/rv570/r580 */ 1487 tmp = INMC(pScrn, R520_MC_CNTL0); 1488 switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { 1489 case 0: info->RamWidth = 32; break; 1490 case 1: info->RamWidth = 64; break; 1491 case 2: info->RamWidth = 128; break; 1492 case 3: info->RamWidth = 256; break; 1493 default: info->RamWidth = 64; break; 1494 } 1495 if (tmp & R520_MC_CHANNEL_SIZE) { 1496 info->RamWidth *= 2; 1497 } 1498 } else if ((info->ChipFamily >= CHIP_FAMILY_R300) && 1499 (info->ChipFamily <= CHIP_FAMILY_RV410)) { 1500 /* r3xx, r4xx */ 1501 tmp = INREG(RADEON_MEM_CNTL); 1502 tmp &= R300_MEM_NUM_CHANNELS_MASK; 1503 switch (tmp) { 1504 case 0: info->RamWidth = 64; break; 1505 case 1: info->RamWidth = 128; break; 1506 case 2: info->RamWidth = 256; break; 1507 default: info->RamWidth = 128; break; 1508 } 1509 } else if ((info->ChipFamily == CHIP_FAMILY_RV100) || 1510 (info->ChipFamily == CHIP_FAMILY_RS100) || 1511 (info->ChipFamily == CHIP_FAMILY_RS200)){ 1512 tmp = INREG(RADEON_MEM_CNTL); 1513 if (tmp & RV100_HALF_MODE) 1514 info->RamWidth = 32; 1515 else 1516 info->RamWidth = 64; 1517 1518 if (!pRADEONEnt->HasCRTC2) { 1519 info->RamWidth /= 4; 1520 info->IsDDR = TRUE; 1521 } 1522 } else if (info->ChipFamily <= CHIP_FAMILY_RV280) { 1523 tmp = INREG(RADEON_MEM_CNTL); 1524 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) 1525 info->RamWidth = 128; 1526 else 1527 info->RamWidth = 64; 1528 } else { 1529 /* newer IGPs */ 1530 info->RamWidth = 128; 1531 } 1532 1533 /* This may not be correct, as some cards can have half of channel disabled 1534 * ToDo: identify these cases 1535 */ 1536} 1537 1538/* 1539 * Depending on card genertation, chipset bugs, etc... the amount of vram 1540 * accessible to the CPU can vary. This function is our best shot at figuring 1541 * it out. Returns a value in KB. 1542 */ 1543static uint32_t RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn) 1544{ 1545 RADEONInfoPtr info = RADEONPTR(pScrn); 1546 unsigned char *RADEONMMIO = info->MMIO; 1547 uint32_t aper_size; 1548 unsigned char byte; 1549 1550 if (info->ChipFamily >= CHIP_FAMILY_R600) 1551 aper_size = INREG(R600_CONFIG_APER_SIZE) / 1024; 1552 else 1553 aper_size = INREG(RADEON_CONFIG_APER_SIZE) / 1024; 1554 1555#ifdef XF86DRI 1556 /* If we use the DRI, we need to check if it's a version that has the 1557 * bug of always cropping MC_FB_LOCATION to one aperture, in which case 1558 * we need to limit the amount of accessible video memory 1559 */ 1560 if (info->directRenderingEnabled && 1561 info->dri->pKernelDRMVersion->version_minor < 23) { 1562 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1563 "[dri] limiting video memory to one aperture of %uK\n", 1564 (unsigned)aper_size); 1565 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1566 "[dri] detected radeon kernel module version 1.%d but" 1567 " 1.23 or newer is required for full memory mapping.\n", 1568 info->dri->pKernelDRMVersion->version_minor); 1569 info->dri->newMemoryMap = FALSE; 1570 return aper_size; 1571 } 1572 info->dri->newMemoryMap = TRUE; 1573#endif /* XF86DRI */ 1574 1575 if (info->ChipFamily >= CHIP_FAMILY_R600) 1576 return aper_size; 1577 1578 /* Set HDP_APER_CNTL only on cards that are known not to be broken, 1579 * that is has the 2nd generation multifunction PCI interface 1580 */ 1581 if (info->ChipFamily == CHIP_FAMILY_RV280 || 1582 info->ChipFamily == CHIP_FAMILY_RV350 || 1583 info->ChipFamily == CHIP_FAMILY_RV380 || 1584 info->ChipFamily == CHIP_FAMILY_R420 || 1585 info->ChipFamily == CHIP_FAMILY_RV410 || 1586 IS_AVIVO_VARIANT) { 1587 OUTREGP (RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, 1588 ~RADEON_HDP_APER_CNTL); 1589 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1590 "Generation 2 PCI interface, using max accessible memory\n"); 1591 return aper_size * 2; 1592 } 1593 1594 /* Older cards have all sorts of funny issues to deal with. First 1595 * check if it's a multifunction card by reading the PCI config 1596 * header type... Limit those to one aperture size 1597 */ 1598 PCI_READ_BYTE(info->PciInfo, &byte, 0xe); 1599 if (byte & 0x80) { 1600 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1601 "Generation 1 PCI interface in multifunction mode" 1602 ", accessible memory limited to one aperture\n"); 1603 return aper_size; 1604 } 1605 1606 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS 1607 * have set it up. We don't write this as it's broken on some ASICs but 1608 * we expect the BIOS to have done the right thing (might be too optimistic...) 1609 */ 1610 if (INREG(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) 1611 return aper_size * 2; 1612 1613 return aper_size; 1614} 1615 1616static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) 1617{ 1618 RADEONInfoPtr info = RADEONPTR(pScrn); 1619 EntityInfoPtr pEnt = info->pEnt; 1620 GDevPtr dev = pEnt->device; 1621 unsigned char *RADEONMMIO = info->MMIO; 1622 MessageType from = X_PROBED; 1623 uint32_t accessible, bar_size; 1624 1625 if ((!IS_AVIVO_VARIANT) && info->IsIGP) { 1626 uint32_t tom = INREG(RADEON_NB_TOM); 1627 1628 pScrn->videoRam = (((tom >> 16) - 1629 (tom & 0xffff) + 1) << 6); 1630 1631 OUTREG(RADEON_CONFIG_MEMSIZE, pScrn->videoRam * 1024); 1632 } else { 1633 if (info->ChipFamily >= CHIP_FAMILY_R600) 1634 pScrn->videoRam = INREG(R600_CONFIG_MEMSIZE) / 1024; 1635 else { 1636 /* Read VRAM size from card */ 1637 pScrn->videoRam = INREG(RADEON_CONFIG_MEMSIZE) / 1024; 1638 1639 /* Some production boards of m6 will return 0 if it's 8 MB */ 1640 if (pScrn->videoRam == 0) { 1641 pScrn->videoRam = 8192; 1642 OUTREG(RADEON_CONFIG_MEMSIZE, 0x800000); 1643 } 1644 } 1645 } 1646 1647 /* Get accessible memory */ 1648 accessible = RADEONGetAccessibleVRAM(pScrn); 1649 1650 /* Crop it to the size of the PCI BAR */ 1651 bar_size = PCI_REGION_SIZE(info->PciInfo, 0) / 1024; 1652 if (bar_size == 0) 1653 bar_size = 0x20000; 1654 if (accessible > bar_size) 1655 accessible = bar_size; 1656 1657 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1658 "Detected total video RAM=%dK, accessible=%uK (PCI BAR=%uK)\n", 1659 pScrn->videoRam, (unsigned)accessible, (unsigned)bar_size); 1660 if (pScrn->videoRam > accessible) 1661 pScrn->videoRam = accessible; 1662 1663 if (!IS_AVIVO_VARIANT) { 1664 info->MemCntl = INREG(RADEON_SDRAM_MODE_REG); 1665 info->BusCntl = INREG(RADEON_BUS_CNTL); 1666 } 1667 1668 RADEONGetVRamType(pScrn); 1669 1670 if (dev->videoRam) { 1671 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1672 "Video RAM override, using %d kB instead of %d kB\n", 1673 dev->videoRam, 1674 pScrn->videoRam); 1675 from = X_CONFIG; 1676 pScrn->videoRam = dev->videoRam; 1677 } 1678 1679 xf86DrvMsg(pScrn->scrnIndex, from, 1680 "Mapped VideoRAM: %d kByte (%d bit %s SDRAM)\n", pScrn->videoRam, info->RamWidth, info->IsDDR?"DDR":"SDR"); 1681 1682 if (info->IsPrimary) { 1683 pScrn->videoRam /= 2; 1684 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1685 "Using %dk of videoram for primary head\n", 1686 pScrn->videoRam); 1687 } 1688 1689 if (info->IsSecondary) { 1690 pScrn->videoRam /= 2; 1691 info->LinearAddr += pScrn->videoRam * 1024; 1692 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1693 "Using %dk of videoram for secondary head\n", 1694 pScrn->videoRam); 1695 } 1696 1697 pScrn->videoRam &= ~1023; 1698 info->FbMapSize = pScrn->videoRam * 1024; 1699 1700 /* if the card is PCI Express reserve the last 32k for the gart table */ 1701#ifdef XF86DRI 1702 if (info->cardType == CARD_PCIE && info->directRenderingEnabled) 1703 /* work out the size of pcie aperture */ 1704 info->FbSecureSize = RADEONDRIGetPciAperTableSize(pScrn); 1705 else 1706#endif 1707 info->FbSecureSize = 0; 1708 1709 return TRUE; 1710} 1711 1712 1713/* This is called by RADEONPreInit to handle config file overrides for 1714 * things like chipset and memory regions. Also determine memory size 1715 * and type. If memory type ever needs an override, put it in this 1716 * routine. 1717 */ 1718static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) 1719{ 1720 RADEONInfoPtr info = RADEONPTR(pScrn); 1721 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1722 EntityInfoPtr pEnt = info->pEnt; 1723 GDevPtr dev = pEnt->device; 1724 unsigned char *RADEONMMIO = info->MMIO; 1725 MessageType from = X_PROBED; 1726 int i; 1727#ifdef XF86DRI 1728 const char *s; 1729 uint32_t cmd_stat; 1730#endif 1731 1732 /* Chipset */ 1733 from = X_PROBED; 1734 if (dev->chipset && *dev->chipset) { 1735 info->Chipset = xf86StringToToken(RADEONChipsets, dev->chipset); 1736 from = X_CONFIG; 1737 } else if (dev->chipID >= 0) { 1738 info->Chipset = dev->chipID; 1739 from = X_CONFIG; 1740 } else { 1741 info->Chipset = PCI_DEV_DEVICE_ID(info->PciInfo); 1742 } 1743 1744 pScrn->chipset = (char *)xf86TokenToString(RADEONChipsets, info->Chipset); 1745 if (!pScrn->chipset) { 1746 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1747 "ChipID 0x%04x is not recognized\n", info->Chipset); 1748 return FALSE; 1749 } 1750 if (info->Chipset < 0) { 1751 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1752 "Chipset \"%s\" is not recognized\n", pScrn->chipset); 1753 return FALSE; 1754 } 1755 xf86DrvMsg(pScrn->scrnIndex, from, 1756 "Chipset: \"%s\" (ChipID = 0x%04x)\n", 1757 pScrn->chipset, 1758 info->Chipset); 1759 1760 pRADEONEnt->HasCRTC2 = TRUE; 1761 info->IsMobility = FALSE; 1762 info->IsIGP = FALSE; 1763 info->IsDellServer = FALSE; 1764 info->HasSingleDAC = FALSE; 1765 info->InternalTVOut = TRUE; 1766 info->get_hardcoded_edid_from_bios = FALSE; 1767 1768 for (i = 0; i < sizeof(RADEONCards) / sizeof(RADEONCardInfo); i++) { 1769 if (info->Chipset == RADEONCards[i].pci_device_id) { 1770 RADEONCardInfo *card = &RADEONCards[i]; 1771 info->ChipFamily = card->chip_family; 1772 info->IsMobility = card->mobility; 1773 info->IsIGP = card->igp; 1774 pRADEONEnt->HasCRTC2 = !card->nocrtc2; 1775 info->HasSingleDAC = card->singledac; 1776 info->InternalTVOut = !card->nointtvout; 1777 break; 1778 } 1779 } 1780 1781 switch (info->Chipset) { 1782 case PCI_CHIP_RN50_515E: /* RN50 is based on the RV100 but 3D isn't guaranteed to work. YMMV. */ 1783 case PCI_CHIP_RN50_5969: 1784 /* Some Sun servers have a hardcoded edid so KVMs work properly */ 1785 if ((PCI_SUB_VENDOR_ID(info->PciInfo) == 0x108e) && 1786 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x4133)) 1787 info->get_hardcoded_edid_from_bios = TRUE; 1788 case PCI_CHIP_RV100_QY: 1789 case PCI_CHIP_RV100_QZ: 1790 /* DELL triple-head configuration. */ 1791 if ((PCI_SUB_VENDOR_ID(info->PciInfo) == PCI_VENDOR_DELL) && 1792 ((PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016c) || 1793 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016d) || 1794 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016e) || 1795 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016f) || 1796 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0170) || 1797 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x017d) || 1798 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x017e) || 1799 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0183) || 1800 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x018a) || 1801 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x019a))) { 1802 info->IsDellServer = TRUE; 1803 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "DELL server detected, force to special setup\n"); 1804 } 1805 break; 1806 case PCI_CHIP_RS482_5974: 1807 /* RH BZ 444586 - non mobility version 1808 * Dell appear to have the Vostro 1100 with a mobility part with the same pci-id */ 1809 if ((PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1462) && 1810 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x7141)) { 1811 info->IsMobility = FALSE; 1812 } 1813 default: 1814 break; 1815 } 1816 1817 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1818 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1819 "R600 support is mostly incomplete and very experimental\n"); 1820 } 1821 1822 if ((info->ChipFamily >= CHIP_FAMILY_RV515) && (info->ChipFamily < CHIP_FAMILY_R600)) { 1823 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1824 "R500 support is under development. Please report any issues to xorg-driver-ati@lists.x.org\n"); 1825 } 1826 1827 from = X_PROBED; 1828 info->LinearAddr = PCI_REGION_BASE(info->PciInfo, 0, REGION_MEM) & ~0x1ffffffULL; 1829 pScrn->memPhysBase = info->LinearAddr; 1830 if (dev->MemBase) { 1831 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1832 "Linear address override, using 0x%016lx instead of 0x%016llx\n", 1833 dev->MemBase, 1834 info->LinearAddr); 1835 info->LinearAddr = dev->MemBase; 1836 from = X_CONFIG; 1837 } else if (!info->LinearAddr) { 1838 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1839 "No valid linear framebuffer address\n"); 1840 return FALSE; 1841 } 1842 xf86DrvMsg(pScrn->scrnIndex, from, 1843 "Linear framebuffer at 0x%016llx\n", info->LinearAddr); 1844 1845#ifndef XSERVER_LIBPCIACCESS 1846 /* BIOS */ 1847 from = X_PROBED; 1848 info->BIOSAddr = info->PciInfo->biosBase & 0xfffe0000; 1849 if (dev->BiosBase) { 1850 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1851 "BIOS address override, using 0x%08lx instead of 0x%08lx\n", 1852 (unsigned long)dev->BiosBase, 1853 (unsigned long)info->BIOSAddr); 1854 info->BIOSAddr = dev->BiosBase; 1855 from = X_CONFIG; 1856 } 1857 if (info->BIOSAddr) { 1858 xf86DrvMsg(pScrn->scrnIndex, from, 1859 "BIOS at 0x%08lx\n", (unsigned long)info->BIOSAddr); 1860 } 1861#endif 1862 1863 /* Read registers used to determine options */ 1864 /* Check chip errata */ 1865 info->ChipErrata = 0; 1866 1867 if (info->ChipFamily == CHIP_FAMILY_R300 && 1868 (INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) 1869 == RADEON_CFG_ATI_REV_A11) 1870 info->ChipErrata |= CHIP_ERRATA_R300_CG; 1871 1872 if (info->ChipFamily == CHIP_FAMILY_RV200 || 1873 info->ChipFamily == CHIP_FAMILY_RS200) 1874 info->ChipErrata |= CHIP_ERRATA_PLL_DUMMYREADS; 1875 1876 if (info->ChipFamily == CHIP_FAMILY_RV100 || 1877 info->ChipFamily == CHIP_FAMILY_RS100 || 1878 info->ChipFamily == CHIP_FAMILY_RS200) 1879 info->ChipErrata |= CHIP_ERRATA_PLL_DELAY; 1880 1881#ifdef XF86DRI 1882 /* AGP/PCI */ 1883 /* Proper autodetection of an AGP capable device requires examining 1884 * PCI config registers to determine if the device implements extended 1885 * PCI capabilities, and then walking the capability list as indicated 1886 * in the PCI 2.2 and AGP 2.0 specifications, to determine if AGP 1887 * capability is present. The procedure is outlined as follows: 1888 * 1889 * 1) Test bit 4 (CAP_LIST) of the PCI status register of the device 1890 * to determine wether or not this device implements any extended 1891 * capabilities. If this bit is zero, then the device is a PCI 2.1 1892 * or earlier device and is not AGP capable, and we can conclude it 1893 * to be a PCI device. 1894 * 1895 * 2) If bit 4 of the status register is set, then the device implements 1896 * extended capabilities. There is an 8 bit wide capabilities pointer 1897 * register located at offset 0x34 in PCI config space which points to 1898 * the first capability in a linked list of extended capabilities that 1899 * this device implements. The lower two bits of this register are 1900 * reserved and MBZ so must be masked out. 1901 * 1902 * 3) The extended capabilities list is formed by one or more extended 1903 * capabilities structures which are aligned on DWORD boundaries. 1904 * The first byte of the structure is the capability ID (CAP_ID) 1905 * indicating what extended capability this structure refers to. The 1906 * second byte of the structure is an offset from the beginning of 1907 * PCI config space pointing to the next capability in the linked 1908 * list (NEXT_PTR) or NULL (0x00) at the end of the list. The lower 1909 * two bits of this pointer are reserved and MBZ. By examining the 1910 * CAP_ID of each capability and walking through the list, we will 1911 * either find the AGP_CAP_ID (0x02) indicating this device is an 1912 * AGP device, or we'll reach the end of the list, indicating it is 1913 * a PCI device. 1914 * 1915 * Mike A. Harris <mharris@redhat.com> 1916 * 1917 * References: 1918 * - PCI Local Bus Specification Revision 2.2, Chapter 6 1919 * - AGP Interface Specification Revision 2.0, Section 6.1.5 1920 */ 1921 1922 info->cardType = CARD_PCI; 1923 1924 PCI_READ_LONG(info->PciInfo, &cmd_stat, PCI_CMD_STAT_REG); 1925 if (cmd_stat & RADEON_CAP_LIST) { 1926 uint32_t cap_ptr, cap_id; 1927 1928 PCI_READ_LONG(info->PciInfo, &cap_ptr, RADEON_CAPABILITIES_PTR_PCI_CONFIG); 1929 cap_ptr &= RADEON_CAP_PTR_MASK; 1930 1931 while(cap_ptr != RADEON_CAP_ID_NULL) { 1932 PCI_READ_LONG(info->PciInfo, &cap_id, cap_ptr); 1933 if ((cap_id & 0xff)== RADEON_CAP_ID_AGP) { 1934 info->cardType = CARD_AGP; 1935 break; 1936 } 1937 if ((cap_id & 0xff)== RADEON_CAP_ID_EXP) { 1938 info->cardType = CARD_PCIE; 1939 break; 1940 } 1941 cap_ptr = (cap_id >> 8) & RADEON_CAP_PTR_MASK; 1942 } 1943 } 1944 1945 1946 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s card detected\n", 1947 (info->cardType==CARD_PCI) ? "PCI" : 1948 (info->cardType==CARD_PCIE) ? "PCIE" : "AGP"); 1949 1950 /* treat PCIE IGP cards as PCI */ 1951 if (info->cardType == CARD_PCIE && info->IsIGP) 1952 info->cardType = CARD_PCI; 1953 1954 if ((info->ChipFamily >= CHIP_FAMILY_R600) && info->IsIGP) 1955 info->cardType = CARD_PCIE; 1956 1957 /* not sure about gart table requirements */ 1958 if ((info->ChipFamily == CHIP_FAMILY_RS600) && info->IsIGP) 1959 info->cardType = CARD_PCIE; 1960 1961 if ((s = xf86GetOptValString(info->Options, OPTION_BUS_TYPE))) { 1962 if (strcmp(s, "AGP") == 0) { 1963 info->cardType = CARD_AGP; 1964 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into AGP mode\n"); 1965 } else if (strcmp(s, "PCI") == 0) { 1966 info->cardType = CARD_PCI; 1967 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI mode\n"); 1968 } else if (strcmp(s, "PCIE") == 0) { 1969 info->cardType = CARD_PCIE; 1970 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI Express mode\n"); 1971 } else { 1972 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, 1973 "Invalid BusType option, using detected type\n"); 1974 } 1975 } 1976#endif 1977 xf86GetOptValBool(info->Options, OPTION_SHOWCACHE, &info->showCache); 1978 if (info->showCache) 1979 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, 1980 "Option ShowCache enabled\n"); 1981 1982#ifdef RENDER 1983 info->RenderAccel = xf86ReturnOptValBool(info->Options, OPTION_RENDER_ACCEL, 1984 info->Chipset != PCI_CHIP_RN50_515E && 1985 info->Chipset != PCI_CHIP_RN50_5969); 1986#endif 1987 1988 info->r4xx_atom = FALSE; 1989 if (((info->ChipFamily == CHIP_FAMILY_R420) || (info->ChipFamily == CHIP_FAMILY_RV410)) && 1990 xf86ReturnOptValBool(info->Options, OPTION_R4XX_ATOM, FALSE)) { 1991 info->r4xx_atom = TRUE; 1992 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Using ATOMBIOS for R4xx chip\n"); 1993 } 1994 1995 return TRUE; 1996} 1997 1998 1999static void RADEONPreInitDDC(ScrnInfoPtr pScrn) 2000{ 2001 RADEONInfoPtr info = RADEONPTR(pScrn); 2002 /* vbeInfoPtr pVbe; */ 2003 2004 info->ddc1 = FALSE; 2005 info->ddc_bios = FALSE; 2006 if (!xf86LoadSubModule(pScrn, "ddc")) { 2007 info->ddc2 = FALSE; 2008 } else { 2009 info->ddc2 = TRUE; 2010 } 2011 2012 /* DDC can use I2C bus */ 2013 /* Load I2C if we have the code to use it */ 2014 if (info->ddc2) { 2015 xf86LoadSubModule(pScrn, "i2c"); 2016 } 2017} 2018 2019/* This is called by RADEONPreInit to initialize gamma correction */ 2020static Bool RADEONPreInitGamma(ScrnInfoPtr pScrn) 2021{ 2022 Gamma zeros = { 0.0, 0.0, 0.0 }; 2023 2024 if (!xf86SetGamma(pScrn, zeros)) return FALSE; 2025 return TRUE; 2026} 2027 2028/* This is called by RADEONPreInit to initialize the hardware cursor */ 2029static Bool RADEONPreInitCursor(ScrnInfoPtr pScrn) 2030{ 2031 RADEONInfoPtr info = RADEONPTR(pScrn); 2032 2033 if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { 2034 if (!xf86LoadSubModule(pScrn, "ramdac")) return FALSE; 2035 } 2036 return TRUE; 2037} 2038 2039/* This is called by RADEONPreInit to initialize hardware acceleration */ 2040static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) 2041{ 2042 RADEONInfoPtr info = RADEONPTR(pScrn); 2043 MessageType from; 2044#if defined(USE_EXA) && defined(USE_XAA) 2045 char *optstr; 2046#endif 2047 2048 if (!(info->accel_state = xcalloc(1, sizeof(struct radeon_accel_state)))) { 2049 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to allocate accel_state rec!\n"); 2050 return FALSE; 2051 } 2052 info->accel_state->fifo_slots = 0; 2053 2054 if ((info->ChipFamily == CHIP_FAMILY_RS100) || 2055 (info->ChipFamily == CHIP_FAMILY_RS200) || 2056 (info->ChipFamily == CHIP_FAMILY_RS300) || 2057 (info->ChipFamily == CHIP_FAMILY_RS400) || 2058 (info->ChipFamily == CHIP_FAMILY_RS480) || 2059 (info->ChipFamily == CHIP_FAMILY_RS600) || 2060 (info->ChipFamily == CHIP_FAMILY_RS690) || 2061 (info->ChipFamily == CHIP_FAMILY_RS740)) 2062 info->accel_state->has_tcl = FALSE; 2063 else { 2064 info->accel_state->has_tcl = TRUE; 2065 } 2066 2067 info->useEXA = FALSE; 2068 2069 if (info->ChipFamily >= CHIP_FAMILY_R600) { 2070 xf86DrvMsg(pScrn->scrnIndex, X_DEFAULT, 2071 "Will attempt to use R6xx/R7xx EXA support if DRI is enabled.\n"); 2072 info->useEXA = TRUE; 2073 } 2074 2075 if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { 2076 int errmaj = 0, errmin = 0; 2077 2078 from = X_DEFAULT; 2079#if defined(USE_EXA) 2080#if defined(USE_XAA) 2081 optstr = (char *)xf86GetOptValString(info->Options, OPTION_ACCELMETHOD); 2082 if (optstr != NULL) { 2083 if (xf86NameCmp(optstr, "EXA") == 0) { 2084 from = X_CONFIG; 2085 info->useEXA = TRUE; 2086 } else if (xf86NameCmp(optstr, "XAA") == 0) { 2087 from = X_CONFIG; 2088 } 2089 } 2090#else /* USE_XAA */ 2091 info->useEXA = TRUE; 2092#endif /* !USE_XAA */ 2093#endif /* USE_EXA */ 2094 if (info->ChipFamily < CHIP_FAMILY_R600) 2095 xf86DrvMsg(pScrn->scrnIndex, from, 2096 "Using %s acceleration architecture\n", 2097 info->useEXA ? "EXA" : "XAA"); 2098 2099#ifdef USE_EXA 2100 if (info->useEXA) { 2101 info->exaReq.majorversion = EXA_VERSION_MAJOR; 2102 info->exaReq.minorversion = EXA_VERSION_MINOR; 2103 2104 if (!LoadSubModule(pScrn->module, "exa", NULL, NULL, NULL, 2105 &info->exaReq, &errmaj, &errmin)) { 2106 LoaderErrorMsg(NULL, "exa", errmaj, errmin); 2107 return FALSE; 2108 } 2109 } 2110#endif /* USE_EXA */ 2111#ifdef USE_XAA 2112 if (!info->useEXA) { 2113 info->xaaReq.majorversion = 1; 2114 info->xaaReq.minorversion = 2; 2115 2116 if (!LoadSubModule(pScrn->module, "xaa", NULL, NULL, NULL, 2117 &info->xaaReq, &errmaj, &errmin)) { 2118 info->xaaReq.minorversion = 1; 2119 2120 if (!LoadSubModule(pScrn->module, "xaa", NULL, NULL, NULL, 2121 &info->xaaReq, &errmaj, &errmin)) { 2122 info->xaaReq.minorversion = 0; 2123 2124 if (!LoadSubModule(pScrn->module, "xaa", NULL, NULL, NULL, 2125 &info->xaaReq, &errmaj, &errmin)) { 2126 LoaderErrorMsg(NULL, "xaa", errmaj, errmin); 2127 return FALSE; 2128 } 2129 } 2130 } 2131 } 2132#endif /* USE_XAA */ 2133 } 2134 2135 return TRUE; 2136} 2137 2138static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10) 2139{ 2140#if (!defined(__powerpc__) && !defined(__sparc__)) || \ 2141 (defined(XSERVER_LIBPCIACCESS) && HAVE_PCI_DEVICE_ENABLE) 2142 RADEONInfoPtr info = RADEONPTR(pScrn); 2143#endif 2144#if !defined(__powerpc__) && !defined(__sparc__) 2145 unsigned char *RADEONMMIO = info->MMIO; 2146 uint32_t fp2_gen_ctl_save = 0; 2147#endif 2148 2149#ifdef XSERVER_LIBPCIACCESS 2150#if HAVE_PCI_DEVICE_ENABLE 2151 pci_device_enable(info->PciInfo); 2152#endif 2153#endif 2154 2155#if !defined(__powerpc__) && !defined(__sparc__) 2156 /* don't need int10 on atom cards. 2157 * in theory all radeons, but the older stuff 2158 * isn't 100% yet 2159 * secondary atom cards tend to hang when initializing int10, 2160 * however, on some stom cards, you can't read the bios without 2161 * intitializing int10. 2162 */ 2163 if (!xf86ReturnOptValBool(info->Options, OPTION_INT10, TRUE)) 2164 return TRUE; 2165 2166 if (xf86LoadSubModule(pScrn, "int10")) { 2167 /* The VGA BIOS on the RV100/QY cannot be read when the digital output 2168 * is enabled. Clear and restore FP2_ON around int10 to avoid this. 2169 */ 2170 if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) { 2171 fp2_gen_ctl_save = INREG(RADEON_FP2_GEN_CNTL); 2172 if (fp2_gen_ctl_save & RADEON_FP2_ON) { 2173 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "disabling digital out\n"); 2174 OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_ctl_save & ~RADEON_FP2_ON); 2175 } 2176 } 2177 2178 xf86DrvMsg(pScrn->scrnIndex,X_INFO,"initializing int10\n"); 2179 *ppInt10 = xf86InitInt10(info->pEnt->index); 2180 2181 if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) { 2182 if (fp2_gen_ctl_save & RADEON_FP2_ON) { 2183 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "re-enabling digital out\n"); 2184 OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_ctl_save); 2185 } 2186 } 2187 } 2188#endif 2189 return TRUE; 2190} 2191 2192#ifdef XF86DRI 2193static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) 2194{ 2195 RADEONInfoPtr info = RADEONPTR(pScrn); 2196 MessageType from; 2197 char *reason; 2198 2199 info->directRenderingEnabled = FALSE; 2200 info->directRenderingInited = FALSE; 2201 2202 if (!(info->dri = xcalloc(1, sizeof(struct radeon_dri)))) { 2203 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate dri rec!\n"); 2204 return FALSE; 2205 } 2206 2207 if (!(info->cp = xcalloc(1, sizeof(struct radeon_cp)))) { 2208 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate cp rec!\n"); 2209 return FALSE; 2210 } 2211 info->cp->CPInUse = FALSE; 2212 info->cp->CPStarted = FALSE; 2213 info->cp->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT; 2214 2215 if (xf86IsEntityShared(info->pEnt->index)) { 2216 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2217 "Direct Rendering Disabled -- " 2218 "Zaphod Dual-head configuration is not working with " 2219 "DRI at present.\n" 2220 "Please use the xrandr 1.2 if you " 2221 "want Dual-head with DRI.\n"); 2222 return FALSE; 2223 } 2224 if (info->IsSecondary) 2225 return FALSE; 2226 2227 if (info->Chipset == PCI_CHIP_RN50_515E || 2228 info->Chipset == PCI_CHIP_RN50_5969) { 2229 if (xf86ReturnOptValBool(info->Options, OPTION_DRI, FALSE)) { 2230 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2231 "Direct rendering for RN50 forced on -- " 2232 "This is NOT officially supported at the hardware level " 2233 "and may cause instability or lockups\n"); 2234 } else { 2235 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2236 "Direct rendering not officially supported on RN50\n"); 2237 return FALSE; 2238 } 2239 } 2240 2241 if (info->ChipFamily == CHIP_FAMILY_RS880) 2242 return FALSE; 2243 2244 if (!xf86ReturnOptValBool(info->Options, OPTION_DRI, TRUE)) { 2245 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2246 "Direct rendering forced off\n"); 2247 return FALSE; 2248 } 2249 2250 if (xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { 2251 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2252 "[dri] Acceleration disabled, not initializing the DRI\n"); 2253 return FALSE; 2254 } 2255 2256 info->dri->pLibDRMVersion = NULL; 2257 info->dri->pKernelDRMVersion = NULL; 2258 2259 if (!RADEONDRIGetVersion(pScrn)) 2260 return FALSE; 2261 2262 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2263 "[dri] Found DRI library version %d.%d.%d and kernel" 2264 " module version %d.%d.%d\n", 2265 info->dri->pLibDRMVersion->version_major, 2266 info->dri->pLibDRMVersion->version_minor, 2267 info->dri->pLibDRMVersion->version_patchlevel, 2268 info->dri->pKernelDRMVersion->version_major, 2269 info->dri->pKernelDRMVersion->version_minor, 2270 info->dri->pKernelDRMVersion->version_patchlevel); 2271 2272 if (info->Chipset == PCI_CHIP_RS400_5A41 || 2273 info->Chipset == PCI_CHIP_RS400_5A42 || 2274 info->Chipset == PCI_CHIP_RC410_5A61 || 2275 info->Chipset == PCI_CHIP_RC410_5A62 || 2276 info->Chipset == PCI_CHIP_RS480_5954 || 2277 info->Chipset == PCI_CHIP_RS480_5955 || 2278 info->Chipset == PCI_CHIP_RS482_5974 || 2279 info->Chipset == PCI_CHIP_RS485_5975) { 2280 2281 if (info->dri->pKernelDRMVersion->version_minor < 27) { 2282 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2283 "Direct rendering broken on XPRESS 200 and 200M with DRI less than 1.27\n"); 2284 return FALSE; 2285 } 2286 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2287 "Direct rendering experimental on RS400/Xpress 200 enabled\n"); 2288 } 2289 2290 if (info->ChipFamily >= CHIP_FAMILY_R300) 2291 info->dri->gartSize = R300_DEFAULT_GART_SIZE; 2292 else 2293 info->dri->gartSize = RADEON_DEFAULT_GART_SIZE; 2294 2295 info->dri->ringSize = RADEON_DEFAULT_RING_SIZE; 2296 info->dri->bufSize = RADEON_DEFAULT_BUFFER_SIZE; 2297 info->dri->gartTexSize = RADEON_DEFAULT_GART_TEX_SIZE; 2298 info->dri->pciAperSize = RADEON_DEFAULT_PCI_APER_SIZE; 2299 info->cp->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT; 2300 2301 if ((xf86GetOptValInteger(info->Options, 2302 OPTION_GART_SIZE, (int *)&(info->dri->gartSize))) || 2303 (xf86GetOptValInteger(info->Options, 2304 OPTION_GART_SIZE_OLD, (int *)&(info->dri->gartSize)))) { 2305 switch (info->dri->gartSize) { 2306 case 4: 2307 case 8: 2308 case 16: 2309 case 32: 2310 case 64: 2311 case 128: 2312 case 256: 2313 break; 2314 2315 default: 2316 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2317 "Illegal GART size: %d MB\n", info->dri->gartSize); 2318 return FALSE; 2319 } 2320 } 2321 2322 if (xf86GetOptValInteger(info->Options, 2323 OPTION_RING_SIZE, &(info->dri->ringSize))) { 2324 if (info->dri->ringSize < 1 || info->dri->ringSize >= (int)info->dri->gartSize) { 2325 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2326 "Illegal ring buffer size: %d MB\n", 2327 info->dri->ringSize); 2328 return FALSE; 2329 } 2330 } 2331 2332 if (xf86GetOptValInteger(info->Options, 2333 OPTION_PCIAPER_SIZE, &(info->dri->pciAperSize))) { 2334 switch(info->dri->pciAperSize) { 2335 case 32: 2336 case 64: 2337 case 128: 2338 case 256: 2339 break; 2340 default: 2341 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2342 "Illegal pci aper size: %d MB\n", 2343 info->dri->pciAperSize); 2344 return FALSE; 2345 } 2346 } 2347 2348 2349 if (xf86GetOptValInteger(info->Options, 2350 OPTION_BUFFER_SIZE, &(info->dri->bufSize))) { 2351 if (info->dri->bufSize < 1 || info->dri->bufSize >= (int)info->dri->gartSize) { 2352 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2353 "Illegal vertex/indirect buffers size: %d MB\n", 2354 info->dri->bufSize); 2355 return FALSE; 2356 } 2357 if (info->dri->bufSize > 2) { 2358 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2359 "Illegal vertex/indirect buffers size: %d MB\n", 2360 info->dri->bufSize); 2361 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2362 "Clamping vertex/indirect buffers size to 2 MB\n"); 2363 info->dri->bufSize = 2; 2364 } 2365 } 2366 2367 if (info->dri->ringSize + info->dri->bufSize + info->dri->gartTexSize > 2368 (int)info->dri->gartSize) { 2369 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2370 "Buffers are too big for requested GART space\n"); 2371 return FALSE; 2372 } 2373 2374 info->dri->gartTexSize = info->dri->gartSize - (info->dri->ringSize + info->dri->bufSize); 2375 2376 if (xf86GetOptValInteger(info->Options, OPTION_USEC_TIMEOUT, 2377 &(info->cp->CPusecTimeout))) { 2378 /* This option checked by the RADEON DRM kernel module */ 2379 } 2380 2381 /* Two options to try and squeeze as much texture memory as possible 2382 * for dedicated 3d rendering boxes 2383 */ 2384 info->dri->noBackBuffer = xf86ReturnOptValBool(info->Options, 2385 OPTION_NO_BACKBUFFER, 2386 FALSE); 2387 2388 info->dri->allowPageFlip = 0; 2389 2390#ifdef DAMAGE 2391 if (info->dri->noBackBuffer) { 2392 from = X_DEFAULT; 2393 reason = " because back buffer disabled"; 2394 } else { 2395 from = xf86GetOptValBool(info->Options, OPTION_PAGE_FLIP, 2396 &info->dri->allowPageFlip) ? X_CONFIG : X_DEFAULT; 2397 2398 if (IS_AVIVO_VARIANT) { 2399 info->dri->allowPageFlip = 0; 2400 reason = " on r5xx and newer chips.\n"; 2401 } else { 2402 reason = ""; 2403 } 2404 2405 } 2406#else 2407 from = X_DEFAULT; 2408 reason = " because Damage layer not available at build time"; 2409#endif 2410 2411 xf86DrvMsg(pScrn->scrnIndex, from, "Page Flipping %sabled%s\n", 2412 info->dri->allowPageFlip ? "en" : "dis", reason); 2413 2414 /* AGP seems to have problems with gart transfers */ 2415 if ((info->ChipFamily >= CHIP_FAMILY_R600) && (info->cardType == CARD_AGP)) 2416 info->DMAForXv = FALSE; 2417 else 2418 info->DMAForXv = TRUE; 2419 from = xf86GetOptValBool(info->Options, OPTION_XV_DMA, &info->DMAForXv) 2420 ? X_CONFIG : X_INFO; 2421 xf86DrvMsg(pScrn->scrnIndex, from, 2422 "Will %stry to use DMA for Xv image transfers\n", 2423 info->DMAForXv ? "" : "not "); 2424 2425 return TRUE; 2426} 2427#endif /* XF86DRI */ 2428 2429static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) 2430{ 2431 RADEONInfoPtr info = RADEONPTR(pScrn); 2432 2433 info->allowColorTiling = xf86ReturnOptValBool(info->Options, 2434 OPTION_COLOR_TILING, TRUE); 2435 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { 2436 /* this may be 4096 on r4xx -- need to double check */ 2437 info->MaxSurfaceWidth = 3968; /* one would have thought 4096...*/ 2438 info->MaxLines = 4096; 2439 } else { 2440 info->MaxSurfaceWidth = 2048; 2441 info->MaxLines = 2048; 2442 } 2443 2444 if (!info->allowColorTiling) 2445 return; 2446 2447 if (info->ChipFamily >= CHIP_FAMILY_R600) 2448 info->allowColorTiling = FALSE; 2449 2450 /* for zaphod disable tiling for now */ 2451 if (info->IsPrimary || info->IsSecondary) 2452 info->allowColorTiling = FALSE; 2453 2454#ifdef XF86DRI 2455 if (info->directRenderingEnabled && 2456 info->dri->pKernelDRMVersion->version_minor < 14) { 2457 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2458 "[dri] color tiling disabled because of version " 2459 "mismatch.\n" 2460 "[dri] radeon.o kernel module version is %d.%d.%d but " 2461 "1.14.0 or later is required for color tiling.\n", 2462 info->dri->pKernelDRMVersion->version_major, 2463 info->dri->pKernelDRMVersion->version_minor, 2464 info->dri->pKernelDRMVersion->version_patchlevel); 2465 info->allowColorTiling = FALSE; 2466 return; 2467 } 2468#endif /* XF86DRI */ 2469 2470 if (info->allowColorTiling) { 2471 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Color tiling enabled by default\n"); 2472 } else { 2473 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Color tiling disabled\n"); 2474 } 2475} 2476 2477 2478static Bool RADEONPreInitXv(ScrnInfoPtr pScrn) 2479{ 2480 RADEONInfoPtr info = RADEONPTR(pScrn); 2481 uint16_t mm_table; 2482 uint16_t bios_header; 2483 uint16_t pll_info_block; 2484#ifdef XvExtension 2485 char* microc_path = NULL; 2486 char* microc_type = NULL; 2487 MessageType from; 2488 2489 if (xf86GetOptValInteger(info->Options, OPTION_VIDEO_KEY, 2490 &(info->videoKey))) { 2491 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "video key set to 0x%x\n", 2492 info->videoKey); 2493 } else { 2494 info->videoKey = 0x1E; 2495 } 2496 2497 if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_CRYSTAL, &(info->RageTheatreCrystal))) { 2498 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre Crystal frequency was specified as %d.%d Mhz\n", 2499 info->RageTheatreCrystal/100, info->RageTheatreCrystal % 100); 2500 } else { 2501 info->RageTheatreCrystal=-1; 2502 } 2503 2504 if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_TUNER_PORT, &(info->RageTheatreTunerPort))) { 2505 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre tuner port was specified as %d\n", 2506 info->RageTheatreTunerPort); 2507 } else { 2508 info->RageTheatreTunerPort=-1; 2509 } 2510 2511 if(info->RageTheatreTunerPort>5){ 2512 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to assign Rage Theatre tuner port to invalid value. Disabling setting\n"); 2513 info->RageTheatreTunerPort=-1; 2514 } 2515 2516 if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_COMPOSITE_PORT, &(info->RageTheatreCompositePort))) { 2517 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre composite port was specified as %d\n", 2518 info->RageTheatreCompositePort); 2519 } else { 2520 info->RageTheatreCompositePort=-1; 2521 } 2522 2523 if(info->RageTheatreCompositePort>6){ 2524 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to assign Rage Theatre composite port to invalid value. Disabling setting\n"); 2525 info->RageTheatreCompositePort=-1; 2526 } 2527 2528 if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_SVIDEO_PORT, &(info->RageTheatreSVideoPort))) { 2529 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre SVideo Port was specified as %d\n", 2530 info->RageTheatreSVideoPort); 2531 } else { 2532 info->RageTheatreSVideoPort=-1; 2533 } 2534 2535 if(info->RageTheatreSVideoPort>6){ 2536 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to assign Rage Theatre SVideo port to invalid value. Disabling setting\n"); 2537 info->RageTheatreSVideoPort=-1; 2538 } 2539 2540 if(xf86GetOptValInteger(info->Options, OPTION_TUNER_TYPE, &(info->tunerType))) { 2541 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Tuner type was specified as %d\n", 2542 info->tunerType); 2543 } else { 2544 info->tunerType=-1; 2545 } 2546 2547 if(info->tunerType>31){ 2548 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to set tuner type to invalid value. Disabling setting\n"); 2549 info->tunerType=-1; 2550 } 2551 2552 if((microc_path = xf86GetOptValString(info->Options, OPTION_RAGE_THEATRE_MICROC_PATH)) != NULL) 2553 { 2554 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre Microcode path was specified as %s\n", microc_path); 2555 info->RageTheatreMicrocPath = microc_path; 2556 } else { 2557 info->RageTheatreMicrocPath= NULL; 2558 } 2559 2560 if((microc_type = xf86GetOptValString(info->Options, OPTION_RAGE_THEATRE_MICROC_TYPE)) != NULL) 2561 { 2562 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre Microcode type was specified as %s\n", microc_type); 2563 info->RageTheatreMicrocType = microc_type; 2564 } else { 2565 info->RageTheatreMicrocType= NULL; 2566 } 2567 2568 if(xf86GetOptValInteger(info->Options, OPTION_SCALER_WIDTH, &(info->overlay_scaler_buffer_width))) { 2569 if ((info->overlay_scaler_buffer_width < 1024) || 2570 (info->overlay_scaler_buffer_width > 2048) || 2571 ((info->overlay_scaler_buffer_width % 64) != 0)) { 2572 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to set illegal scaler width. Using default\n"); 2573 from = X_DEFAULT; 2574 info->overlay_scaler_buffer_width = 0; 2575 } else 2576 from = X_CONFIG; 2577 } else { 2578 from = X_DEFAULT; 2579 info->overlay_scaler_buffer_width = 0; 2580 } 2581 if (!info->overlay_scaler_buffer_width) { 2582 /* overlay scaler line length differs for different revisions 2583 this needs to be maintained by hand */ 2584 switch(info->ChipFamily){ 2585 case CHIP_FAMILY_R200: 2586 case CHIP_FAMILY_R300: 2587 case CHIP_FAMILY_RV350: 2588 info->overlay_scaler_buffer_width = 1920; 2589 break; 2590 default: 2591 info->overlay_scaler_buffer_width = 1536; 2592 } 2593 } 2594 xf86DrvMsg(pScrn->scrnIndex, from, "Assuming overlay scaler buffer width is %d\n", 2595 info->overlay_scaler_buffer_width); 2596#endif 2597 2598 /* Rescue MM_TABLE before VBIOS is freed */ 2599 info->MM_TABLE_valid = FALSE; 2600 2601 if((info->VBIOS==NULL)||(info->VBIOS[0]!=0x55)||(info->VBIOS[1]!=0xaa)){ 2602 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Cannot access BIOS or it is not valid.\n" 2603 "\t\tIf your card is TV-in capable you will need to specify options RageTheatreCrystal, RageTheatreTunerPort, \n" 2604 "\t\tRageTheatreSVideoPort and TunerType in /etc/X11/xorg.conf.\n" 2605 ); 2606 info->MM_TABLE_valid = FALSE; 2607 return TRUE; 2608 } 2609 2610 bios_header=info->VBIOS[0x48]; 2611 bios_header+=(((int)info->VBIOS[0x49]+0)<<8); 2612 2613 mm_table=info->VBIOS[bios_header+0x38]; 2614 if(mm_table==0) 2615 { 2616 xf86DrvMsg(pScrn->scrnIndex,X_INFO,"No MM_TABLE found - assuming CARD is not TV-in capable.\n"); 2617 info->MM_TABLE_valid = FALSE; 2618 return TRUE; 2619 } 2620 mm_table+=(((int)info->VBIOS[bios_header+0x39]+0)<<8)-2; 2621 2622 if(mm_table>0) 2623 { 2624 memcpy(&(info->MM_TABLE), &(info->VBIOS[mm_table]), sizeof(info->MM_TABLE)); 2625 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "MM_TABLE: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 2626 info->MM_TABLE.table_revision, 2627 info->MM_TABLE.table_size, 2628 info->MM_TABLE.tuner_type, 2629 info->MM_TABLE.audio_chip, 2630 info->MM_TABLE.product_id, 2631 info->MM_TABLE.tuner_voltage_teletext_fm, 2632 info->MM_TABLE.i2s_config, 2633 info->MM_TABLE.video_decoder_type, 2634 info->MM_TABLE.video_decoder_host_config, 2635 info->MM_TABLE.input[0], 2636 info->MM_TABLE.input[1], 2637 info->MM_TABLE.input[2], 2638 info->MM_TABLE.input[3], 2639 info->MM_TABLE.input[4]); 2640 2641 /* Is it an MM_TABLE we know about ? */ 2642 if(info->MM_TABLE.table_size != 0xc){ 2643 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "This card has MM_TABLE we do not recognize.\n" 2644 "\t\tIf your card is TV-in capable you will need to specify options RageTheatreCrystal, RageTheatreTunerPort, \n" 2645 "\t\tRageTheatreSVideoPort and TunerType in /etc/X11/xorg.conf.\n" 2646 ); 2647 info->MM_TABLE_valid = FALSE; 2648 return TRUE; 2649 } 2650 info->MM_TABLE_valid = TRUE; 2651 } else { 2652 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "No MM_TABLE found - assuming card is not TV-in capable (mm_table=%d).\n", mm_table); 2653 info->MM_TABLE_valid = FALSE; 2654 } 2655 2656 pll_info_block=info->VBIOS[bios_header+0x30]; 2657 pll_info_block+=(((int)info->VBIOS[bios_header+0x31]+0)<<8); 2658 2659 info->video_decoder_type=info->VBIOS[pll_info_block+0x08]; 2660 info->video_decoder_type+=(((int)info->VBIOS[pll_info_block+0x09]+0)<<8); 2661 2662 return TRUE; 2663} 2664 2665static Bool 2666RADEONPreInitBIOS(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) 2667{ 2668 RADEONInfoPtr info = RADEONPTR(pScrn); 2669 2670 if (!RADEONGetBIOSInfo(pScrn, pInt10)) { 2671 /* Avivo chips require bios for atom */ 2672 if (IS_AVIVO_VARIANT) 2673 return FALSE; 2674 } 2675 return TRUE; 2676} 2677 2678static void RADEONFixZaphodOutputs(ScrnInfoPtr pScrn) 2679{ 2680 RADEONInfoPtr info = RADEONPTR(pScrn); 2681 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 2682 2683 if (info->IsPrimary) { 2684 xf86OutputDestroy(config->output[0]); 2685 while(config->num_output > 1) { 2686 xf86OutputDestroy(config->output[1]); 2687 } 2688 } else { 2689 while(config->num_output > 1) { 2690 xf86OutputDestroy(config->output[1]); 2691 } 2692 } 2693} 2694 2695static Bool RADEONPreInitControllers(ScrnInfoPtr pScrn) 2696{ 2697 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 2698 RADEONInfoPtr info = RADEONPTR(pScrn); 2699 int i; 2700 int mask; 2701 int found = 0; 2702 2703 if (!info->IsPrimary && !info->IsSecondary) 2704 mask = 3; 2705 else if (info->IsPrimary) 2706 mask = 1; 2707 else 2708 mask = 2; 2709 2710 if (!RADEONAllocateControllers(pScrn, mask)) 2711 return FALSE; 2712 2713 RADEONGetClockInfo(pScrn); 2714 2715 if (!RADEONSetupConnectors(pScrn)) { 2716 return FALSE; 2717 } 2718 2719 if (info->IsPrimary || info->IsSecondary) { 2720 /* fixup outputs for zaphod */ 2721 RADEONFixZaphodOutputs(pScrn); 2722 } 2723 2724 RADEONPrintPortMap(pScrn); 2725 2726 info->first_load_no_devices = FALSE; 2727 for (i = 0; i < config->num_output; i++) { 2728 xf86OutputPtr output = config->output[i]; 2729 2730 output->status = (*output->funcs->detect) (output); 2731 ErrorF("finished output detect: %d\n", i); 2732 if (info->IsPrimary || info->IsSecondary) { 2733 if (output->status != XF86OutputStatusConnected) 2734 return FALSE; 2735 } 2736 if (output->status != XF86OutputStatusDisconnected) 2737 found++; 2738 } 2739 2740 if (!found) { 2741 /* nothing connected, light up some defaults so the server comes up */ 2742 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No connected devices found!\n"); 2743 info->first_load_no_devices = TRUE; 2744 } 2745 2746 ErrorF("finished all detect\n"); 2747 return TRUE; 2748} 2749 2750static void 2751RADEONProbeDDC(ScrnInfoPtr pScrn, int indx) 2752{ 2753 vbeInfoPtr pVbe; 2754 2755 if (xf86LoadSubModule(pScrn, "vbe")) { 2756 pVbe = VBEInit(NULL,indx); 2757 ConfiguredMonitor = vbeDoEDID(pVbe, NULL); 2758 } 2759} 2760 2761static Bool 2762RADEONCRTCResize(ScrnInfoPtr scrn, int width, int height) 2763{ 2764 scrn->virtualX = width; 2765 scrn->virtualY = height; 2766 /* RADEONSetPitch(scrn); */ 2767 return TRUE; 2768} 2769 2770static const xf86CrtcConfigFuncsRec RADEONCRTCResizeFuncs = { 2771 RADEONCRTCResize 2772}; 2773 2774Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) 2775{ 2776 xf86CrtcConfigPtr xf86_config; 2777 RADEONInfoPtr info; 2778 xf86Int10InfoPtr pInt10 = NULL; 2779 void *int10_save = NULL; 2780 const char *s; 2781 int crtc_max_X, crtc_max_Y; 2782 RADEONEntPtr pRADEONEnt; 2783 DevUnion* pPriv; 2784 2785 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2786 "RADEONPreInit\n"); 2787 if (pScrn->numEntities != 1) return FALSE; 2788 2789 if (!RADEONGetRec(pScrn)) return FALSE; 2790 2791 info = RADEONPTR(pScrn); 2792 info->MMIO = NULL; 2793 2794 info->IsSecondary = FALSE; 2795 info->IsPrimary = FALSE; 2796 2797 info->pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]); 2798 if (info->pEnt->location.type != BUS_PCI) goto fail; 2799 2800 pPriv = xf86GetEntityPrivate(pScrn->entityList[0], 2801 getRADEONEntityIndex()); 2802 pRADEONEnt = pPriv->ptr; 2803 2804 if(xf86IsEntityShared(pScrn->entityList[0])) 2805 { 2806 if(xf86IsPrimInitDone(pScrn->entityList[0])) 2807 { 2808 info->IsSecondary = TRUE; 2809 pRADEONEnt->pSecondaryScrn = pScrn; 2810 info->SavedReg = &pRADEONEnt->SavedReg; 2811 info->ModeReg = &pRADEONEnt->ModeReg; 2812 } 2813 else 2814 { 2815 info->IsPrimary = TRUE; 2816 xf86SetPrimInitDone(pScrn->entityList[0]); 2817 pRADEONEnt->pPrimaryScrn = pScrn; 2818 pRADEONEnt->HasSecondary = FALSE; 2819 info->SavedReg = &pRADEONEnt->SavedReg; 2820 info->ModeReg = &pRADEONEnt->ModeReg; 2821 } 2822 } else { 2823 info->SavedReg = &pRADEONEnt->SavedReg; 2824 info->ModeReg = &pRADEONEnt->ModeReg; 2825 } 2826 2827 info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index); 2828 info->PciTag = pciTag(PCI_DEV_BUS(info->PciInfo), 2829 PCI_DEV_DEV(info->PciInfo), 2830 PCI_DEV_FUNC(info->PciInfo)); 2831 info->MMIOAddr = PCI_REGION_BASE(info->PciInfo, 2, REGION_MEM) & ~0xffULL; 2832 info->MMIOSize = PCI_REGION_SIZE(info->PciInfo, 2); 2833 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TOTO SAYS %016llx\n", 2834 (unsigned long long)PCI_REGION_BASE(info->PciInfo, 2835 2, REGION_MEM)); 2836 if (info->pEnt->device->IOBase) { 2837 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, 2838 "MMIO address override, using 0x%08lx instead of 0x%016llx\n", 2839 info->pEnt->device->IOBase, 2840 info->MMIOAddr); 2841 info->MMIOAddr = info->pEnt->device->IOBase; 2842 } else if (!info->MMIOAddr) { 2843 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid MMIO address\n"); 2844 goto fail1; 2845 } 2846 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2847 "MMIO registers at 0x%016llx: size %ldKB\n", info->MMIOAddr, info->MMIOSize / 1024); 2848 2849 if(!RADEONMapMMIO(pScrn)) { 2850 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2851 "Memory map the MMIO region failed\n"); 2852 goto fail1; 2853 } 2854 2855#if !defined(__alpha__) 2856 if ( 2857#ifndef XSERVER_LIBPCIACCESS 2858 xf86GetPciDomain(info->PciTag) || 2859#endif 2860 !xf86IsPrimaryPci(info->PciInfo)) 2861 RADEONPreInt10Save(pScrn, &int10_save); 2862#else 2863 /* [Alpha] On the primary, the console already ran the BIOS and we're 2864 * going to run it again - so make sure to "fix up" the card 2865 * so that (1) we can read the BIOS ROM and (2) the BIOS will 2866 * get the memory config right. 2867 */ 2868 RADEONPreInt10Save(pScrn, &int10_save); 2869#endif 2870 2871 if (flags & PROBE_DETECT) { 2872 RADEONProbeDDC(pScrn, info->pEnt->index); 2873 RADEONPostInt10Check(pScrn, int10_save); 2874 if(info->MMIO) RADEONUnmapMMIO(pScrn); 2875 return TRUE; 2876 } 2877 2878 2879 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2880 "PCI bus %d card %d func %d\n", 2881 PCI_DEV_BUS(info->PciInfo), 2882 PCI_DEV_DEV(info->PciInfo), 2883 PCI_DEV_FUNC(info->PciInfo)); 2884 2885 if (xf86RegisterResources(info->pEnt->index, 0, ResExclusive)) 2886 goto fail; 2887 2888 xf86SetOperatingState(resVga, info->pEnt->index, ResUnusedOpr); 2889 2890 pScrn->racMemFlags = RAC_FB | RAC_COLORMAP | RAC_VIEWPORT | RAC_CURSOR; 2891 pScrn->monitor = pScrn->confScreen->monitor; 2892 2893 /* Allocate an xf86CrtcConfig */ 2894 xf86CrtcConfigInit (pScrn, &RADEONCRTCResizeFuncs); 2895 xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 2896 2897 2898 if (!RADEONPreInitVisual(pScrn)) 2899 goto fail; 2900 2901 /* We can't do this until we have a 2902 pScrn->display. */ 2903 xf86CollectOptions(pScrn, NULL); 2904 if (!(info->Options = xalloc(sizeof(RADEONOptions)))) 2905 goto fail; 2906 2907 memcpy(info->Options, RADEONOptions, sizeof(RADEONOptions)); 2908 xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options); 2909 2910 /* By default, don't do VGA IOs on ppc/sparc */ 2911#if defined(__powerpc__) || defined(__sparc__) || !defined(WITH_VGAHW) 2912 info->VGAAccess = FALSE; 2913#else 2914 info->VGAAccess = TRUE; 2915#endif 2916 2917#ifdef WITH_VGAHW 2918 xf86GetOptValBool(info->Options, OPTION_VGA_ACCESS, &info->VGAAccess); 2919 if (info->VGAAccess) { 2920 if (!xf86LoadSubModule(pScrn, "vgahw")) 2921 info->VGAAccess = FALSE; 2922 else { 2923 if (!vgaHWGetHWRec(pScrn)) 2924 info->VGAAccess = FALSE; 2925 } 2926 if (!info->VGAAccess) 2927 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Loading VGA module failed," 2928 " trying to run without it\n"); 2929 } else 2930 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VGAAccess option set to FALSE," 2931 " VGA module load skipped\n"); 2932 if (info->VGAAccess) 2933 vgaHWGetIOBase(VGAHWPTR(pScrn)); 2934#endif 2935 2936 2937 if (!RADEONPreInitWeight(pScrn)) 2938 goto fail; 2939 2940 info->DispPriority = 1; 2941 if ((s = xf86GetOptValString(info->Options, OPTION_DISP_PRIORITY))) { 2942 if (strcmp(s, "AUTO") == 0) { 2943 info->DispPriority = 1; 2944 } else if (strcmp(s, "BIOS") == 0) { 2945 info->DispPriority = 0; 2946 } else if (strcmp(s, "HIGH") == 0) { 2947 info->DispPriority = 2; 2948 } else 2949 info->DispPriority = 1; 2950 } 2951 2952 if (!RADEONPreInitChipType(pScrn)) 2953 goto fail; 2954 2955 if (!RADEONPreInitInt10(pScrn, &pInt10)) 2956 goto fail; 2957 2958 RADEONPostInt10Check(pScrn, int10_save); 2959 2960 if (!RADEONPreInitBIOS(pScrn, pInt10)) 2961 goto fail; 2962 2963 /* Save BIOS scratch registers */ 2964 RADEONSaveBIOSRegisters(pScrn, info->SavedReg); 2965 2966#ifdef XF86DRI 2967 /* PreInit DRI first of all since we need that for getting a proper 2968 * memory map 2969 */ 2970 info->directRenderingEnabled = RADEONPreInitDRI(pScrn); 2971#endif 2972 if (!info->directRenderingEnabled) { 2973 if (info->ChipFamily >= CHIP_FAMILY_R600) { 2974 info->r600_shadow_fb = TRUE; 2975 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2976 "using shadow framebuffer\n"); 2977 if (!xf86LoadSubModule(pScrn, "shadow")) 2978 info->r600_shadow_fb = FALSE; 2979 } 2980 } 2981 2982 if (!RADEONPreInitVRAM(pScrn)) 2983 goto fail; 2984 2985 RADEONPreInitColorTiling(pScrn); 2986 2987 /* we really need an FB manager... */ 2988 if (pScrn->display->virtualX) { 2989 crtc_max_X = pScrn->display->virtualX; 2990 crtc_max_Y = pScrn->display->virtualY; 2991 if (info->allowColorTiling) { 2992 if (crtc_max_X > info->MaxSurfaceWidth || 2993 crtc_max_Y > info->MaxLines) { 2994 info->allowColorTiling = FALSE; 2995 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2996 "Requested desktop size exceeds surface limts for tiling, ColorTiling disabled\n"); 2997 } 2998 } 2999 if (crtc_max_X > 8192) 3000 crtc_max_X = 8192; 3001 if (crtc_max_Y > 8192) 3002 crtc_max_Y = 8192; 3003 } else { 3004 /* 3005 * note that these aren't really the CRTC limits, they're just 3006 * heuristics until we have a better memory manager. 3007 */ 3008 if (pScrn->videoRam <= 16384) { 3009 crtc_max_X = 1600; 3010 crtc_max_Y = 1200; 3011 } else if (IS_R300_VARIANT) { 3012 crtc_max_X = 2560; 3013 crtc_max_Y = 1200; 3014 } else if (IS_AVIVO_VARIANT) { 3015 crtc_max_X = 2560; 3016 crtc_max_Y = 1600; 3017 } else { 3018 crtc_max_X = 2048; 3019 crtc_max_Y = 1200; 3020 } 3021 } 3022 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Max desktop size set to %dx%d\n", 3023 crtc_max_X, crtc_max_Y); 3024 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3025 "For a larger or smaller max desktop size, add a Virtual line to your xorg.conf\n"); 3026 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3027 "If you are having trouble with 3D, " 3028 "reduce the desktop size by adjusting the Virtual line to your xorg.conf\n"); 3029 3030 /*xf86CrtcSetSizeRange (pScrn, 320, 200, info->MaxSurfaceWidth, info->MaxLines);*/ 3031 xf86CrtcSetSizeRange (pScrn, 320, 200, crtc_max_X, crtc_max_Y); 3032 3033 RADEONPreInitDDC(pScrn); 3034 3035 if (!RADEONPreInitControllers(pScrn)) 3036 goto fail; 3037 3038 3039 ErrorF("before xf86InitialConfiguration\n"); 3040 3041 if (!xf86InitialConfiguration (pScrn, FALSE)) 3042 { 3043 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid modes.\n"); 3044 goto fail; 3045 } 3046 3047 /* fix up cloning on rn50 cards 3048 * since they only have one crtc sometimes the xserver doesn't assign 3049 * a crtc to one of the outputs even though both outputs have common modes 3050 * which results in only one monitor being enabled. Assign a crtc here so 3051 * that both outputs light up. 3052 */ 3053 if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) { 3054 int i; 3055 3056 for (i = 0; i < xf86_config->num_output; i++) { 3057 xf86OutputPtr output = xf86_config->output[i]; 3058 3059 /* XXX: double check crtc mode */ 3060 if ((output->probed_modes != NULL) && (output->crtc == NULL)) 3061 output->crtc = xf86_config->crtc[0]; 3062 } 3063 } 3064 3065 ErrorF("after xf86InitialConfiguration\n"); 3066 3067 RADEONSetPitch(pScrn); 3068 3069 /* Set display resolution */ 3070 xf86SetDpi(pScrn, 0, 0); 3071 3072 /* Get ScreenInit function */ 3073 if (!xf86LoadSubModule(pScrn, "fb")) return FALSE; 3074 3075 if (!RADEONPreInitGamma(pScrn)) goto fail; 3076 3077 if (!RADEONPreInitCursor(pScrn)) goto fail; 3078 3079 if (!RADEONPreInitAccel(pScrn)) goto fail; 3080 3081 if (!IS_AVIVO_VARIANT) { 3082 if (!RADEONPreInitXv(pScrn)) goto fail; 3083 } 3084 3085 if (!xf86RandR12PreInit (pScrn)) 3086 { 3087 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "RandR initialization failure\n"); 3088 goto fail; 3089 } 3090 3091 if (pScrn->modes == NULL) { 3092 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No modes.\n"); 3093 goto fail; 3094 } 3095 3096 3097 /* Free int10 info */ 3098 if (pInt10) 3099 xf86FreeInt10(pInt10); 3100 3101 if(info->MMIO) RADEONUnmapMMIO(pScrn); 3102 info->MMIO = NULL; 3103 3104 xf86DrvMsg(pScrn->scrnIndex, X_NOTICE, 3105 "For information on using the multimedia capabilities\n\tof this" 3106 " adapter, please see http://gatos.sf.net.\n"); 3107 3108 xf86DrvMsg(pScrn->scrnIndex, X_NOTICE, 3109 "MergedFB support has been removed and replaced with" 3110 " xrandr 1.2 support\n"); 3111 3112 return TRUE; 3113 3114fail: 3115 /* Pre-init failed. */ 3116 /* Free the video bios (if applicable) */ 3117 if (info->VBIOS) { 3118 xfree(info->VBIOS); 3119 info->VBIOS = NULL; 3120 } 3121 3122 /* Free int10 info */ 3123 if (pInt10) 3124 xf86FreeInt10(pInt10); 3125 3126#ifdef WITH_VGAHW 3127 if (info->VGAAccess) 3128 vgaHWFreeHWRec(pScrn); 3129#endif 3130 3131 if(info->MMIO) RADEONUnmapMMIO(pScrn); 3132 info->MMIO = NULL; 3133 3134 fail1: 3135 RADEONFreeRec(pScrn); 3136 3137 return FALSE; 3138} 3139 3140/* Load a palette */ 3141static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors, 3142 int *indices, LOCO *colors, VisualPtr pVisual) 3143{ 3144 RADEONInfoPtr info = RADEONPTR(pScrn); 3145 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 3146 int i; 3147 int index, j; 3148 uint16_t lut_r[256], lut_g[256], lut_b[256]; 3149 int c; 3150 3151#ifdef XF86DRI 3152 if (info->cp->CPStarted && pScrn->pScreen) DRILock(pScrn->pScreen, 0); 3153#endif 3154 3155 if (info->accelOn && pScrn->pScreen) 3156 RADEON_SYNC(info, pScrn); 3157 3158 { 3159 3160 for (c = 0; c < xf86_config->num_crtc; c++) { 3161 xf86CrtcPtr crtc = xf86_config->crtc[c]; 3162 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 3163 3164 for (i = 0 ; i < 256; i++) { 3165 lut_r[i] = radeon_crtc->lut_r[i] << 6; 3166 lut_g[i] = radeon_crtc->lut_g[i] << 6; 3167 lut_b[i] = radeon_crtc->lut_b[i] << 6; 3168 } 3169 3170 switch (info->CurrentLayout.depth) { 3171 case 15: 3172 for (i = 0; i < numColors; i++) { 3173 index = indices[i]; 3174 for (j = 0; j < 8; j++) { 3175 lut_r[index * 8 + j] = colors[index].red << 6; 3176 lut_g[index * 8 + j] = colors[index].green << 6; 3177 lut_b[index * 8 + j] = colors[index].blue << 6; 3178 } 3179 } 3180 case 16: 3181 for (i = 0; i < numColors; i++) { 3182 index = indices[i]; 3183 3184 if (i <= 31) { 3185 for (j = 0; j < 8; j++) { 3186 lut_r[index * 8 + j] = colors[index].red << 6; 3187 lut_b[index * 8 + j] = colors[index].blue << 6; 3188 } 3189 } 3190 3191 for (j = 0; j < 4; j++) { 3192 lut_g[index * 4 + j] = colors[index].green << 6; 3193 } 3194 } 3195 default: 3196 for (i = 0; i < numColors; i++) { 3197 index = indices[i]; 3198 lut_r[index] = colors[index].red << 6; 3199 lut_g[index] = colors[index].green << 6; 3200 lut_b[index] = colors[index].blue << 6; 3201 } 3202 break; 3203 } 3204 3205 /* Make the change through RandR */ 3206#ifdef RANDR_12_INTERFACE 3207 if (crtc->randr_crtc) 3208 RRCrtcGammaSet(crtc->randr_crtc, lut_r, lut_g, lut_b); 3209 else 3210#endif 3211 crtc->funcs->gamma_set(crtc, lut_r, lut_g, lut_b, 256); 3212 } 3213 } 3214 3215#ifdef XF86DRI 3216 if (info->cp->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen); 3217#endif 3218} 3219 3220static void RADEONBlockHandler(int i, pointer blockData, 3221 pointer pTimeout, pointer pReadmask) 3222{ 3223 ScreenPtr pScreen = screenInfo.screens[i]; 3224 ScrnInfoPtr pScrn = xf86Screens[i]; 3225 RADEONInfoPtr info = RADEONPTR(pScrn); 3226 3227 pScreen->BlockHandler = info->BlockHandler; 3228 (*pScreen->BlockHandler) (i, blockData, pTimeout, pReadmask); 3229 pScreen->BlockHandler = RADEONBlockHandler; 3230 3231 if (info->VideoTimerCallback) 3232 (*info->VideoTimerCallback)(pScrn, currentTime.milliseconds); 3233 3234#if defined(RENDER) && defined(USE_XAA) 3235 if(info->accel_state->RenderCallback) 3236 (*info->accel_state->RenderCallback)(pScrn); 3237#endif 3238 3239#ifdef USE_EXA 3240 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; 3241#endif 3242} 3243 3244static void 3245RADEONPointerMoved(int index, int x, int y) 3246{ 3247 ScrnInfoPtr pScrn = xf86Screens[index]; 3248 RADEONInfoPtr info = RADEONPTR(pScrn); 3249 int newX = x, newY = y; 3250 3251 switch (info->rotation) { 3252 case RR_Rotate_0: 3253 break; 3254 case RR_Rotate_90: 3255 newX = y; 3256 newY = pScrn->pScreen->width - x - 1; 3257 break; 3258 case RR_Rotate_180: 3259 newX = pScrn->pScreen->width - x - 1; 3260 newY = pScrn->pScreen->height - y - 1; 3261 break; 3262 case RR_Rotate_270: 3263 newX = pScrn->pScreen->height - y - 1; 3264 newY = x; 3265 break; 3266 } 3267 3268 (*info->PointerMoved)(index, newX, newY); 3269} 3270 3271static void 3272RADEONInitBIOSRegisters(ScrnInfoPtr pScrn) 3273{ 3274 RADEONInfoPtr info = RADEONPTR(pScrn); 3275 unsigned char *RADEONMMIO = info->MMIO; 3276 RADEONSavePtr save = info->ModeReg; 3277 3278 save->bios_0_scratch = info->SavedReg->bios_0_scratch; 3279 save->bios_1_scratch = info->SavedReg->bios_1_scratch; 3280 save->bios_2_scratch = info->SavedReg->bios_2_scratch; 3281 save->bios_3_scratch = info->SavedReg->bios_3_scratch; 3282 save->bios_4_scratch = info->SavedReg->bios_4_scratch; 3283 save->bios_5_scratch = info->SavedReg->bios_5_scratch; 3284 save->bios_6_scratch = info->SavedReg->bios_6_scratch; 3285 save->bios_7_scratch = info->SavedReg->bios_7_scratch; 3286 3287 if (info->IsAtomBios) { 3288 /* let the bios control the backlight */ 3289 save->bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; 3290 /* tell the bios not to handle mode switching */ 3291 save->bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | 3292 ATOM_S6_ACC_MODE); 3293 3294 if (info->ChipFamily >= CHIP_FAMILY_R600) { 3295 OUTREG(R600_BIOS_2_SCRATCH, save->bios_2_scratch); 3296 OUTREG(R600_BIOS_6_SCRATCH, save->bios_6_scratch); 3297 } else { 3298 OUTREG(RADEON_BIOS_2_SCRATCH, save->bios_2_scratch); 3299 OUTREG(RADEON_BIOS_6_SCRATCH, save->bios_6_scratch); 3300 } 3301 } else { 3302 /* let the bios control the backlight */ 3303 save->bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; 3304 /* tell the bios not to handle mode switching */ 3305 save->bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS | 3306 RADEON_ACC_MODE_CHANGE); 3307 /* tell the bios a driver is loaded */ 3308 save->bios_7_scratch |= RADEON_DRV_LOADED; 3309 3310 OUTREG(RADEON_BIOS_0_SCRATCH, save->bios_0_scratch); 3311 OUTREG(RADEON_BIOS_6_SCRATCH, save->bios_6_scratch); 3312 //OUTREG(RADEON_BIOS_7_SCRATCH, save->bios_7_scratch); 3313 } 3314 3315} 3316 3317 3318/* Called at the start of each server generation. */ 3319Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, 3320 int argc, char **argv) 3321{ 3322 ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; 3323 RADEONInfoPtr info = RADEONPTR(pScrn); 3324 int hasDRI = 0; 3325#ifdef RENDER 3326 int subPixelOrder = SubPixelUnknown; 3327 char* s; 3328#endif 3329 3330 3331 info->accelOn = FALSE; 3332#ifdef USE_XAA 3333 info->accel_state->accel = NULL; 3334#endif 3335#ifdef XF86DRI 3336 pScrn->fbOffset = info->dri->frontOffset; 3337#endif 3338 3339 if (info->IsSecondary) pScrn->fbOffset = pScrn->videoRam * 1024; 3340#ifdef XF86DRI 3341 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3342 "RADEONScreenInit %lx %ld %d\n", 3343 pScrn->memPhysBase, pScrn->fbOffset, info->dri->frontOffset); 3344#else 3345 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3346 "RADEONScreenInit %lx %ld\n", 3347 pScrn->memPhysBase, pScrn->fbOffset); 3348#endif 3349 if (!RADEONMapMem(pScrn)) return FALSE; 3350 3351#ifdef XF86DRI 3352 info->dri->fbX = 0; 3353 info->dri->fbY = 0; 3354#endif 3355 3356 info->PaletteSavedOnVT = FALSE; 3357 3358 info->crtc_on = FALSE; 3359 info->crtc2_on = FALSE; 3360 3361 /* save the real front buffer size 3362 * it changes with randr, rotation, etc. 3363 */ 3364 info->virtualX = pScrn->virtualX; 3365 info->virtualY = pScrn->virtualY; 3366 3367 RADEONSave(pScrn); 3368 3369 /* set initial bios scratch reg state */ 3370 RADEONInitBIOSRegisters(pScrn); 3371 3372 /* blank the outputs/crtcs */ 3373 RADEONBlank(pScrn); 3374 3375 if (info->IsMobility && !IS_AVIVO_VARIANT) { 3376 if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { 3377 RADEONSetDynamicClock(pScrn, 1); 3378 } else { 3379 RADEONSetDynamicClock(pScrn, 0); 3380 } 3381 } else if (IS_AVIVO_VARIANT) { 3382 if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { 3383 atombios_static_pwrmgt_setup(pScrn, 1); 3384 atombios_dyn_clk_setup(pScrn, 1); 3385 } 3386 } 3387 3388 if (IS_R300_VARIANT || IS_RV100_VARIANT) 3389 RADEONForceSomeClocks(pScrn); 3390 3391 if (info->allowColorTiling && (pScrn->virtualX > info->MaxSurfaceWidth)) { 3392 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3393 "Color tiling not supported with virtual x resolutions larger than %d, disabling\n", 3394 info->MaxSurfaceWidth); 3395 info->allowColorTiling = FALSE; 3396 } 3397 if (info->allowColorTiling) { 3398 info->tilingEnabled = (pScrn->currentMode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; 3399 } 3400 3401 /* Visual setup */ 3402 miClearVisualTypes(); 3403 if (!miSetVisualTypes(pScrn->depth, 3404 miGetDefaultVisualMask(pScrn->depth), 3405 pScrn->rgbBits, 3406 pScrn->defaultVisual)) return FALSE; 3407 miSetPixmapDepths (); 3408 3409#ifdef XF86DRI 3410 if (info->directRenderingEnabled) { 3411 MessageType from; 3412 3413 info->dri->depthBits = pScrn->depth; 3414 3415 from = xf86GetOptValInteger(info->Options, OPTION_DEPTH_BITS, 3416 &info->dri->depthBits) 3417 ? X_CONFIG : X_DEFAULT; 3418 3419 if (info->dri->depthBits != 16 && info->dri->depthBits != 24) { 3420 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3421 "Value for Option \"DepthBits\" must be 16 or 24\n"); 3422 info->dri->depthBits = pScrn->depth; 3423 from = X_DEFAULT; 3424 } 3425 3426 xf86DrvMsg(pScrn->scrnIndex, from, 3427 "Using %d bit depth buffer\n", info->dri->depthBits); 3428 } 3429 3430 3431 hasDRI = info->directRenderingEnabled; 3432#endif /* XF86DRI */ 3433 3434 /* Initialize the memory map, this basically calculates the values 3435 * we'll use later on for MC_FB_LOCATION & MC_AGP_LOCATION 3436 */ 3437 RADEONInitMemoryMap(pScrn); 3438 3439 /* empty the surfaces */ 3440 if (info->ChipFamily < CHIP_FAMILY_R600) { 3441 unsigned char *RADEONMMIO = info->MMIO; 3442 unsigned int j; 3443 for (j = 0; j < 8; j++) { 3444 OUTREG(RADEON_SURFACE0_INFO + 16 * j, 0); 3445 OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * j, 0); 3446 OUTREG(RADEON_SURFACE0_UPPER_BOUND + 16 * j, 0); 3447 } 3448 } 3449 3450#ifdef XF86DRI 3451 /* Depth moves are disabled by default since they are extremely slow */ 3452 info->dri->depthMoves = xf86ReturnOptValBool(info->Options, 3453 OPTION_DEPTH_MOVE, FALSE); 3454 if (info->dri->depthMoves && info->allowColorTiling) { 3455 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Enabling depth moves\n"); 3456 } else if (info->dri->depthMoves) { 3457 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3458 "Depth moves don't work without color tiling, disabled\n"); 3459 info->dri->depthMoves = FALSE; 3460 } else { 3461 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3462 "Depth moves disabled by default\n"); 3463 } 3464#endif 3465 3466 /* Initial setup of surfaces */ 3467 if (info->ChipFamily < CHIP_FAMILY_R600) { 3468 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3469 "Setting up initial surfaces\n"); 3470 RADEONChangeSurfaces(pScrn); 3471 } 3472 3473 /* Memory manager setup */ 3474 3475 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3476 "Setting up accel memmap\n"); 3477 3478#ifdef USE_EXA 3479 if (info->useEXA) { 3480#ifdef XF86DRI 3481 if (hasDRI) { 3482 info->accelDFS = xf86ReturnOptValBool(info->Options, OPTION_ACCEL_DFS, 3483 info->cardType != CARD_AGP); 3484 3485 /* Reserve approx. half of offscreen memory for local textures by 3486 * default, can be overridden with Option "FBTexPercent". 3487 * Round down to a whole number of texture regions. 3488 */ 3489 info->dri->textureSize = 50; 3490 3491 if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT, 3492 &(info->dri->textureSize))) { 3493 if (info->dri->textureSize < 0 || info->dri->textureSize > 100) { 3494 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3495 "Illegal texture memory percentage: %dx, setting to default 50%%\n", 3496 info->dri->textureSize); 3497 info->dri->textureSize = 50; 3498 } 3499 } 3500 } 3501#endif /* XF86DRI */ 3502 3503 if (!RADEONSetupMemEXA(pScreen)) 3504 return FALSE; 3505 } 3506#endif 3507 3508#if defined(XF86DRI) && defined(USE_XAA) 3509 if (!info->useEXA && hasDRI) { 3510 info->dri->textureSize = -1; 3511 if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT, 3512 &(info->dri->textureSize))) { 3513 if (info->dri->textureSize < 0 || info->dri->textureSize > 100) { 3514 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3515 "Illegal texture memory percentage: %dx, using default behaviour\n", 3516 info->dri->textureSize); 3517 info->dri->textureSize = -1; 3518 } 3519 } 3520 if (!RADEONSetupMemXAA_DRI(scrnIndex, pScreen)) 3521 return FALSE; 3522 pScrn->fbOffset = info->dri->frontOffset; 3523 } 3524#endif 3525 3526#ifdef USE_XAA 3527 if (!info->useEXA && !hasDRI && !RADEONSetupMemXAA(scrnIndex, pScreen)) 3528 return FALSE; 3529#endif 3530 3531 info->accel_state->dst_pitch_offset = 3532 (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64) 3533 << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10)); 3534 3535 /* Setup DRI after visuals have been established, but before fbScreenInit is 3536 * called. fbScreenInit will eventually call the driver's InitGLXVisuals 3537 * call back. */ 3538#ifdef XF86DRI 3539 if (info->directRenderingEnabled) { 3540 /* FIXME: When we move to dynamic allocation of back and depth 3541 * buffers, we will want to revisit the following check for 3 3542 * times the virtual size of the screen below. 3543 */ 3544 int width_bytes = (pScrn->displayWidth * 3545 info->CurrentLayout.pixel_bytes); 3546 int maxy = info->FbMapSize / width_bytes; 3547 3548 if (maxy <= pScrn->virtualY * 3) { 3549 xf86DrvMsg(scrnIndex, X_ERROR, 3550 "Static buffer allocation failed. Disabling DRI.\n"); 3551 xf86DrvMsg(scrnIndex, X_ERROR, 3552 "At least %d kB of video memory needed at this " 3553 "resolution and depth.\n", 3554 (pScrn->displayWidth * pScrn->virtualY * 3555 info->CurrentLayout.pixel_bytes * 3 + 1023) / 1024); 3556 info->directRenderingEnabled = FALSE; 3557 } else { 3558 info->directRenderingEnabled = RADEONDRIScreenInit(pScreen); 3559 } 3560 } 3561 3562 /* Tell DRI about new memory map */ 3563 if (info->directRenderingEnabled && info->dri->newMemoryMap) { 3564 if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_NEW_MEMMAP, 1) < 0) { 3565 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 3566 "[drm] failed to enable new memory map\n"); 3567 RADEONDRICloseScreen(pScreen); 3568 info->directRenderingEnabled = FALSE; 3569 } 3570 } 3571#endif 3572 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3573 "Initializing fb layer\n"); 3574 3575 if (info->r600_shadow_fb) { 3576 info->fb_shadow = xcalloc(1, 3577 pScrn->displayWidth * pScrn->virtualY * 3578 ((pScrn->bitsPerPixel + 7) >> 3)); 3579 if (info->fb_shadow == NULL) { 3580 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3581 "Failed to allocate shadow framebuffer\n"); 3582 info->r600_shadow_fb = FALSE; 3583 } else { 3584 if (!fbScreenInit(pScreen, info->fb_shadow, 3585 pScrn->virtualX, pScrn->virtualY, 3586 pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, 3587 pScrn->bitsPerPixel)) 3588 return FALSE; 3589 } 3590 } 3591 3592 if (info->r600_shadow_fb == FALSE) { 3593 /* Init fb layer */ 3594 if (!fbScreenInit(pScreen, info->FB, 3595 pScrn->virtualX, pScrn->virtualY, 3596 pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, 3597 pScrn->bitsPerPixel)) 3598 return FALSE; 3599 } 3600 3601 xf86SetBlackWhitePixels(pScreen); 3602 3603 if (pScrn->bitsPerPixel > 8) { 3604 VisualPtr visual; 3605 3606 visual = pScreen->visuals + pScreen->numVisuals; 3607 while (--visual >= pScreen->visuals) { 3608 if ((visual->class | DynamicClass) == DirectColor) { 3609 visual->offsetRed = pScrn->offset.red; 3610 visual->offsetGreen = pScrn->offset.green; 3611 visual->offsetBlue = pScrn->offset.blue; 3612 visual->redMask = pScrn->mask.red; 3613 visual->greenMask = pScrn->mask.green; 3614 visual->blueMask = pScrn->mask.blue; 3615 } 3616 } 3617 } 3618 3619 /* Must be after RGB order fixed */ 3620 fbPictureInit (pScreen, 0, 0); 3621 3622#ifdef RENDER 3623 if ((s = xf86GetOptValString(info->Options, OPTION_SUBPIXEL_ORDER))) { 3624 if (strcmp(s, "RGB") == 0) subPixelOrder = SubPixelHorizontalRGB; 3625 else if (strcmp(s, "BGR") == 0) subPixelOrder = SubPixelHorizontalBGR; 3626 else if (strcmp(s, "NONE") == 0) subPixelOrder = SubPixelNone; 3627 PictureSetSubpixelOrder (pScreen, subPixelOrder); 3628 } 3629#endif 3630 3631 pScrn->vtSema = TRUE; 3632 3633 /* restore the memory map here otherwise we may get a hang when 3634 * initializing the drm below 3635 */ 3636 RADEONInitMemMapRegisters(pScrn, info->ModeReg, info); 3637 RADEONRestoreMemMapRegisters(pScrn, info->ModeReg); 3638 3639 /* Backing store setup */ 3640 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3641 "Initializing backing store\n"); 3642 miInitializeBackingStore(pScreen); 3643 xf86SetBackingStore(pScreen); 3644 3645 /* DRI finalisation */ 3646#ifdef XF86DRI 3647 if (info->directRenderingEnabled && 3648 (info->cardType==CARD_PCIE || info->cardType==CARD_PCI) && 3649 info->dri->pKernelDRMVersion->version_minor >= 19) 3650 { 3651 if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_LOCATION, info->dri->pciGartOffset) < 0) 3652 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3653 "[drm] failed set pci gart location\n"); 3654 3655 if (info->dri->pKernelDRMVersion->version_minor >= 26) { 3656 if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_TABLE_SIZE, info->dri->pciGartSize) < 0) 3657 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3658 "[drm] failed set pci gart table size\n"); 3659 } 3660 } 3661 if (info->directRenderingEnabled) { 3662 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3663 "DRI Finishing init !\n"); 3664 info->directRenderingEnabled = RADEONDRIFinishScreenInit(pScreen); 3665 } 3666 if (info->directRenderingEnabled) { 3667 /* DRI final init might have changed the memory map, we need to adjust 3668 * our local image to make sure we restore them properly on mode 3669 * changes or VT switches 3670 */ 3671 RADEONAdjustMemMapRegisters(pScrn, info->ModeReg); 3672 3673 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n"); 3674 3675 /* we might already be in tiled mode, tell drm about it */ 3676 if (info->directRenderingEnabled && info->tilingEnabled) { 3677 if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0) 3678 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3679 "[drm] failed changing tiling status\n"); 3680 } 3681 } else { 3682 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 3683 "Direct rendering disabled\n"); 3684 } 3685#endif 3686 3687 /* Make sure surfaces are allright since DRI setup may have changed them */ 3688 if (info->ChipFamily < CHIP_FAMILY_R600) { 3689 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3690 "Setting up final surfaces\n"); 3691 3692 RADEONChangeSurfaces(pScrn); 3693 } 3694 3695 3696 /* Enable aceleration */ 3697 if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { 3698 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3699 "Initializing Acceleration\n"); 3700 if (RADEONAccelInit(pScreen)) { 3701 xf86DrvMsg(scrnIndex, X_INFO, "Acceleration enabled\n"); 3702 info->accelOn = TRUE; 3703 } else { 3704 xf86DrvMsg(scrnIndex, X_ERROR, 3705 "Acceleration initialization failed\n"); 3706 xf86DrvMsg(scrnIndex, X_INFO, "Acceleration disabled\n"); 3707 info->accelOn = FALSE; 3708 } 3709 } else { 3710 xf86DrvMsg(scrnIndex, X_INFO, "Acceleration disabled\n"); 3711 info->accelOn = FALSE; 3712 } 3713 3714 /* Init DPMS */ 3715 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3716 "Initializing DPMS\n"); 3717 xf86DPMSInit(pScreen, xf86DPMSSet, 0); 3718 3719 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3720 "Initializing Cursor\n"); 3721 3722 /* Set Silken Mouse */ 3723 xf86SetSilkenMouse(pScreen); 3724 3725 /* Cursor setup */ 3726 miDCInitialize(pScreen, xf86GetPointerScreenFuncs()); 3727 3728 /* Hardware cursor setup */ 3729 if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { 3730 if (RADEONCursorInit(pScreen)) { 3731#ifdef USE_XAA 3732 if (!info->useEXA) { 3733 int width, height; 3734 3735 if (xf86QueryLargestOffscreenArea(pScreen, &width, &height, 3736 0, 0, 0)) { 3737 xf86DrvMsg(scrnIndex, X_INFO, 3738 "Largest offscreen area available: %d x %d\n", 3739 width, height); 3740 } 3741 } 3742#endif /* USE_XAA */ 3743 } else { 3744 xf86DrvMsg(scrnIndex, X_ERROR, 3745 "Hardware cursor initialization failed\n"); 3746 xf86DrvMsg(scrnIndex, X_INFO, "Using software cursor\n"); 3747 } 3748 } else { 3749 xf86DrvMsg(scrnIndex, X_INFO, "Using software cursor\n"); 3750 } 3751 3752 /* DGA setup */ 3753 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3754 "Initializing DGA\n"); 3755 RADEONDGAInit(pScreen); 3756 3757 /* Init Xv */ 3758 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3759 "Initializing Xv\n"); 3760 RADEONInitVideo(pScreen); 3761 3762 if (info->r600_shadow_fb == TRUE) { 3763 if (!shadowSetup(pScreen)) { 3764 return FALSE; 3765 } 3766 } 3767 3768 /* set the modes with desired rotation, etc. */ 3769 if (!xf86SetDesiredModes (pScrn)) 3770 return FALSE; 3771 3772 /* Provide SaveScreen & wrap BlockHandler and CloseScreen */ 3773 /* Wrap CloseScreen */ 3774 info->CloseScreen = pScreen->CloseScreen; 3775 pScreen->CloseScreen = RADEONCloseScreen; 3776 pScreen->SaveScreen = RADEONSaveScreen; 3777 info->BlockHandler = pScreen->BlockHandler; 3778 pScreen->BlockHandler = RADEONBlockHandler; 3779 info->CreateScreenResources = pScreen->CreateScreenResources; 3780 pScreen->CreateScreenResources = RADEONCreateScreenResources; 3781 3782 if (!xf86CrtcScreenInit (pScreen)) 3783 return FALSE; 3784 3785 /* Wrap pointer motion to flip touch screen around */ 3786 info->PointerMoved = pScrn->PointerMoved; 3787 pScrn->PointerMoved = RADEONPointerMoved; 3788 3789 /* Colormap setup */ 3790 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3791 "Initializing color map\n"); 3792 if (!miCreateDefColormap(pScreen)) return FALSE; 3793 /* all radeons support 10 bit CLUTs */ 3794 if (!xf86HandleColormaps(pScreen, 256, 10, 3795 RADEONLoadPalette, NULL, 3796 CMAP_PALETTED_TRUECOLOR 3797#if 0 /* This option messes up text mode! (eich@suse.de) */ 3798 | CMAP_LOAD_EVEN_IF_OFFSCREEN 3799#endif 3800 | CMAP_RELOAD_ON_MODE_SWITCH)) return FALSE; 3801 3802 /* Note unused options */ 3803 if (serverGeneration == 1) 3804 xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options); 3805 3806 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3807 "RADEONScreenInit finished\n"); 3808 3809 return TRUE; 3810} 3811 3812/* Write memory mapping registers */ 3813void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, 3814 RADEONSavePtr restore) 3815{ 3816 RADEONInfoPtr info = RADEONPTR(pScrn); 3817 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 3818 unsigned char *RADEONMMIO = info->MMIO; 3819 int timeout; 3820 uint32_t mc_fb_loc, mc_agp_loc, mc_agp_loc_hi; 3821 3822 radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &mc_fb_loc, 3823 &mc_agp_loc, &mc_agp_loc_hi); 3824 3825 if (info->IsSecondary) 3826 return; 3827 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3828 "RADEONRestoreMemMapRegisters() : \n"); 3829 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3830 " MC_FB_LOCATION : 0x%08x 0x%08x\n", 3831 (unsigned)restore->mc_fb_location, (unsigned int)mc_fb_loc); 3832 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3833 " MC_AGP_LOCATION : 0x%08x\n", 3834 (unsigned)restore->mc_agp_location); 3835 3836 if (IS_AVIVO_VARIANT) { 3837 3838 if (mc_fb_loc != restore->mc_fb_location || 3839 mc_agp_loc != restore->mc_agp_location) { 3840 uint32_t tmp; 3841 3842 RADEONWaitForIdleMMIO(pScrn); 3843 3844 OUTREG(AVIVO_D1VGA_CONTROL, INREG(AVIVO_D1VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 3845 OUTREG(AVIVO_D2VGA_CONTROL, INREG(AVIVO_D2VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 3846 3847 /* Stop display & memory access */ 3848 tmp = INREG(AVIVO_D1CRTC_CONTROL); 3849 OUTREG(AVIVO_D1CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN); 3850 3851 tmp = INREG(AVIVO_D2CRTC_CONTROL); 3852 OUTREG(AVIVO_D2CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN); 3853 3854 tmp = INREG(AVIVO_D2CRTC_CONTROL); 3855 3856 usleep(10000); 3857 timeout = 0; 3858 while (!(radeon_get_mc_idle(pScrn))) { 3859 if (++timeout > 1000000) { 3860 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3861 "Timeout trying to update memory controller settings !\n"); 3862 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3863 "You will probably crash now ... \n"); 3864 /* Nothing we can do except maybe try to kill the server, 3865 * let's wait 2 seconds to leave the above message a chance 3866 * to maybe hit the disk and continue trying to setup despite 3867 * the MC being non-idle 3868 */ 3869 usleep(2000000); 3870 } 3871 usleep(10); 3872 } 3873 3874 radeon_write_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, 3875 restore->mc_fb_location, 3876 restore->mc_agp_location, 3877 restore->mc_agp_location_hi); 3878 3879 if (info->ChipFamily < CHIP_FAMILY_R600) { 3880 OUTREG(AVIVO_HDP_FB_LOCATION, restore->mc_fb_location); 3881 } else { 3882 OUTREG(R600_HDP_NONSURFACE_BASE, (restore->mc_fb_location << 16) & 0xff0000); 3883 } 3884 3885 /* Reset the engine and HDP */ 3886 if (info->ChipFamily < CHIP_FAMILY_R600) 3887 RADEONEngineReset(pScrn); 3888 } 3889 } else { 3890 3891 /* Write memory mapping registers only if their value change 3892 * since we must ensure no access is done while they are 3893 * reprogrammed 3894 */ 3895 if (mc_fb_loc != restore->mc_fb_location || 3896 mc_agp_loc != restore->mc_agp_location) { 3897 uint32_t crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl; 3898 uint32_t old_mc_status; 3899 3900 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3901 " Map Changed ! Applying ...\n"); 3902 3903 /* Make sure engine is idle. We assume the CCE is stopped 3904 * at this point 3905 */ 3906 RADEONWaitForIdleMMIO(pScrn); 3907 3908 if (info->IsIGP) 3909 goto igp_no_mcfb; 3910 3911 /* Capture MC_STATUS in case things go wrong ... */ 3912 old_mc_status = INREG(RADEON_MC_STATUS); 3913 3914 /* Stop display & memory access */ 3915 ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL); 3916 OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE); 3917 crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL); 3918 OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS); 3919 crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); 3920 RADEONWaitForVerticalSync(pScrn); 3921 OUTREG(RADEON_CRTC_GEN_CNTL, 3922 (crtc_gen_cntl 3923 & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) 3924 | RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN); 3925 3926 if (pRADEONEnt->HasCRTC2) { 3927 crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); 3928 RADEONWaitForVerticalSync2(pScrn); 3929 OUTREG(RADEON_CRTC2_GEN_CNTL, 3930 (crtc2_gen_cntl 3931 & ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) 3932 | RADEON_CRTC2_DISP_REQ_EN_B); 3933 } 3934 3935 /* Make sure the chip settles down (paranoid !) */ 3936 usleep(100000); 3937 timeout = 0; 3938 while (!(radeon_get_mc_idle(pScrn))) { 3939 if (++timeout > 1000000) { 3940 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3941 "Timeout trying to update memory controller settings !\n"); 3942 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3943 "MC_STATUS = 0x%08x (on entry = 0x%08x)\n", 3944 (unsigned int)INREG(RADEON_MC_STATUS), (unsigned int)old_mc_status); 3945 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3946 "You will probably crash now ... \n"); 3947 /* Nothing we can do except maybe try to kill the server, 3948 * let's wait 2 seconds to leave the above message a chance 3949 * to maybe hit the disk and continue trying to setup despite 3950 * the MC being non-idle 3951 */ 3952 usleep(2000000); 3953 } 3954 usleep(10); 3955 } 3956 3957 /* Update maps, first clearing out AGP to make sure we don't get 3958 * a temporary overlap 3959 */ 3960 OUTREG(RADEON_MC_AGP_LOCATION, 0xfffffffc); 3961 OUTREG(RADEON_MC_FB_LOCATION, restore->mc_fb_location); 3962 radeon_write_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, restore->mc_fb_location, 3963 0xfffffffc, 0); 3964 igp_no_mcfb: 3965 radeon_write_mc_fb_agp_location(pScrn, LOC_AGP, 0, 3966 restore->mc_agp_location, 0); 3967 /* Make sure map fully reached the chip */ 3968 (void)INREG(RADEON_MC_FB_LOCATION); 3969 3970 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3971 " Map applied, resetting engine ...\n"); 3972 3973 /* Reset the engine and HDP */ 3974 RADEONEngineReset(pScrn); 3975 3976 /* Make sure we have sane offsets before re-enabling the CRTCs, disable 3977 * stereo, clear offsets, and wait for offsets to catch up with hw 3978 */ 3979 3980 OUTREG(RADEON_CRTC_OFFSET_CNTL, RADEON_CRTC_OFFSET_FLIP_CNTL); 3981 OUTREG(RADEON_CRTC_OFFSET, 0); 3982 OUTREG(RADEON_CUR_OFFSET, 0); 3983 timeout = 0; 3984 while(INREG(RADEON_CRTC_OFFSET) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) { 3985 if (timeout++ > 1000000) { 3986 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3987 "Timeout waiting for CRTC offset to update !\n"); 3988 break; 3989 } 3990 usleep(1000); 3991 } 3992 if (pRADEONEnt->HasCRTC2) { 3993 OUTREG(RADEON_CRTC2_OFFSET_CNTL, RADEON_CRTC2_OFFSET_FLIP_CNTL); 3994 OUTREG(RADEON_CRTC2_OFFSET, 0); 3995 OUTREG(RADEON_CUR2_OFFSET, 0); 3996 timeout = 0; 3997 while(INREG(RADEON_CRTC2_OFFSET) & RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET) { 3998 if (timeout++ > 1000000) { 3999 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4000 "Timeout waiting for CRTC2 offset to update !\n"); 4001 break; 4002 } 4003 usleep(1000); 4004 } 4005 } 4006 } 4007 4008 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 4009 "Updating display base addresses...\n"); 4010 4011 OUTREG(RADEON_DISPLAY_BASE_ADDR, restore->display_base_addr); 4012 if (pRADEONEnt->HasCRTC2) 4013 OUTREG(RADEON_DISPLAY2_BASE_ADDR, restore->display2_base_addr); 4014 OUTREG(RADEON_OV0_BASE_ADDR, restore->ov0_base_addr); 4015 (void)INREG(RADEON_OV0_BASE_ADDR); 4016 4017 /* More paranoia delays, wait 100ms */ 4018 usleep(100000); 4019 4020 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 4021 "Memory map updated.\n"); 4022 } 4023} 4024 4025#ifdef XF86DRI 4026static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) 4027{ 4028 RADEONInfoPtr info = RADEONPTR(pScrn); 4029 uint32_t fb, agp, agp_hi; 4030 int changed = 0; 4031 4032 if (info->IsSecondary) 4033 return; 4034 4035 radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &fb, &agp, &agp_hi); 4036 4037 if (fb != save->mc_fb_location || agp != save->mc_agp_location || 4038 agp_hi != save->mc_agp_location_hi) 4039 changed = 1; 4040 4041 if (changed) { 4042 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 4043 "DRI init changed memory map, adjusting ...\n"); 4044 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 4045 " MC_FB_LOCATION was: 0x%08lx is: 0x%08lx\n", 4046 (long unsigned int)info->mc_fb_location, (long unsigned int)fb); 4047 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 4048 " MC_AGP_LOCATION was: 0x%08lx is: 0x%08lx\n", 4049 (long unsigned int)info->mc_agp_location, (long unsigned int)agp); 4050 info->mc_fb_location = fb; 4051 info->mc_agp_location = agp; 4052 if (info->ChipFamily >= CHIP_FAMILY_R600) 4053 info->fbLocation = (info->mc_fb_location & 0xffff) << 24; 4054 else 4055 info->fbLocation = (info->mc_fb_location & 0xffff) << 16; 4056 4057 info->accel_state->dst_pitch_offset = 4058 (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64) 4059 << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10)); 4060 RADEONInitMemMapRegisters(pScrn, save, info); 4061 RADEONRestoreMemMapRegisters(pScrn, save); 4062 } 4063 4064#ifdef USE_EXA 4065 if (info->accelDFS || (info->ChipFamily >= CHIP_FAMILY_R600)) 4066 { 4067 drm_radeon_getparam_t gp; 4068 int gart_base; 4069 4070 memset(&gp, 0, sizeof(gp)); 4071 gp.param = RADEON_PARAM_GART_BASE; 4072 gp.value = &gart_base; 4073 4074 if (drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_GETPARAM, &gp, 4075 sizeof(gp)) < 0) { 4076 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4077 "Failed to determine GART area MC location, not using " 4078 "accelerated DownloadFromScreen hook!\n"); 4079 info->accelDFS = FALSE; 4080 } else { 4081 info->gartLocation = gart_base; 4082 } 4083 } 4084#endif /* USE_EXA */ 4085} 4086#endif 4087 4088/* restore original surface info (for fb console). */ 4089static void RADEONRestoreSurfaces(ScrnInfoPtr pScrn, RADEONSavePtr restore) 4090{ 4091 RADEONInfoPtr info = RADEONPTR(pScrn); 4092 unsigned char *RADEONMMIO = info->MMIO; 4093 unsigned int surfnr; 4094 4095 for ( surfnr = 0; surfnr < 8; surfnr++ ) { 4096 OUTREG(RADEON_SURFACE0_INFO + 16 * surfnr, restore->surfaces[surfnr][0]); 4097 OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * surfnr, restore->surfaces[surfnr][1]); 4098 OUTREG(RADEON_SURFACE0_UPPER_BOUND + 16 * surfnr, restore->surfaces[surfnr][2]); 4099 } 4100} 4101 4102/* save original surface info (for fb console). */ 4103static void RADEONSaveSurfaces(ScrnInfoPtr pScrn, RADEONSavePtr save) 4104{ 4105 RADEONInfoPtr info = RADEONPTR(pScrn); 4106 unsigned char *RADEONMMIO = info->MMIO; 4107 unsigned int surfnr; 4108 4109 for ( surfnr = 0; surfnr < 8; surfnr++ ) { 4110 save->surfaces[surfnr][0] = INREG(RADEON_SURFACE0_INFO + 16 * surfnr); 4111 save->surfaces[surfnr][1] = INREG(RADEON_SURFACE0_LOWER_BOUND + 16 * surfnr); 4112 save->surfaces[surfnr][2] = INREG(RADEON_SURFACE0_UPPER_BOUND + 16 * surfnr); 4113 } 4114} 4115 4116void RADEONChangeSurfaces(ScrnInfoPtr pScrn) 4117{ 4118 /* the idea here is to only set up front buffer as tiled, and back/depth buffer when needed. 4119 Everything else is left as untiled. This means we need to use eplicit src/dst pitch control 4120 when blitting, based on the src/target address, and can no longer use a default offset. 4121 But OTOH we don't need to dynamically change surfaces (for xv for instance), and some 4122 ugly offset / fb reservation (cursor) is gone. And as a bonus, everything actually works... 4123 For simplicity, just always update everything (just let the ioctl fail - could do better). 4124 All surface addresses are relative to RADEON_MC_FB_LOCATION */ 4125 4126 RADEONInfoPtr info = RADEONPTR(pScrn); 4127 int cpp = info->CurrentLayout.pixel_bytes; 4128 /* depth/front/back pitch must be identical (and the same as displayWidth) */ 4129 int width_bytes = pScrn->displayWidth * cpp; 4130 int bufferSize = ((((pScrn->virtualY + 15) & ~15) * width_bytes 4131 + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN); 4132 unsigned int color_pattern, swap_pattern; 4133 4134 if (!info->allowColorTiling) 4135 return; 4136 4137 swap_pattern = 0; 4138#if X_BYTE_ORDER == X_BIG_ENDIAN 4139 switch (pScrn->bitsPerPixel) { 4140 case 16: 4141 swap_pattern = RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; 4142 break; 4143 4144 case 32: 4145 swap_pattern = RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; 4146 break; 4147 } 4148#endif 4149 if (info->ChipFamily < CHIP_FAMILY_R200) { 4150 color_pattern = RADEON_SURF_TILE_COLOR_MACRO; 4151 } else if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { 4152 color_pattern = R300_SURF_TILE_COLOR_MACRO; 4153 } else { 4154 color_pattern = R200_SURF_TILE_COLOR_MACRO; 4155 } 4156#ifdef XF86DRI 4157 if (info->directRenderingInited) { 4158 drm_radeon_surface_free_t drmsurffree; 4159 drm_radeon_surface_alloc_t drmsurfalloc; 4160 int retvalue; 4161 int depthCpp = (info->dri->depthBits - 8) / 4; 4162 int depth_width_bytes = pScrn->displayWidth * depthCpp; 4163 int depthBufferSize = ((((pScrn->virtualY + 15) & ~15) * depth_width_bytes 4164 + RADEON_BUFFER_ALIGN) & ~RADEON_BUFFER_ALIGN); 4165 unsigned int depth_pattern; 4166 4167 drmsurffree.address = info->dri->frontOffset; 4168 retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_FREE, 4169 &drmsurffree, sizeof(drmsurffree)); 4170 4171 if (!((info->ChipFamily == CHIP_FAMILY_RV100) || 4172 (info->ChipFamily == CHIP_FAMILY_RS100) || 4173 (info->ChipFamily == CHIP_FAMILY_RS200))) { 4174 drmsurffree.address = info->dri->depthOffset; 4175 retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_FREE, 4176 &drmsurffree, sizeof(drmsurffree)); 4177 } 4178 4179 if (!info->dri->noBackBuffer) { 4180 drmsurffree.address = info->dri->backOffset; 4181 retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_FREE, 4182 &drmsurffree, sizeof(drmsurffree)); 4183 } 4184 4185 drmsurfalloc.size = bufferSize; 4186 drmsurfalloc.address = info->dri->frontOffset; 4187 drmsurfalloc.flags = swap_pattern; 4188 4189 if (info->tilingEnabled) { 4190 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) 4191 drmsurfalloc.flags |= (width_bytes / 8) | color_pattern; 4192 else 4193 drmsurfalloc.flags |= (width_bytes / 16) | color_pattern; 4194 } 4195 retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_ALLOC, 4196 &drmsurfalloc, sizeof(drmsurfalloc)); 4197 if (retvalue < 0) 4198 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4199 "drm: could not allocate surface for front buffer!\n"); 4200 4201 if ((info->dri->have3DWindows) && (!info->dri->noBackBuffer)) { 4202 drmsurfalloc.address = info->dri->backOffset; 4203 retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_ALLOC, 4204 &drmsurfalloc, sizeof(drmsurfalloc)); 4205 if (retvalue < 0) 4206 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4207 "drm: could not allocate surface for back buffer!\n"); 4208 } 4209 4210 if (info->ChipFamily < CHIP_FAMILY_R200) { 4211 if (depthCpp == 2) 4212 depth_pattern = RADEON_SURF_TILE_DEPTH_16BPP; 4213 else 4214 depth_pattern = RADEON_SURF_TILE_DEPTH_32BPP; 4215 } else if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { 4216 if (depthCpp == 2) 4217 depth_pattern = R300_SURF_TILE_COLOR_MACRO; 4218 else 4219 depth_pattern = R300_SURF_TILE_COLOR_MACRO | R300_SURF_TILE_DEPTH_32BPP; 4220 } else { 4221 if (depthCpp == 2) 4222 depth_pattern = R200_SURF_TILE_DEPTH_16BPP; 4223 else 4224 depth_pattern = R200_SURF_TILE_DEPTH_32BPP; 4225 } 4226 4227 /* rv100 and probably the derivative igps don't have depth tiling on all the time? */ 4228 if (info->dri->have3DWindows && 4229 (!((info->ChipFamily == CHIP_FAMILY_RV100) || 4230 (info->ChipFamily == CHIP_FAMILY_RS100) || 4231 (info->ChipFamily == CHIP_FAMILY_RS200)))) { 4232 drm_radeon_surface_alloc_t drmsurfalloc; 4233 drmsurfalloc.size = depthBufferSize; 4234 drmsurfalloc.address = info->dri->depthOffset; 4235 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) 4236 drmsurfalloc.flags = swap_pattern | (depth_width_bytes / 8) | depth_pattern; 4237 else 4238 drmsurfalloc.flags = swap_pattern | (depth_width_bytes / 16) | depth_pattern; 4239 retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_ALLOC, 4240 &drmsurfalloc, sizeof(drmsurfalloc)); 4241 if (retvalue < 0) 4242 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4243 "drm: could not allocate surface for depth buffer!\n"); 4244 } 4245 } 4246 else 4247#endif 4248 { 4249 unsigned int surf_info = swap_pattern; 4250 unsigned char *RADEONMMIO = info->MMIO; 4251 /* we don't need anything like WaitForFifo, no? */ 4252 if (info->tilingEnabled) { 4253 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) 4254 surf_info |= (width_bytes / 8) | color_pattern; 4255 else 4256 surf_info |= (width_bytes / 16) | color_pattern; 4257 } 4258 OUTREG(RADEON_SURFACE0_INFO, surf_info); 4259 OUTREG(RADEON_SURFACE0_LOWER_BOUND, 0); 4260 OUTREG(RADEON_SURFACE0_UPPER_BOUND, bufferSize - 1); 4261/* xf86DrvMsg(pScrn->scrnIndex, X_INFO, 4262 "surface0 set to %x, LB 0x%x UB 0x%x\n", 4263 surf_info, 0, bufferSize - 1024);*/ 4264 } 4265 4266 /* Update surface images */ 4267 if (info->ChipFamily < CHIP_FAMILY_R600) 4268 RADEONSaveSurfaces(pScrn, info->ModeReg); 4269} 4270 4271/* Read memory map */ 4272static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) 4273{ 4274 RADEONInfoPtr info = RADEONPTR(pScrn); 4275 unsigned char *RADEONMMIO = info->MMIO; 4276 4277 radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &save->mc_fb_location, 4278 &save->mc_agp_location, &save->mc_agp_location_hi); 4279 4280 if (!IS_AVIVO_VARIANT) { 4281 save->display_base_addr = INREG(RADEON_DISPLAY_BASE_ADDR); 4282 save->display2_base_addr = INREG(RADEON_DISPLAY2_BASE_ADDR); 4283 save->ov0_base_addr = INREG(RADEON_OV0_BASE_ADDR); 4284 } 4285} 4286 4287 4288#if 0 4289/* Read palette data */ 4290static void RADEONSavePalette(ScrnInfoPtr pScrn, RADEONSavePtr save) 4291{ 4292 RADEONInfoPtr info = RADEONPTR(pScrn); 4293 unsigned char *RADEONMMIO = info->MMIO; 4294 int i; 4295 4296#ifdef ENABLE_FLAT_PANEL 4297 /* Select palette 0 (main CRTC) if using FP-enabled chip */ 4298 /* if (info->Port1 == MT_DFP) PAL_SELECT(1); */ 4299#endif 4300 PAL_SELECT(1); 4301 INPAL_START(0); 4302 for (i = 0; i < 256; i++) save->palette2[i] = INPAL_NEXT(); 4303 PAL_SELECT(0); 4304 INPAL_START(0); 4305 for (i = 0; i < 256; i++) save->palette[i] = INPAL_NEXT(); 4306 save->palette_valid = TRUE; 4307} 4308#endif 4309 4310static void 4311avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) 4312{ 4313 RADEONInfoPtr info = RADEONPTR(pScrn); 4314 unsigned char *RADEONMMIO = info->MMIO; 4315 struct avivo_state *state = &save->avivo; 4316 int i, j; 4317 4318 // state->vga_memory_base = INREG(AVIVO_VGA_MEMORY_BASE); 4319 // state->vga_fb_start = INREG(AVIVO_VGA_FB_START); 4320 state->vga1_cntl = INREG(AVIVO_D1VGA_CONTROL); 4321 state->vga2_cntl = INREG(AVIVO_D2VGA_CONTROL); 4322 4323 state->crtc_master_en = INREG(AVIVO_DC_CRTC_MASTER_EN); 4324 state->crtc_tv_control = INREG(AVIVO_DC_CRTC_TV_CONTROL); 4325 state->dc_lb_memory_split = INREG(AVIVO_DC_LB_MEMORY_SPLIT); 4326 4327 state->pll1.ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC); 4328 state->pll1.ref_div = INREG(AVIVO_EXT1_PPLL_REF_DIV); 4329 state->pll1.fb_div = INREG(AVIVO_EXT1_PPLL_FB_DIV); 4330 state->pll1.post_div_src = INREG(AVIVO_EXT1_PPLL_POST_DIV_SRC); 4331 state->pll1.post_div = INREG(AVIVO_EXT1_PPLL_POST_DIV); 4332 state->pll1.ext_ppll_cntl = INREG(AVIVO_EXT1_PPLL_CNTL); 4333 state->pll1.pll_cntl = INREG(AVIVO_P1PLL_CNTL); 4334 state->pll1.int_ss_cntl = INREG(AVIVO_P1PLL_INT_SS_CNTL); 4335 4336 state->pll2.ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC); 4337 state->pll2.ref_div = INREG(AVIVO_EXT2_PPLL_REF_DIV); 4338 state->pll2.fb_div = INREG(AVIVO_EXT2_PPLL_FB_DIV); 4339 state->pll2.post_div_src = INREG(AVIVO_EXT2_PPLL_POST_DIV_SRC); 4340 state->pll2.post_div = INREG(AVIVO_EXT2_PPLL_POST_DIV); 4341 state->pll2.ext_ppll_cntl = INREG(AVIVO_EXT2_PPLL_CNTL); 4342 state->pll2.pll_cntl = INREG(AVIVO_P2PLL_CNTL); 4343 state->pll2.int_ss_cntl = INREG(AVIVO_P2PLL_INT_SS_CNTL); 4344 4345 state->vga25_ppll.ref_div_src = INREG(AVIVO_VGA25_PPLL_REF_DIV_SRC); 4346 state->vga25_ppll.ref_div = INREG(AVIVO_VGA25_PPLL_REF_DIV); 4347 state->vga25_ppll.fb_div = INREG(AVIVO_VGA25_PPLL_FB_DIV); 4348 state->vga25_ppll.post_div_src = INREG(AVIVO_VGA25_PPLL_POST_DIV_SRC); 4349 state->vga25_ppll.post_div = INREG(AVIVO_VGA25_PPLL_POST_DIV); 4350 state->vga25_ppll.pll_cntl = INREG(AVIVO_VGA25_PPLL_CNTL); 4351 4352 state->vga28_ppll.ref_div_src = INREG(AVIVO_VGA28_PPLL_REF_DIV_SRC); 4353 state->vga28_ppll.ref_div = INREG(AVIVO_VGA28_PPLL_REF_DIV); 4354 state->vga28_ppll.fb_div = INREG(AVIVO_VGA28_PPLL_FB_DIV); 4355 state->vga28_ppll.post_div_src = INREG(AVIVO_VGA28_PPLL_POST_DIV_SRC); 4356 state->vga28_ppll.post_div = INREG(AVIVO_VGA28_PPLL_POST_DIV); 4357 state->vga28_ppll.pll_cntl = INREG(AVIVO_VGA28_PPLL_CNTL); 4358 4359 state->vga41_ppll.ref_div_src = INREG(AVIVO_VGA41_PPLL_REF_DIV_SRC); 4360 state->vga41_ppll.ref_div = INREG(AVIVO_VGA41_PPLL_REF_DIV); 4361 state->vga41_ppll.fb_div = INREG(AVIVO_VGA41_PPLL_FB_DIV); 4362 state->vga41_ppll.post_div_src = INREG(AVIVO_VGA41_PPLL_POST_DIV_SRC); 4363 state->vga41_ppll.post_div = INREG(AVIVO_VGA41_PPLL_POST_DIV); 4364 state->vga41_ppll.pll_cntl = INREG(AVIVO_VGA41_PPLL_CNTL); 4365 4366 state->crtc1.pll_source = INREG(AVIVO_PCLK_CRTC1_CNTL); 4367 4368 state->crtc1.h_total = INREG(AVIVO_D1CRTC_H_TOTAL); 4369 state->crtc1.h_blank_start_end = INREG(AVIVO_D1CRTC_H_BLANK_START_END); 4370 state->crtc1.h_sync_a = INREG(AVIVO_D1CRTC_H_SYNC_A); 4371 state->crtc1.h_sync_a_cntl = INREG(AVIVO_D1CRTC_H_SYNC_A_CNTL); 4372 state->crtc1.h_sync_b = INREG(AVIVO_D1CRTC_H_SYNC_B); 4373 state->crtc1.h_sync_b_cntl = INREG(AVIVO_D1CRTC_H_SYNC_B_CNTL); 4374 4375 state->crtc1.v_total = INREG(AVIVO_D1CRTC_V_TOTAL); 4376 state->crtc1.v_blank_start_end = INREG(AVIVO_D1CRTC_V_BLANK_START_END); 4377 state->crtc1.v_sync_a = INREG(AVIVO_D1CRTC_V_SYNC_A); 4378 state->crtc1.v_sync_a_cntl = INREG(AVIVO_D1CRTC_V_SYNC_A_CNTL); 4379 state->crtc1.v_sync_b = INREG(AVIVO_D1CRTC_V_SYNC_B); 4380 state->crtc1.v_sync_b_cntl = INREG(AVIVO_D1CRTC_V_SYNC_B_CNTL); 4381 4382 state->crtc1.control = INREG(AVIVO_D1CRTC_CONTROL); 4383 state->crtc1.blank_control = INREG(AVIVO_D1CRTC_BLANK_CONTROL); 4384 state->crtc1.interlace_control = INREG(AVIVO_D1CRTC_INTERLACE_CONTROL); 4385 state->crtc1.stereo_control = INREG(AVIVO_D1CRTC_STEREO_CONTROL); 4386 4387 state->crtc1.cursor_control = INREG(AVIVO_D1CUR_CONTROL); 4388 4389 state->grph1.enable = INREG(AVIVO_D1GRPH_ENABLE); 4390 state->grph1.control = INREG(AVIVO_D1GRPH_CONTROL); 4391 state->grph1.control = INREG(AVIVO_D1GRPH_CONTROL); 4392 state->grph1.prim_surf_addr = INREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS); 4393 state->grph1.sec_surf_addr = INREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS); 4394 state->grph1.pitch = INREG(AVIVO_D1GRPH_PITCH); 4395 state->grph1.x_offset = INREG(AVIVO_D1GRPH_SURFACE_OFFSET_X); 4396 state->grph1.y_offset = INREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y); 4397 state->grph1.x_start = INREG(AVIVO_D1GRPH_X_START); 4398 state->grph1.y_start = INREG(AVIVO_D1GRPH_Y_START); 4399 state->grph1.x_end = INREG(AVIVO_D1GRPH_X_END); 4400 state->grph1.y_end = INREG(AVIVO_D1GRPH_Y_END); 4401 4402 state->grph1.desktop_height = INREG(AVIVO_D1MODE_DESKTOP_HEIGHT); 4403 state->grph1.viewport_start = INREG(AVIVO_D1MODE_VIEWPORT_START); 4404 state->grph1.viewport_size = INREG(AVIVO_D1MODE_VIEWPORT_SIZE); 4405 state->grph1.mode_data_format = INREG(AVIVO_D1MODE_DATA_FORMAT); 4406 4407 state->crtc2.pll_source = INREG(AVIVO_PCLK_CRTC2_CNTL); 4408 4409 state->crtc2.h_total = INREG(AVIVO_D2CRTC_H_TOTAL); 4410 state->crtc2.h_blank_start_end = INREG(AVIVO_D2CRTC_H_BLANK_START_END); 4411 state->crtc2.h_sync_a = INREG(AVIVO_D2CRTC_H_SYNC_A); 4412 state->crtc2.h_sync_a_cntl = INREG(AVIVO_D2CRTC_H_SYNC_A_CNTL); 4413 state->crtc2.h_sync_b = INREG(AVIVO_D2CRTC_H_SYNC_B); 4414 state->crtc2.h_sync_b_cntl = INREG(AVIVO_D2CRTC_H_SYNC_B_CNTL); 4415 4416 state->crtc2.v_total = INREG(AVIVO_D2CRTC_V_TOTAL); 4417 state->crtc2.v_blank_start_end = INREG(AVIVO_D2CRTC_V_BLANK_START_END); 4418 state->crtc2.v_sync_a = INREG(AVIVO_D2CRTC_V_SYNC_A); 4419 state->crtc2.v_sync_a_cntl = INREG(AVIVO_D2CRTC_V_SYNC_A_CNTL); 4420 state->crtc2.v_sync_b = INREG(AVIVO_D2CRTC_V_SYNC_B); 4421 state->crtc2.v_sync_b_cntl = INREG(AVIVO_D2CRTC_V_SYNC_B_CNTL); 4422 4423 state->crtc2.control = INREG(AVIVO_D2CRTC_CONTROL); 4424 state->crtc2.blank_control = INREG(AVIVO_D2CRTC_BLANK_CONTROL); 4425 state->crtc2.interlace_control = INREG(AVIVO_D2CRTC_INTERLACE_CONTROL); 4426 state->crtc2.stereo_control = INREG(AVIVO_D2CRTC_STEREO_CONTROL); 4427 4428 state->crtc2.cursor_control = INREG(AVIVO_D2CUR_CONTROL); 4429 4430 state->grph2.enable = INREG(AVIVO_D2GRPH_ENABLE); 4431 state->grph2.control = INREG(AVIVO_D2GRPH_CONTROL); 4432 state->grph2.control = INREG(AVIVO_D2GRPH_CONTROL); 4433 state->grph2.prim_surf_addr = INREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS); 4434 state->grph2.sec_surf_addr = INREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS); 4435 state->grph2.pitch = INREG(AVIVO_D2GRPH_PITCH); 4436 state->grph2.x_offset = INREG(AVIVO_D2GRPH_SURFACE_OFFSET_X); 4437 state->grph2.y_offset = INREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y); 4438 state->grph2.x_start = INREG(AVIVO_D2GRPH_X_START); 4439 state->grph2.y_start = INREG(AVIVO_D2GRPH_Y_START); 4440 state->grph2.x_end = INREG(AVIVO_D2GRPH_X_END); 4441 state->grph2.y_end = INREG(AVIVO_D2GRPH_Y_END); 4442 4443 state->grph2.desktop_height = INREG(AVIVO_D2MODE_DESKTOP_HEIGHT); 4444 state->grph2.viewport_start = INREG(AVIVO_D2MODE_VIEWPORT_START); 4445 state->grph2.viewport_size = INREG(AVIVO_D2MODE_VIEWPORT_SIZE); 4446 state->grph2.mode_data_format = INREG(AVIVO_D2MODE_DATA_FORMAT); 4447 4448 if (IS_DCE3_VARIANT) { 4449 /* save DVOA regs */ 4450 state->dvoa[0] = INREG(0x7080); 4451 state->dvoa[1] = INREG(0x7084); 4452 state->dvoa[2] = INREG(0x708c); 4453 state->dvoa[3] = INREG(0x7090); 4454 state->dvoa[4] = INREG(0x7094); 4455 state->dvoa[5] = INREG(0x70ac); 4456 state->dvoa[6] = INREG(0x70b0); 4457 4458 j = 0; 4459 /* save DAC regs */ 4460 for (i = 0x7000; i <= 0x7040; i += 4) { 4461 state->daca[j] = INREG(i); 4462 state->dacb[j] = INREG(i + 0x100); 4463 j++; 4464 } 4465 for (i = 0x7058; i <= 0x7060; i += 4) { 4466 state->daca[j] = INREG(i); 4467 state->dacb[j] = INREG(i + 0x100); 4468 j++; 4469 } 4470 for (i = 0x7068; i <= 0x706c; i += 4) { 4471 state->daca[j] = INREG(i); 4472 state->dacb[j] = INREG(i + 0x100); 4473 j++; 4474 } 4475 for (i = 0x7ef0; i <= 0x7ef8; i += 4) { 4476 state->daca[j] = INREG(i); 4477 state->dacb[j] = INREG(i + 0x100); 4478 j++; 4479 } 4480 state->daca[j] = INREG(0x7050); 4481 state->dacb[j] = INREG(0x7050 + 0x100); 4482 4483 j = 0; 4484 /* save FMT regs */ 4485 for (i = 0x6700; i <= 0x6744; i += 4) { 4486 state->fmt1[j] = INREG(i); 4487 state->fmt2[j] = INREG(i + 0x800); 4488 j++; 4489 } 4490 4491 j = 0; 4492 /* save DIG regs */ 4493 for (i = 0x75a0; i <= 0x75e0; i += 4) { 4494 state->dig1[j] = INREG(i); 4495 state->dig2[j] = INREG(i + 0x400); 4496 j++; 4497 } 4498 for (i = 0x75e8; i <= 0x75ec; i += 4) { 4499 state->dig1[j] = INREG(i); 4500 state->dig2[j] = INREG(i + 0x400); 4501 j++; 4502 } 4503 4504 j = 0; 4505 /* save HDMI regs */ 4506 for (i = 0x7400; i <= 0x741c; i += 4) { 4507 state->hdmi1[j] = INREG(i); 4508 state->hdmi2[j] = INREG(i + 0x400); 4509 j++; 4510 } 4511 for (i = 0x7430; i <= 0x74ec; i += 4) { 4512 state->hdmi1[j] = INREG(i); 4513 state->hdmi2[j] = INREG(i + 0x400); 4514 j++; 4515 } 4516 state->hdmi1[j] = INREG(0x7428); 4517 state->hdmi2[j] = INREG(0x7828); 4518 4519 j = 0; 4520 /* save AUX regs */ 4521 for (i = 0x7780; i <= 0x77b4; i += 4) { 4522 state->aux_cntl1[j] = INREG(i); 4523 state->aux_cntl2[j] = INREG(i + 0x040); 4524 state->aux_cntl3[j] = INREG(i + 0x400); 4525 state->aux_cntl4[j] = INREG(i + 0x440); 4526 if (IS_DCE32_VARIANT) { 4527 state->aux_cntl5[j] = INREG(i + 0x500); 4528 state->aux_cntl6[j] = INREG(i + 0x540); 4529 } 4530 j++; 4531 } 4532 4533 j = 0; 4534 /* save UNIPHY regs */ 4535 if (IS_DCE32_VARIANT) { 4536 for (i = 0x7680; i <= 0x7690; i += 4) { 4537 state->uniphy1[j] = INREG(i); 4538 state->uniphy2[j] = INREG(i + 0x20); 4539 state->uniphy3[j] = INREG(i + 0x400); 4540 state->uniphy4[j] = INREG(i + 0x420); 4541 state->uniphy5[j] = INREG(i + 0x840); 4542 state->uniphy6[j] = INREG(i + 0x940); 4543 j++; 4544 } 4545 for (i = 0x7698; i <= 0x769c; i += 4) { 4546 state->uniphy1[j] = INREG(i); 4547 state->uniphy2[j] = INREG(i + 0x20); 4548 state->uniphy3[j] = INREG(i + 0x400); 4549 state->uniphy4[j] = INREG(i + 0x420); 4550 state->uniphy5[j] = INREG(i + 0x840); 4551 state->uniphy6[j] = INREG(i + 0x940); 4552 j++; 4553 } 4554 } else { 4555 for (i = 0x7ec0; i <= 0x7edc; i += 4) { 4556 state->uniphy1[j] = INREG(i); 4557 state->uniphy2[j] = INREG(i + 0x100); 4558 j++; 4559 } 4560 } 4561 j = 0; 4562 /* save PHY,LINK regs */ 4563 for (i = 0x7f20; i <= 0x7f34; i += 4) { 4564 state->phy[j] = INREG(i); 4565 j++; 4566 } 4567 for (i = 0x7f9c; i <= 0x7fa4; i += 4) { 4568 state->phy[j] = INREG(i); 4569 j++; 4570 } 4571 state->phy[j] = INREG(0x7f40); 4572 4573 j = 0; 4574 /* save LVTMA regs */ 4575 for (i = 0x7f00; i <= 0x7f1c; i += 4) { 4576 state->lvtma[j] = INREG(i); 4577 j++; 4578 } 4579 for (i = 0x7f80; i <= 0x7f98; i += 4) { 4580 state->lvtma[j] = INREG(i); 4581 j++; 4582 } 4583 } else { 4584 j = 0; 4585 /* save DVOA regs */ 4586 for (i = 0x7980; i <= 0x79bc; i += 4) { 4587 state->dvoa[j] = INREG(i); 4588 j++; 4589 } 4590 4591 j = 0; 4592 /* save DAC regs */ 4593 for (i = 0x7800; i <= 0x782c; i += 4) { 4594 state->daca[j] = INREG(i); 4595 state->dacb[j] = INREG(i + 0x200); 4596 j++; 4597 } 4598 for (i = 0x7834; i <= 0x7840; i += 4) { 4599 state->daca[j] = INREG(i); 4600 state->dacb[j] = INREG(i + 0x200); 4601 j++; 4602 } 4603 for (i = 0x7850; i <= 0x7868; i += 4) { 4604 state->daca[j] = INREG(i); 4605 state->dacb[j] = INREG(i + 0x200); 4606 j++; 4607 } 4608 4609 j = 0; 4610 /* save TMDSA regs */ 4611 for (i = 0x7880; i <= 0x78e0; i += 4) { 4612 state->tmdsa[j] = INREG(i); 4613 j++; 4614 } 4615 for (i = 0x7904; i <= 0x7918; i += 4) { 4616 state->tmdsa[j] = INREG(i); 4617 j++; 4618 } 4619 4620 j = 0; 4621 /* save LVTMA regs */ 4622 for (i = 0x7a80; i <= 0x7b18; i += 4) { 4623 state->lvtma[j] = INREG(i); 4624 j++; 4625 } 4626 4627 if ((info->ChipFamily == CHIP_FAMILY_RS600) || 4628 (info->ChipFamily == CHIP_FAMILY_RS690) || 4629 (info->ChipFamily == CHIP_FAMILY_RS740)) { 4630 j = 0; 4631 /* save DDIA regs */ 4632 for (i = 0x7200; i <= 0x7290; i += 4) { 4633 state->ddia[j] = INREG(i); 4634 j++; 4635 } 4636 } 4637 } 4638 4639 /* scalers */ 4640 j = 0; 4641 for (i = 0x6578; i <= 0x65e4; i += 4) { 4642 state->d1scl[j] = INREG(i); 4643 state->d2scl[j] = INREG(i + 0x800); 4644 j++; 4645 } 4646 for (i = 0x6600; i <= 0x662c; i += 4) { 4647 state->d1scl[j] = INREG(i); 4648 state->d2scl[j] = INREG(i + 0x800); 4649 j++; 4650 } 4651 j = 0; 4652 for (i = 0x66e8; i <= 0x66fc; i += 4) { 4653 state->dxscl[j] = INREG(i); 4654 j++; 4655 } 4656 state->dxscl[6] = INREG(0x6e30); 4657 state->dxscl[7] = INREG(0x6e34); 4658 4659 if (state->crtc1.control & AVIVO_CRTC_EN) 4660 info->crtc_on = TRUE; 4661 4662 if (state->crtc2.control & AVIVO_CRTC_EN) 4663 info->crtc2_on = TRUE; 4664 4665} 4666 4667static void 4668avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) 4669{ 4670 RADEONInfoPtr info = RADEONPTR(pScrn); 4671 unsigned char *RADEONMMIO = info->MMIO; 4672 struct avivo_state *state = &restore->avivo; 4673 int i, j; 4674 4675 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "avivo_restore !\n"); 4676 4677 /* Disable VGA control for now.. maybe needs to be changed */ 4678 OUTREG(AVIVO_D1VGA_CONTROL, 0); 4679 OUTREG(AVIVO_D2VGA_CONTROL, 0); 4680 4681 /* Disable CRTCs */ 4682 OUTREG(AVIVO_D1CRTC_CONTROL, 4683 (INREG(AVIVO_D1CRTC_CONTROL) & ~0x300) | 0x01000000); 4684 OUTREG(AVIVO_D2CRTC_CONTROL, 4685 (INREG(AVIVO_D2CRTC_CONTROL) & ~0x300) | 0x01000000); 4686 OUTREG(AVIVO_D1CRTC_CONTROL, 4687 INREG(AVIVO_D1CRTC_CONTROL) & ~0x1); 4688 OUTREG(AVIVO_D2CRTC_CONTROL, 4689 INREG(AVIVO_D2CRTC_CONTROL) & ~0x1); 4690 OUTREG(AVIVO_D1CRTC_CONTROL, 4691 INREG(AVIVO_D1CRTC_CONTROL) | 0x100); 4692 OUTREG(AVIVO_D2CRTC_CONTROL, 4693 INREG(AVIVO_D2CRTC_CONTROL) | 0x100); 4694 4695 /* Lock graph registers */ 4696 OUTREG(AVIVO_D1GRPH_UPDATE, AVIVO_D1GRPH_UPDATE_LOCK); 4697 OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, state->grph1.prim_surf_addr); 4698 OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS, state->grph1.sec_surf_addr); 4699 OUTREG(AVIVO_D1GRPH_CONTROL, state->grph1.control); 4700 OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X, state->grph1.x_offset); 4701 OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y, state->grph1.y_offset); 4702 OUTREG(AVIVO_D1GRPH_X_START, state->grph1.x_start); 4703 OUTREG(AVIVO_D1GRPH_Y_START, state->grph1.y_start); 4704 OUTREG(AVIVO_D1GRPH_X_END, state->grph1.x_end); 4705 OUTREG(AVIVO_D1GRPH_Y_END, state->grph1.y_end); 4706 OUTREG(AVIVO_D1GRPH_PITCH, state->grph1.pitch); 4707 OUTREG(AVIVO_D1GRPH_ENABLE, state->grph1.enable); 4708 OUTREG(AVIVO_D1GRPH_UPDATE, 0); 4709 4710 OUTREG(AVIVO_D2GRPH_UPDATE, AVIVO_D1GRPH_UPDATE_LOCK); 4711 OUTREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, state->grph2.prim_surf_addr); 4712 OUTREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS, state->grph2.sec_surf_addr); 4713 OUTREG(AVIVO_D2GRPH_CONTROL, state->grph2.control); 4714 OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_X, state->grph2.x_offset); 4715 OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y, state->grph2.y_offset); 4716 OUTREG(AVIVO_D2GRPH_X_START, state->grph2.x_start); 4717 OUTREG(AVIVO_D2GRPH_Y_START, state->grph2.y_start); 4718 OUTREG(AVIVO_D2GRPH_X_END, state->grph2.x_end); 4719 OUTREG(AVIVO_D2GRPH_Y_END, state->grph2.y_end); 4720 OUTREG(AVIVO_D2GRPH_PITCH, state->grph2.pitch); 4721 OUTREG(AVIVO_D2GRPH_ENABLE, state->grph2.enable); 4722 OUTREG(AVIVO_D2GRPH_UPDATE, 0); 4723 4724 /* Whack some mode regs too */ 4725 OUTREG(AVIVO_D1SCL_UPDATE, AVIVO_D1SCL_UPDATE_LOCK); 4726 OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT, state->grph1.desktop_height); 4727 OUTREG(AVIVO_D1MODE_VIEWPORT_START, state->grph1.viewport_start); 4728 OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE, state->grph1.viewport_size); 4729 OUTREG(AVIVO_D1MODE_DATA_FORMAT, state->grph1.mode_data_format); 4730 OUTREG(AVIVO_D1SCL_UPDATE, 0); 4731 4732 OUTREG(AVIVO_D2SCL_UPDATE, AVIVO_D1SCL_UPDATE_LOCK); 4733 OUTREG(AVIVO_D2MODE_DESKTOP_HEIGHT, state->grph2.desktop_height); 4734 OUTREG(AVIVO_D2MODE_VIEWPORT_START, state->grph2.viewport_start); 4735 OUTREG(AVIVO_D2MODE_VIEWPORT_SIZE, state->grph2.viewport_size); 4736 OUTREG(AVIVO_D2MODE_DATA_FORMAT, state->grph2.mode_data_format); 4737 OUTREG(AVIVO_D2SCL_UPDATE, 0); 4738 4739 /* Set the PLL */ 4740 OUTREG(AVIVO_EXT1_PPLL_REF_DIV_SRC, state->pll1.ref_div_src); 4741 OUTREG(AVIVO_EXT1_PPLL_REF_DIV, state->pll1.ref_div); 4742 OUTREG(AVIVO_EXT1_PPLL_FB_DIV, state->pll1.fb_div); 4743 OUTREG(AVIVO_EXT1_PPLL_POST_DIV_SRC, state->pll1.post_div_src); 4744 OUTREG(AVIVO_EXT1_PPLL_POST_DIV, state->pll1.post_div); 4745 OUTREG(AVIVO_EXT1_PPLL_CNTL, state->pll1.ext_ppll_cntl); 4746 OUTREG(AVIVO_P1PLL_CNTL, state->pll1.pll_cntl); 4747 OUTREG(AVIVO_P1PLL_INT_SS_CNTL, state->pll1.int_ss_cntl); 4748 4749 OUTREG(AVIVO_EXT2_PPLL_REF_DIV_SRC, state->pll2.ref_div_src); 4750 OUTREG(AVIVO_EXT2_PPLL_REF_DIV, state->pll2.ref_div); 4751 OUTREG(AVIVO_EXT2_PPLL_FB_DIV, state->pll2.fb_div); 4752 OUTREG(AVIVO_EXT2_PPLL_POST_DIV_SRC, state->pll2.post_div_src); 4753 OUTREG(AVIVO_EXT2_PPLL_POST_DIV, state->pll2.post_div); 4754 OUTREG(AVIVO_EXT2_PPLL_CNTL, state->pll2.ext_ppll_cntl); 4755 OUTREG(AVIVO_P2PLL_CNTL, state->pll2.pll_cntl); 4756 OUTREG(AVIVO_P2PLL_INT_SS_CNTL, state->pll2.int_ss_cntl); 4757 4758 OUTREG(AVIVO_PCLK_CRTC1_CNTL, state->crtc1.pll_source); 4759 OUTREG(AVIVO_PCLK_CRTC2_CNTL, state->crtc2.pll_source); 4760 4761 /* Set the vga PLL */ 4762 OUTREG(AVIVO_VGA25_PPLL_REF_DIV_SRC, state->vga25_ppll.ref_div_src); 4763 OUTREG(AVIVO_VGA25_PPLL_REF_DIV, state->vga25_ppll.ref_div); 4764 OUTREG(AVIVO_VGA25_PPLL_FB_DIV, state->vga25_ppll.fb_div); 4765 OUTREG(AVIVO_VGA25_PPLL_POST_DIV_SRC, state->vga25_ppll.post_div_src); 4766 OUTREG(AVIVO_VGA25_PPLL_POST_DIV, state->vga25_ppll.post_div); 4767 OUTREG(AVIVO_VGA25_PPLL_CNTL, state->vga25_ppll.pll_cntl); 4768 4769 OUTREG(AVIVO_VGA28_PPLL_REF_DIV_SRC, state->vga28_ppll.ref_div_src); 4770 OUTREG(AVIVO_VGA28_PPLL_REF_DIV, state->vga28_ppll.ref_div); 4771 OUTREG(AVIVO_VGA28_PPLL_FB_DIV, state->vga28_ppll.fb_div); 4772 OUTREG(AVIVO_VGA28_PPLL_POST_DIV_SRC, state->vga28_ppll.post_div_src); 4773 OUTREG(AVIVO_VGA28_PPLL_POST_DIV, state->vga28_ppll.post_div); 4774 OUTREG(AVIVO_VGA28_PPLL_CNTL, state->vga28_ppll.pll_cntl); 4775 4776 OUTREG(AVIVO_VGA41_PPLL_REF_DIV_SRC, state->vga41_ppll.ref_div_src); 4777 OUTREG(AVIVO_VGA41_PPLL_REF_DIV, state->vga41_ppll.ref_div); 4778 OUTREG(AVIVO_VGA41_PPLL_FB_DIV, state->vga41_ppll.fb_div); 4779 OUTREG(AVIVO_VGA41_PPLL_POST_DIV_SRC, state->vga41_ppll.post_div_src); 4780 OUTREG(AVIVO_VGA41_PPLL_POST_DIV, state->vga41_ppll.post_div); 4781 OUTREG(AVIVO_VGA41_PPLL_CNTL, state->vga41_ppll.pll_cntl); 4782 4783 /* Set the CRTC */ 4784 OUTREG(AVIVO_D1CRTC_H_TOTAL, state->crtc1.h_total); 4785 OUTREG(AVIVO_D1CRTC_H_BLANK_START_END, state->crtc1.h_blank_start_end); 4786 OUTREG(AVIVO_D1CRTC_H_SYNC_A, state->crtc1.h_sync_a); 4787 OUTREG(AVIVO_D1CRTC_H_SYNC_A_CNTL, state->crtc1.h_sync_a_cntl); 4788 OUTREG(AVIVO_D1CRTC_H_SYNC_B, state->crtc1.h_sync_b); 4789 OUTREG(AVIVO_D1CRTC_H_SYNC_B_CNTL, state->crtc1.h_sync_b_cntl); 4790 4791 OUTREG(AVIVO_D1CRTC_V_TOTAL, state->crtc1.v_total); 4792 OUTREG(AVIVO_D1CRTC_V_BLANK_START_END, state->crtc1.v_blank_start_end); 4793 OUTREG(AVIVO_D1CRTC_V_SYNC_A, state->crtc1.v_sync_a); 4794 OUTREG(AVIVO_D1CRTC_V_SYNC_A_CNTL, state->crtc1.v_sync_a_cntl); 4795 OUTREG(AVIVO_D1CRTC_V_SYNC_B, state->crtc1.v_sync_b); 4796 OUTREG(AVIVO_D1CRTC_V_SYNC_B_CNTL, state->crtc1.v_sync_b_cntl); 4797 4798 OUTREG(AVIVO_D1CRTC_INTERLACE_CONTROL, state->crtc1.interlace_control); 4799 OUTREG(AVIVO_D1CRTC_STEREO_CONTROL, state->crtc1.stereo_control); 4800 4801 OUTREG(AVIVO_D1CUR_CONTROL, state->crtc1.cursor_control); 4802 4803 /* XXX Fix scaler */ 4804 4805 OUTREG(AVIVO_D2CRTC_H_TOTAL, state->crtc2.h_total); 4806 OUTREG(AVIVO_D2CRTC_H_BLANK_START_END, state->crtc2.h_blank_start_end); 4807 OUTREG(AVIVO_D2CRTC_H_SYNC_A, state->crtc2.h_sync_a); 4808 OUTREG(AVIVO_D2CRTC_H_SYNC_A_CNTL, state->crtc2.h_sync_a_cntl); 4809 OUTREG(AVIVO_D2CRTC_H_SYNC_B, state->crtc2.h_sync_b); 4810 OUTREG(AVIVO_D2CRTC_H_SYNC_B_CNTL, state->crtc2.h_sync_b_cntl); 4811 4812 OUTREG(AVIVO_D2CRTC_V_TOTAL, state->crtc2.v_total); 4813 OUTREG(AVIVO_D2CRTC_V_BLANK_START_END, state->crtc2.v_blank_start_end); 4814 OUTREG(AVIVO_D2CRTC_V_SYNC_A, state->crtc2.v_sync_a); 4815 OUTREG(AVIVO_D2CRTC_V_SYNC_A_CNTL, state->crtc2.v_sync_a_cntl); 4816 OUTREG(AVIVO_D2CRTC_V_SYNC_B, state->crtc2.v_sync_b); 4817 OUTREG(AVIVO_D2CRTC_V_SYNC_B_CNTL, state->crtc2.v_sync_b_cntl); 4818 4819 OUTREG(AVIVO_D2CRTC_INTERLACE_CONTROL, state->crtc2.interlace_control); 4820 OUTREG(AVIVO_D2CRTC_STEREO_CONTROL, state->crtc2.stereo_control); 4821 4822 OUTREG(AVIVO_D2CUR_CONTROL, state->crtc2.cursor_control); 4823 4824 if (IS_DCE3_VARIANT) { 4825 /* DVOA regs */ 4826 OUTREG(0x7080, state->dvoa[0]); 4827 OUTREG(0x7084, state->dvoa[1]); 4828 OUTREG(0x708c, state->dvoa[2]); 4829 OUTREG(0x7090, state->dvoa[3]); 4830 OUTREG(0x7094, state->dvoa[4]); 4831 OUTREG(0x70ac, state->dvoa[5]); 4832 OUTREG(0x70b0, state->dvoa[6]); 4833 4834 j = 0; 4835 /* DAC regs */ 4836 for (i = 0x7000; i <= 0x7040; i += 4) { 4837 OUTREG(i, state->daca[j]); 4838 OUTREG((i + 0x100), state->dacb[j]); 4839 j++; 4840 } 4841 for (i = 0x7058; i <= 0x7060; i += 4) { 4842 OUTREG(i, state->daca[j]); 4843 OUTREG((i + 0x100), state->dacb[j]); 4844 j++; 4845 } 4846 for (i = 0x7068; i <= 0x706c; i += 4) { 4847 OUTREG(i, state->daca[j]); 4848 OUTREG((i + 0x100), state->dacb[j]); 4849 j++; 4850 } 4851 for (i = 0x7ef0; i <= 0x7ef8; i += 4) { 4852 OUTREG(i, state->daca[j]); 4853 OUTREG((i + 0x100), state->dacb[j]); 4854 j++; 4855 } 4856 OUTREG(0x7050, state->daca[j]); 4857 OUTREG((0x7050 + 0x100), state->dacb[j]); 4858 4859 j = 0; 4860 /* FMT regs */ 4861 for (i = 0x6700; i <= 0x6744; i += 4) { 4862 OUTREG(i, state->fmt1[j]); 4863 OUTREG((i + 0x800), state->fmt2[j]); 4864 j++; 4865 } 4866 4867 j = 0; 4868 /* DIG regs */ 4869 for (i = 0x75a0; i <= 0x75e0; i += 4) { 4870 OUTREG(i, state->dig1[j]); 4871 OUTREG((i + 0x400), state->dig2[j]); 4872 j++; 4873 } 4874 for (i = 0x75e8; i <= 0x75ec; i += 4) { 4875 OUTREG(i, state->dig1[j]); 4876 OUTREG((i + 0x400), state->dig2[j]); 4877 j++; 4878 } 4879 4880 j = 0; 4881 /* HDMI regs */ 4882 for (i = 0x7400; i <= 0x741c; i += 4) { 4883 OUTREG(i, state->hdmi1[j]); 4884 OUTREG((i + 0x400), state->hdmi2[j]); 4885 j++; 4886 } 4887 for (i = 0x7430; i <= 0x74ec; i += 4) { 4888 OUTREG(i, state->hdmi1[j]); 4889 OUTREG((i + 0x400), state->hdmi2[j]); 4890 j++; 4891 } 4892 OUTREG(0x7428, state->hdmi1[j]); 4893 OUTREG((0x7428 + 0x400), state->hdmi2[j]); 4894 4895 j = 0; 4896 /* save AUX regs */ 4897 for (i = 0x7780; i <= 0x77b4; i += 4) { 4898 OUTREG(i, state->aux_cntl1[j]); 4899 OUTREG((i + 0x040), state->aux_cntl2[j]); 4900 OUTREG((i + 0x400), state->aux_cntl3[j]); 4901 OUTREG((i + 0x440), state->aux_cntl4[j]); 4902 if (IS_DCE32_VARIANT) { 4903 OUTREG((i + 0x500), state->aux_cntl5[j]); 4904 OUTREG((i + 0x540), state->aux_cntl6[j]); 4905 } 4906 j++; 4907 } 4908 4909 j = 0; 4910 /* save UNIPHY regs */ 4911 if (IS_DCE32_VARIANT) { 4912 for (i = 0x7680; i <= 0x7690; i += 4) { 4913 OUTREG(i, state->uniphy1[j]); 4914 OUTREG((i + 0x20), state->uniphy2[j]); 4915 OUTREG((i + 0x400), state->uniphy3[j]); 4916 OUTREG((i + 0x420), state->uniphy4[j]); 4917 OUTREG((i + 0x840), state->uniphy5[j]); 4918 OUTREG((i + 0x940), state->uniphy6[j]); 4919 j++; 4920 } 4921 for (i = 0x7698; i <= 0x769c; i += 4) { 4922 OUTREG(i, state->uniphy1[j]); 4923 OUTREG((i + 0x20), state->uniphy2[j]); 4924 OUTREG((i + 0x400), state->uniphy3[j]); 4925 OUTREG((i + 0x420), state->uniphy4[j]); 4926 OUTREG((i + 0x840), state->uniphy5[j]); 4927 OUTREG((i + 0x940), state->uniphy6[j]); 4928 j++; 4929 } 4930 } else { 4931 for (i = 0x7ec0; i <= 0x7edc; i += 4) { 4932 OUTREG(i, state->uniphy1[j]); 4933 OUTREG((i + 0x100), state->uniphy2[j]); 4934 j++; 4935 } 4936 } 4937 j = 0; 4938 /* save PHY,LINK regs */ 4939 for (i = 0x7f20; i <= 0x7f34; i += 4) { 4940 OUTREG(i, state->phy[j]); 4941 j++; 4942 } 4943 for (i = 0x7f9c; i <= 0x7fa4; i += 4) { 4944 OUTREG(i, state->phy[j]); 4945 j++; 4946 } 4947 state->phy[j] = INREG(0x7f40); 4948 4949 j = 0; 4950 /* save LVTMA regs */ 4951 for (i = 0x7f00; i <= 0x7f1c; i += 4) { 4952 OUTREG(i, state->lvtma[j]); 4953 j++; 4954 } 4955 for (i = 0x7f80; i <= 0x7f98; i += 4) { 4956 OUTREG(i, state->lvtma[j]); 4957 j++; 4958 } 4959 } else { 4960 j = 0; 4961 /* DVOA regs */ 4962 for (i = 0x7980; i <= 0x79bc; i += 4) { 4963 OUTREG(i, state->dvoa[j]); 4964 j++; 4965 } 4966 4967 j = 0; 4968 /* DAC regs */ /* -- MIGHT NEED ORDERING FIX & DELAYS -- */ 4969 for (i = 0x7800; i <= 0x782c; i += 4) { 4970 OUTREG(i, state->daca[j]); 4971 OUTREG((i + 0x200), state->dacb[j]); 4972 j++; 4973 } 4974 for (i = 0x7834; i <= 0x7840; i += 4) { 4975 OUTREG(i, state->daca[j]); 4976 OUTREG((i + 0x200), state->dacb[j]); 4977 j++; 4978 } 4979 for (i = 0x7850; i <= 0x7868; i += 4) { 4980 OUTREG(i, state->daca[j]); 4981 OUTREG((i + 0x200), state->dacb[j]); 4982 j++; 4983 } 4984 4985 j = 0; 4986 /* TMDSA regs */ 4987 for (i = 0x7880; i <= 0x78e0; i += 4) { 4988 OUTREG(i, state->tmdsa[j]); 4989 j++; 4990 } 4991 for (i = 0x7904; i <= 0x7918; i += 4) { 4992 OUTREG(i, state->tmdsa[j]); 4993 j++; 4994 } 4995 4996 j = 0; 4997 /* LVTMA regs */ 4998 for (i = 0x7a80; i <= 0x7b18; i += 4) { 4999 OUTREG(i, state->lvtma[j]); 5000 j++; 5001 } 5002 5003 /* DDIA regs */ 5004 if ((info->ChipFamily == CHIP_FAMILY_RS600) || 5005 (info->ChipFamily == CHIP_FAMILY_RS690) || 5006 (info->ChipFamily == CHIP_FAMILY_RS740)) { 5007 j = 0; 5008 for (i = 0x7200; i <= 0x7290; i += 4) { 5009 OUTREG(i, state->ddia[j]); 5010 j++; 5011 } 5012 } 5013 } 5014 5015 /* scalers */ 5016 j = 0; 5017 for (i = 0x6578; i <= 0x65e4; i += 4) { 5018 OUTREG(i, state->d1scl[j]); 5019 OUTREG((i + 0x800), state->d2scl[j]); 5020 j++; 5021 } 5022 for (i = 0x6600; i <= 0x662c; i += 4) { 5023 OUTREG(i, state->d1scl[j]); 5024 OUTREG((i + 0x800), state->d2scl[j]); 5025 j++; 5026 } 5027 j = 0; 5028 for (i = 0x66e8; i <= 0x66fc; i += 4) { 5029 OUTREG(i, state->dxscl[j]); 5030 j++; 5031 } 5032 OUTREG(0x6e30, state->dxscl[6]); 5033 OUTREG(0x6e34, state->dxscl[7]); 5034 5035 /* Enable CRTCs */ 5036 if (state->crtc1.control & 1) { 5037 OUTREG(AVIVO_D1CRTC_CONTROL, 0x01000101); 5038 INREG(AVIVO_D1CRTC_CONTROL); 5039 OUTREG(AVIVO_D1CRTC_CONTROL, 0x00010101); 5040 } 5041 if (state->crtc2.control & 1) { 5042 OUTREG(AVIVO_D2CRTC_CONTROL, 0x01000101); 5043 INREG(AVIVO_D2CRTC_CONTROL); 5044 OUTREG(AVIVO_D2CRTC_CONTROL, 0x00010101); 5045 } 5046 5047 /* Where should that go ? */ 5048 OUTREG(AVIVO_DC_CRTC_TV_CONTROL, state->crtc_tv_control); 5049 OUTREG(AVIVO_DC_LB_MEMORY_SPLIT, state->dc_lb_memory_split); 5050 5051 /* Need fixing too ? */ 5052 OUTREG(AVIVO_D1CRTC_BLANK_CONTROL, state->crtc1.blank_control); 5053 OUTREG(AVIVO_D2CRTC_BLANK_CONTROL, state->crtc2.blank_control); 5054 5055 /* Dbl check */ 5056 OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl); 5057 OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl); 5058 5059 /* Should only enable outputs here */ 5060} 5061 5062static void avivo_restore_vga_regs(ScrnInfoPtr pScrn, RADEONSavePtr restore) 5063{ 5064 RADEONInfoPtr info = RADEONPTR(pScrn); 5065 unsigned char *RADEONMMIO = info->MMIO; 5066 struct avivo_state *state = &restore->avivo; 5067 5068 OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl); 5069 OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl); 5070} 5071 5072static void 5073RADEONRestoreBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) 5074{ 5075 RADEONInfoPtr info = RADEONPTR(pScrn); 5076 unsigned char *RADEONMMIO = info->MMIO; 5077 5078 if (info->ChipFamily >= CHIP_FAMILY_R600) { 5079 OUTREG(R600_BIOS_0_SCRATCH, restore->bios_0_scratch); 5080 OUTREG(R600_BIOS_1_SCRATCH, restore->bios_1_scratch); 5081 OUTREG(R600_BIOS_2_SCRATCH, restore->bios_2_scratch); 5082 OUTREG(R600_BIOS_3_SCRATCH, restore->bios_3_scratch); 5083 OUTREG(R600_BIOS_4_SCRATCH, restore->bios_4_scratch); 5084 OUTREG(R600_BIOS_5_SCRATCH, restore->bios_5_scratch); 5085 OUTREG(R600_BIOS_6_SCRATCH, restore->bios_6_scratch); 5086 OUTREG(R600_BIOS_7_SCRATCH, restore->bios_7_scratch); 5087 } else { 5088 OUTREG(RADEON_BIOS_0_SCRATCH, restore->bios_0_scratch); 5089 OUTREG(RADEON_BIOS_1_SCRATCH, restore->bios_1_scratch); 5090 OUTREG(RADEON_BIOS_2_SCRATCH, restore->bios_2_scratch); 5091 OUTREG(RADEON_BIOS_3_SCRATCH, restore->bios_3_scratch); 5092 OUTREG(RADEON_BIOS_4_SCRATCH, restore->bios_4_scratch); 5093 OUTREG(RADEON_BIOS_5_SCRATCH, restore->bios_5_scratch); 5094 OUTREG(RADEON_BIOS_6_SCRATCH, restore->bios_6_scratch); 5095 OUTREG(RADEON_BIOS_7_SCRATCH, restore->bios_7_scratch); 5096 } 5097} 5098 5099static void 5100RADEONSaveBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) 5101{ 5102 RADEONInfoPtr info = RADEONPTR(pScrn); 5103 unsigned char *RADEONMMIO = info->MMIO; 5104 5105 if (info->ChipFamily >= CHIP_FAMILY_R600) { 5106 save->bios_0_scratch = INREG(R600_BIOS_0_SCRATCH); 5107 save->bios_1_scratch = INREG(R600_BIOS_1_SCRATCH); 5108 save->bios_2_scratch = INREG(R600_BIOS_2_SCRATCH); 5109 save->bios_3_scratch = INREG(R600_BIOS_3_SCRATCH); 5110 save->bios_4_scratch = INREG(R600_BIOS_4_SCRATCH); 5111 save->bios_5_scratch = INREG(R600_BIOS_5_SCRATCH); 5112 save->bios_6_scratch = INREG(R600_BIOS_6_SCRATCH); 5113 save->bios_7_scratch = INREG(R600_BIOS_7_SCRATCH); 5114 } else { 5115 save->bios_0_scratch = INREG(RADEON_BIOS_0_SCRATCH); 5116 save->bios_1_scratch = INREG(RADEON_BIOS_1_SCRATCH); 5117 save->bios_2_scratch = INREG(RADEON_BIOS_2_SCRATCH); 5118 save->bios_3_scratch = INREG(RADEON_BIOS_3_SCRATCH); 5119 save->bios_4_scratch = INREG(RADEON_BIOS_4_SCRATCH); 5120 save->bios_5_scratch = INREG(RADEON_BIOS_5_SCRATCH); 5121 save->bios_6_scratch = INREG(RADEON_BIOS_6_SCRATCH); 5122 save->bios_7_scratch = INREG(RADEON_BIOS_7_SCRATCH); 5123 } 5124} 5125 5126/* Save everything needed to restore the original VC state */ 5127static void RADEONSave(ScrnInfoPtr pScrn) 5128{ 5129 RADEONInfoPtr info = RADEONPTR(pScrn); 5130 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 5131 unsigned char *RADEONMMIO = info->MMIO; 5132 RADEONSavePtr save = info->SavedReg; 5133 5134 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5135 "RADEONSave\n"); 5136 5137#ifdef WITH_VGAHW 5138 if (info->VGAAccess) { 5139 vgaHWPtr hwp = VGAHWPTR(pScrn); 5140 5141 vgaHWUnlock(hwp); 5142# if defined(__powerpc__) 5143 /* temporary hack to prevent crashing on PowerMacs when trying to 5144 * read VGA fonts and colormap, will find a better solution 5145 * in the future. TODO: Check if there's actually some VGA stuff 5146 * setup in the card at all !! 5147 */ 5148 vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE); /* Save mode only */ 5149# elif defined(__linux__) 5150 /* Save only mode * & fonts */ 5151 vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS ); 5152# else 5153 /* Save mode * & fonts & cmap */ 5154 vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_ALL); 5155# endif 5156 vgaHWLock(hwp); 5157 } 5158#endif 5159 5160 if (IS_AVIVO_VARIANT) { 5161 RADEONSaveMemMapRegisters(pScrn, save); 5162 avivo_save(pScrn, save); 5163 } else { 5164 save->dp_datatype = INREG(RADEON_DP_DATATYPE); 5165 save->rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET); 5166 save->clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX); 5167 RADEONPllErrataAfterIndex(info); 5168 5169 RADEONSaveMemMapRegisters(pScrn, save); 5170 RADEONSaveCommonRegisters(pScrn, save); 5171 RADEONSavePLLRegisters(pScrn, save); 5172 RADEONSaveCrtcRegisters(pScrn, save); 5173 RADEONSaveFPRegisters(pScrn, save); 5174 RADEONSaveDACRegisters(pScrn, save); 5175 if (pRADEONEnt->HasCRTC2) { 5176 RADEONSaveCrtc2Registers(pScrn, save); 5177 RADEONSavePLL2Registers(pScrn, save); 5178 } 5179 if (info->InternalTVOut) 5180 RADEONSaveTVRegisters(pScrn, save); 5181 } 5182 5183 if (info->ChipFamily < CHIP_FAMILY_R600) 5184 RADEONSaveSurfaces(pScrn, save); 5185 5186} 5187 5188/* Restore the original (text) mode */ 5189static void RADEONRestore(ScrnInfoPtr pScrn) 5190{ 5191 RADEONInfoPtr info = RADEONPTR(pScrn); 5192 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 5193 unsigned char *RADEONMMIO = info->MMIO; 5194 RADEONSavePtr restore = info->SavedReg; 5195 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 5196 xf86CrtcPtr crtc; 5197 5198 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5199 "RADEONRestore\n"); 5200 5201#if X_BYTE_ORDER == X_BIG_ENDIAN 5202 if (info->ChipFamily < CHIP_FAMILY_R600) { 5203 RADEONWaitForFifo(pScrn, 1); 5204 OUTREG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_NONE); 5205 } 5206#endif 5207 5208 RADEONBlank(pScrn); 5209 5210 if (IS_AVIVO_VARIANT) { 5211 RADEONRestoreMemMapRegisters(pScrn, restore); 5212 avivo_restore(pScrn, restore); 5213 } else { 5214 OUTREG(RADEON_CLOCK_CNTL_INDEX, restore->clock_cntl_index); 5215 RADEONPllErrataAfterIndex(info); 5216 OUTREG(RADEON_RBBM_SOFT_RESET, restore->rbbm_soft_reset); 5217 OUTREG(RADEON_DP_DATATYPE, restore->dp_datatype); 5218 OUTREG(RADEON_GRPH_BUFFER_CNTL, restore->grph_buffer_cntl); 5219 OUTREG(RADEON_GRPH2_BUFFER_CNTL, restore->grph2_buffer_cntl); 5220 5221 if (!info->IsSecondary) { 5222 RADEONRestoreMemMapRegisters(pScrn, restore); 5223 RADEONRestoreCommonRegisters(pScrn, restore); 5224 5225 if (pRADEONEnt->HasCRTC2) { 5226 RADEONRestoreCrtc2Registers(pScrn, restore); 5227 RADEONRestorePLL2Registers(pScrn, restore); 5228 } 5229 5230 RADEONRestoreCrtcRegisters(pScrn, restore); 5231 RADEONRestorePLLRegisters(pScrn, restore); 5232 RADEONRestoreRMXRegisters(pScrn, restore); 5233 RADEONRestoreFPRegisters(pScrn, restore); 5234 RADEONRestoreFP2Registers(pScrn, restore); 5235 RADEONRestoreLVDSRegisters(pScrn, restore); 5236 5237 if (info->InternalTVOut) 5238 RADEONRestoreTVRegisters(pScrn, restore); 5239 } 5240 5241 RADEONRestoreBIOSRegisters(pScrn, restore); 5242 } 5243 5244 5245#if 1 5246 /* Temp fix to "solve" VT switch problems. When switching VTs on 5247 * some systems, the console can either hang or the fonts can be 5248 * corrupted. This hack solves the problem 99% of the time. A 5249 * correct fix is being worked on. 5250 */ 5251 usleep(100000); 5252#endif 5253 5254 if (info->ChipFamily < CHIP_FAMILY_R600) 5255 RADEONRestoreSurfaces(pScrn, restore); 5256 5257 /* need to make sure we don't enable a crtc by accident or we may get a hang */ 5258 if (pRADEONEnt->HasCRTC2 && !info->IsSecondary) { 5259 if (info->crtc2_on && xf86_config->num_crtc > 1) { 5260 crtc = xf86_config->crtc[1]; 5261 crtc->funcs->dpms(crtc, DPMSModeOn); 5262 } 5263 } 5264 if (info->crtc_on) { 5265 crtc = xf86_config->crtc[0]; 5266 crtc->funcs->dpms(crtc, DPMSModeOn); 5267 } 5268 5269#ifdef WITH_VGAHW 5270 if (info->VGAAccess) { 5271 vgaHWPtr hwp = VGAHWPTR(pScrn); 5272 vgaHWUnlock(hwp); 5273# if defined(__powerpc__) 5274 /* Temporary hack to prevent crashing on PowerMacs when trying to 5275 * write VGA fonts, will find a better solution in the future 5276 */ 5277 vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE ); 5278# elif defined(__linux__) 5279 vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS ); 5280# else 5281 vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_ALL ); 5282# endif 5283 vgaHWLock(hwp); 5284 } 5285#endif 5286 5287 /* to restore console mode, DAC registers should be set after every other registers are set, 5288 * otherwise,we may get blank screen 5289 */ 5290 if (IS_AVIVO_VARIANT) 5291 avivo_restore_vga_regs(pScrn, restore); 5292 5293 if (!IS_AVIVO_VARIANT) 5294 RADEONRestoreDACRegisters(pScrn, restore); 5295 5296#if 0 5297 RADEONWaitForVerticalSync(pScrn); 5298#endif 5299} 5300 5301#if 0 5302/* Define initial palette for requested video mode. This doesn't do 5303 * anything for XFree86 4.0. 5304 */ 5305static void RADEONInitPalette(RADEONSavePtr save) 5306{ 5307 save->palette_valid = FALSE; 5308} 5309#endif 5310 5311static Bool RADEONSaveScreen(ScreenPtr pScreen, int mode) 5312{ 5313 ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; 5314 Bool unblank; 5315 5316 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5317 "RADEONSaveScreen(%d)\n", mode); 5318 5319 unblank = xf86IsUnblank(mode); 5320 if (unblank) SetTimeSinceLastInputEvent(); 5321 5322 if ((pScrn != NULL) && pScrn->vtSema) { 5323 if (unblank) 5324 RADEONUnblank(pScrn); 5325 else 5326 RADEONBlank(pScrn); 5327 } 5328 return TRUE; 5329} 5330 5331Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) 5332{ 5333 ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; 5334 RADEONInfoPtr info = RADEONPTR(pScrn); 5335 Bool tilingOld = info->tilingEnabled; 5336 Bool ret; 5337#ifdef XF86DRI 5338 Bool CPStarted = info->cp->CPStarted; 5339 5340 if (CPStarted) { 5341 DRILock(pScrn->pScreen, 0); 5342 RADEONCP_STOP(pScrn, info); 5343 } 5344#endif 5345 5346 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5347 "RADEONSwitchMode() !n"); 5348 5349 if (info->allowColorTiling) { 5350 info->tilingEnabled = (mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; 5351#ifdef XF86DRI 5352 if (info->directRenderingEnabled && (info->tilingEnabled != tilingOld)) { 5353 drm_radeon_sarea_t *pSAREAPriv; 5354 if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0) 5355 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 5356 "[drm] failed changing tiling status\n"); 5357 pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen); 5358 info->tilingEnabled = pSAREAPriv->tiling_enabled ? TRUE : FALSE; 5359 } 5360#endif 5361 } 5362 5363 if (info->accelOn) 5364 RADEON_SYNC(info, pScrn); 5365 5366 ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0); 5367 5368 if (info->tilingEnabled != tilingOld) { 5369 /* need to redraw front buffer, I guess this can be considered a hack ? */ 5370 xf86EnableDisableFBAccess(scrnIndex, FALSE); 5371 RADEONChangeSurfaces(pScrn); 5372 xf86EnableDisableFBAccess(scrnIndex, TRUE); 5373 /* xf86SetRootClip would do, but can't access that here */ 5374 } 5375 5376 if (info->accelOn) { 5377 RADEON_SYNC(info, pScrn); 5378 if (info->ChipFamily < CHIP_FAMILY_R600) 5379 RADEONEngineRestore(pScrn); 5380 } 5381 5382#ifdef XF86DRI 5383 if (CPStarted) { 5384 RADEONCP_START(pScrn, info); 5385 DRIUnlock(pScrn->pScreen); 5386 } 5387#endif 5388 5389 /* reset ecp for overlay */ 5390 info->ecp_div = -1; 5391 5392 return ret; 5393} 5394 5395#ifdef X_XF86MiscPassMessage 5396Bool RADEONHandleMessage(int scrnIndex, const char* msgtype, 5397 const char* msgval, char** retmsg) 5398{ 5399 ErrorF("RADEONHandleMessage(%d, \"%s\", \"%s\", retmsg)\n", scrnIndex, 5400 msgtype, msgval); 5401 *retmsg = ""; 5402 return 0; 5403} 5404#endif 5405 5406#ifndef HAVE_XF86MODEBANDWIDTH 5407/** Calculates the memory bandwidth (in MiB/sec) of a mode. */ 5408_X_HIDDEN unsigned int 5409xf86ModeBandwidth(DisplayModePtr mode, int depth) 5410{ 5411 float a_active, a_total, active_percent, pixels_per_second; 5412 int bytes_per_pixel = (depth + 7) / 8; 5413 5414 if (!mode->HTotal || !mode->VTotal || !mode->Clock) 5415 return 0; 5416 5417 a_active = mode->HDisplay * mode->VDisplay; 5418 a_total = mode->HTotal * mode->VTotal; 5419 active_percent = a_active / a_total; 5420 pixels_per_second = active_percent * mode->Clock * 1000.0; 5421 5422 return (unsigned int)(pixels_per_second * bytes_per_pixel / (1024 * 1024)); 5423} 5424#endif 5425 5426/* Used to disallow modes that are not supported by the hardware */ 5427ModeStatus RADEONValidMode(int scrnIndex, DisplayModePtr mode, 5428 Bool verbose, int flag) 5429{ 5430 ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; 5431 RADEONInfoPtr info = RADEONPTR(pScrn); 5432 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 5433 5434 /* 5435 * RN50 has effective maximum mode bandwidth of about 300MiB/s. 5436 * XXX should really do this for all chips by properly computing 5437 * memory bandwidth and an overhead factor. 5438 */ 5439 if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) { 5440 if (xf86ModeBandwidth(mode, pScrn->bitsPerPixel) > 300) 5441 return MODE_BANDWIDTH; 5442 } 5443 5444 /* There are problems with double scan mode at high clocks 5445 * They're likely related PLL and display buffer settings. 5446 * Disable these modes for now. 5447 */ 5448 if (mode->Flags & V_DBLSCAN) { 5449 if ((mode->CrtcHDisplay >= 1024) || (mode->CrtcVDisplay >= 768)) 5450 return MODE_CLOCK_RANGE; 5451 } 5452 return MODE_OK; 5453} 5454 5455/* Adjust viewport into virtual desktop such that (0,0) in viewport 5456 * space is (x,y) in virtual space. 5457 */ 5458void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool crtc2) 5459{ 5460 RADEONInfoPtr info = RADEONPTR(pScrn); 5461 unsigned char *RADEONMMIO = info->MMIO; 5462 int Base, reg, regcntl, crtcoffsetcntl, xytilereg, crtcxytile = 0; 5463#ifdef XF86DRI 5464 drm_radeon_sarea_t *pSAREAPriv; 5465 XF86DRISAREAPtr pSAREA; 5466#endif 5467 5468#if 0 /* Verbose */ 5469 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5470 "RADEONDoAdjustFrame(%d,%d,%d)\n", x, y, clone); 5471#endif 5472 5473 if (info->showCache && y) { 5474 int lastline = info->FbMapSize / 5475 ((pScrn->displayWidth * pScrn->bitsPerPixel) / 8); 5476 5477 lastline -= pScrn->currentMode->VDisplay; 5478 y += (pScrn->virtualY - 1) * (y / 3 + 1); 5479 if (y > lastline) y = lastline; 5480 } 5481 5482 Base = pScrn->fbOffset; 5483 5484 /* note we cannot really simply use the info->ModeReg.crtc_offset_cntl value, since the 5485 drm might have set FLIP_CNTL since we wrote that. Unfortunately FLIP_CNTL causes 5486 flickering when scrolling vertically in a virtual screen, possibly because crtc will 5487 pick up the new offset value at the end of each scanline, but the new offset_cntl value 5488 only after a vsync. We'd probably need to wait (in drm) for vsync and only then update 5489 OFFSET and OFFSET_CNTL, if the y coord has changed. Seems hard to fix. */ 5490 if (crtc2) { 5491 reg = RADEON_CRTC2_OFFSET; 5492 regcntl = RADEON_CRTC2_OFFSET_CNTL; 5493 xytilereg = R300_CRTC2_TILE_X0_Y0; 5494 } else { 5495 reg = RADEON_CRTC_OFFSET; 5496 regcntl = RADEON_CRTC_OFFSET_CNTL; 5497 xytilereg = R300_CRTC_TILE_X0_Y0; 5498 } 5499 crtcoffsetcntl = INREG(regcntl) & ~0xf; 5500#if 0 5501 /* try to get rid of flickering when scrolling at least for 2d */ 5502#ifdef XF86DRI 5503 if (!info->dri->have3DWindows) 5504#endif 5505 crtcoffsetcntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL; 5506#endif 5507 if (info->tilingEnabled) { 5508 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { 5509 /* On r300/r400 when tiling is enabled crtc_offset is set to the address of 5510 * the surface. the x/y offsets are handled by the X_Y tile reg for each crtc 5511 * Makes tiling MUCH easier. 5512 */ 5513 crtcxytile = x | (y << 16); 5514 Base &= ~0x7ff; 5515 } else { 5516 int byteshift = info->CurrentLayout.bitsPerPixel >> 4; 5517 /* crtc uses 256(bytes)x8 "half-tile" start addresses? */ 5518 int tile_addr = (((y >> 3) * info->CurrentLayout.displayWidth + x) >> (8 - byteshift)) << 11; 5519 Base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); 5520 crtcoffsetcntl = crtcoffsetcntl | (y % 16); 5521 } 5522 } 5523 else { 5524 int offset = y * info->CurrentLayout.displayWidth + x; 5525 switch (info->CurrentLayout.pixel_code) { 5526 case 15: 5527 case 16: offset *= 2; break; 5528 case 24: offset *= 3; break; 5529 case 32: offset *= 4; break; 5530 } 5531 Base += offset; 5532 } 5533 5534 Base &= ~7; /* 3 lower bits are always 0 */ 5535 5536#ifdef XF86DRI 5537 if (info->directRenderingInited) { 5538 /* note cannot use pScrn->pScreen since this is unitialized when called from 5539 RADEONScreenInit, and we need to call from there to get mergedfb + pageflip working */ 5540 /*** NOTE: r3/4xx will need sarea and drm pageflip updates to handle the xytile regs for 5541 *** pageflipping! 5542 ***/ 5543 pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]); 5544 /* can't get at sarea in a semi-sane way? */ 5545 pSAREA = (void *)((char*)pSAREAPriv - sizeof(XF86DRISAREARec)); 5546 5547 if (crtc2) { 5548 pSAREAPriv->crtc2_base = Base; 5549 } 5550 else { 5551 pSAREA->frame.x = (Base / info->CurrentLayout.pixel_bytes) 5552 % info->CurrentLayout.displayWidth; 5553 pSAREA->frame.y = (Base / info->CurrentLayout.pixel_bytes) 5554 / info->CurrentLayout.displayWidth; 5555 pSAREA->frame.width = pScrn->frameX1 - x + 1; 5556 pSAREA->frame.height = pScrn->frameY1 - y + 1; 5557 } 5558 5559 if (pSAREAPriv->pfCurrentPage == 1) { 5560 Base += info->dri->backOffset - info->dri->frontOffset; 5561 } 5562 } 5563#endif 5564 5565 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { 5566 OUTREG(xytilereg, crtcxytile); 5567 } else { 5568 OUTREG(regcntl, crtcoffsetcntl); 5569 } 5570 5571 OUTREG(reg, Base); 5572} 5573 5574void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags) 5575{ 5576 ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; 5577 RADEONInfoPtr info = RADEONPTR(pScrn); 5578 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 5579 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 5580 xf86OutputPtr output = config->output[config->compat_output]; 5581 xf86CrtcPtr crtc = output->crtc; 5582 5583 /* not handled */ 5584 if (IS_AVIVO_VARIANT) 5585 return; 5586 5587#ifdef XF86DRI 5588 if (info->cp->CPStarted && pScrn->pScreen) DRILock(pScrn->pScreen, 0); 5589#endif 5590 5591 if (info->accelOn) 5592 RADEON_SYNC(info, pScrn); 5593 5594 if (crtc && crtc->enabled) { 5595 if (crtc == pRADEONEnt->pCrtc[0]) 5596 RADEONDoAdjustFrame(pScrn, crtc->desiredX + x, crtc->desiredY + y, FALSE); 5597 else 5598 RADEONDoAdjustFrame(pScrn, crtc->desiredX + x, crtc->desiredY + y, TRUE); 5599 crtc->x = output->initial_x + x; 5600 crtc->y = output->initial_y + y; 5601 } 5602 5603 5604#ifdef XF86DRI 5605 if (info->cp->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen); 5606#endif 5607} 5608 5609/* Called when VT switching back to the X server. Reinitialize the 5610 * video mode. 5611 */ 5612Bool RADEONEnterVT(int scrnIndex, int flags) 5613{ 5614 ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; 5615 RADEONInfoPtr info = RADEONPTR(pScrn); 5616 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 5617 int i; 5618 5619 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5620 "RADEONEnterVT\n"); 5621 5622 if (!radeon_card_posted(pScrn)) { /* Softboot V_BIOS */ 5623 if (info->IsAtomBios) { 5624 rhdAtomASICInit(info->atomBIOS); 5625 } else { 5626 xf86Int10InfoPtr pInt; 5627 5628 pInt = xf86InitInt10 (info->pEnt->index); 5629 if (pInt) { 5630 pInt->num = 0xe6; 5631 xf86ExecX86int10 (pInt); 5632 xf86FreeInt10 (pInt); 5633 } else { 5634 RADEONGetBIOSInitTableOffsets(pScrn); 5635 RADEONPostCardFromBIOSTables(pScrn); 5636 } 5637 } 5638 } 5639 5640 /* Makes sure the engine is idle before doing anything */ 5641 RADEONWaitForIdleMMIO(pScrn); 5642 5643 if (info->IsMobility && !IS_AVIVO_VARIANT) { 5644 if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { 5645 RADEONSetDynamicClock(pScrn, 1); 5646 } else { 5647 RADEONSetDynamicClock(pScrn, 0); 5648 } 5649 } else if (IS_AVIVO_VARIANT) { 5650 if (xf86ReturnOptValBool(info->Options, OPTION_DYNAMIC_CLOCKS, FALSE)) { 5651 atombios_static_pwrmgt_setup(pScrn, 1); 5652 atombios_dyn_clk_setup(pScrn, 1); 5653 } 5654 } 5655 5656 if (IS_R300_VARIANT || IS_RV100_VARIANT) 5657 RADEONForceSomeClocks(pScrn); 5658 5659 for (i = 0; i < config->num_crtc; i++) 5660 radeon_crtc_modeset_ioctl(config->crtc[i], TRUE); 5661 5662 pScrn->vtSema = TRUE; 5663 5664 if (!xf86SetDesiredModes(pScrn)) 5665 return FALSE; 5666 5667 if (info->ChipFamily < CHIP_FAMILY_R600) 5668 RADEONRestoreSurfaces(pScrn, info->ModeReg); 5669#ifdef XF86DRI 5670 if (info->directRenderingEnabled) { 5671 if (info->cardType == CARD_PCIE && 5672 info->dri->pKernelDRMVersion->version_minor >= 19 && 5673 info->FbSecureSize) { 5674#if X_BYTE_ORDER == X_BIG_ENDIAN 5675 unsigned char *RADEONMMIO = info->MMIO; 5676 unsigned int sctrl = INREG(RADEON_SURFACE_CNTL); 5677 5678 /* we need to backup the PCIE GART TABLE from fb memory */ 5679 OUTREG(RADEON_SURFACE_CNTL, 0); 5680#endif 5681 memcpy(info->FB + info->dri->pciGartOffset, info->dri->pciGartBackup, info->dri->pciGartSize); 5682#if X_BYTE_ORDER == X_BIG_ENDIAN 5683 OUTREG(RADEON_SURFACE_CNTL, sctrl); 5684#endif 5685 } 5686 5687 /* get the DRI back into shape after resume */ 5688 RADEONDRISetVBlankInterrupt (pScrn, TRUE); 5689 RADEONDRIResume(pScrn->pScreen); 5690 RADEONAdjustMemMapRegisters(pScrn, info->ModeReg); 5691 5692 } 5693#endif 5694 /* this will get XVideo going again, but only if XVideo was initialised 5695 during server startup (hence the info->adaptor if). */ 5696 if (info->adaptor) 5697 RADEONResetVideo(pScrn); 5698 5699 if (info->accelOn && (info->ChipFamily < CHIP_FAMILY_R600)) 5700 RADEONEngineRestore(pScrn); 5701 5702 if (info->accelOn && info->accel_state) 5703 info->accel_state->XInited3D = FALSE; 5704 5705#ifdef XF86DRI 5706 if (info->directRenderingEnabled) { 5707 if (info->ChipFamily >= CHIP_FAMILY_R600) 5708 R600LoadShaders(pScrn); 5709 RADEONCP_START(pScrn, info); 5710 DRIUnlock(pScrn->pScreen); 5711 } 5712#endif 5713 5714 return TRUE; 5715} 5716 5717/* Called when VT switching away from the X server. Restore the 5718 * original text mode. 5719 */ 5720void RADEONLeaveVT(int scrnIndex, int flags) 5721{ 5722 ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; 5723 RADEONInfoPtr info = RADEONPTR(pScrn); 5724 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 5725 int i; 5726 5727 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5728 "RADEONLeaveVT\n"); 5729#ifdef XF86DRI 5730 if (RADEONPTR(pScrn)->directRenderingInited) { 5731 5732 RADEONDRISetVBlankInterrupt (pScrn, FALSE); 5733 DRILock(pScrn->pScreen, 0); 5734 RADEONCP_STOP(pScrn, info); 5735 5736 if (info->cardType == CARD_PCIE && 5737 info->dri->pKernelDRMVersion->version_minor >= 19 && 5738 info->FbSecureSize) { 5739#if X_BYTE_ORDER == X_BIG_ENDIAN 5740 unsigned char *RADEONMMIO = info->MMIO; 5741 unsigned int sctrl = INREG(RADEON_SURFACE_CNTL); 5742 5743 /* we need to backup the PCIE GART TABLE from fb memory */ 5744 OUTREG(RADEON_SURFACE_CNTL, 0); 5745#endif 5746 memcpy(info->dri->pciGartBackup, (info->FB + info->dri->pciGartOffset), info->dri->pciGartSize); 5747#if X_BYTE_ORDER == X_BIG_ENDIAN 5748 OUTREG(RADEON_SURFACE_CNTL, sctrl); 5749#endif 5750 } 5751 5752 /* Make sure 3D clients will re-upload textures to video RAM */ 5753 if (info->dri->textureSize) { 5754 drm_radeon_sarea_t *pSAREAPriv = 5755 (drm_radeon_sarea_t*)DRIGetSAREAPrivate(pScrn->pScreen); 5756 struct drm_tex_region *list = pSAREAPriv->tex_list[0]; 5757 int age = ++pSAREAPriv->tex_age[0]; 5758 5759 i = 0; 5760 5761 do { 5762 list[i].age = age; 5763 i = list[i].next; 5764 } while (i != 0); 5765 } 5766 } 5767#endif 5768 5769 5770 for (i = 0; i < config->num_crtc; i++) { 5771 xf86CrtcPtr crtc = config->crtc[i]; 5772 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 5773 5774 radeon_crtc->initialized = FALSE; 5775 5776#ifndef HAVE_FREE_SHADOW 5777 if (crtc->rotatedPixmap || crtc->rotatedData) { 5778 crtc->funcs->shadow_destroy(crtc, crtc->rotatedPixmap, 5779 crtc->rotatedData); 5780 crtc->rotatedPixmap = NULL; 5781 crtc->rotatedData = NULL; 5782 } 5783#endif 5784 } 5785 5786#ifdef HAVE_FREE_SHADOW 5787 xf86RotateFreeShadow(pScrn); 5788#endif 5789 5790 xf86_hide_cursors (pScrn); 5791 5792 RADEONRestore(pScrn); 5793 5794 for (i = 0; i < config->num_crtc; i++) 5795 radeon_crtc_modeset_ioctl(config->crtc[i], FALSE); 5796 5797 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5798 "Ok, leaving now...\n"); 5799} 5800 5801/* Called at the end of each server generation. Restore the original 5802 * text mode, unmap video memory, and unwrap and call the saved 5803 * CloseScreen function. 5804 */ 5805static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) 5806{ 5807 ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; 5808 RADEONInfoPtr info = RADEONPTR(pScrn); 5809 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 5810 int i; 5811 5812 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5813 "RADEONCloseScreen\n"); 5814 5815 /* Mark acceleration as stopped or we might try to access the engine at 5816 * wrong times, especially if we had DRI, after DRI has been stopped 5817 */ 5818 info->accelOn = FALSE; 5819 5820 for (i = 0; i < config->num_crtc; i++) { 5821 xf86CrtcPtr crtc = config->crtc[i]; 5822 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 5823 5824 radeon_crtc->initialized = FALSE; 5825 } 5826 5827#ifdef XF86DRI 5828#ifdef DAMAGE 5829 if (info->dri && info->dri->pDamage) { 5830 PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen); 5831 5832 DamageUnregister(&pPix->drawable, info->dri->pDamage); 5833 DamageDestroy(info->dri->pDamage); 5834 info->dri->pDamage = NULL; 5835 } 5836#endif 5837 5838 RADEONDRIStop(pScreen); 5839#endif 5840 5841#ifdef USE_XAA 5842 if(!info->useEXA && info->accel_state->RenderTex) { 5843 xf86FreeOffscreenLinear(info->accel_state->RenderTex); 5844 info->accel_state->RenderTex = NULL; 5845 } 5846#endif /* USE_XAA */ 5847 5848 if (pScrn->vtSema) { 5849 RADEONRestore(pScrn); 5850 } 5851 5852 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5853 "Disposing accel...\n"); 5854#ifdef USE_EXA 5855 if (info->accel_state->exa) { 5856 exaDriverFini(pScreen); 5857 xfree(info->accel_state->exa); 5858 info->accel_state->exa = NULL; 5859 } 5860#endif /* USE_EXA */ 5861#ifdef USE_XAA 5862 if (!info->useEXA) { 5863 if (info->accel_state->accel) 5864 XAADestroyInfoRec(info->accel_state->accel); 5865 info->accel_state->accel = NULL; 5866 5867 if (info->accel_state->scratch_save) 5868 xfree(info->accel_state->scratch_save); 5869 info->accel_state->scratch_save = NULL; 5870 } 5871#endif /* USE_XAA */ 5872 5873 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5874 "Disposing cursor info\n"); 5875 if (info->cursor) xf86DestroyCursorInfoRec(info->cursor); 5876 info->cursor = NULL; 5877 5878 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5879 "Disposing DGA\n"); 5880 if (info->DGAModes) xfree(info->DGAModes); 5881 info->DGAModes = NULL; 5882 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5883 "Unmapping memory\n"); 5884 RADEONUnmapMem(pScrn); 5885 5886 pScrn->vtSema = FALSE; 5887 5888 xf86ClearPrimInitDone(info->pEnt->index); 5889 5890 pScreen->BlockHandler = info->BlockHandler; 5891 pScreen->CloseScreen = info->CloseScreen; 5892 return (*pScreen->CloseScreen)(scrnIndex, pScreen); 5893} 5894 5895void RADEONFreeScreen(int scrnIndex, int flags) 5896{ 5897 ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; 5898 RADEONInfoPtr info = RADEONPTR(pScrn); 5899 5900 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5901 "RADEONFreeScreen\n"); 5902 5903 /* when server quits at PreInit, we don't need do this anymore*/ 5904 if (!info) return; 5905 5906#ifdef WITH_VGAHW 5907 if (info->VGAAccess && xf86LoaderCheckSymbol("vgaHWFreeHWRec")) 5908 vgaHWFreeHWRec(pScrn); 5909#endif 5910 RADEONFreeRec(pScrn); 5911} 5912 5913static void RADEONForceSomeClocks(ScrnInfoPtr pScrn) 5914{ 5915 /* It appears from r300 and rv100 may need some clocks forced-on */ 5916 uint32_t tmp; 5917 5918 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); 5919 tmp |= RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_VIP; 5920 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); 5921} 5922 5923static void RADEONSetDynamicClock(ScrnInfoPtr pScrn, int mode) 5924{ 5925 RADEONInfoPtr info = RADEONPTR(pScrn); 5926 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 5927 unsigned char *RADEONMMIO = info->MMIO; 5928 uint32_t tmp; 5929 switch(mode) { 5930 case 0: /* Turn everything OFF (ForceON to everything)*/ 5931 if ( !pRADEONEnt->HasCRTC2 ) { 5932 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); 5933 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_HDP | 5934 RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_TOP | 5935 RADEON_SCLK_FORCE_E2 | RADEON_SCLK_FORCE_SE | 5936 RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_VIP | 5937 RADEON_SCLK_FORCE_RE | RADEON_SCLK_FORCE_PB | 5938 RADEON_SCLK_FORCE_TAM | RADEON_SCLK_FORCE_TDM | 5939 RADEON_SCLK_FORCE_RB); 5940 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); 5941 } else if (info->ChipFamily == CHIP_FAMILY_RV350) { 5942 /* for RV350/M10, no delays are required. */ 5943 tmp = INPLL(pScrn, R300_SCLK_CNTL2); 5944 tmp |= (R300_SCLK_FORCE_TCL | 5945 R300_SCLK_FORCE_GA | 5946 R300_SCLK_FORCE_CBA); 5947 OUTPLL(pScrn, R300_SCLK_CNTL2, tmp); 5948 5949 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); 5950 tmp |= (RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | 5951 RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 | 5952 RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 | 5953 R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT | 5954 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR | 5955 R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX | 5956 R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK | 5957 R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0); 5958 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); 5959 5960 tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL); 5961 tmp |= RADEON_SCLK_MORE_FORCEON; 5962 OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp); 5963 5964 tmp = INPLL(pScrn, RADEON_MCLK_CNTL); 5965 tmp |= (RADEON_FORCEON_MCLKA | 5966 RADEON_FORCEON_MCLKB | 5967 RADEON_FORCEON_YCLKA | 5968 RADEON_FORCEON_YCLKB | 5969 RADEON_FORCEON_MC); 5970 OUTPLL(pScrn, RADEON_MCLK_CNTL, tmp); 5971 5972 tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); 5973 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | 5974 RADEON_PIXCLK_DAC_ALWAYS_ONb | 5975 R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF); 5976 OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp); 5977 5978 tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL); 5979 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | 5980 RADEON_PIX2CLK_DAC_ALWAYS_ONb | 5981 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | 5982 R300_DVOCLK_ALWAYS_ONb | 5983 RADEON_PIXCLK_BLEND_ALWAYS_ONb | 5984 RADEON_PIXCLK_GV_ALWAYS_ONb | 5985 R300_PIXCLK_DVO_ALWAYS_ONb | 5986 RADEON_PIXCLK_LVDS_ALWAYS_ONb | 5987 RADEON_PIXCLK_TMDS_ALWAYS_ONb | 5988 R300_PIXCLK_TRANS_ALWAYS_ONb | 5989 R300_PIXCLK_TVO_ALWAYS_ONb | 5990 R300_P2G2CLK_ALWAYS_ONb | 5991 R300_P2G2CLK_ALWAYS_ONb | 5992 R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF); 5993 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp); 5994 } else { 5995 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); 5996 tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2); 5997 tmp |= RADEON_SCLK_FORCE_SE; 5998 5999 if ( !pRADEONEnt->HasCRTC2 ) { 6000 tmp |= ( RADEON_SCLK_FORCE_RB | 6001 RADEON_SCLK_FORCE_TDM | 6002 RADEON_SCLK_FORCE_TAM | 6003 RADEON_SCLK_FORCE_PB | 6004 RADEON_SCLK_FORCE_RE | 6005 RADEON_SCLK_FORCE_VIP | 6006 RADEON_SCLK_FORCE_IDCT | 6007 RADEON_SCLK_FORCE_TOP | 6008 RADEON_SCLK_FORCE_DISP1 | 6009 RADEON_SCLK_FORCE_DISP2 | 6010 RADEON_SCLK_FORCE_HDP ); 6011 } else if ((info->ChipFamily == CHIP_FAMILY_R300) || 6012 (info->ChipFamily == CHIP_FAMILY_R350)) { 6013 tmp |= ( RADEON_SCLK_FORCE_HDP | 6014 RADEON_SCLK_FORCE_DISP1 | 6015 RADEON_SCLK_FORCE_DISP2 | 6016 RADEON_SCLK_FORCE_TOP | 6017 RADEON_SCLK_FORCE_IDCT | 6018 RADEON_SCLK_FORCE_VIP); 6019 } 6020 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); 6021 6022 usleep(16000); 6023 6024 if ((info->ChipFamily == CHIP_FAMILY_R300) || 6025 (info->ChipFamily == CHIP_FAMILY_R350)) { 6026 tmp = INPLL(pScrn, R300_SCLK_CNTL2); 6027 tmp |= ( R300_SCLK_FORCE_TCL | 6028 R300_SCLK_FORCE_GA | 6029 R300_SCLK_FORCE_CBA); 6030 OUTPLL(pScrn, R300_SCLK_CNTL2, tmp); 6031 usleep(16000); 6032 } 6033 6034 if (info->IsIGP) { 6035 tmp = INPLL(pScrn, RADEON_MCLK_CNTL); 6036 tmp &= ~(RADEON_FORCEON_MCLKA | 6037 RADEON_FORCEON_YCLKA); 6038 OUTPLL(pScrn, RADEON_MCLK_CNTL, tmp); 6039 usleep(16000); 6040 } 6041 6042 if ((info->ChipFamily == CHIP_FAMILY_RV200) || 6043 (info->ChipFamily == CHIP_FAMILY_RV250) || 6044 (info->ChipFamily == CHIP_FAMILY_RV280)) { 6045 tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL); 6046 tmp |= RADEON_SCLK_MORE_FORCEON; 6047 OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp); 6048 usleep(16000); 6049 } 6050 6051 tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL); 6052 tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb | 6053 RADEON_PIX2CLK_DAC_ALWAYS_ONb | 6054 RADEON_PIXCLK_BLEND_ALWAYS_ONb | 6055 RADEON_PIXCLK_GV_ALWAYS_ONb | 6056 RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb | 6057 RADEON_PIXCLK_LVDS_ALWAYS_ONb | 6058 RADEON_PIXCLK_TMDS_ALWAYS_ONb); 6059 6060 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp); 6061 usleep(16000); 6062 6063 tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); 6064 tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | 6065 RADEON_PIXCLK_DAC_ALWAYS_ONb); 6066 OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp); 6067 } 6068 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Dynamic Clock Scaling Disabled\n"); 6069 break; 6070 case 1: 6071 if (!pRADEONEnt->HasCRTC2) { 6072 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); 6073 if ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) > 6074 RADEON_CFG_ATI_REV_A13) { 6075 tmp &= ~(RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_RB); 6076 } 6077 tmp &= ~(RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 | 6078 RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_SE | 6079 RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_RE | 6080 RADEON_SCLK_FORCE_PB | RADEON_SCLK_FORCE_TAM | 6081 RADEON_SCLK_FORCE_TDM); 6082 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); 6083 } else if ((info->ChipFamily == CHIP_FAMILY_R300) || 6084 (info->ChipFamily == CHIP_FAMILY_R350) || 6085 (info->ChipFamily == CHIP_FAMILY_RV350)) { 6086 if (info->ChipFamily == CHIP_FAMILY_RV350) { 6087 tmp = INPLL(pScrn, R300_SCLK_CNTL2); 6088 tmp &= ~(R300_SCLK_FORCE_TCL | 6089 R300_SCLK_FORCE_GA | 6090 R300_SCLK_FORCE_CBA); 6091 tmp |= (R300_SCLK_TCL_MAX_DYN_STOP_LAT | 6092 R300_SCLK_GA_MAX_DYN_STOP_LAT | 6093 R300_SCLK_CBA_MAX_DYN_STOP_LAT); 6094 OUTPLL(pScrn, R300_SCLK_CNTL2, tmp); 6095 6096 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); 6097 tmp &= ~(RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP | 6098 RADEON_SCLK_FORCE_HDP | RADEON_SCLK_FORCE_DISP1 | 6099 RADEON_SCLK_FORCE_TOP | RADEON_SCLK_FORCE_E2 | 6100 R300_SCLK_FORCE_VAP | RADEON_SCLK_FORCE_IDCT | 6101 RADEON_SCLK_FORCE_VIP | R300_SCLK_FORCE_SR | 6102 R300_SCLK_FORCE_PX | R300_SCLK_FORCE_TX | 6103 R300_SCLK_FORCE_US | RADEON_SCLK_FORCE_TV_SCLK | 6104 R300_SCLK_FORCE_SU | RADEON_SCLK_FORCE_OV0); 6105 tmp |= RADEON_DYN_STOP_LAT_MASK; 6106 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); 6107 6108 tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL); 6109 tmp &= ~RADEON_SCLK_MORE_FORCEON; 6110 tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT; 6111 OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp); 6112 6113 tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); 6114 tmp |= (RADEON_PIXCLK_ALWAYS_ONb | 6115 RADEON_PIXCLK_DAC_ALWAYS_ONb); 6116 OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp); 6117 6118 tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL); 6119 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | 6120 RADEON_PIX2CLK_DAC_ALWAYS_ONb | 6121 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb | 6122 R300_DVOCLK_ALWAYS_ONb | 6123 RADEON_PIXCLK_BLEND_ALWAYS_ONb | 6124 RADEON_PIXCLK_GV_ALWAYS_ONb | 6125 R300_PIXCLK_DVO_ALWAYS_ONb | 6126 RADEON_PIXCLK_LVDS_ALWAYS_ONb | 6127 RADEON_PIXCLK_TMDS_ALWAYS_ONb | 6128 R300_PIXCLK_TRANS_ALWAYS_ONb | 6129 R300_PIXCLK_TVO_ALWAYS_ONb | 6130 R300_P2G2CLK_ALWAYS_ONb | 6131 R300_P2G2CLK_ALWAYS_ONb); 6132 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp); 6133 6134 tmp = INPLL(pScrn, RADEON_MCLK_MISC); 6135 tmp |= (RADEON_MC_MCLK_DYN_ENABLE | 6136 RADEON_IO_MCLK_DYN_ENABLE); 6137 OUTPLL(pScrn, RADEON_MCLK_MISC, tmp); 6138 6139 tmp = INPLL(pScrn, RADEON_MCLK_CNTL); 6140 tmp |= (RADEON_FORCEON_MCLKA | 6141 RADEON_FORCEON_MCLKB); 6142 6143 tmp &= ~(RADEON_FORCEON_YCLKA | 6144 RADEON_FORCEON_YCLKB | 6145 RADEON_FORCEON_MC); 6146 6147 /* Some releases of vbios have set DISABLE_MC_MCLKA 6148 and DISABLE_MC_MCLKB bits in the vbios table. Setting these 6149 bits will cause H/W hang when reading video memory with dynamic clocking 6150 enabled. */ 6151 if ((tmp & R300_DISABLE_MC_MCLKA) && 6152 (tmp & R300_DISABLE_MC_MCLKB)) { 6153 /* If both bits are set, then check the active channels */ 6154 tmp = INPLL(pScrn, RADEON_MCLK_CNTL); 6155 if (info->RamWidth == 64) { 6156 if (INREG(RADEON_MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY) 6157 tmp &= ~R300_DISABLE_MC_MCLKB; 6158 else 6159 tmp &= ~R300_DISABLE_MC_MCLKA; 6160 } else { 6161 tmp &= ~(R300_DISABLE_MC_MCLKA | 6162 R300_DISABLE_MC_MCLKB); 6163 } 6164 } 6165 6166 OUTPLL(pScrn, RADEON_MCLK_CNTL, tmp); 6167 } else { 6168 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); 6169 tmp &= ~(R300_SCLK_FORCE_VAP); 6170 tmp |= RADEON_SCLK_FORCE_CP; 6171 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); 6172 usleep(15000); 6173 6174 tmp = INPLL(pScrn, R300_SCLK_CNTL2); 6175 tmp &= ~(R300_SCLK_FORCE_TCL | 6176 R300_SCLK_FORCE_GA | 6177 R300_SCLK_FORCE_CBA); 6178 OUTPLL(pScrn, R300_SCLK_CNTL2, tmp); 6179 } 6180 } else { 6181 tmp = INPLL(pScrn, RADEON_CLK_PWRMGT_CNTL); 6182 6183 tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK | 6184 RADEON_DISP_DYN_STOP_LAT_MASK | 6185 RADEON_DYN_STOP_MODE_MASK); 6186 6187 tmp |= (RADEON_ENGIN_DYNCLK_MODE | 6188 (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT)); 6189 OUTPLL(pScrn, RADEON_CLK_PWRMGT_CNTL, tmp); 6190 usleep(15000); 6191 6192 tmp = INPLL(pScrn, RADEON_CLK_PIN_CNTL); 6193 tmp |= RADEON_SCLK_DYN_START_CNTL; 6194 OUTPLL(pScrn, RADEON_CLK_PIN_CNTL, tmp); 6195 usleep(15000); 6196 6197 /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200 6198 to lockup randomly, leave them as set by BIOS. 6199 */ 6200 tmp = INPLL(pScrn, RADEON_SCLK_CNTL); 6201 /*tmp &= RADEON_SCLK_SRC_SEL_MASK;*/ 6202 tmp &= ~RADEON_SCLK_FORCEON_MASK; 6203 6204 /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300*/ 6205 if (((info->ChipFamily == CHIP_FAMILY_RV250) && 6206 ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) < 6207 RADEON_CFG_ATI_REV_A13)) || 6208 ((info->ChipFamily == CHIP_FAMILY_RV100) && 6209 ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <= 6210 RADEON_CFG_ATI_REV_A13))){ 6211 tmp |= RADEON_SCLK_FORCE_CP; 6212 tmp |= RADEON_SCLK_FORCE_VIP; 6213 } 6214 6215 OUTPLL(pScrn, RADEON_SCLK_CNTL, tmp); 6216 6217 if ((info->ChipFamily == CHIP_FAMILY_RV200) || 6218 (info->ChipFamily == CHIP_FAMILY_RV250) || 6219 (info->ChipFamily == CHIP_FAMILY_RV280)) { 6220 tmp = INPLL(pScrn, RADEON_SCLK_MORE_CNTL); 6221 tmp &= ~RADEON_SCLK_MORE_FORCEON; 6222 6223 /* RV200::A11 A12 RV250::A11 A12 */ 6224 if (((info->ChipFamily == CHIP_FAMILY_RV200) || 6225 (info->ChipFamily == CHIP_FAMILY_RV250)) && 6226 ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) < 6227 RADEON_CFG_ATI_REV_A13)) { 6228 tmp |= RADEON_SCLK_MORE_FORCEON; 6229 } 6230 OUTPLL(pScrn, RADEON_SCLK_MORE_CNTL, tmp); 6231 usleep(15000); 6232 } 6233 6234 /* RV200::A11 A12, RV250::A11 A12 */ 6235 if (((info->ChipFamily == CHIP_FAMILY_RV200) || 6236 (info->ChipFamily == CHIP_FAMILY_RV250)) && 6237 ((INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) < 6238 RADEON_CFG_ATI_REV_A13)) { 6239 tmp = INPLL(pScrn, RADEON_PLL_PWRMGT_CNTL); 6240 tmp |= RADEON_TCL_BYPASS_DISABLE; 6241 OUTPLL(pScrn, RADEON_PLL_PWRMGT_CNTL, tmp); 6242 } 6243 usleep(15000); 6244 6245 /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK)*/ 6246 tmp = INPLL(pScrn, RADEON_PIXCLKS_CNTL); 6247 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb | 6248 RADEON_PIX2CLK_DAC_ALWAYS_ONb | 6249 RADEON_PIXCLK_BLEND_ALWAYS_ONb | 6250 RADEON_PIXCLK_GV_ALWAYS_ONb | 6251 RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb | 6252 RADEON_PIXCLK_LVDS_ALWAYS_ONb | 6253 RADEON_PIXCLK_TMDS_ALWAYS_ONb); 6254 6255 OUTPLL(pScrn, RADEON_PIXCLKS_CNTL, tmp); 6256 usleep(15000); 6257 6258 tmp = INPLL(pScrn, RADEON_VCLK_ECP_CNTL); 6259 tmp |= (RADEON_PIXCLK_ALWAYS_ONb | 6260 RADEON_PIXCLK_DAC_ALWAYS_ONb); 6261 6262 OUTPLL(pScrn, RADEON_VCLK_ECP_CNTL, tmp); 6263 usleep(15000); 6264 } 6265 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Dynamic Clock Scaling Enabled\n"); 6266 break; 6267 default: 6268 break; 6269 } 6270} 6271