radeon_driver.c revision e68e9bb9
1/* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining 8 * a copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation on the rights to use, copy, modify, merge, 11 * publish, distribute, sublicense, and/or sell copies of the Software, 12 * and to permit persons to whom the Software is furnished to do so, 13 * subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 */ 28 29#ifdef HAVE_CONFIG_H 30#include "config.h" 31#endif 32 33/* 34 * Authors: 35 * Kevin E. Martin <martin@xfree86.org> 36 * Rickard E. Faith <faith@valinux.com> 37 * Alan Hourihane <alanh@fairlite.demon.co.uk> 38 * 39 * Credits: 40 * 41 * Thanks to Ani Joshi <ajoshi@shell.unixbox.com> for providing source 42 * code to his Radeon driver. Portions of this file are based on the 43 * initialization code for that driver. 44 * 45 * References: 46 * 47 * !!!! FIXME !!!! 48 * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical 49 * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April 50 * 1999. 51 * 52 * RAGE 128 Software Development Manual (Technical Reference Manual P/N 53 * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. 54 * 55 * This server does not yet support these XFree86 4.0 features: 56 * !!!! FIXME !!!! 57 * DDC1 & DDC2 58 * shadowfb 59 * overlay planes 60 * 61 * Modified by Marc Aurele La France (tsi@xfree86.org) for ATI driver merge. 62 * 63 * Mergedfb and pseudo xinerama support added by Alex Deucher (agd5f@yahoo.com) 64 * based on the sis driver by Thomas Winischhofer. 65 * 66 */ 67 68#include <string.h> 69#include <stdio.h> 70 71 /* Driver data structures */ 72#include "radeon.h" 73#include "radeon_reg.h" 74#include "radeon_macros.h" 75#include "radeon_probe.h" 76#include "radeon_version.h" 77#include "radeon_atombios.h" 78 79#ifdef XF86DRI 80#define _XF86DRI_SERVER_ 81#include "radeon_dri.h" 82#include "radeon_drm.h" 83#include "sarea.h" 84#endif 85 86#include "fb.h" 87 88 /* colormap initialization */ 89#include "micmap.h" 90#include "dixstruct.h" 91 92 /* X and server generic header files */ 93#include "xf86.h" 94#include "xf86_OSproc.h" 95#include "xf86RandR12.h" 96#if GET_ABI_MAJOR(ABI_VIDEODRV_VERSION) < 6 97#include "xf86RAC.h" 98#include "xf86Resources.h" 99#endif 100#include "xf86cmap.h" 101#include "vbe.h" 102 103#include "shadow.h" 104 /* vgaHW definitions */ 105#ifdef WITH_VGAHW 106#include "vgaHW.h" 107#endif 108 109#ifdef HAVE_XEXTPROTO_71 110#include <X11/extensions/dpmsconst.h> 111#else 112#define DPMS_SERVER 113#include <X11/extensions/dpms.h> 114#endif 115 116 117#include "atipciids.h" 118#include "radeon_chipset_gen.h" 119 120 121#include "radeon_chipinfo_gen.h" 122 123 /* Forward definitions for driver functions */ 124static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen); 125static Bool RADEONSaveScreen(ScreenPtr pScreen, int mode); 126static void RADEONSave(ScrnInfoPtr pScrn); 127 128static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 129 130static void 131RADEONSaveBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 132 133#ifdef XF86DRI 134static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 135#endif 136 137static const OptionInfoRec RADEONOptions[] = { 138 { OPTION_NOACCEL, "NoAccel", OPTV_BOOLEAN, {0}, FALSE }, 139 { OPTION_SW_CURSOR, "SWcursor", OPTV_BOOLEAN, {0}, FALSE }, 140 { OPTION_DAC_6BIT, "Dac6Bit", OPTV_BOOLEAN, {0}, FALSE }, 141 { OPTION_DAC_8BIT, "Dac8Bit", OPTV_BOOLEAN, {0}, TRUE }, 142#ifdef XF86DRI 143 { OPTION_BUS_TYPE, "BusType", OPTV_ANYSTR, {0}, FALSE }, 144 { OPTION_CP_PIO, "CPPIOMode", OPTV_BOOLEAN, {0}, FALSE }, 145 { OPTION_USEC_TIMEOUT, "CPusecTimeout", OPTV_INTEGER, {0}, FALSE }, 146 { OPTION_AGP_MODE, "AGPMode", OPTV_INTEGER, {0}, FALSE }, 147 { OPTION_AGP_FW, "AGPFastWrite", OPTV_BOOLEAN, {0}, FALSE }, 148 { OPTION_GART_SIZE_OLD, "AGPSize", OPTV_INTEGER, {0}, FALSE }, 149 { OPTION_GART_SIZE, "GARTSize", OPTV_INTEGER, {0}, FALSE }, 150 { OPTION_RING_SIZE, "RingSize", OPTV_INTEGER, {0}, FALSE }, 151 { OPTION_BUFFER_SIZE, "BufferSize", OPTV_INTEGER, {0}, FALSE }, 152 { OPTION_DEPTH_MOVE, "EnableDepthMoves", OPTV_BOOLEAN, {0}, FALSE }, 153 { OPTION_PAGE_FLIP, "EnablePageFlip", OPTV_BOOLEAN, {0}, FALSE }, 154 { OPTION_NO_BACKBUFFER, "NoBackBuffer", OPTV_BOOLEAN, {0}, FALSE }, 155 { OPTION_XV_DMA, "DMAForXv", OPTV_BOOLEAN, {0}, FALSE }, 156 { OPTION_FBTEX_PERCENT, "FBTexPercent", OPTV_INTEGER, {0}, FALSE }, 157 { OPTION_DEPTH_BITS, "DepthBits", OPTV_INTEGER, {0}, FALSE }, 158 { OPTION_PCIAPER_SIZE, "PCIAPERSize", OPTV_INTEGER, {0}, FALSE }, 159#ifdef USE_EXA 160 { OPTION_ACCEL_DFS, "AccelDFS", OPTV_BOOLEAN, {0}, FALSE }, 161#endif 162#endif 163 { OPTION_IGNORE_EDID, "IgnoreEDID", OPTV_BOOLEAN, {0}, FALSE }, 164 { OPTION_CUSTOM_EDID, "CustomEDID", OPTV_ANYSTR, {0}, FALSE }, 165 { OPTION_DISP_PRIORITY, "DisplayPriority", OPTV_ANYSTR, {0}, FALSE }, 166 { OPTION_PANEL_SIZE, "PanelSize", OPTV_ANYSTR, {0}, FALSE }, 167 { OPTION_MIN_DOTCLOCK, "ForceMinDotClock", OPTV_FREQ, {0}, FALSE }, 168 { OPTION_COLOR_TILING, "ColorTiling", OPTV_BOOLEAN, {0}, FALSE }, 169#ifdef XvExtension 170 { OPTION_VIDEO_KEY, "VideoKey", OPTV_INTEGER, {0}, FALSE }, 171 { OPTION_RAGE_THEATRE_CRYSTAL, "RageTheatreCrystal", OPTV_INTEGER, {0}, FALSE }, 172 { OPTION_RAGE_THEATRE_TUNER_PORT, "RageTheatreTunerPort", OPTV_INTEGER, {0}, FALSE }, 173 { OPTION_RAGE_THEATRE_COMPOSITE_PORT, "RageTheatreCompositePort", OPTV_INTEGER, {0}, FALSE }, 174 { OPTION_RAGE_THEATRE_SVIDEO_PORT, "RageTheatreSVideoPort", OPTV_INTEGER, {0}, FALSE }, 175 { OPTION_TUNER_TYPE, "TunerType", OPTV_INTEGER, {0}, FALSE }, 176 { OPTION_RAGE_THEATRE_MICROC_PATH, "RageTheatreMicrocPath", OPTV_STRING, {0}, FALSE }, 177 { OPTION_RAGE_THEATRE_MICROC_TYPE, "RageTheatreMicrocType", OPTV_STRING, {0}, FALSE }, 178 { OPTION_SCALER_WIDTH, "ScalerWidth", OPTV_INTEGER, {0}, FALSE }, 179#endif 180#ifdef RENDER 181 { OPTION_RENDER_ACCEL, "RenderAccel", OPTV_BOOLEAN, {0}, FALSE }, 182 { OPTION_SUBPIXEL_ORDER, "SubPixelOrder", OPTV_ANYSTR, {0}, FALSE }, 183#endif 184 { OPTION_CLOCK_GATING, "ClockGating", OPTV_BOOLEAN, {0}, FALSE }, 185 { OPTION_VGA_ACCESS, "VGAAccess", OPTV_BOOLEAN, {0}, TRUE }, 186 { OPTION_REVERSE_DDC, "ReverseDDC", OPTV_BOOLEAN, {0}, FALSE }, 187 { OPTION_LVDS_PROBE_PLL, "LVDSProbePLL", OPTV_BOOLEAN, {0}, FALSE }, 188 { OPTION_ACCELMETHOD, "AccelMethod", OPTV_STRING, {0}, FALSE }, 189 { OPTION_DRI, "DRI", OPTV_BOOLEAN, {0}, FALSE }, 190 { OPTION_CONNECTORTABLE, "ConnectorTable", OPTV_STRING, {0}, FALSE }, 191 { OPTION_DEFAULT_CONNECTOR_TABLE, "DefaultConnectorTable", OPTV_BOOLEAN, {0}, FALSE }, 192 { OPTION_DEFAULT_TMDS_PLL, "DefaultTMDSPLL", OPTV_BOOLEAN, {0}, FALSE }, 193#if defined(__powerpc__) 194 { OPTION_MAC_MODEL, "MacModel", OPTV_STRING, {0}, FALSE }, 195#endif 196 { OPTION_TVDAC_LOAD_DETECT, "TVDACLoadDetect", OPTV_BOOLEAN, {0}, FALSE }, 197 { OPTION_FORCE_TVOUT, "ForceTVOut", OPTV_BOOLEAN, {0}, FALSE }, 198 { OPTION_TVSTD, "TVStandard", OPTV_STRING, {0}, FALSE }, 199 { OPTION_IGNORE_LID_STATUS, "IgnoreLidStatus", OPTV_BOOLEAN, {0}, FALSE }, 200 { OPTION_DEFAULT_TVDAC_ADJ, "DefaultTVDACAdj", OPTV_BOOLEAN, {0}, FALSE }, 201 { OPTION_INT10, "Int10", OPTV_BOOLEAN, {0}, FALSE }, 202 { OPTION_EXA_VSYNC, "EXAVSync", OPTV_BOOLEAN, {0}, FALSE }, 203 { OPTION_ATOM_TVOUT, "ATOMTVOut", OPTV_BOOLEAN, {0}, FALSE }, 204 { OPTION_R4XX_ATOM, "R4xxATOM", OPTV_BOOLEAN, {0}, FALSE }, 205 { OPTION_FORCE_LOW_POWER, "ForceLowPowerMode", OPTV_BOOLEAN, {0}, FALSE }, 206 { OPTION_DYNAMIC_PM, "DynamicPM", OPTV_BOOLEAN, {0}, FALSE }, 207 { OPTION_NEW_PLL, "NewPLL", OPTV_BOOLEAN, {0}, FALSE }, 208 { OPTION_ZAPHOD_HEADS, "ZaphodHeads", OPTV_STRING, {0}, FALSE }, 209 { -1, NULL, OPTV_NONE, {0}, FALSE } 210}; 211 212const OptionInfoRec *RADEONOptionsWeak(void) { return RADEONOptions; } 213 214extern _X_EXPORT int gRADEONEntityIndex; 215 216static int getRADEONEntityIndex(void) 217{ 218 return gRADEONEntityIndex; 219} 220 221struct RADEONInt10Save { 222 uint32_t MEM_CNTL; 223 uint32_t MEMSIZE; 224 uint32_t MPP_TB_CONFIG; 225}; 226 227static Bool RADEONMapMMIO(ScrnInfoPtr pScrn); 228static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn); 229 230static void * 231radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode, 232 CARD32 *size, void *closure) 233{ 234 ScrnInfoPtr pScrn = xf86Screens[screen->myNum]; 235 RADEONInfoPtr info = RADEONPTR(pScrn); 236 int stride; 237 238 stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8; 239 *size = stride; 240 241 return ((uint8_t *)info->FB + pScrn->fbOffset + row * stride + offset); 242} 243static Bool 244RADEONCreateScreenResources (ScreenPtr pScreen) 245{ 246 ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; 247 RADEONInfoPtr info = RADEONPTR(pScrn); 248 PixmapPtr pixmap; 249 250 pScreen->CreateScreenResources = info->CreateScreenResources; 251 if (!(*pScreen->CreateScreenResources)(pScreen)) 252 return FALSE; 253 pScreen->CreateScreenResources = RADEONCreateScreenResources; 254 255 if (info->r600_shadow_fb) { 256 pixmap = pScreen->GetScreenPixmap(pScreen); 257 258 if (!shadowAdd(pScreen, pixmap, shadowUpdatePackedWeak(), 259 radeonShadowWindow, 0, NULL)) 260 return FALSE; 261 } 262 return TRUE; 263} 264 265RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn) 266{ 267 DevUnion *pPriv; 268 RADEONInfoPtr info = RADEONPTR(pScrn); 269 pPriv = xf86GetEntityPrivate(info->pEnt->index, 270 getRADEONEntityIndex()); 271 return pPriv->ptr; 272} 273 274static void 275RADEONPreInt10Save(ScrnInfoPtr pScrn, void **pPtr) 276{ 277 RADEONInfoPtr info = RADEONPTR(pScrn); 278 unsigned char *RADEONMMIO = info->MMIO; 279 uint32_t CardTmp; 280 static struct RADEONInt10Save SaveStruct = { 0, 0, 0 }; 281 282 if (!IS_AVIVO_VARIANT) { 283 /* Save the values and zap MEM_CNTL */ 284 SaveStruct.MEM_CNTL = INREG(RADEON_MEM_CNTL); 285 SaveStruct.MEMSIZE = INREG(RADEON_CONFIG_MEMSIZE); 286 SaveStruct.MPP_TB_CONFIG = INREG(RADEON_MPP_TB_CONFIG); 287 288 /* 289 * Zap MEM_CNTL and set MPP_TB_CONFIG<31:24> to 4 290 */ 291 OUTREG(RADEON_MEM_CNTL, 0); 292 CardTmp = SaveStruct.MPP_TB_CONFIG & 0x00ffffffu; 293 CardTmp |= 0x04 << 24; 294 OUTREG(RADEON_MPP_TB_CONFIG, CardTmp); 295 } 296 297 *pPtr = (void *)&SaveStruct; 298} 299 300static void 301RADEONPostInt10Check(ScrnInfoPtr pScrn, void *ptr) 302{ 303 RADEONInfoPtr info = RADEONPTR(pScrn); 304 unsigned char *RADEONMMIO = info->MMIO; 305 struct RADEONInt10Save *pSave = ptr; 306 uint32_t CardTmp; 307 308 /* If we don't have a valid (non-zero) saved MEM_CNTL, get out now */ 309 if (!pSave || !pSave->MEM_CNTL) 310 return; 311 312 if (IS_AVIVO_VARIANT) 313 return; 314 315 /* 316 * If either MEM_CNTL is currently zero or inconistent (configured for 317 * two channels with the two channels configured differently), restore 318 * the saved registers. 319 */ 320 CardTmp = INREG(RADEON_MEM_CNTL); 321 if (!CardTmp || 322 ((CardTmp & 1) && 323 (((CardTmp >> 8) & 0xff) != ((CardTmp >> 24) & 0xff)))) { 324 /* Restore the saved registers */ 325 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 326 "Restoring MEM_CNTL (%08lx), setting to %08lx\n", 327 (unsigned long)CardTmp, (unsigned long)pSave->MEM_CNTL); 328 OUTREG(RADEON_MEM_CNTL, pSave->MEM_CNTL); 329 330 CardTmp = INREG(RADEON_CONFIG_MEMSIZE); 331 if (CardTmp != pSave->MEMSIZE) { 332 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 333 "Restoring CONFIG_MEMSIZE (%08lx), setting to %08lx\n", 334 (unsigned long)CardTmp, (unsigned long)pSave->MEMSIZE); 335 OUTREG(RADEON_CONFIG_MEMSIZE, pSave->MEMSIZE); 336 } 337 } 338 339 CardTmp = INREG(RADEON_MPP_TB_CONFIG); 340 if ((CardTmp & 0xff000000u) != (pSave->MPP_TB_CONFIG & 0xff000000u)) { 341 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 342 "Restoring MPP_TB_CONFIG<31:24> (%02lx), setting to %02lx\n", 343 (unsigned long)CardTmp >> 24, 344 (unsigned long)pSave->MPP_TB_CONFIG >> 24); 345 CardTmp &= 0x00ffffffu; 346 CardTmp |= (pSave->MPP_TB_CONFIG & 0xff000000u); 347 OUTREG(RADEON_MPP_TB_CONFIG, CardTmp); 348 } 349} 350 351/* Allocate our private RADEONInfoRec */ 352Bool RADEONGetRec(ScrnInfoPtr pScrn) 353{ 354 if (pScrn->driverPrivate) return TRUE; 355 356 pScrn->driverPrivate = xnfcalloc(sizeof(RADEONInfoRec), 1); 357 return TRUE; 358} 359 360/* Free our private RADEONInfoRec */ 361void RADEONFreeRec(ScrnInfoPtr pScrn) 362{ 363 RADEONInfoPtr info; 364 int i; 365 366 if (!pScrn || !pScrn->driverPrivate) return; 367 368 info = RADEONPTR(pScrn); 369 370 if (info->cp) { 371 free(info->cp); 372 info->cp = NULL; 373 } 374 375 if (info->dri) { 376 free(info->dri); 377 info->dri = NULL; 378 } 379 380 if (info->accel_state) { 381 free(info->accel_state); 382 info->accel_state = NULL; 383 } 384 385 for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) { 386 if (info->encoders[i]) { 387 if (info->encoders[i]->dev_priv) { 388 free(info->encoders[i]->dev_priv); 389 info->encoders[i]->dev_priv = NULL; 390 } 391 free(info->encoders[i]); 392 info->encoders[i]= NULL; 393 } 394 } 395 396 free(pScrn->driverPrivate); 397 pScrn->driverPrivate = NULL; 398} 399 400/* Memory map the MMIO region. Used during pre-init and by RADEONMapMem, 401 * below 402 */ 403static Bool RADEONMapMMIO(ScrnInfoPtr pScrn) 404{ 405#ifdef XSERVER_LIBPCIACCESS 406 int err; 407#endif 408 RADEONInfoPtr info = RADEONPTR(pScrn); 409 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 410 411 if (pRADEONEnt->MMIO) { 412 pRADEONEnt->MMIO_cnt++; 413 info->MMIO = pRADEONEnt->MMIO; 414 return TRUE; 415 } 416 417#ifndef XSERVER_LIBPCIACCESS 418 419 info->MMIO = xf86MapPciMem(pScrn->scrnIndex, 420 VIDMEM_MMIO | VIDMEM_READSIDEEFFECT, 421 info->PciTag, 422 info->MMIOAddr, 423 info->MMIOSize); 424 425 if (!info->MMIO) 426 return FALSE; 427#else 428 429 err = pci_device_map_range(info->PciInfo, 430 info->MMIOAddr, 431 info->MMIOSize, 432 PCI_DEV_MAP_FLAG_WRITABLE, 433 &info->MMIO); 434 435 if (err) { 436 xf86DrvMsg (pScrn->scrnIndex, X_ERROR, 437 "Unable to map MMIO aperture. %s (%d)\n", 438 strerror (err), err); 439 return FALSE; 440 } 441 442#endif 443 444 pRADEONEnt->MMIO = info->MMIO; 445 pRADEONEnt->MMIO_cnt = 1; 446 return TRUE; 447} 448 449/* Unmap the MMIO region. Used during pre-init and by RADEONUnmapMem, 450 * below 451 */ 452static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn) 453{ 454 RADEONInfoPtr info = RADEONPTR(pScrn); 455 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 456 457 /* refcount for zaphod */ 458 if (--pRADEONEnt->MMIO_cnt != 0) { 459 info->MMIO = NULL; 460 return TRUE; 461 } 462 463#ifndef XSERVER_LIBPCIACCESS 464 xf86UnMapVidMem(pScrn->scrnIndex, info->MMIO, info->MMIOSize); 465#else 466 pci_device_unmap_range(info->PciInfo, info->MMIO, info->MMIOSize); 467#endif 468 469 pRADEONEnt->MMIO = NULL; 470 info->MMIO = NULL; 471 return TRUE; 472} 473 474/* Memory map the frame buffer. Used by RADEONMapMem, below. */ 475static Bool RADEONMapFB(ScrnInfoPtr pScrn) 476{ 477#ifdef XSERVER_LIBPCIACCESS 478 int err; 479#endif 480 RADEONInfoPtr info = RADEONPTR(pScrn); 481 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 482 483 if (pRADEONEnt->FB) { 484 pRADEONEnt->FB_cnt++; 485 info->FB = pRADEONEnt->FB; 486 return TRUE; 487 } 488 489 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 490 "Map: 0x%016llx, 0x%08lx\n", info->LinearAddr, info->FbMapSize); 491 492#ifndef XSERVER_LIBPCIACCESS 493 494 info->FB = xf86MapPciMem(pScrn->scrnIndex, 495 VIDMEM_FRAMEBUFFER, 496 info->PciTag, 497 info->LinearAddr, 498 info->FbMapSize); 499 500 if (!info->FB) return FALSE; 501 502#else 503 504 err = pci_device_map_range(info->PciInfo, 505 info->LinearAddr, 506 info->FbMapSize, 507 PCI_DEV_MAP_FLAG_WRITABLE | 508 PCI_DEV_MAP_FLAG_WRITE_COMBINE, 509 &info->FB); 510 511 if (err) { 512 xf86DrvMsg (pScrn->scrnIndex, X_ERROR, 513 "Unable to map FB aperture. %s (%d)\n", 514 strerror (err), err); 515 return FALSE; 516 } 517 518#endif 519 520 pRADEONEnt->FB = info->FB; 521 pRADEONEnt->FB_cnt = 1; 522 return TRUE; 523} 524 525/* Unmap the frame buffer. Used by RADEONUnmapMem, below. */ 526static Bool RADEONUnmapFB(ScrnInfoPtr pScrn) 527{ 528 RADEONInfoPtr info = RADEONPTR(pScrn); 529 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 530 531 /* refcount for zaphod */ 532 if (--pRADEONEnt->FB_cnt != 0) { 533 info->FB = NULL; 534 return TRUE; 535 } 536 537#ifndef XSERVER_LIBPCIACCESS 538 xf86UnMapVidMem(pScrn->scrnIndex, info->FB, info->FbMapSize); 539#else 540 pci_device_unmap_range(info->PciInfo, info->FB, info->FbMapSize); 541#endif 542 543 pRADEONEnt->FB = NULL; 544 info->FB = NULL; 545 return TRUE; 546} 547 548/* Memory map the MMIO region and the frame buffer */ 549static Bool RADEONMapMem(ScrnInfoPtr pScrn) 550{ 551 if (!RADEONMapMMIO(pScrn)) return FALSE; 552 if (!RADEONMapFB(pScrn)) { 553 RADEONUnmapMMIO(pScrn); 554 return FALSE; 555 } 556 return TRUE; 557} 558 559/* Unmap the MMIO region and the frame buffer */ 560static Bool RADEONUnmapMem(ScrnInfoPtr pScrn) 561{ 562 if (!RADEONUnmapMMIO(pScrn) || !RADEONUnmapFB(pScrn)) return FALSE; 563 return TRUE; 564} 565 566void RADEONPllErrataAfterIndex(RADEONInfoPtr info) 567{ 568 unsigned char *RADEONMMIO = info->MMIO; 569 570 if (!(info->ChipErrata & CHIP_ERRATA_PLL_DUMMYREADS)) 571 return; 572 573 /* This workaround is necessary on rv200 and RS200 or PLL 574 * reads may return garbage (among others...) 575 */ 576 (void)INREG(RADEON_CLOCK_CNTL_DATA); 577 (void)INREG(RADEON_CRTC_GEN_CNTL); 578} 579 580void RADEONPllErrataAfterData(RADEONInfoPtr info) 581{ 582 unsigned char *RADEONMMIO = info->MMIO; 583 584 /* This workarounds is necessary on RV100, RS100 and RS200 chips 585 * or the chip could hang on a subsequent access 586 */ 587 if (info->ChipErrata & CHIP_ERRATA_PLL_DELAY) { 588 /* we can't deal with posted writes here ... */ 589 usleep(5000); 590 } 591 592 /* This function is required to workaround a hardware bug in some (all?) 593 * revisions of the R300. This workaround should be called after every 594 * CLOCK_CNTL_INDEX register access. If not, register reads afterward 595 * may not be correct. 596 */ 597 if (info->ChipErrata & CHIP_ERRATA_R300_CG) { 598 uint32_t save, tmp; 599 600 save = INREG(RADEON_CLOCK_CNTL_INDEX); 601 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 602 OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp); 603 tmp = INREG(RADEON_CLOCK_CNTL_DATA); 604 OUTREG(RADEON_CLOCK_CNTL_INDEX, save); 605 } 606} 607 608/* Read PLL register */ 609unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr) 610{ 611 RADEONInfoPtr info = RADEONPTR(pScrn); 612 unsigned char *RADEONMMIO = info->MMIO; 613 uint32_t data; 614 615 OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f); 616 RADEONPllErrataAfterIndex(info); 617 data = INREG(RADEON_CLOCK_CNTL_DATA); 618 RADEONPllErrataAfterData(info); 619 620 return data; 621} 622 623/* Write PLL information */ 624void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, uint32_t data) 625{ 626 RADEONInfoPtr info = RADEONPTR(pScrn); 627 unsigned char *RADEONMMIO = info->MMIO; 628 629 OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) | 630 RADEON_PLL_WR_EN)); 631 RADEONPllErrataAfterIndex(info); 632 OUTREG(RADEON_CLOCK_CNTL_DATA, data); 633 RADEONPllErrataAfterData(info); 634} 635 636/* Read MC register */ 637unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr) 638{ 639 RADEONInfoPtr info = RADEONPTR(pScrn); 640 unsigned char *RADEONMMIO = info->MMIO; 641 uint32_t data; 642 643 if ((info->ChipFamily == CHIP_FAMILY_RS690) || 644 (info->ChipFamily == CHIP_FAMILY_RS740)) { 645 OUTREG(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); 646 data = INREG(RS690_MC_DATA); 647 } else if (info->ChipFamily == CHIP_FAMILY_RS600) { 648 OUTREG(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) | RS600_MC_IND_CITF_ARB0)); 649 data = INREG(RS600_MC_DATA); 650 } else if ((info->ChipFamily == CHIP_FAMILY_RS780) || 651 (info->ChipFamily == CHIP_FAMILY_RS880)) { 652 OUTREG(RS780_MC_INDEX, (addr & RS780_MC_INDEX_MASK)); 653 data = INREG(RS780_MC_DATA); 654 } else if (info->ChipFamily >= CHIP_FAMILY_R600) { 655 data = 0; 656 } else if (IS_AVIVO_VARIANT) { 657 OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000); 658 (void)INREG(AVIVO_MC_INDEX); 659 data = INREG(AVIVO_MC_DATA); 660 661 OUTREG(AVIVO_MC_INDEX, 0); 662 (void)INREG(AVIVO_MC_INDEX); 663 } else { 664 OUTREG(R300_MC_IND_INDEX, addr & 0x3f); 665 (void)INREG(R300_MC_IND_INDEX); 666 data = INREG(R300_MC_IND_DATA); 667 668 OUTREG(R300_MC_IND_INDEX, 0); 669 (void)INREG(R300_MC_IND_INDEX); 670 } 671 672 return data; 673} 674 675/* Write MC information */ 676void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, uint32_t data) 677{ 678 RADEONInfoPtr info = RADEONPTR(pScrn); 679 unsigned char *RADEONMMIO = info->MMIO; 680 681 if ((info->ChipFamily == CHIP_FAMILY_RS690) || 682 (info->ChipFamily == CHIP_FAMILY_RS740)) { 683 OUTREG(RS690_MC_INDEX, ((addr & RS690_MC_INDEX_MASK) | 684 RS690_MC_INDEX_WR_EN)); 685 OUTREG(RS690_MC_DATA, data); 686 OUTREG(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); 687 } else if (info->ChipFamily == CHIP_FAMILY_RS600) { 688 OUTREG(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) | 689 RS600_MC_IND_CITF_ARB0 | 690 RS600_MC_IND_WR_EN)); 691 OUTREG(RS600_MC_DATA, data); 692 } else if ((info->ChipFamily == CHIP_FAMILY_RS780) || 693 (info->ChipFamily == CHIP_FAMILY_RS880)) { 694 OUTREG(RS780_MC_INDEX, ((addr & RS780_MC_INDEX_MASK) | 695 RS780_MC_INDEX_WR_EN)); 696 OUTREG(RS780_MC_DATA, data); 697 } else if (info->ChipFamily >= CHIP_FAMILY_R600) { 698 // do nothing 699 } else if (IS_AVIVO_VARIANT) { 700 OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0xff0000); 701 (void)INREG(AVIVO_MC_INDEX); 702 OUTREG(AVIVO_MC_DATA, data); 703 OUTREG(AVIVO_MC_INDEX, 0); 704 (void)INREG(AVIVO_MC_INDEX); 705 } else { 706 OUTREG(R300_MC_IND_INDEX, (((addr) & 0x3f) | 707 R300_MC_IND_WR_EN)); 708 (void)INREG(R300_MC_IND_INDEX); 709 OUTREG(R300_MC_IND_DATA, data); 710 OUTREG(R300_MC_IND_INDEX, 0); 711 (void)INREG(R300_MC_IND_INDEX); 712 } 713} 714 715/* Read PCIE register */ 716unsigned RADEONINPCIE(ScrnInfoPtr pScrn, int addr) 717{ 718 RADEONInfoPtr info = RADEONPTR(pScrn); 719 unsigned char *RADEONMMIO = info->MMIO; 720 CARD32 data; 721 722 OUTREG(RADEON_PCIE_INDEX, addr & 0xff); 723 data = INREG(RADEON_PCIE_DATA); 724 725 return data; 726} 727 728/* Write PCIE register */ 729void RADEONOUTPCIE(ScrnInfoPtr pScrn, int addr, uint32_t data) 730{ 731 RADEONInfoPtr info = RADEONPTR(pScrn); 732 unsigned char *RADEONMMIO = info->MMIO; 733 734 OUTREG(RADEON_PCIE_INDEX, ((addr) & 0xff)); 735 OUTREG(RADEON_PCIE_DATA, data); 736} 737 738/* Read PCIE PORT register */ 739unsigned R600INPCIE_PORT(ScrnInfoPtr pScrn, int addr) 740{ 741 RADEONInfoPtr info = RADEONPTR(pScrn); 742 unsigned char *RADEONMMIO = info->MMIO; 743 CARD32 data; 744 745 OUTREG(R600_PCIE_PORT_INDEX, addr & 0xff); 746 data = INREG(R600_PCIE_PORT_DATA); 747 748 return data; 749} 750 751/* Write PCIE PORT register */ 752void R600OUTPCIE_PORT(ScrnInfoPtr pScrn, int addr, uint32_t data) 753{ 754 RADEONInfoPtr info = RADEONPTR(pScrn); 755 unsigned char *RADEONMMIO = info->MMIO; 756 757 OUTREG(R600_PCIE_PORT_INDEX, ((addr) & 0xff)); 758 OUTREG(R600_PCIE_PORT_DATA, data); 759} 760 761static Bool radeon_get_mc_idle(ScrnInfoPtr pScrn) 762{ 763 RADEONInfoPtr info = RADEONPTR(pScrn); 764 unsigned char *RADEONMMIO = info->MMIO; 765 766 if (info->ChipFamily >= CHIP_FAMILY_CEDAR) { 767 if (INREG(R600_SRBM_STATUS) & 0x1f00) 768 return FALSE; 769 else 770 return TRUE; 771 } else if (info->ChipFamily >= CHIP_FAMILY_R600) { 772 if (INREG(R600_SRBM_STATUS) & 0x3f00) 773 return FALSE; 774 else 775 return TRUE; 776 } else if (info->ChipFamily == CHIP_FAMILY_RV515) { 777 if (INMC(pScrn, RV515_MC_STATUS) & RV515_MC_STATUS_IDLE) 778 return TRUE; 779 else 780 return FALSE; 781 } else if (info->ChipFamily == CHIP_FAMILY_RS600) { 782 if (INMC(pScrn, RS600_MC_STATUS) & RS600_MC_IDLE) 783 return TRUE; 784 else 785 return FALSE; 786 } else if ((info->ChipFamily == CHIP_FAMILY_RS690) || 787 (info->ChipFamily == CHIP_FAMILY_RS740)) { 788 if (INMC(pScrn, RS690_MC_STATUS) & RS690_MC_STATUS_IDLE) 789 return TRUE; 790 else 791 return FALSE; 792 } else if (info->ChipFamily >= CHIP_FAMILY_R520) { 793 if (INMC(pScrn, R520_MC_STATUS) & R520_MC_STATUS_IDLE) 794 return TRUE; 795 else 796 return FALSE; 797 } else if ((info->ChipFamily == CHIP_FAMILY_RS400) || 798 (info->ChipFamily == CHIP_FAMILY_RS480)) { 799 if (INREG(RADEON_MC_STATUS) & RADEON_MC_IDLE) 800 return TRUE; 801 else 802 return FALSE; 803 } else if (IS_R300_VARIANT) { 804 if (INREG(RADEON_MC_STATUS) & R300_MC_IDLE) 805 return TRUE; 806 else 807 return FALSE; 808 } else { 809 if (INREG(RADEON_MC_STATUS) & RADEON_MC_IDLE) 810 return TRUE; 811 else 812 return FALSE; 813 } 814} 815 816#define LOC_FB 0x1 817#define LOC_AGP 0x2 818static void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, uint32_t fb_loc, uint32_t agp_loc, uint32_t agp_loc_hi) 819{ 820 RADEONInfoPtr info = RADEONPTR(pScrn); 821 unsigned char *RADEONMMIO = info->MMIO; 822 823 /* evergreen is same as r7xx */ 824 if (info->ChipFamily >= CHIP_FAMILY_RV770) { 825 if (mask & LOC_FB) 826 OUTREG(R700_MC_VM_FB_LOCATION, fb_loc); 827 if (mask & LOC_AGP) { 828 OUTREG(R700_MC_VM_AGP_BOT, agp_loc); 829 OUTREG(R700_MC_VM_AGP_TOP, agp_loc_hi); 830 } 831 } else if (info->ChipFamily >= CHIP_FAMILY_R600) { 832 if (mask & LOC_FB) 833 OUTREG(R600_MC_VM_FB_LOCATION, fb_loc); 834 if (mask & LOC_AGP) { 835 OUTREG(R600_MC_VM_AGP_BOT, agp_loc); 836 OUTREG(R600_MC_VM_AGP_TOP, agp_loc_hi); 837 } 838 } else if (info->ChipFamily == CHIP_FAMILY_RV515) { 839 if (mask & LOC_FB) 840 OUTMC(pScrn, RV515_MC_FB_LOCATION, fb_loc); 841 if (mask & LOC_AGP) 842 OUTMC(pScrn, RV515_MC_AGP_LOCATION, agp_loc); 843 (void)INMC(pScrn, RV515_MC_AGP_LOCATION); 844 } else if (info->ChipFamily == CHIP_FAMILY_RS600) { 845 if (mask & LOC_FB) 846 OUTMC(pScrn, RS600_MC_FB_LOCATION, fb_loc); 847 if (mask & LOC_AGP) 848 OUTMC(pScrn, RS600_MC_AGP_LOCATION, agp_loc); 849 } else if ((info->ChipFamily == CHIP_FAMILY_RS690) || 850 (info->ChipFamily == CHIP_FAMILY_RS740)) { 851 if (mask & LOC_FB) 852 OUTMC(pScrn, RS690_MC_FB_LOCATION, fb_loc); 853 if (mask & LOC_AGP) 854 OUTMC(pScrn, RS690_MC_AGP_LOCATION, agp_loc); 855 } else if (info->ChipFamily >= CHIP_FAMILY_R520) { 856 if (mask & LOC_FB) 857 OUTMC(pScrn, R520_MC_FB_LOCATION, fb_loc); 858 if (mask & LOC_AGP) 859 OUTMC(pScrn, R520_MC_AGP_LOCATION, agp_loc); 860 (void)INMC(pScrn, R520_MC_FB_LOCATION); 861 } else { 862 if (mask & LOC_FB) 863 OUTREG(RADEON_MC_FB_LOCATION, fb_loc); 864 if (mask & LOC_AGP) 865 OUTREG(RADEON_MC_AGP_LOCATION, agp_loc); 866 } 867} 868 869static void radeon_read_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, uint32_t *fb_loc, uint32_t *agp_loc, uint32_t *agp_loc_hi) 870{ 871 RADEONInfoPtr info = RADEONPTR(pScrn); 872 unsigned char *RADEONMMIO = info->MMIO; 873 874 /* evergreen is same as r7xx */ 875 if (info->ChipFamily >= CHIP_FAMILY_RV770) { 876 if (mask & LOC_FB) 877 *fb_loc = INREG(R700_MC_VM_FB_LOCATION); 878 if (mask & LOC_AGP) { 879 *agp_loc = INREG(R700_MC_VM_AGP_BOT); 880 *agp_loc_hi = INREG(R700_MC_VM_AGP_TOP); 881 } 882 } else if (info->ChipFamily >= CHIP_FAMILY_R600) { 883 if (mask & LOC_FB) 884 *fb_loc = INREG(R600_MC_VM_FB_LOCATION); 885 if (mask & LOC_AGP) { 886 *agp_loc = INREG(R600_MC_VM_AGP_BOT); 887 *agp_loc_hi = INREG(R600_MC_VM_AGP_TOP); 888 } 889 } else if (info->ChipFamily == CHIP_FAMILY_RV515) { 890 if (mask & LOC_FB) 891 *fb_loc = INMC(pScrn, RV515_MC_FB_LOCATION); 892 if (mask & LOC_AGP) { 893 *agp_loc = INMC(pScrn, RV515_MC_AGP_LOCATION); 894 *agp_loc_hi = 0; 895 } 896 } else if (info->ChipFamily == CHIP_FAMILY_RS600) { 897 if (mask & LOC_FB) 898 *fb_loc = INMC(pScrn, RS600_MC_FB_LOCATION); 899 if (mask & LOC_AGP) { 900 *agp_loc = INMC(pScrn, RS600_MC_AGP_LOCATION); 901 *agp_loc_hi = 0; 902 } 903 } else if ((info->ChipFamily == CHIP_FAMILY_RS690) || 904 (info->ChipFamily == CHIP_FAMILY_RS740)) { 905 if (mask & LOC_FB) 906 *fb_loc = INMC(pScrn, RS690_MC_FB_LOCATION); 907 if (mask & LOC_AGP) { 908 *agp_loc = INMC(pScrn, RS690_MC_AGP_LOCATION); 909 *agp_loc_hi = 0; 910 } 911 } else if (info->ChipFamily >= CHIP_FAMILY_R520) { 912 if (mask & LOC_FB) 913 *fb_loc = INMC(pScrn, R520_MC_FB_LOCATION); 914 if (mask & LOC_AGP) { 915 *agp_loc = INMC(pScrn, R520_MC_AGP_LOCATION); 916 *agp_loc_hi = 0; 917 } 918 } else { 919 if (mask & LOC_FB) 920 *fb_loc = INREG(RADEON_MC_FB_LOCATION); 921 if (mask & LOC_AGP) 922 *agp_loc = INREG(RADEON_MC_AGP_LOCATION); 923 } 924} 925 926#if 0 927/* Read PAL information (only used for debugging) */ 928static int RADEONINPAL(int idx) 929{ 930 RADEONInfoPtr info = RADEONPTR(pScrn); 931 unsigned char *RADEONMMIO = info->MMIO; 932 933 OUTREG(RADEON_PALETTE_INDEX, idx << 16); 934 return INREG(RADEON_PALETTE_DATA); 935} 936#endif 937 938/* Wait for vertical sync on primary CRTC */ 939void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn) 940{ 941 RADEONInfoPtr info = RADEONPTR(pScrn); 942 unsigned char *RADEONMMIO = info->MMIO; 943 uint32_t crtc_gen_cntl; 944 struct timeval timeout; 945 946 crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); 947 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) || 948 !(crtc_gen_cntl & RADEON_CRTC_EN)) 949 return; 950 951 /* Clear the CRTC_VBLANK_SAVE bit */ 952 OUTREG(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR); 953 954 /* Wait for it to go back up */ 955 radeon_init_timeout(&timeout, RADEON_VSYNC_TIMEOUT); 956 while (!(INREG(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_SAVE) && 957 !radeon_timedout(&timeout)) 958 usleep(100); 959} 960 961/* Wait for vertical sync on secondary CRTC */ 962void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn) 963{ 964 RADEONInfoPtr info = RADEONPTR(pScrn); 965 unsigned char *RADEONMMIO = info->MMIO; 966 uint32_t crtc2_gen_cntl; 967 struct timeval timeout; 968 969 crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); 970 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) || 971 !(crtc2_gen_cntl & RADEON_CRTC2_EN)) 972 return; 973 974 /* Clear the CRTC2_VBLANK_SAVE bit */ 975 OUTREG(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR); 976 977 /* Wait for it to go back up */ 978 radeon_init_timeout(&timeout, RADEON_VSYNC_TIMEOUT); 979 while (!(INREG(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_SAVE) && 980 !radeon_timedout(&timeout)) 981 usleep(100); 982} 983 984 985/* Compute log base 2 of val */ 986int RADEONMinBits(int val) 987{ 988 int bits; 989 990 if (!val) return 1; 991 for (bits = 0; val; val >>= 1, ++bits); 992 return bits; 993} 994 995/* Compute n/d with rounding */ 996static int RADEONDiv(int n, int d) 997{ 998 return (n + (d / 2)) / d; 999} 1000 1001static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn) 1002{ 1003 RADEONInfoPtr info = RADEONPTR(pScrn); 1004 RADEONPLLPtr pll = &info->pll; 1005 unsigned char *RADEONMMIO = info->MMIO; 1006 unsigned char ppll_div_sel; 1007 unsigned mpll_fb_div, spll_fb_div, M; 1008 unsigned xclk, tmp, ref_div; 1009 int hTotal, vTotal, num, denom, m, n; 1010 float hz, prev_xtal, vclk, xtal, mpll, spll; 1011 long total_usecs; 1012 struct timeval start, stop, to1, to2; 1013 unsigned int f1, f2, f3; 1014 int tries = 0; 1015 1016 prev_xtal = 0; 1017 again: 1018 xtal = 0; 1019 if (++tries > 10) 1020 goto failed; 1021 1022 gettimeofday(&to1, NULL); 1023 f1 = INREG(RADEON_CRTC_CRNT_FRAME); 1024 for (;;) { 1025 f2 = INREG(RADEON_CRTC_CRNT_FRAME); 1026 if (f1 != f2) 1027 break; 1028 gettimeofday(&to2, NULL); 1029 if ((to2.tv_sec - to1.tv_sec) > 1) { 1030 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Clock not counting...\n"); 1031 goto failed; 1032 } 1033 } 1034 gettimeofday(&start, NULL); 1035 for(;;) { 1036 f3 = INREG(RADEON_CRTC_CRNT_FRAME); 1037 if (f3 != f2) 1038 break; 1039 gettimeofday(&to2, NULL); 1040 if ((to2.tv_sec - start.tv_sec) > 1) 1041 goto failed; 1042 } 1043 gettimeofday(&stop, NULL); 1044 1045 if ((stop.tv_sec - start.tv_sec) != 0) 1046 goto again; 1047 total_usecs = abs(stop.tv_usec - start.tv_usec); 1048 if (total_usecs == 0) 1049 goto again; 1050 hz = 1000000.0/(float)total_usecs; 1051 1052 hTotal = ((INREG(RADEON_CRTC_H_TOTAL_DISP) & 0x3ff) + 1) * 8; 1053 vTotal = ((INREG(RADEON_CRTC_V_TOTAL_DISP) & 0xfff) + 1); 1054 vclk = (float)(hTotal * (float)(vTotal * hz)); 1055 1056 switch((INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x30000) >> 16) { 1057 case 0: 1058 default: 1059 num = 1; 1060 denom = 1; 1061 break; 1062 case 1: 1063 n = ((INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) >> 16) & 0xff); 1064 m = (INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) & 0xff); 1065 num = 2*n; 1066 denom = 2*m; 1067 break; 1068 case 2: 1069 n = ((INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) >> 8) & 0xff); 1070 m = (INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) & 0xff); 1071 num = 2*n; 1072 denom = 2*m; 1073 break; 1074 } 1075 1076 ppll_div_sel = INREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; 1077 RADEONPllErrataAfterIndex(info); 1078 1079 n = (INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel) & 0x7ff); 1080 m = (INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x3ff); 1081 1082 num *= n; 1083 denom *= m; 1084 1085 switch ((INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) { 1086 case 1: 1087 denom *= 2; 1088 break; 1089 case 2: 1090 denom *= 4; 1091 break; 1092 case 3: 1093 denom *= 8; 1094 break; 1095 case 4: 1096 denom *= 3; 1097 break; 1098 case 6: 1099 denom *= 6; 1100 break; 1101 case 7: 1102 denom *= 12; 1103 break; 1104 } 1105 1106 xtal = (int)(vclk *(float)denom/(float)num); 1107 1108 if ((xtal > 26900000) && (xtal < 27100000)) 1109 xtal = 2700; 1110 else if ((xtal > 14200000) && (xtal < 14400000)) 1111 xtal = 1432; 1112 else if ((xtal > 29400000) && (xtal < 29600000)) 1113 xtal = 2950; 1114 else 1115 goto again; 1116 failed: 1117 if (xtal == 0) { 1118 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Failed to probe xtal value ! " 1119 "Using default 27Mhz\n"); 1120 xtal = 2700; 1121 } else { 1122 if (prev_xtal == 0) { 1123 prev_xtal = xtal; 1124 tries = 0; 1125 goto again; 1126 } else if (prev_xtal != xtal) { 1127 prev_xtal = 0; 1128 goto again; 1129 } 1130 } 1131 1132 tmp = INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV); 1133 ref_div = INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x3ff; 1134 1135 /* Some sanity check based on the BIOS code .... */ 1136 if (ref_div < 2) { 1137 uint32_t tmp; 1138 tmp = INPLL(pScrn, RADEON_PPLL_REF_DIV); 1139 if (IS_R300_VARIANT 1140 || (info->ChipFamily == CHIP_FAMILY_RS300) 1141 || (info->ChipFamily == CHIP_FAMILY_RS400) 1142 || (info->ChipFamily == CHIP_FAMILY_RS480)) 1143 ref_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> 1144 R300_PPLL_REF_DIV_ACC_SHIFT; 1145 else 1146 ref_div = tmp & RADEON_PPLL_REF_DIV_MASK; 1147 if (ref_div < 2) 1148 ref_div = 12; 1149 } 1150 1151 /* Calculate "base" xclk straight from MPLL, though that isn't 1152 * really useful (hopefully). This isn't called XCLK anymore on 1153 * radeon's... 1154 */ 1155 mpll_fb_div = (tmp & 0xff00) >> 8; 1156 spll_fb_div = (tmp & 0xff0000) >> 16; 1157 M = (tmp & 0xff); 1158 xclk = RADEONDiv((2 * mpll_fb_div * xtal), (M)); 1159 1160 /* 1161 * Calculate MCLK based on MCLK-A 1162 */ 1163 mpll = (2.0 * (float)mpll_fb_div * (xtal / 100.0)) / (float)M; 1164 spll = (2.0 * (float)spll_fb_div * (xtal / 100.0)) / (float)M; 1165 1166 tmp = INPLL(pScrn, RADEON_MCLK_CNTL) & 0x7; 1167 switch(tmp) { 1168 case 1: info->mclk = mpll; break; 1169 case 2: info->mclk = mpll / 2.0; break; 1170 case 3: info->mclk = mpll / 4.0; break; 1171 case 4: info->mclk = mpll / 8.0; break; 1172 case 7: info->mclk = spll; break; 1173 default: 1174 info->mclk = 200.00; 1175 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unsupported MCLKA source" 1176 " setting %d, can't probe MCLK value !\n", tmp); 1177 } 1178 1179 /* 1180 * Calculate SCLK 1181 */ 1182 tmp = INPLL(pScrn, RADEON_SCLK_CNTL) & 0x7; 1183 switch(tmp) { 1184 case 1: info->sclk = spll; break; 1185 case 2: info->sclk = spll / 2.0; break; 1186 case 3: info->sclk = spll / 4.0; break; 1187 case 4: info->sclk = spll / 8.0; break; 1188 case 7: info->sclk = mpll; break; 1189 default: 1190 info->sclk = 200.00; 1191 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unsupported SCLK source" 1192 " setting %d, can't probe SCLK value !\n", tmp); 1193 } 1194 1195 /* we're done, hopefully these are sane values */ 1196 pll->reference_div = ref_div; 1197 pll->xclk = xclk; 1198 pll->reference_freq = xtal; 1199 1200 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Probed PLL values: xtal: %f Mhz, " 1201 "sclk: %f Mhz, mclk: %f Mhz\n", xtal/100.0, info->sclk, info->mclk); 1202 1203 return TRUE; 1204} 1205 1206static void RADEONGetClockInfo(ScrnInfoPtr pScrn) 1207{ 1208 RADEONInfoPtr info = RADEONPTR (pScrn); 1209 RADEONPLLPtr pll = &info->pll; 1210 double min_dotclock; 1211 1212 if (RADEONGetClockInfoFromBIOS(pScrn)) { 1213 if (pll->reference_div < 2) { 1214 /* retrive it from register setting for fitting into current PLL algorithm. 1215 We'll probably need a new routine to calculate the best ref_div from BIOS 1216 provided min_input_pll and max_input_pll 1217 */ 1218 if (!IS_AVIVO_VARIANT) { 1219 uint32_t tmp; 1220 tmp = INPLL(pScrn, RADEON_PPLL_REF_DIV); 1221 if (IS_R300_VARIANT || 1222 (info->ChipFamily == CHIP_FAMILY_RS300) || 1223 (info->ChipFamily == CHIP_FAMILY_RS400) || 1224 (info->ChipFamily == CHIP_FAMILY_RS480)) { 1225 pll->reference_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT; 1226 } else { 1227 pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; 1228 } 1229 } 1230 if (pll->reference_div < 2) pll->reference_div = 12; 1231 } 1232 } else { 1233 xf86DrvMsg (pScrn->scrnIndex, X_WARNING, 1234 "Video BIOS not detected, using default clock settings!\n"); 1235 1236 /* Default min/max PLL values */ 1237 if (info->ChipFamily == CHIP_FAMILY_R420 || info->ChipFamily == CHIP_FAMILY_RV410) { 1238 pll->pll_in_min = 100; 1239 pll->pll_in_max = 1350; 1240 pll->pll_out_min = 20000; 1241 pll->pll_out_max = 50000; 1242 } else { 1243 pll->pll_in_min = 40; 1244 pll->pll_in_max = 500; 1245 pll->pll_out_min = 12500; 1246 pll->pll_out_max = 35000; 1247 } 1248 1249 if (!RADEONProbePLLParameters(pScrn)) { 1250 if (info->IsIGP) 1251 pll->reference_freq = 1432; 1252 else 1253 pll->reference_freq = 2700; 1254 1255 pll->reference_div = 12; 1256 pll->xclk = 10300; 1257 1258 info->sclk = 200.00; 1259 info->mclk = 200.00; 1260 } 1261 } 1262 1263 /* card limits for computing PLLs */ 1264 if (IS_AVIVO_VARIANT) { 1265 pll->min_post_div = 2; 1266 pll->max_post_div = 0x7f; 1267 pll->min_frac_feedback_div = 0; 1268 pll->max_frac_feedback_div = 9; 1269 } else { 1270 pll->min_post_div = 1; 1271 pll->max_post_div = 12; //16 on crtc0 1272 pll->min_frac_feedback_div = 0; 1273 pll->max_frac_feedback_div = 0; 1274 } 1275 pll->min_ref_div = 2; 1276 pll->max_ref_div = 0x3ff; 1277 pll->min_feedback_div = 4; 1278 pll->max_feedback_div = 0x7ff; 1279 pll->best_vco = 0; 1280 1281 xf86DrvMsg (pScrn->scrnIndex, X_INFO, 1282 "PLL parameters: rf=%u rd=%u min=%u max=%u; xclk=%u\n", 1283 pll->reference_freq, 1284 pll->reference_div, 1285 (unsigned)pll->pll_out_min, (unsigned)pll->pll_out_max, 1286 pll->xclk); 1287 1288 /* (Some?) Radeon BIOSes seem too lie about their minimum dot 1289 * clocks. Allow users to override the detected minimum dot clock 1290 * value (e.g., and allow it to be suitable for TV sets). 1291 */ 1292 if (xf86GetOptValFreq(info->Options, OPTION_MIN_DOTCLOCK, 1293 OPTUNITS_MHZ, &min_dotclock)) { 1294 if (min_dotclock < 12 || min_dotclock*100 >= pll->pll_out_max) { 1295 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1296 "Illegal minimum dotclock specified %.2f MHz " 1297 "(option ignored)\n", 1298 min_dotclock); 1299 } else { 1300 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1301 "Forced minimum dotclock to %.2f MHz " 1302 "(instead of detected %.2f MHz)\n", 1303 min_dotclock, ((double)pll->pll_out_min/1000)); 1304 pll->pll_out_min = min_dotclock * 1000; 1305 } 1306 } 1307} 1308 1309 1310 1311/* This is called by RADEONPreInit to set up the default visual */ 1312Bool RADEONPreInitVisual(ScrnInfoPtr pScrn) 1313{ 1314 RADEONInfoPtr info = RADEONPTR(pScrn); 1315 1316 if (!xf86SetDepthBpp(pScrn, 0, 0, 0, Support32bppFb)) 1317 return FALSE; 1318 1319 switch (pScrn->depth) { 1320 case 8: 1321 case 15: 1322 case 16: 1323 case 24: 1324 break; 1325 1326 default: 1327 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1328 "Given depth (%d) is not supported by %s driver\n", 1329 pScrn->depth, RADEON_DRIVER_NAME); 1330 return FALSE; 1331 } 1332 1333 xf86PrintDepthBpp(pScrn); 1334 1335 info->pix24bpp = xf86GetBppFromDepth(pScrn, 1336 pScrn->depth); 1337 info->CurrentLayout.bitsPerPixel = pScrn->bitsPerPixel; 1338 info->CurrentLayout.depth = pScrn->depth; 1339 info->CurrentLayout.pixel_bytes = pScrn->bitsPerPixel / 8; 1340 info->CurrentLayout.pixel_code = (pScrn->bitsPerPixel != 16 1341 ? pScrn->bitsPerPixel 1342 : pScrn->depth); 1343 1344 if (info->pix24bpp == 24) { 1345 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1346 "Radeon does NOT support 24bpp\n"); 1347 return FALSE; 1348 } 1349 1350 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1351 "Pixel depth = %d bits stored in %d byte%s (%d bpp pixmaps)\n", 1352 pScrn->depth, 1353 info->CurrentLayout.pixel_bytes, 1354 info->CurrentLayout.pixel_bytes > 1 ? "s" : "", 1355 info->pix24bpp); 1356 1357 if (!xf86SetDefaultVisual(pScrn, -1)) return FALSE; 1358 1359 if (pScrn->depth > 8 && pScrn->defaultVisual != TrueColor) { 1360 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1361 "Default visual (%s) is not supported at depth %d\n", 1362 xf86GetVisualName(pScrn->defaultVisual), pScrn->depth); 1363 return FALSE; 1364 } 1365 return TRUE; 1366} 1367 1368/* This is called by RADEONPreInit to handle all color weight issues */ 1369Bool RADEONPreInitWeight(ScrnInfoPtr pScrn) 1370{ 1371 RADEONInfoPtr info = RADEONPTR(pScrn); 1372 1373 /* Save flag for 6 bit DAC to use for 1374 setting CRTC registers. Otherwise use 1375 an 8 bit DAC, even if xf86SetWeight sets 1376 pScrn->rgbBits to some value other than 1377 8. */ 1378 info->dac6bits = FALSE; 1379 1380 if (pScrn->depth > 8) { 1381 rgb defaultWeight = { 0, 0, 0 }; 1382 1383 if (!xf86SetWeight(pScrn, defaultWeight, defaultWeight)) return FALSE; 1384 } else { 1385 pScrn->rgbBits = 8; 1386 if (xf86ReturnOptValBool(info->Options, OPTION_DAC_6BIT, FALSE)) { 1387 pScrn->rgbBits = 6; 1388 info->dac6bits = TRUE; 1389 } 1390 } 1391 1392 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1393 "Using %d bits per RGB (%d bit DAC)\n", 1394 pScrn->rgbBits, info->dac6bits ? 6 : 8); 1395 1396 return TRUE; 1397} 1398 1399void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, 1400 RADEONInfoPtr info) 1401{ 1402 save->mc_fb_location = info->mc_fb_location; 1403 save->mc_agp_location = info->mc_agp_location; 1404 1405 if (IS_AVIVO_VARIANT) { 1406 save->mc_agp_location_hi = info->mc_agp_location_hi; 1407 } else { 1408 save->display_base_addr = info->fbLocation; 1409 save->display2_base_addr = info->fbLocation; 1410 save->ov0_base_addr = info->fbLocation; 1411 } 1412} 1413 1414static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) 1415{ 1416 RADEONInfoPtr info = RADEONPTR(pScrn); 1417 unsigned char *RADEONMMIO = info->MMIO; 1418 uint64_t mem_size; 1419 uint64_t aper_size; 1420 1421 radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &info->mc_fb_location, 1422 &info->mc_agp_location, &info->mc_agp_location_hi); 1423 1424 /* We shouldn't use info->videoRam here which might have been clipped 1425 * but the real video RAM instead 1426 */ 1427 if (info->ChipFamily >= CHIP_FAMILY_CEDAR) { 1428 /* size in MB on evergreen */ 1429 /* XXX watch for overflow!!! */ 1430 mem_size = INREG(R600_CONFIG_MEMSIZE) * 1024 * 1024; 1431 aper_size = INREG(R600_CONFIG_APER_SIZE) * 1024 * 1024; 1432 } else if (info->ChipFamily >= CHIP_FAMILY_R600) { 1433 mem_size = INREG(R600_CONFIG_MEMSIZE); 1434 aper_size = INREG(R600_CONFIG_APER_SIZE); 1435 } else { 1436 mem_size = INREG(RADEON_CONFIG_MEMSIZE); 1437 aper_size = INREG(RADEON_CONFIG_APER_SIZE); 1438 } 1439 1440 if (mem_size == 0) 1441 mem_size = 0x800000; 1442 1443 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 1444 Novell bug 204882 + along with lots of ubuntu ones */ 1445 if (aper_size > mem_size) 1446 mem_size = aper_size; 1447 1448 /* don't map the whole FB in the internal address space. 1449 * we don't currently use fb space larger than the aperture 1450 * size and on cards with more than 512 MB of vram, this can overflow 1451 * the internal top of gart calculation on some systems. 1452 * Limit it to cards with more than 512 MB as this causes problems 1453 * on some other cards due to the way the ddx and drm set up the 1454 * internal memory map. 1455 * See fdo bug 24301. 1456 */ 1457 if (mem_size > 0x20000000) 1458 mem_size = aper_size; 1459 1460#ifdef XF86DRI 1461 /* Apply memory map limitation if using an old DRI */ 1462 if (info->directRenderingEnabled && !info->dri->newMemoryMap) { 1463 if (aper_size < mem_size) 1464 mem_size = aper_size; 1465 } 1466#endif 1467 1468 if ((info->ChipFamily != CHIP_FAMILY_RS600) && 1469 (info->ChipFamily != CHIP_FAMILY_RS690) && 1470 (info->ChipFamily != CHIP_FAMILY_RS740) && 1471 (info->ChipFamily != CHIP_FAMILY_RS780) && 1472 (info->ChipFamily != CHIP_FAMILY_RS880)) { 1473 if (info->IsIGP) 1474 info->mc_fb_location = INREG(RADEON_NB_TOM); 1475 else 1476#ifdef XF86DRI 1477 /* Old DRI has restrictions on the memory map */ 1478 if ( info->directRenderingEnabled && 1479 info->dri->pKernelDRMVersion->version_minor < 10 ) 1480 info->mc_fb_location = (mem_size - 1) & 0xffff0000U; 1481 else 1482#endif 1483 { 1484 uint64_t aper0_base; 1485 1486 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1487 aper0_base = INREG(R600_CONFIG_F0_BASE); 1488 } else { 1489 aper0_base = INREG(RADEON_CONFIG_APER_0_BASE); 1490 } 1491 1492 /* Recent chips have an "issue" with the memory controller, the 1493 * location must be aligned to the size. We just align it down, 1494 * too bad if we walk over the top of system memory, we don't 1495 * use DMA without a remapped anyway. 1496 * Affected chips are rv280, all r3xx, and all r4xx, but not IGP 1497 */ 1498 if (info->ChipFamily == CHIP_FAMILY_RV280 || 1499 info->ChipFamily == CHIP_FAMILY_R300 || 1500 info->ChipFamily == CHIP_FAMILY_R350 || 1501 info->ChipFamily == CHIP_FAMILY_RV350 || 1502 info->ChipFamily == CHIP_FAMILY_RV380 || 1503 info->ChipFamily == CHIP_FAMILY_R420 || 1504 info->ChipFamily == CHIP_FAMILY_RV410) 1505 aper0_base &= ~(mem_size - 1); 1506 1507 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1508 uint64_t mc_fb = ((aper0_base >> 24) & 0xffff) | 1509 (((aper0_base + mem_size - 1) >> 8) & 0xffff0000); 1510 info->mc_fb_location = mc_fb & 0xffffffff; 1511 ErrorF("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location); 1512 } else { 1513 uint64_t mc_fb = ((aper0_base >> 16) & 0xffff) | 1514 ((aper0_base + mem_size - 1) & 0xffff0000U); 1515 info->mc_fb_location = mc_fb & 0xffffffff; 1516 } 1517 } 1518 } 1519 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1520 info->fbLocation = (info->mc_fb_location & 0xffff) << 24; 1521 } else { 1522 info->fbLocation = (info->mc_fb_location & 0xffff) << 16; 1523 } 1524 /* Just disable the damn AGP apertures for now, it may be 1525 * re-enabled later by the DRM 1526 */ 1527 if (IS_AVIVO_VARIANT) 1528 info->mc_agp_location = 0x003f0000; 1529 else 1530 info->mc_agp_location = 0xffffffc0; 1531 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1532 "RADEONInitMemoryMap() : \n"); 1533 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1534 " mem_size : 0x%08x\n", (unsigned)mem_size); 1535 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1536 " MC_FB_LOCATION : 0x%08x\n", (unsigned)info->mc_fb_location); 1537 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1538 " MC_AGP_LOCATION : 0x%08x\n", 1539 (unsigned)info->mc_agp_location); 1540} 1541 1542static void RADEONGetVRamType(ScrnInfoPtr pScrn) 1543{ 1544 RADEONInfoPtr info = RADEONPTR(pScrn); 1545 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1546 unsigned char *RADEONMMIO = info->MMIO; 1547 uint32_t tmp; 1548 1549 if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300)) 1550 info->IsDDR = TRUE; 1551 else if (INREG(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) 1552 info->IsDDR = TRUE; 1553 else 1554 info->IsDDR = FALSE; 1555 1556 if ((info->ChipFamily >= CHIP_FAMILY_R600) && 1557 (info->ChipFamily <= CHIP_FAMILY_RV635)) { 1558 int chansize; 1559 /* r6xx */ 1560 tmp = INREG(R600_RAMCFG); 1561 if (tmp & R600_CHANSIZE_OVERRIDE) 1562 chansize = 16; 1563 else if (tmp & R600_CHANSIZE) 1564 chansize = 64; 1565 else 1566 chansize = 32; 1567 if (info->ChipFamily == CHIP_FAMILY_R600) 1568 info->RamWidth = 8 * chansize; 1569 else if (info->ChipFamily == CHIP_FAMILY_RV670) 1570 info->RamWidth = 4 * chansize; 1571 else if ((info->ChipFamily == CHIP_FAMILY_RV610) || 1572 (info->ChipFamily == CHIP_FAMILY_RV620)) 1573 info->RamWidth = chansize; 1574 else if ((info->ChipFamily == CHIP_FAMILY_RV630) || 1575 (info->ChipFamily == CHIP_FAMILY_RV635)) 1576 info->RamWidth = 2 * chansize; 1577 } else if (info->ChipFamily == CHIP_FAMILY_RV515) { 1578 /* rv515/rv550 */ 1579 tmp = INMC(pScrn, RV515_MC_CNTL); 1580 tmp &= RV515_MEM_NUM_CHANNELS_MASK; 1581 switch (tmp) { 1582 case 0: info->RamWidth = 64; break; 1583 case 1: info->RamWidth = 128; break; 1584 default: info->RamWidth = 128; break; 1585 } 1586 } else if ((info->ChipFamily >= CHIP_FAMILY_R520) && 1587 (info->ChipFamily <= CHIP_FAMILY_RV570)){ 1588 /* r520/rv530/rv560/rv570/r580 */ 1589 tmp = INMC(pScrn, R520_MC_CNTL0); 1590 switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { 1591 case 0: info->RamWidth = 32; break; 1592 case 1: info->RamWidth = 64; break; 1593 case 2: info->RamWidth = 128; break; 1594 case 3: info->RamWidth = 256; break; 1595 default: info->RamWidth = 64; break; 1596 } 1597 if (tmp & R520_MC_CHANNEL_SIZE) { 1598 info->RamWidth *= 2; 1599 } 1600 } else if ((info->ChipFamily >= CHIP_FAMILY_R300) && 1601 (info->ChipFamily <= CHIP_FAMILY_RV410)) { 1602 /* r3xx, r4xx */ 1603 tmp = INREG(RADEON_MEM_CNTL); 1604 tmp &= R300_MEM_NUM_CHANNELS_MASK; 1605 switch (tmp) { 1606 case 0: info->RamWidth = 64; break; 1607 case 1: info->RamWidth = 128; break; 1608 case 2: info->RamWidth = 256; break; 1609 default: info->RamWidth = 128; break; 1610 } 1611 } else if ((info->ChipFamily == CHIP_FAMILY_RV100) || 1612 (info->ChipFamily == CHIP_FAMILY_RS100) || 1613 (info->ChipFamily == CHIP_FAMILY_RS200)){ 1614 tmp = INREG(RADEON_MEM_CNTL); 1615 if (tmp & RV100_HALF_MODE) 1616 info->RamWidth = 32; 1617 else 1618 info->RamWidth = 64; 1619 1620 if (!pRADEONEnt->HasCRTC2) { 1621 info->RamWidth /= 4; 1622 info->IsDDR = TRUE; 1623 } 1624 } else if (info->ChipFamily <= CHIP_FAMILY_RV280) { 1625 tmp = INREG(RADEON_MEM_CNTL); 1626 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) 1627 info->RamWidth = 128; 1628 else 1629 info->RamWidth = 64; 1630 } else { 1631 /* newer IGPs */ 1632 info->RamWidth = 128; 1633 } 1634 1635 /* This may not be correct, as some cards can have half of channel disabled 1636 * ToDo: identify these cases 1637 */ 1638} 1639 1640/* 1641 * Depending on card genertation, chipset bugs, etc... the amount of vram 1642 * accessible to the CPU can vary. This function is our best shot at figuring 1643 * it out. Returns a value in KB. 1644 */ 1645static uint32_t RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn) 1646{ 1647 RADEONInfoPtr info = RADEONPTR(pScrn); 1648 unsigned char *RADEONMMIO = info->MMIO; 1649 uint32_t aper_size; 1650 unsigned char byte; 1651 1652 if (info->ChipFamily >= CHIP_FAMILY_CEDAR) 1653 /* size in MB */ 1654 aper_size = INREG(R600_CONFIG_APER_SIZE) * 1024; 1655 else if (info->ChipFamily >= CHIP_FAMILY_R600) 1656 aper_size = INREG(R600_CONFIG_APER_SIZE) / 1024; 1657 else 1658 aper_size = INREG(RADEON_CONFIG_APER_SIZE) / 1024; 1659 1660#ifdef XF86DRI 1661 /* If we use the DRI, we need to check if it's a version that has the 1662 * bug of always cropping MC_FB_LOCATION to one aperture, in which case 1663 * we need to limit the amount of accessible video memory 1664 */ 1665 if (info->directRenderingEnabled && 1666 info->dri->pKernelDRMVersion->version_minor < 23) { 1667 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1668 "[dri] limiting video memory to one aperture of %uK\n", 1669 (unsigned)aper_size); 1670 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1671 "[dri] detected radeon kernel module version 1.%d but" 1672 " 1.23 or newer is required for full memory mapping.\n", 1673 info->dri->pKernelDRMVersion->version_minor); 1674 info->dri->newMemoryMap = FALSE; 1675 return aper_size; 1676 } 1677 info->dri->newMemoryMap = TRUE; 1678#endif /* XF86DRI */ 1679 1680 if (info->ChipFamily >= CHIP_FAMILY_R600) 1681 return aper_size; 1682 1683 /* Set HDP_APER_CNTL only on cards that are known not to be broken, 1684 * that is has the 2nd generation multifunction PCI interface 1685 */ 1686 if (info->ChipFamily == CHIP_FAMILY_RV280 || 1687 info->ChipFamily == CHIP_FAMILY_RV350 || 1688 info->ChipFamily == CHIP_FAMILY_RV380 || 1689 info->ChipFamily == CHIP_FAMILY_R420 || 1690 info->ChipFamily == CHIP_FAMILY_RV410 || 1691 IS_AVIVO_VARIANT) { 1692 OUTREGP (RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, 1693 ~RADEON_HDP_APER_CNTL); 1694 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1695 "Generation 2 PCI interface, using max accessible memory\n"); 1696 return aper_size * 2; 1697 } 1698 1699 /* Older cards have all sorts of funny issues to deal with. First 1700 * check if it's a multifunction card by reading the PCI config 1701 * header type... Limit those to one aperture size 1702 */ 1703 PCI_READ_BYTE(info->PciInfo, &byte, 0xe); 1704 if (byte & 0x80) { 1705 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1706 "Generation 1 PCI interface in multifunction mode" 1707 ", accessible memory limited to one aperture\n"); 1708 return aper_size; 1709 } 1710 1711 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS 1712 * have set it up. We don't write this as it's broken on some ASICs but 1713 * we expect the BIOS to have done the right thing (might be too optimistic...) 1714 */ 1715 if (INREG(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) 1716 return aper_size * 2; 1717 1718 return aper_size; 1719} 1720 1721static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) 1722{ 1723 RADEONInfoPtr info = RADEONPTR(pScrn); 1724 EntityInfoPtr pEnt = info->pEnt; 1725 GDevPtr dev = pEnt->device; 1726 unsigned char *RADEONMMIO = info->MMIO; 1727 MessageType from = X_PROBED; 1728 uint32_t accessible, bar_size; 1729 1730 if ((!IS_AVIVO_VARIANT) && info->IsIGP) { 1731 uint32_t tom = INREG(RADEON_NB_TOM); 1732 1733 pScrn->videoRam = (((tom >> 16) - 1734 (tom & 0xffff) + 1) << 6); 1735 1736 OUTREG(RADEON_CONFIG_MEMSIZE, pScrn->videoRam * 1024); 1737 } else { 1738 if (info->ChipFamily >= CHIP_FAMILY_CEDAR) 1739 /* R600_CONFIG_MEMSIZE is MB on evergreen */ 1740 /* XXX watch for overflow!!! */ 1741 pScrn->videoRam = INREG(R600_CONFIG_MEMSIZE) * 1024; 1742 else if (info->ChipFamily >= CHIP_FAMILY_R600) 1743 pScrn->videoRam = INREG(R600_CONFIG_MEMSIZE) / 1024; 1744 else { 1745 /* Read VRAM size from card */ 1746 pScrn->videoRam = INREG(RADEON_CONFIG_MEMSIZE) / 1024; 1747 1748 /* Some production boards of m6 will return 0 if it's 8 MB */ 1749 if (pScrn->videoRam == 0) { 1750 pScrn->videoRam = 8192; 1751 OUTREG(RADEON_CONFIG_MEMSIZE, 0x800000); 1752 } 1753 } 1754 } 1755 1756 /* Get accessible memory */ 1757 accessible = RADEONGetAccessibleVRAM(pScrn); 1758 1759 /* Crop it to the size of the PCI BAR */ 1760 bar_size = PCI_REGION_SIZE(info->PciInfo, 0) / 1024; 1761 if (bar_size == 0) 1762 bar_size = 0x20000; 1763 if (accessible > bar_size) 1764 accessible = bar_size; 1765 1766 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1767 "Detected total video RAM=%dK, accessible=%uK (PCI BAR=%uK)\n", 1768 pScrn->videoRam, (unsigned)accessible, (unsigned)bar_size); 1769 if (pScrn->videoRam > accessible) 1770 pScrn->videoRam = accessible; 1771 1772 if (!IS_AVIVO_VARIANT) { 1773 info->MemCntl = INREG(RADEON_SDRAM_MODE_REG); 1774 info->BusCntl = INREG(RADEON_BUS_CNTL); 1775 } 1776 1777 RADEONGetVRamType(pScrn); 1778 1779 if (dev->videoRam) { 1780 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1781 "Video RAM override, using %d kB instead of %d kB\n", 1782 dev->videoRam, 1783 pScrn->videoRam); 1784 from = X_CONFIG; 1785 pScrn->videoRam = dev->videoRam; 1786 } 1787 1788 xf86DrvMsg(pScrn->scrnIndex, from, 1789 "Mapped VideoRAM: %d kByte (%d bit %s SDRAM)\n", pScrn->videoRam, info->RamWidth, info->IsDDR?"DDR":"SDR"); 1790 1791 /* Do this before we truncate since we only map fb once */ 1792 info->FbMapSize = (pScrn->videoRam & ~1023) * 1024; 1793 1794 if (info->IsPrimary) { 1795 pScrn->videoRam /= 2; 1796 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1797 "Using %dk of videoram for primary head\n", 1798 pScrn->videoRam); 1799 } else if (info->IsSecondary) { 1800 pScrn->videoRam /= 2; 1801 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1802 "Using %dk of videoram for secondary head\n", 1803 pScrn->videoRam); 1804 } 1805 pScrn->videoRam &= ~1023; 1806 1807 /* if the card is PCI Express reserve the last 32k for the gart table */ 1808#ifdef XF86DRI 1809 if (info->cardType == CARD_PCIE && info->directRenderingEnabled) 1810 /* work out the size of pcie aperture */ 1811 info->FbSecureSize = RADEONDRIGetPciAperTableSize(pScrn); 1812 else 1813#endif 1814 info->FbSecureSize = 0; 1815 1816 return TRUE; 1817} 1818 1819 1820/* This is called by RADEONPreInit to handle config file overrides for 1821 * things like chipset and memory regions. Also determine memory size 1822 * and type. If memory type ever needs an override, put it in this 1823 * routine. 1824 */ 1825static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) 1826{ 1827 RADEONInfoPtr info = RADEONPTR(pScrn); 1828 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1829 EntityInfoPtr pEnt = info->pEnt; 1830 GDevPtr dev = pEnt->device; 1831 unsigned char *RADEONMMIO = info->MMIO; 1832 MessageType from = X_PROBED; 1833 int i; 1834#ifdef XF86DRI 1835 const char *s; 1836 uint32_t cmd_stat; 1837#endif 1838 1839 /* Chipset */ 1840 from = X_PROBED; 1841 if (dev->chipset && *dev->chipset) { 1842 info->Chipset = xf86StringToToken(RADEONChipsets, dev->chipset); 1843 from = X_CONFIG; 1844 } else if (dev->chipID >= 0) { 1845 info->Chipset = dev->chipID; 1846 from = X_CONFIG; 1847 } else { 1848 info->Chipset = PCI_DEV_DEVICE_ID(info->PciInfo); 1849 } 1850 1851 pScrn->chipset = (char *)xf86TokenToString(RADEONChipsets, info->Chipset); 1852 if (!pScrn->chipset) { 1853 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1854 "ChipID 0x%04x is not recognized\n", info->Chipset); 1855 return FALSE; 1856 } 1857 if (info->Chipset < 0) { 1858 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1859 "Chipset \"%s\" is not recognized\n", pScrn->chipset); 1860 return FALSE; 1861 } 1862 xf86DrvMsg(pScrn->scrnIndex, from, 1863 "Chipset: \"%s\" (ChipID = 0x%04x)\n", 1864 pScrn->chipset, 1865 info->Chipset); 1866 1867 pRADEONEnt->HasCRTC2 = TRUE; 1868 info->IsMobility = FALSE; 1869 info->IsIGP = FALSE; 1870 info->IsDellServer = FALSE; 1871 info->HasSingleDAC = FALSE; 1872 info->InternalTVOut = TRUE; 1873 info->get_hardcoded_edid_from_bios = FALSE; 1874 1875 for (i = 0; i < sizeof(RADEONCards) / sizeof(RADEONCardInfo); i++) { 1876 if (info->Chipset == RADEONCards[i].pci_device_id) { 1877 RADEONCardInfo *card = &RADEONCards[i]; 1878 info->ChipFamily = card->chip_family; 1879 info->IsMobility = card->mobility; 1880 info->IsIGP = card->igp; 1881 pRADEONEnt->HasCRTC2 = !card->nocrtc2; 1882 info->HasSingleDAC = card->singledac; 1883 info->InternalTVOut = !card->nointtvout; 1884 break; 1885 } 1886 } 1887 1888 switch (info->Chipset) { 1889 case PCI_CHIP_RN50_515E: /* RN50 is based on the RV100 but 3D isn't guaranteed to work. YMMV. */ 1890 case PCI_CHIP_RN50_5969: 1891 /* Some Sun servers have a hardcoded edid so KVMs work properly */ 1892 if ((PCI_SUB_VENDOR_ID(info->PciInfo) == 0x108e) && 1893 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x4133)) 1894 info->get_hardcoded_edid_from_bios = TRUE; 1895 case PCI_CHIP_RV100_QY: 1896 case PCI_CHIP_RV100_QZ: 1897 /* DELL triple-head configuration. */ 1898 if (((PCI_SUB_VENDOR_ID(info->PciInfo) == PCI_VENDOR_DELL) && 1899 ((PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016c) || 1900 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016d) || 1901 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016e) || 1902 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016f) || 1903 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0170) || 1904 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x017d) || 1905 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x017e) || 1906 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0183) || 1907 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x018a) || 1908 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x019a) || 1909 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x01b1) || 1910 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x01b2) || 1911 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0205))) || 1912 ((PCI_SUB_VENDOR_ID(info->PciInfo) == PCI_VENDOR_HP) && 1913 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x31fb))) { 1914 info->IsDellServer = TRUE; 1915 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "DELL/HP server detected, force to special setup\n"); 1916 } 1917 break; 1918 case PCI_CHIP_RS482_5974: 1919 /* RH BZ 444586 - non mobility version 1920 * Dell appear to have the Vostro 1100 with a mobility part with the same pci-id */ 1921 if ((PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1462) && 1922 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x7141)) { 1923 info->IsMobility = FALSE; 1924 } 1925 default: 1926 break; 1927 } 1928 1929 from = X_PROBED; 1930 info->LinearAddr = PCI_REGION_BASE(info->PciInfo, 0, REGION_MEM) & ~0x1ffffffULL; 1931 pScrn->memPhysBase = info->LinearAddr; 1932 if (dev->MemBase) { 1933 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1934 "Linear address override, using 0x%016lx instead of 0x%016llx\n", 1935 dev->MemBase, 1936 info->LinearAddr); 1937 info->LinearAddr = dev->MemBase; 1938 from = X_CONFIG; 1939 } else if (!info->LinearAddr) { 1940 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1941 "No valid linear framebuffer address\n"); 1942 return FALSE; 1943 } 1944 xf86DrvMsg(pScrn->scrnIndex, from, 1945 "Linear framebuffer at 0x%016llx\n", info->LinearAddr); 1946 1947#ifndef XSERVER_LIBPCIACCESS 1948 /* BIOS */ 1949 from = X_PROBED; 1950 info->BIOSAddr = info->PciInfo->biosBase & 0xfffe0000; 1951 if (dev->BiosBase) { 1952 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1953 "BIOS address override, using 0x%08lx instead of 0x%08lx\n", 1954 (unsigned long)dev->BiosBase, 1955 (unsigned long)info->BIOSAddr); 1956 info->BIOSAddr = dev->BiosBase; 1957 from = X_CONFIG; 1958 } 1959 if (info->BIOSAddr) { 1960 xf86DrvMsg(pScrn->scrnIndex, from, 1961 "BIOS at 0x%08lx\n", (unsigned long)info->BIOSAddr); 1962 } 1963#endif 1964 1965 /* Read registers used to determine options */ 1966 /* Check chip errata */ 1967 info->ChipErrata = 0; 1968 1969 if (info->ChipFamily == CHIP_FAMILY_R300 && 1970 (INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) 1971 == RADEON_CFG_ATI_REV_A11) 1972 info->ChipErrata |= CHIP_ERRATA_R300_CG; 1973 1974 if (info->ChipFamily == CHIP_FAMILY_RV200 || 1975 info->ChipFamily == CHIP_FAMILY_RS200) 1976 info->ChipErrata |= CHIP_ERRATA_PLL_DUMMYREADS; 1977 1978 if (info->ChipFamily == CHIP_FAMILY_RV100 || 1979 info->ChipFamily == CHIP_FAMILY_RS100 || 1980 info->ChipFamily == CHIP_FAMILY_RS200) 1981 info->ChipErrata |= CHIP_ERRATA_PLL_DELAY; 1982 1983#ifdef XF86DRI 1984 /* AGP/PCI */ 1985 /* Proper autodetection of an AGP capable device requires examining 1986 * PCI config registers to determine if the device implements extended 1987 * PCI capabilities, and then walking the capability list as indicated 1988 * in the PCI 2.2 and AGP 2.0 specifications, to determine if AGP 1989 * capability is present. The procedure is outlined as follows: 1990 * 1991 * 1) Test bit 4 (CAP_LIST) of the PCI status register of the device 1992 * to determine wether or not this device implements any extended 1993 * capabilities. If this bit is zero, then the device is a PCI 2.1 1994 * or earlier device and is not AGP capable, and we can conclude it 1995 * to be a PCI device. 1996 * 1997 * 2) If bit 4 of the status register is set, then the device implements 1998 * extended capabilities. There is an 8 bit wide capabilities pointer 1999 * register located at offset 0x34 in PCI config space which points to 2000 * the first capability in a linked list of extended capabilities that 2001 * this device implements. The lower two bits of this register are 2002 * reserved and MBZ so must be masked out. 2003 * 2004 * 3) The extended capabilities list is formed by one or more extended 2005 * capabilities structures which are aligned on DWORD boundaries. 2006 * The first byte of the structure is the capability ID (CAP_ID) 2007 * indicating what extended capability this structure refers to. The 2008 * second byte of the structure is an offset from the beginning of 2009 * PCI config space pointing to the next capability in the linked 2010 * list (NEXT_PTR) or NULL (0x00) at the end of the list. The lower 2011 * two bits of this pointer are reserved and MBZ. By examining the 2012 * CAP_ID of each capability and walking through the list, we will 2013 * either find the AGP_CAP_ID (0x02) indicating this device is an 2014 * AGP device, or we'll reach the end of the list, indicating it is 2015 * a PCI device. 2016 * 2017 * Mike A. Harris <mharris@redhat.com> 2018 * 2019 * References: 2020 * - PCI Local Bus Specification Revision 2.2, Chapter 6 2021 * - AGP Interface Specification Revision 2.0, Section 6.1.5 2022 */ 2023 2024 info->cardType = CARD_PCI; 2025 2026 PCI_READ_LONG(info->PciInfo, &cmd_stat, PCI_CMD_STAT_REG); 2027 if (cmd_stat & RADEON_CAP_LIST) { 2028 uint32_t cap_ptr, cap_id; 2029 2030 PCI_READ_LONG(info->PciInfo, &cap_ptr, RADEON_CAPABILITIES_PTR_PCI_CONFIG); 2031 cap_ptr &= RADEON_CAP_PTR_MASK; 2032 2033 while(cap_ptr != RADEON_CAP_ID_NULL) { 2034 PCI_READ_LONG(info->PciInfo, &cap_id, cap_ptr); 2035 if ((cap_id & 0xff)== RADEON_CAP_ID_AGP) { 2036 info->cardType = CARD_AGP; 2037 break; 2038 } 2039 if ((cap_id & 0xff)== RADEON_CAP_ID_EXP) { 2040 info->cardType = CARD_PCIE; 2041 break; 2042 } 2043 cap_ptr = (cap_id >> 8) & RADEON_CAP_PTR_MASK; 2044 } 2045 } 2046 2047 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s card detected\n", 2048 (info->cardType==CARD_PCI) ? "PCI" : 2049 (info->cardType==CARD_PCIE) ? "PCIE" : "AGP"); 2050 2051 /* treat PCIE IGP cards as PCI */ 2052 if (info->cardType == CARD_PCIE && info->IsIGP) 2053 info->cardType = CARD_PCI; 2054 2055 /* some rs4xx cards report as agp */ 2056 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 2057 (info->ChipFamily == CHIP_FAMILY_RS480)) 2058 info->cardType = CARD_PCI; 2059 2060 if ((info->ChipFamily >= CHIP_FAMILY_R600) && info->IsIGP) 2061 info->cardType = CARD_PCIE; 2062 2063 /* not sure about gart table requirements */ 2064 if ((info->ChipFamily == CHIP_FAMILY_RS600) && info->IsIGP) 2065 info->cardType = CARD_PCIE; 2066 2067 if ((s = xf86GetOptValString(info->Options, OPTION_BUS_TYPE))) { 2068 if (strcmp(s, "AGP") == 0) { 2069 info->cardType = CARD_AGP; 2070 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into AGP mode\n"); 2071 } else if ((strcmp(s, "PCI") == 0) || 2072 (strcmp(s, "PCIE") == 0)) { 2073 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 2074 (info->ChipFamily == CHIP_FAMILY_RS480) || 2075 (info->ChipFamily == CHIP_FAMILY_RS690) || 2076 (info->ChipFamily == CHIP_FAMILY_RS740)) { 2077 info->cardType = CARD_PCI; 2078 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI mode\n"); 2079 } else if (info->ChipFamily >= CHIP_FAMILY_RV380) { 2080 info->cardType = CARD_PCIE; 2081 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI Express mode\n"); 2082 } else { 2083 info->cardType = CARD_PCI; 2084 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI mode\n"); 2085 } 2086 } else { 2087 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, 2088 "Invalid BusType option, using detected type\n"); 2089 } 2090 } 2091#endif 2092#ifdef RENDER 2093 info->RenderAccel = xf86ReturnOptValBool(info->Options, OPTION_RENDER_ACCEL, 2094 info->Chipset != PCI_CHIP_RN50_515E && 2095 info->Chipset != PCI_CHIP_RN50_5969); 2096#endif 2097 2098 info->r4xx_atom = FALSE; 2099 if (((info->ChipFamily == CHIP_FAMILY_R420) || (info->ChipFamily == CHIP_FAMILY_RV410)) && 2100 xf86ReturnOptValBool(info->Options, OPTION_R4XX_ATOM, FALSE)) { 2101 info->r4xx_atom = TRUE; 2102 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Using ATOMBIOS for R4xx chip\n"); 2103 } 2104 2105 return TRUE; 2106} 2107 2108 2109static void RADEONPreInitDDC(ScrnInfoPtr pScrn) 2110{ 2111 RADEONInfoPtr info = RADEONPTR(pScrn); 2112 /* vbeInfoPtr pVbe; */ 2113 2114 info->ddc1 = FALSE; 2115 info->ddc_bios = FALSE; 2116 if (!xf86LoadSubModule(pScrn, "ddc")) { 2117 info->ddc2 = FALSE; 2118 } else { 2119 info->ddc2 = TRUE; 2120 } 2121 2122 /* DDC can use I2C bus */ 2123 /* Load I2C if we have the code to use it */ 2124 if (info->ddc2) { 2125 xf86LoadSubModule(pScrn, "i2c"); 2126 } 2127} 2128 2129/* This is called by RADEONPreInit to initialize gamma correction */ 2130static Bool RADEONPreInitGamma(ScrnInfoPtr pScrn) 2131{ 2132 Gamma zeros = { 0.0, 0.0, 0.0 }; 2133 2134 if (!xf86SetGamma(pScrn, zeros)) return FALSE; 2135 return TRUE; 2136} 2137 2138/* This is called by RADEONPreInit to initialize the hardware cursor */ 2139static Bool RADEONPreInitCursor(ScrnInfoPtr pScrn) 2140{ 2141 RADEONInfoPtr info = RADEONPTR(pScrn); 2142 2143 if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { 2144 if (!xf86LoadSubModule(pScrn, "ramdac")) return FALSE; 2145 } 2146 return TRUE; 2147} 2148 2149/* This is called by RADEONPreInit to initialize hardware acceleration */ 2150static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) 2151{ 2152 RADEONInfoPtr info = RADEONPTR(pScrn); 2153 MessageType from; 2154#if defined(USE_EXA) && defined(USE_XAA) 2155 char *optstr; 2156#endif 2157#ifdef XF86DRI /* zaphod FbMapSize is wrong, but no dri then */ 2158 int maxy = info->FbMapSize / (pScrn->displayWidth * info->CurrentLayout.pixel_bytes); 2159#endif 2160 2161 if (!(info->accel_state = calloc(1, sizeof(struct radeon_accel_state)))) { 2162 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to allocate accel_state rec!\n"); 2163 return FALSE; 2164 } 2165 info->accel_state->fifo_slots = 0; 2166 2167 if ((info->ChipFamily == CHIP_FAMILY_RS100) || 2168 (info->ChipFamily == CHIP_FAMILY_RS200) || 2169 (info->ChipFamily == CHIP_FAMILY_RS300) || 2170 (info->ChipFamily == CHIP_FAMILY_RS400) || 2171 (info->ChipFamily == CHIP_FAMILY_RS480) || 2172 (info->ChipFamily == CHIP_FAMILY_RS600) || 2173 (info->ChipFamily == CHIP_FAMILY_RS690) || 2174 (info->ChipFamily == CHIP_FAMILY_RS740)) 2175 info->accel_state->has_tcl = FALSE; 2176 else { 2177 info->accel_state->has_tcl = TRUE; 2178 } 2179 2180 /* if we have shadow fb bail */ 2181 if (info->r600_shadow_fb) { 2182 info->useEXA = FALSE; 2183 return TRUE; 2184 } 2185 2186#ifdef XF86DRI 2187 if ((!info->directRenderingEnabled) || 2188 (maxy <= pScrn->virtualY * 3) || 2189 (pScrn->videoRam <= 32768)) 2190 info->useEXA = FALSE; 2191 else 2192 info->useEXA = TRUE; 2193#else 2194 info->useEXA = FALSE; 2195#endif 2196 2197 if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { 2198 int errmaj = 0, errmin = 0; 2199 2200 from = X_DEFAULT; 2201#if defined(USE_EXA) 2202#if defined(USE_XAA) 2203 optstr = (char *)xf86GetOptValString(info->Options, OPTION_ACCELMETHOD); 2204 if (optstr != NULL) { 2205 if (xf86NameCmp(optstr, "EXA") == 0) { 2206 from = X_CONFIG; 2207 info->useEXA = TRUE; 2208 } else if (xf86NameCmp(optstr, "XAA") == 0) { 2209 from = X_CONFIG; 2210 if (info->ChipFamily < CHIP_FAMILY_R600) 2211 info->useEXA = FALSE; 2212 } 2213 } 2214#else /* USE_XAA */ 2215 info->useEXA = TRUE; 2216#endif /* !USE_XAA */ 2217#endif /* USE_EXA */ 2218 if (info->ChipFamily < CHIP_FAMILY_R600) 2219 xf86DrvMsg(pScrn->scrnIndex, from, 2220 "Using %s acceleration architecture\n", 2221 info->useEXA ? "EXA" : "XAA"); 2222 else 2223 xf86DrvMsg(pScrn->scrnIndex, X_DEFAULT, 2224 "Will attempt to use R6xx/R7xx EXA support if DRI is enabled.\n"); 2225 2226#ifdef USE_EXA 2227 if (info->useEXA) { 2228 info->exaReq.majorversion = EXA_VERSION_MAJOR; 2229 info->exaReq.minorversion = EXA_VERSION_MINOR; 2230 2231 if (!LoadSubModule(pScrn->module, "exa", NULL, NULL, NULL, 2232 &info->exaReq, &errmaj, &errmin)) { 2233 LoaderErrorMsg(NULL, "exa", errmaj, errmin); 2234 return FALSE; 2235 } 2236 } 2237#endif /* USE_EXA */ 2238#ifdef USE_XAA 2239 if (!info->useEXA) { 2240 info->xaaReq.majorversion = 1; 2241 info->xaaReq.minorversion = 2; 2242 2243 if (!LoadSubModule(pScrn->module, "xaa", NULL, NULL, NULL, 2244 &info->xaaReq, &errmaj, &errmin)) { 2245 info->xaaReq.minorversion = 1; 2246 2247 if (!LoadSubModule(pScrn->module, "xaa", NULL, NULL, NULL, 2248 &info->xaaReq, &errmaj, &errmin)) { 2249 info->xaaReq.minorversion = 0; 2250 2251 if (!LoadSubModule(pScrn->module, "xaa", NULL, NULL, NULL, 2252 &info->xaaReq, &errmaj, &errmin)) { 2253 LoaderErrorMsg(NULL, "xaa", errmaj, errmin); 2254 return FALSE; 2255 } 2256 } 2257 } 2258 } 2259#endif /* USE_XAA */ 2260 } else { 2261 /* NoAccel */ 2262 info->useEXA = FALSE; 2263 } 2264 2265 return TRUE; 2266} 2267 2268static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10) 2269{ 2270#if (!defined(__powerpc__) && !defined(__sparc__)) || \ 2271 (defined(XSERVER_LIBPCIACCESS) && HAVE_PCI_DEVICE_ENABLE) 2272 RADEONInfoPtr info = RADEONPTR(pScrn); 2273#endif 2274#if !defined(__powerpc__) && !defined(__sparc__) 2275 unsigned char *RADEONMMIO = info->MMIO; 2276 uint32_t fp2_gen_ctl_save = 0; 2277#endif 2278 2279#ifdef XSERVER_LIBPCIACCESS 2280#if HAVE_PCI_DEVICE_ENABLE 2281 pci_device_enable(info->PciInfo); 2282#endif 2283#endif 2284 2285#if !defined(__powerpc__) && !defined(__sparc__) 2286 /* don't need int10 on atom cards. 2287 * in theory all radeons, but the older stuff 2288 * isn't 100% yet 2289 * secondary atom cards tend to hang when initializing int10, 2290 * however, on some stom cards, you can't read the bios without 2291 * intitializing int10. 2292 */ 2293 if (!xf86ReturnOptValBool(info->Options, OPTION_INT10, TRUE)) 2294 return TRUE; 2295 2296 if (xf86LoadSubModule(pScrn, "int10")) { 2297 /* The VGA BIOS on the RV100/QY cannot be read when the digital output 2298 * is enabled. Clear and restore FP2_ON around int10 to avoid this. 2299 */ 2300 if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) { 2301 fp2_gen_ctl_save = INREG(RADEON_FP2_GEN_CNTL); 2302 if (fp2_gen_ctl_save & RADEON_FP2_ON) { 2303 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "disabling digital out\n"); 2304 OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_ctl_save & ~RADEON_FP2_ON); 2305 } 2306 } 2307 2308 xf86DrvMsg(pScrn->scrnIndex,X_INFO,"initializing int10\n"); 2309 *ppInt10 = xf86InitInt10(info->pEnt->index); 2310 2311 if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) { 2312 if (fp2_gen_ctl_save & RADEON_FP2_ON) { 2313 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "re-enabling digital out\n"); 2314 OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_ctl_save); 2315 } 2316 } 2317 } 2318#endif 2319 return TRUE; 2320} 2321 2322#ifdef XF86DRI 2323static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) 2324{ 2325 RADEONInfoPtr info = RADEONPTR(pScrn); 2326 MessageType from; 2327 char *reason; 2328 2329 info->directRenderingEnabled = FALSE; 2330 info->directRenderingInited = FALSE; 2331 2332 if (!(info->dri = calloc(1, sizeof(struct radeon_dri)))) { 2333 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate dri rec!\n"); 2334 return FALSE; 2335 } 2336 2337 if (!(info->cp = calloc(1, sizeof(struct radeon_cp)))) { 2338 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate cp rec!\n"); 2339 return FALSE; 2340 } 2341 info->cp->CPInUse = FALSE; 2342 info->cp->CPStarted = FALSE; 2343 info->cp->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT; 2344 2345 if (xf86IsEntityShared(info->pEnt->index)) { 2346 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2347 "Direct Rendering Disabled -- " 2348 "Zaphod Dual-head configuration is not working with " 2349 "DRI at present.\n" 2350 "Please use the xrandr 1.2 if you " 2351 "want Dual-head with DRI.\n"); 2352 return FALSE; 2353 } 2354 if (info->IsSecondary) 2355 return FALSE; 2356 2357 if (info->ChipFamily >= CHIP_FAMILY_CEDAR) { 2358 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2359 "No DRI yet on Evergreen\n"); 2360 return FALSE; 2361 } 2362 2363 if (info->Chipset == PCI_CHIP_RN50_515E || 2364 info->Chipset == PCI_CHIP_RN50_5969) { 2365 if (xf86ReturnOptValBool(info->Options, OPTION_DRI, FALSE)) { 2366 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2367 "Direct rendering for RN50 forced on -- " 2368 "This is NOT officially supported at the hardware level " 2369 "and may cause instability or lockups\n"); 2370 } else { 2371 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2372 "Direct rendering not officially supported on RN50\n"); 2373 return FALSE; 2374 } 2375 } 2376 2377 if (!xf86ReturnOptValBool(info->Options, OPTION_DRI, TRUE)) { 2378 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2379 "Direct rendering forced off\n"); 2380 return FALSE; 2381 } 2382 2383 if (xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { 2384 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2385 "[dri] Acceleration disabled, not initializing the DRI\n"); 2386 return FALSE; 2387 } 2388 2389 info->dri->pLibDRMVersion = NULL; 2390 info->dri->pKernelDRMVersion = NULL; 2391 2392 if (!RADEONDRIGetVersion(pScrn)) 2393 return FALSE; 2394 2395 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2396 "[dri] Found DRI library version %d.%d.%d and kernel" 2397 " module version %d.%d.%d\n", 2398 info->dri->pLibDRMVersion->version_major, 2399 info->dri->pLibDRMVersion->version_minor, 2400 info->dri->pLibDRMVersion->version_patchlevel, 2401 info->dri->pKernelDRMVersion->version_major, 2402 info->dri->pKernelDRMVersion->version_minor, 2403 info->dri->pKernelDRMVersion->version_patchlevel); 2404 2405 if (info->Chipset == PCI_CHIP_RS400_5A41 || 2406 info->Chipset == PCI_CHIP_RS400_5A42 || 2407 info->Chipset == PCI_CHIP_RC410_5A61 || 2408 info->Chipset == PCI_CHIP_RC410_5A62 || 2409 info->Chipset == PCI_CHIP_RS480_5954 || 2410 info->Chipset == PCI_CHIP_RS480_5955 || 2411 info->Chipset == PCI_CHIP_RS482_5974 || 2412 info->Chipset == PCI_CHIP_RS485_5975) { 2413 2414 if (info->dri->pKernelDRMVersion->version_minor < 27) { 2415 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2416 "Direct rendering broken on XPRESS 200 and 200M with DRI less than 1.27\n"); 2417 return FALSE; 2418 } 2419 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2420 "Direct rendering experimental on RS400/Xpress 200 enabled\n"); 2421 } 2422 2423 if (info->ChipFamily >= CHIP_FAMILY_R300) 2424 info->dri->gartSize = R300_DEFAULT_GART_SIZE; 2425 else 2426 info->dri->gartSize = RADEON_DEFAULT_GART_SIZE; 2427 2428 info->dri->ringSize = RADEON_DEFAULT_RING_SIZE; 2429 info->dri->bufSize = RADEON_DEFAULT_BUFFER_SIZE; 2430 info->dri->gartTexSize = RADEON_DEFAULT_GART_TEX_SIZE; 2431 info->dri->pciAperSize = RADEON_DEFAULT_PCI_APER_SIZE; 2432 info->cp->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT; 2433 2434 if ((xf86GetOptValInteger(info->Options, 2435 OPTION_GART_SIZE, (int *)&(info->dri->gartSize))) || 2436 (xf86GetOptValInteger(info->Options, 2437 OPTION_GART_SIZE_OLD, (int *)&(info->dri->gartSize)))) { 2438 switch (info->dri->gartSize) { 2439 case 4: 2440 case 8: 2441 case 16: 2442 case 32: 2443 case 64: 2444 case 128: 2445 case 256: 2446 break; 2447 2448 default: 2449 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2450 "Illegal GART size: %d MB\n", info->dri->gartSize); 2451 return FALSE; 2452 } 2453 } 2454 2455 if (xf86GetOptValInteger(info->Options, 2456 OPTION_RING_SIZE, &(info->dri->ringSize))) { 2457 if (info->dri->ringSize < 1 || info->dri->ringSize >= (int)info->dri->gartSize) { 2458 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2459 "Illegal ring buffer size: %d MB\n", 2460 info->dri->ringSize); 2461 return FALSE; 2462 } 2463 } 2464 2465 if (xf86GetOptValInteger(info->Options, 2466 OPTION_PCIAPER_SIZE, &(info->dri->pciAperSize))) { 2467 switch(info->dri->pciAperSize) { 2468 case 32: 2469 case 64: 2470 case 128: 2471 case 256: 2472 break; 2473 default: 2474 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2475 "Illegal pci aper size: %d MB\n", 2476 info->dri->pciAperSize); 2477 return FALSE; 2478 } 2479 } 2480 2481 2482 if (xf86GetOptValInteger(info->Options, 2483 OPTION_BUFFER_SIZE, &(info->dri->bufSize))) { 2484 if (info->dri->bufSize < 1 || info->dri->bufSize >= (int)info->dri->gartSize) { 2485 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2486 "Illegal vertex/indirect buffers size: %d MB\n", 2487 info->dri->bufSize); 2488 return FALSE; 2489 } 2490 if (info->dri->bufSize > 2) { 2491 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2492 "Illegal vertex/indirect buffers size: %d MB\n", 2493 info->dri->bufSize); 2494 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2495 "Clamping vertex/indirect buffers size to 2 MB\n"); 2496 info->dri->bufSize = 2; 2497 } 2498 } 2499 2500 if (info->dri->ringSize + info->dri->bufSize + info->dri->gartTexSize > 2501 (int)info->dri->gartSize) { 2502 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2503 "Buffers are too big for requested GART space\n"); 2504 return FALSE; 2505 } 2506 2507 info->dri->gartTexSize = info->dri->gartSize - (info->dri->ringSize + info->dri->bufSize); 2508 2509 if (xf86GetOptValInteger(info->Options, OPTION_USEC_TIMEOUT, 2510 &(info->cp->CPusecTimeout))) { 2511 /* This option checked by the RADEON DRM kernel module */ 2512 } 2513 2514 /* Two options to try and squeeze as much texture memory as possible 2515 * for dedicated 3d rendering boxes 2516 */ 2517 info->dri->noBackBuffer = xf86ReturnOptValBool(info->Options, 2518 OPTION_NO_BACKBUFFER, 2519 FALSE); 2520 2521 info->dri->allowPageFlip = 0; 2522 2523#ifdef DAMAGE 2524 if (info->dri->noBackBuffer) { 2525 from = X_DEFAULT; 2526 reason = " because back buffer disabled"; 2527 } else { 2528 from = xf86GetOptValBool(info->Options, OPTION_PAGE_FLIP, 2529 &info->dri->allowPageFlip) ? X_CONFIG : X_DEFAULT; 2530 2531 if (IS_AVIVO_VARIANT) { 2532 info->dri->allowPageFlip = 0; 2533 reason = " on r5xx and newer chips.\n"; 2534 } else { 2535 reason = ""; 2536 } 2537 2538 } 2539#else 2540 from = X_DEFAULT; 2541 reason = " because Damage layer not available at build time"; 2542#endif 2543 2544 xf86DrvMsg(pScrn->scrnIndex, from, "Page Flipping %sabled%s\n", 2545 info->dri->allowPageFlip ? "en" : "dis", reason); 2546 2547 /* AGP seems to have problems with gart transfers */ 2548 if ((info->ChipFamily >= CHIP_FAMILY_R600) && (info->cardType == CARD_AGP)) 2549 info->DMAForXv = FALSE; 2550 else 2551 info->DMAForXv = TRUE; 2552 from = xf86GetOptValBool(info->Options, OPTION_XV_DMA, &info->DMAForXv) 2553 ? X_CONFIG : X_INFO; 2554 xf86DrvMsg(pScrn->scrnIndex, from, 2555 "Will %stry to use DMA for Xv image transfers\n", 2556 info->DMAForXv ? "" : "not "); 2557 2558 return TRUE; 2559} 2560#endif /* XF86DRI */ 2561 2562static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) 2563{ 2564 RADEONInfoPtr info = RADEONPTR(pScrn); 2565 2566 info->allowColorTiling = xf86ReturnOptValBool(info->Options, 2567 OPTION_COLOR_TILING, TRUE); 2568 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { 2569 /* this may be 4096 on r4xx -- need to double check */ 2570 info->MaxSurfaceWidth = 3968; /* one would have thought 4096...*/ 2571 info->MaxLines = 4096; 2572 } else { 2573 info->MaxSurfaceWidth = 2048; 2574 info->MaxLines = 2048; 2575 } 2576 2577 if (!info->allowColorTiling) 2578 return; 2579 2580 if (info->ChipFamily >= CHIP_FAMILY_R600) 2581 info->allowColorTiling = FALSE; 2582 2583 /* for zaphod disable tiling for now */ 2584 if (info->IsPrimary || info->IsSecondary) 2585 info->allowColorTiling = FALSE; 2586 2587#ifdef XF86DRI 2588 if (info->directRenderingEnabled && 2589 info->dri->pKernelDRMVersion->version_minor < 14) { 2590 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2591 "[dri] color tiling disabled because of version " 2592 "mismatch.\n" 2593 "[dri] radeon.o kernel module version is %d.%d.%d but " 2594 "1.14.0 or later is required for color tiling.\n", 2595 info->dri->pKernelDRMVersion->version_major, 2596 info->dri->pKernelDRMVersion->version_minor, 2597 info->dri->pKernelDRMVersion->version_patchlevel); 2598 info->allowColorTiling = FALSE; 2599 return; 2600 } 2601#endif /* XF86DRI */ 2602 2603 if (info->allowColorTiling) { 2604 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Color tiling enabled by default\n"); 2605 } else { 2606 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Color tiling disabled\n"); 2607 } 2608} 2609 2610 2611static Bool RADEONPreInitXv(ScrnInfoPtr pScrn) 2612{ 2613 RADEONInfoPtr info = RADEONPTR(pScrn); 2614 uint16_t mm_table; 2615 uint16_t bios_header; 2616 uint16_t pll_info_block; 2617#ifdef XvExtension 2618 char* microc_path = NULL; 2619 char* microc_type = NULL; 2620 MessageType from; 2621 2622 if (xf86GetOptValInteger(info->Options, OPTION_VIDEO_KEY, 2623 &(info->videoKey))) { 2624 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "video key set to 0x%x\n", 2625 info->videoKey); 2626 } else { 2627 info->videoKey = 0x1E; 2628 } 2629 2630 if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_CRYSTAL, &(info->RageTheatreCrystal))) { 2631 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre Crystal frequency was specified as %d.%d Mhz\n", 2632 info->RageTheatreCrystal/100, info->RageTheatreCrystal % 100); 2633 } else { 2634 info->RageTheatreCrystal=-1; 2635 } 2636 2637 if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_TUNER_PORT, &(info->RageTheatreTunerPort))) { 2638 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre tuner port was specified as %d\n", 2639 info->RageTheatreTunerPort); 2640 } else { 2641 info->RageTheatreTunerPort=-1; 2642 } 2643 2644 if(info->RageTheatreTunerPort>5){ 2645 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to assign Rage Theatre tuner port to invalid value. Disabling setting\n"); 2646 info->RageTheatreTunerPort=-1; 2647 } 2648 2649 if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_COMPOSITE_PORT, &(info->RageTheatreCompositePort))) { 2650 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre composite port was specified as %d\n", 2651 info->RageTheatreCompositePort); 2652 } else { 2653 info->RageTheatreCompositePort=-1; 2654 } 2655 2656 if(info->RageTheatreCompositePort>6){ 2657 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to assign Rage Theatre composite port to invalid value. Disabling setting\n"); 2658 info->RageTheatreCompositePort=-1; 2659 } 2660 2661 if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_SVIDEO_PORT, &(info->RageTheatreSVideoPort))) { 2662 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre SVideo Port was specified as %d\n", 2663 info->RageTheatreSVideoPort); 2664 } else { 2665 info->RageTheatreSVideoPort=-1; 2666 } 2667 2668 if(info->RageTheatreSVideoPort>6){ 2669 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to assign Rage Theatre SVideo port to invalid value. Disabling setting\n"); 2670 info->RageTheatreSVideoPort=-1; 2671 } 2672 2673 if(xf86GetOptValInteger(info->Options, OPTION_TUNER_TYPE, &(info->tunerType))) { 2674 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Tuner type was specified as %d\n", 2675 info->tunerType); 2676 } else { 2677 info->tunerType=-1; 2678 } 2679 2680 if(info->tunerType>31){ 2681 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to set tuner type to invalid value. Disabling setting\n"); 2682 info->tunerType=-1; 2683 } 2684 2685 if((microc_path = xf86GetOptValString(info->Options, OPTION_RAGE_THEATRE_MICROC_PATH)) != NULL) 2686 { 2687 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre Microcode path was specified as %s\n", microc_path); 2688 info->RageTheatreMicrocPath = microc_path; 2689 } else { 2690 info->RageTheatreMicrocPath= NULL; 2691 } 2692 2693 if((microc_type = xf86GetOptValString(info->Options, OPTION_RAGE_THEATRE_MICROC_TYPE)) != NULL) 2694 { 2695 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre Microcode type was specified as %s\n", microc_type); 2696 info->RageTheatreMicrocType = microc_type; 2697 } else { 2698 info->RageTheatreMicrocType= NULL; 2699 } 2700 2701 if(xf86GetOptValInteger(info->Options, OPTION_SCALER_WIDTH, &(info->overlay_scaler_buffer_width))) { 2702 if ((info->overlay_scaler_buffer_width < 1024) || 2703 (info->overlay_scaler_buffer_width > 2048) || 2704 ((info->overlay_scaler_buffer_width % 64) != 0)) { 2705 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to set illegal scaler width. Using default\n"); 2706 from = X_DEFAULT; 2707 info->overlay_scaler_buffer_width = 0; 2708 } else 2709 from = X_CONFIG; 2710 } else { 2711 from = X_DEFAULT; 2712 info->overlay_scaler_buffer_width = 0; 2713 } 2714 if (!info->overlay_scaler_buffer_width) { 2715 /* overlay scaler line length differs for different revisions 2716 this needs to be maintained by hand */ 2717 switch(info->ChipFamily){ 2718 case CHIP_FAMILY_R200: 2719 case CHIP_FAMILY_R300: 2720 case CHIP_FAMILY_R350: 2721 case CHIP_FAMILY_RV350: 2722 case CHIP_FAMILY_RV380: 2723 case CHIP_FAMILY_R420: 2724 case CHIP_FAMILY_RV410: 2725 info->overlay_scaler_buffer_width = 1920; 2726 break; 2727 default: 2728 info->overlay_scaler_buffer_width = 1536; 2729 } 2730 } 2731 xf86DrvMsg(pScrn->scrnIndex, from, "Assuming overlay scaler buffer width is %d\n", 2732 info->overlay_scaler_buffer_width); 2733#endif 2734 2735 /* Rescue MM_TABLE before VBIOS is freed */ 2736 info->MM_TABLE_valid = FALSE; 2737 2738 if((info->VBIOS==NULL)||(info->VBIOS[0]!=0x55)||(info->VBIOS[1]!=0xaa)){ 2739 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Cannot access BIOS or it is not valid.\n" 2740 "\t\tIf your card is TV-in capable you will need to specify options RageTheatreCrystal, RageTheatreTunerPort, \n" 2741 "\t\tRageTheatreSVideoPort and TunerType in /etc/X11/xorg.conf.\n" 2742 ); 2743 info->MM_TABLE_valid = FALSE; 2744 return TRUE; 2745 } 2746 2747 bios_header=info->VBIOS[0x48]; 2748 bios_header+=(((int)info->VBIOS[0x49]+0)<<8); 2749 2750 mm_table=info->VBIOS[bios_header+0x38]; 2751 if(mm_table==0) 2752 { 2753 xf86DrvMsg(pScrn->scrnIndex,X_INFO,"No MM_TABLE found - assuming CARD is not TV-in capable.\n"); 2754 info->MM_TABLE_valid = FALSE; 2755 return TRUE; 2756 } 2757 mm_table+=(((int)info->VBIOS[bios_header+0x39]+0)<<8)-2; 2758 2759 if(mm_table>0) 2760 { 2761 memcpy(&(info->MM_TABLE), &(info->VBIOS[mm_table]), sizeof(info->MM_TABLE)); 2762 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "MM_TABLE: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 2763 info->MM_TABLE.table_revision, 2764 info->MM_TABLE.table_size, 2765 info->MM_TABLE.tuner_type, 2766 info->MM_TABLE.audio_chip, 2767 info->MM_TABLE.product_id, 2768 info->MM_TABLE.tuner_voltage_teletext_fm, 2769 info->MM_TABLE.i2s_config, 2770 info->MM_TABLE.video_decoder_type, 2771 info->MM_TABLE.video_decoder_host_config, 2772 info->MM_TABLE.input[0], 2773 info->MM_TABLE.input[1], 2774 info->MM_TABLE.input[2], 2775 info->MM_TABLE.input[3], 2776 info->MM_TABLE.input[4]); 2777 2778 /* Is it an MM_TABLE we know about ? */ 2779 if(info->MM_TABLE.table_size != 0xc){ 2780 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "This card has MM_TABLE we do not recognize.\n" 2781 "\t\tIf your card is TV-in capable you will need to specify options RageTheatreCrystal, RageTheatreTunerPort, \n" 2782 "\t\tRageTheatreSVideoPort and TunerType in /etc/X11/xorg.conf.\n" 2783 ); 2784 info->MM_TABLE_valid = FALSE; 2785 return TRUE; 2786 } 2787 info->MM_TABLE_valid = TRUE; 2788 } else { 2789 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "No MM_TABLE found - assuming card is not TV-in capable (mm_table=%d).\n", mm_table); 2790 info->MM_TABLE_valid = FALSE; 2791 } 2792 2793 pll_info_block=info->VBIOS[bios_header+0x30]; 2794 pll_info_block+=(((int)info->VBIOS[bios_header+0x31]+0)<<8); 2795 2796 info->video_decoder_type=info->VBIOS[pll_info_block+0x08]; 2797 info->video_decoder_type+=(((int)info->VBIOS[pll_info_block+0x09]+0)<<8); 2798 2799 return TRUE; 2800} 2801 2802static Bool 2803RADEONPreInitBIOS(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) 2804{ 2805 RADEONInfoPtr info = RADEONPTR(pScrn); 2806 2807 if (!RADEONGetBIOSInfo(pScrn, pInt10)) { 2808 /* Avivo chips require bios for atom */ 2809 if (IS_AVIVO_VARIANT) 2810 return FALSE; 2811 } 2812 return TRUE; 2813} 2814 2815Bool 2816RADEONZaphodStringMatches(ScrnInfoPtr pScrn, const char *s, char *output_name) 2817{ 2818 int i = 0; 2819 char s1[20]; 2820 2821 do { 2822 switch(*s) { 2823 case ',': 2824 s1[i] = '\0'; 2825 i = 0; 2826 if (strcmp(s1, output_name) == 0) 2827 return TRUE; 2828 break; 2829 case ' ': 2830 case '\t': 2831 case '\n': 2832 case '\r': 2833 break; 2834 default: 2835 s1[i] = *s; 2836 i++; 2837 break; 2838 } 2839 } while(*s++); 2840 2841 s1[i] = '\0'; 2842 if (strcmp(s1, output_name) == 0) 2843 return TRUE; 2844 2845 return FALSE; 2846} 2847 2848static void RADEONFixZaphodOutputs(ScrnInfoPtr pScrn) 2849{ 2850 RADEONInfoPtr info = RADEONPTR(pScrn); 2851 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 2852 int o; 2853 char *s; 2854 2855 if ((s = xf86GetOptValString(info->Options, OPTION_ZAPHOD_HEADS))) { 2856 for (o = config->num_output; o > 0; o--) { 2857 if (!RADEONZaphodStringMatches(pScrn, s, config->output[o - 1]->name)) 2858 xf86OutputDestroy(config->output[o - 1]); 2859 } 2860 } else { 2861 if (info->IsPrimary) { 2862 xf86OutputDestroy(config->output[0]); 2863 while (config->num_output > 1) { 2864 xf86OutputDestroy(config->output[1]); 2865 } 2866 } else { 2867 while (config->num_output > 1) { 2868 xf86OutputDestroy(config->output[1]); 2869 } 2870 } 2871 } 2872} 2873 2874static Bool RADEONPreInitControllers(ScrnInfoPtr pScrn) 2875{ 2876 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 2877 RADEONInfoPtr info = RADEONPTR(pScrn); 2878 int i; 2879 int mask; 2880 int found = 0; 2881 2882 if (info->IsPrimary) 2883 mask = 1; 2884 else if (info->IsSecondary) 2885 mask = 2; 2886 else 2887 mask = 3; 2888 2889 if (!RADEONAllocateControllers(pScrn, mask)) 2890 return FALSE; 2891 2892 RADEONGetClockInfo(pScrn); 2893 2894 if (info->IsAtomBios && info->IsIGP) 2895 RADEONATOMGetIGPInfo(pScrn); 2896 2897 if (!RADEONSetupConnectors(pScrn)) { 2898 return FALSE; 2899 } 2900 2901 if (info->IsPrimary || info->IsSecondary) { 2902 /* fixup outputs for zaphod */ 2903 RADEONFixZaphodOutputs(pScrn); 2904 } 2905 2906 RADEONPrintPortMap(pScrn); 2907 2908 info->first_load_no_devices = FALSE; 2909 for (i = 0; i < config->num_output; i++) { 2910 xf86OutputPtr output = config->output[i]; 2911 2912 output->status = (*output->funcs->detect) (output); 2913 ErrorF("finished output detect: %d\n", i); 2914 if (info->IsPrimary || info->IsSecondary) { 2915 if (output->status != XF86OutputStatusConnected) 2916 return FALSE; 2917 } 2918 if (output->status != XF86OutputStatusDisconnected) 2919 found++; 2920 } 2921 2922 if (!found) { 2923 /* nothing connected, light up some defaults so the server comes up */ 2924 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No connected devices found!\n"); 2925 info->first_load_no_devices = TRUE; 2926 } 2927 2928 ErrorF("finished all detect\n"); 2929 return TRUE; 2930} 2931 2932static void 2933RADEONProbeDDC(ScrnInfoPtr pScrn, int indx) 2934{ 2935 vbeInfoPtr pVbe; 2936 2937 if (xf86LoadSubModule(pScrn, "vbe")) { 2938 pVbe = VBEInit(NULL,indx); 2939 ConfiguredMonitor = vbeDoEDID(pVbe, NULL); 2940 } 2941} 2942 2943static Bool 2944RADEONCRTCResize(ScrnInfoPtr scrn, int width, int height) 2945{ 2946 scrn->virtualX = width; 2947 scrn->virtualY = height; 2948 /* RADEONSetPitch(scrn); */ 2949 return TRUE; 2950} 2951 2952static const xf86CrtcConfigFuncsRec RADEONCRTCResizeFuncs = { 2953 RADEONCRTCResize 2954}; 2955 2956Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) 2957{ 2958 xf86CrtcConfigPtr xf86_config; 2959 RADEONInfoPtr info; 2960 xf86Int10InfoPtr pInt10 = NULL; 2961 void *int10_save = NULL; 2962 const char *s; 2963 RADEONEntPtr pRADEONEnt; 2964 DevUnion* pPriv; 2965 2966 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2967 "RADEONPreInit\n"); 2968 if (pScrn->numEntities != 1) return FALSE; 2969 2970 if (!RADEONGetRec(pScrn)) return FALSE; 2971 2972 info = RADEONPTR(pScrn); 2973 info->MMIO = NULL; 2974 2975 info->IsSecondary = FALSE; 2976 info->IsPrimary = FALSE; 2977 info->kms_enabled = FALSE; 2978 2979 info->pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]); 2980 if (info->pEnt->location.type != BUS_PCI) goto fail; 2981 2982 pPriv = xf86GetEntityPrivate(pScrn->entityList[0], 2983 getRADEONEntityIndex()); 2984 pRADEONEnt = pPriv->ptr; 2985 2986 if(xf86IsEntityShared(pScrn->entityList[0])) 2987 { 2988 if(xf86IsPrimInitDone(pScrn->entityList[0])) 2989 { 2990 info->IsSecondary = TRUE; 2991 pRADEONEnt->pSecondaryScrn = pScrn; 2992 info->SavedReg = &pRADEONEnt->SavedReg; 2993 info->ModeReg = &pRADEONEnt->ModeReg; 2994 } 2995 else 2996 { 2997 info->IsPrimary = TRUE; 2998 xf86SetPrimInitDone(pScrn->entityList[0]); 2999 pRADEONEnt->pPrimaryScrn = pScrn; 3000 pRADEONEnt->HasSecondary = FALSE; 3001 info->SavedReg = &pRADEONEnt->SavedReg; 3002 info->ModeReg = &pRADEONEnt->ModeReg; 3003 } 3004 } else { 3005 info->SavedReg = &pRADEONEnt->SavedReg; 3006 info->ModeReg = &pRADEONEnt->ModeReg; 3007 } 3008 3009 info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index); 3010 info->PciTag = pciTag(PCI_DEV_BUS(info->PciInfo), 3011 PCI_DEV_DEV(info->PciInfo), 3012 PCI_DEV_FUNC(info->PciInfo)); 3013 info->MMIOAddr = PCI_REGION_BASE(info->PciInfo, 2, REGION_MEM) & ~0xffULL; 3014 info->MMIOSize = PCI_REGION_SIZE(info->PciInfo, 2); 3015 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TOTO SAYS %016llx\n", 3016 (unsigned long long)PCI_REGION_BASE(info->PciInfo, 3017 2, REGION_MEM)); 3018 if (info->pEnt->device->IOBase) { 3019 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, 3020 "MMIO address override, using 0x%08lx instead of 0x%016llx\n", 3021 info->pEnt->device->IOBase, 3022 info->MMIOAddr); 3023 info->MMIOAddr = info->pEnt->device->IOBase; 3024 } else if (!info->MMIOAddr) { 3025 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid MMIO address\n"); 3026 goto fail1; 3027 } 3028 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3029 "MMIO registers at 0x%016llx: size %ldKB\n", info->MMIOAddr, info->MMIOSize / 1024); 3030 3031 if(!RADEONMapMMIO(pScrn)) { 3032 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3033 "Memory map the MMIO region failed\n"); 3034 goto fail1; 3035 } 3036 3037#if !defined(__alpha__) 3038 if ( 3039#ifndef XSERVER_LIBPCIACCESS 3040 xf86GetPciDomain(info->PciTag) || 3041#endif 3042 !xf86IsPrimaryPci(info->PciInfo)) 3043 RADEONPreInt10Save(pScrn, &int10_save); 3044#else 3045 /* [Alpha] On the primary, the console already ran the BIOS and we're 3046 * going to run it again - so make sure to "fix up" the card 3047 * so that (1) we can read the BIOS ROM and (2) the BIOS will 3048 * get the memory config right. 3049 */ 3050 RADEONPreInt10Save(pScrn, &int10_save); 3051#endif 3052 3053 if (flags & PROBE_DETECT) { 3054 RADEONProbeDDC(pScrn, info->pEnt->index); 3055 RADEONPostInt10Check(pScrn, int10_save); 3056 if(info->MMIO) RADEONUnmapMMIO(pScrn); 3057 return TRUE; 3058 } 3059 3060 3061 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3062 "PCI bus %d card %d func %d\n", 3063 PCI_DEV_BUS(info->PciInfo), 3064 PCI_DEV_DEV(info->PciInfo), 3065 PCI_DEV_FUNC(info->PciInfo)); 3066 3067#ifndef XSERVER_LIBPCIACCESS 3068 if (xf86RegisterResources(info->pEnt->index, 0, ResExclusive)) 3069 goto fail; 3070 3071 xf86SetOperatingState(resVga, info->pEnt->index, ResUnusedOpr); 3072 3073 pScrn->racMemFlags = RAC_FB | RAC_COLORMAP | RAC_VIEWPORT | RAC_CURSOR; 3074#endif 3075 pScrn->monitor = pScrn->confScreen->monitor; 3076 3077 /* Allocate an xf86CrtcConfig */ 3078 xf86CrtcConfigInit (pScrn, &RADEONCRTCResizeFuncs); 3079 xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 3080 3081 3082 if (!RADEONPreInitVisual(pScrn)) 3083 goto fail; 3084 3085 /* We can't do this until we have a 3086 pScrn->display. */ 3087 xf86CollectOptions(pScrn, NULL); 3088 if (!(info->Options = malloc(sizeof(RADEONOptions)))) 3089 goto fail; 3090 3091 memcpy(info->Options, RADEONOptions, sizeof(RADEONOptions)); 3092 xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options); 3093 3094 /* By default, don't do VGA IOs on ppc/sparc */ 3095#if defined(__powerpc__) || defined(__sparc__) || !defined(WITH_VGAHW) 3096 info->VGAAccess = FALSE; 3097#else 3098 info->VGAAccess = TRUE; 3099#endif 3100 3101#ifdef WITH_VGAHW 3102 xf86GetOptValBool(info->Options, OPTION_VGA_ACCESS, &info->VGAAccess); 3103 if (info->VGAAccess) { 3104 if (!xf86LoadSubModule(pScrn, "vgahw")) 3105 info->VGAAccess = FALSE; 3106 else { 3107 if (!vgaHWGetHWRec(pScrn)) 3108 info->VGAAccess = FALSE; 3109 } 3110 if (!info->VGAAccess) 3111 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Loading VGA module failed," 3112 " trying to run without it\n"); 3113 } else 3114 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VGAAccess option set to FALSE," 3115 " VGA module load skipped\n"); 3116 if (info->VGAAccess) 3117 vgaHWGetIOBase(VGAHWPTR(pScrn)); 3118#endif 3119 3120 3121 if (!RADEONPreInitWeight(pScrn)) 3122 goto fail; 3123 3124 info->DispPriority = 1; 3125 if ((s = xf86GetOptValString(info->Options, OPTION_DISP_PRIORITY))) { 3126 if (strcmp(s, "AUTO") == 0) { 3127 info->DispPriority = 1; 3128 } else if (strcmp(s, "BIOS") == 0) { 3129 info->DispPriority = 0; 3130 } else if (strcmp(s, "HIGH") == 0) { 3131 info->DispPriority = 2; 3132 } else 3133 info->DispPriority = 1; 3134 } 3135 3136 if (!RADEONPreInitChipType(pScrn)) 3137 goto fail; 3138 3139 if (!RADEONPreInitInt10(pScrn, &pInt10)) 3140 goto fail; 3141 3142 RADEONPostInt10Check(pScrn, int10_save); 3143 3144 if (!RADEONPreInitBIOS(pScrn, pInt10)) 3145 goto fail; 3146 3147 /* Save BIOS scratch registers */ 3148 RADEONSaveBIOSRegisters(pScrn, info->SavedReg); 3149 3150#ifdef XF86DRI 3151 /* PreInit DRI first of all since we need that for getting a proper 3152 * memory map 3153 */ 3154 info->directRenderingEnabled = RADEONPreInitDRI(pScrn); 3155#endif 3156 if (!info->directRenderingEnabled) { 3157 if (info->ChipFamily >= CHIP_FAMILY_R600) { 3158 info->r600_shadow_fb = TRUE; 3159 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3160 "using shadow framebuffer\n"); 3161 if (!xf86LoadSubModule(pScrn, "shadow")) 3162 info->r600_shadow_fb = FALSE; 3163 } 3164 } 3165 3166 if (!RADEONPreInitVRAM(pScrn)) 3167 goto fail; 3168 3169 RADEONPreInitColorTiling(pScrn); 3170 3171 if (IS_AVIVO_VARIANT) 3172 xf86CrtcSetSizeRange (pScrn, 320, 200, 8192, 8192); 3173 else 3174 xf86CrtcSetSizeRange (pScrn, 320, 200, 4096, 4096); 3175 3176 RADEONPreInitDDC(pScrn); 3177 3178 if (!RADEONPreInitControllers(pScrn)) 3179 goto fail; 3180 3181 if (!xf86InitialConfiguration (pScrn, FALSE)) 3182 { 3183 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid modes.\n"); 3184 goto fail; 3185 } 3186 3187 /* fix up cloning on rn50 cards 3188 * since they only have one crtc sometimes the xserver doesn't assign 3189 * a crtc to one of the outputs even though both outputs have common modes 3190 * which results in only one monitor being enabled. Assign a crtc here so 3191 * that both outputs light up. 3192 */ 3193 if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) { 3194 int i; 3195 3196 for (i = 0; i < xf86_config->num_output; i++) { 3197 xf86OutputPtr output = xf86_config->output[i]; 3198 3199 /* XXX: double check crtc mode */ 3200 if ((output->probed_modes != NULL) && (output->crtc == NULL)) 3201 output->crtc = xf86_config->crtc[0]; 3202 } 3203 } 3204 3205 RADEONSetPitch(pScrn); 3206 3207 /* Set display resolution */ 3208 xf86SetDpi(pScrn, 0, 0); 3209 3210 /* Get ScreenInit function */ 3211 if (!xf86LoadSubModule(pScrn, "fb")) return FALSE; 3212 3213 if (!RADEONPreInitGamma(pScrn)) goto fail; 3214 3215 if (!RADEONPreInitCursor(pScrn)) goto fail; 3216 3217 if (!RADEONPreInitAccel(pScrn)) goto fail; 3218 3219 if (!IS_AVIVO_VARIANT) { 3220 if (!RADEONPreInitXv(pScrn)) goto fail; 3221 } 3222 3223 if (!xf86RandR12PreInit (pScrn)) 3224 { 3225 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "RandR initialization failure\n"); 3226 goto fail; 3227 } 3228 3229 if (pScrn->modes == NULL) { 3230 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No modes.\n"); 3231 goto fail; 3232 } 3233 3234 3235 /* Free int10 info */ 3236 if (pInt10) 3237 xf86FreeInt10(pInt10); 3238 3239 if(info->MMIO) RADEONUnmapMMIO(pScrn); 3240 info->MMIO = NULL; 3241 3242 xf86DrvMsg(pScrn->scrnIndex, X_NOTICE, 3243 "MergedFB support has been removed and replaced with" 3244 " xrandr 1.2 support\n"); 3245 3246 return TRUE; 3247 3248fail: 3249 /* Pre-init failed. */ 3250 /* Free the video bios (if applicable) */ 3251 if (info->VBIOS) { 3252 free(info->VBIOS); 3253 info->VBIOS = NULL; 3254 } 3255 3256 /* Free int10 info */ 3257 if (pInt10) 3258 xf86FreeInt10(pInt10); 3259 3260#ifdef WITH_VGAHW 3261 if (info->VGAAccess) 3262 vgaHWFreeHWRec(pScrn); 3263#endif 3264 3265 if(info->MMIO) RADEONUnmapMMIO(pScrn); 3266 info->MMIO = NULL; 3267 3268 fail1: 3269 RADEONFreeRec(pScrn); 3270 3271 return FALSE; 3272} 3273 3274/* Load a palette */ 3275static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors, 3276 int *indices, LOCO *colors, VisualPtr pVisual) 3277{ 3278 RADEONInfoPtr info = RADEONPTR(pScrn); 3279 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 3280 int i; 3281 int index, j; 3282 uint16_t lut_r[256], lut_g[256], lut_b[256]; 3283 int c; 3284 3285#ifdef XF86DRI 3286 if (info->cp->CPStarted && pScrn->pScreen) DRILock(pScrn->pScreen, 0); 3287#endif 3288 3289 if (info->accelOn && pScrn->pScreen) 3290 RADEON_SYNC(info, pScrn); 3291 3292 { 3293 3294 for (c = 0; c < xf86_config->num_crtc; c++) { 3295 xf86CrtcPtr crtc = xf86_config->crtc[c]; 3296 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 3297 3298 for (i = 0 ; i < 256; i++) { 3299 lut_r[i] = radeon_crtc->lut_r[i] << 6; 3300 lut_g[i] = radeon_crtc->lut_g[i] << 6; 3301 lut_b[i] = radeon_crtc->lut_b[i] << 6; 3302 } 3303 3304 switch (info->CurrentLayout.depth) { 3305 case 15: 3306 for (i = 0; i < numColors; i++) { 3307 index = indices[i]; 3308 for (j = 0; j < 8; j++) { 3309 lut_r[index * 8 + j] = colors[index].red << 6; 3310 lut_g[index * 8 + j] = colors[index].green << 6; 3311 lut_b[index * 8 + j] = colors[index].blue << 6; 3312 } 3313 } 3314 case 16: 3315 for (i = 0; i < numColors; i++) { 3316 index = indices[i]; 3317 3318 if (i <= 31) { 3319 for (j = 0; j < 8; j++) { 3320 lut_r[index * 8 + j] = colors[index].red << 6; 3321 lut_b[index * 8 + j] = colors[index].blue << 6; 3322 } 3323 } 3324 3325 for (j = 0; j < 4; j++) { 3326 lut_g[index * 4 + j] = colors[index].green << 6; 3327 } 3328 } 3329 default: 3330 for (i = 0; i < numColors; i++) { 3331 index = indices[i]; 3332 lut_r[index] = colors[index].red << 6; 3333 lut_g[index] = colors[index].green << 6; 3334 lut_b[index] = colors[index].blue << 6; 3335 } 3336 break; 3337 } 3338 3339 /* Make the change through RandR */ 3340#ifdef RANDR_12_INTERFACE 3341 if (crtc->randr_crtc) 3342 RRCrtcGammaSet(crtc->randr_crtc, lut_r, lut_g, lut_b); 3343 else 3344#endif 3345 crtc->funcs->gamma_set(crtc, lut_r, lut_g, lut_b, 256); 3346 } 3347 } 3348 3349#ifdef XF86DRI 3350 if (info->cp->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen); 3351#endif 3352} 3353 3354static void RADEONBlockHandler(int i, pointer blockData, 3355 pointer pTimeout, pointer pReadmask) 3356{ 3357 ScreenPtr pScreen = screenInfo.screens[i]; 3358 ScrnInfoPtr pScrn = xf86Screens[i]; 3359 RADEONInfoPtr info = RADEONPTR(pScrn); 3360 3361 pScreen->BlockHandler = info->BlockHandler; 3362 (*pScreen->BlockHandler) (i, blockData, pTimeout, pReadmask); 3363 pScreen->BlockHandler = RADEONBlockHandler; 3364 3365 if (info->VideoTimerCallback) 3366 (*info->VideoTimerCallback)(pScrn, currentTime.milliseconds); 3367 3368#if defined(RENDER) && defined(USE_XAA) 3369 if(info->accel_state->RenderCallback) 3370 (*info->accel_state->RenderCallback)(pScrn); 3371#endif 3372 3373#ifdef USE_EXA 3374 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; 3375#endif 3376 3377 if (info->pm.dynamic_mode_enabled) 3378 RADEONPMBlockHandler(pScrn); 3379} 3380 3381static void 3382RADEONInitBIOSRegisters(ScrnInfoPtr pScrn) 3383{ 3384 RADEONInfoPtr info = RADEONPTR(pScrn); 3385 unsigned char *RADEONMMIO = info->MMIO; 3386 RADEONSavePtr save = info->ModeReg; 3387 3388 save->bios_0_scratch = info->SavedReg->bios_0_scratch; 3389 save->bios_1_scratch = info->SavedReg->bios_1_scratch; 3390 save->bios_2_scratch = info->SavedReg->bios_2_scratch; 3391 save->bios_3_scratch = info->SavedReg->bios_3_scratch; 3392 save->bios_4_scratch = info->SavedReg->bios_4_scratch; 3393 save->bios_5_scratch = info->SavedReg->bios_5_scratch; 3394 save->bios_6_scratch = info->SavedReg->bios_6_scratch; 3395 save->bios_7_scratch = info->SavedReg->bios_7_scratch; 3396 3397 if (info->IsAtomBios) { 3398 /* let the bios control the backlight */ 3399 save->bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; 3400 /* tell the bios not to handle mode switching */ 3401 save->bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | 3402 ATOM_S6_ACC_MODE); 3403 3404 if (info->ChipFamily >= CHIP_FAMILY_R600) { 3405 OUTREG(R600_BIOS_2_SCRATCH, save->bios_2_scratch); 3406 OUTREG(R600_BIOS_6_SCRATCH, save->bios_6_scratch); 3407 } else { 3408 OUTREG(RADEON_BIOS_2_SCRATCH, save->bios_2_scratch); 3409 OUTREG(RADEON_BIOS_6_SCRATCH, save->bios_6_scratch); 3410 } 3411 } else { 3412 /* let the bios control the backlight */ 3413 save->bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; 3414 /* tell the bios not to handle mode switching */ 3415 save->bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS | 3416 RADEON_ACC_MODE_CHANGE); 3417 /* tell the bios a driver is loaded */ 3418 save->bios_7_scratch |= RADEON_DRV_LOADED; 3419 3420 OUTREG(RADEON_BIOS_0_SCRATCH, save->bios_0_scratch); 3421 OUTREG(RADEON_BIOS_6_SCRATCH, save->bios_6_scratch); 3422 //OUTREG(RADEON_BIOS_7_SCRATCH, save->bios_7_scratch); 3423 } 3424 3425} 3426 3427 3428/* Called at the start of each server generation. */ 3429Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, 3430 int argc, char **argv) 3431{ 3432 ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; 3433 RADEONInfoPtr info = RADEONPTR(pScrn); 3434 int hasDRI = 0; 3435#ifdef RENDER 3436 int subPixelOrder = SubPixelUnknown; 3437 char* s; 3438#endif 3439 3440 3441 info->accelOn = FALSE; 3442#ifdef USE_XAA 3443 info->accel_state->accel = NULL; 3444#endif 3445#ifdef XF86DRI 3446 pScrn->fbOffset = info->dri->frontOffset; 3447#endif 3448 3449 if (info->IsSecondary) 3450 pScrn->fbOffset = pScrn->videoRam * 1024; 3451#ifdef XF86DRI 3452 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3453 "RADEONScreenInit %lx %ld %d\n", 3454 pScrn->memPhysBase, pScrn->fbOffset, info->dri->frontOffset); 3455#else 3456 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3457 "RADEONScreenInit %lx %ld\n", 3458 pScrn->memPhysBase, pScrn->fbOffset); 3459#endif 3460 if (!RADEONMapMem(pScrn)) return FALSE; 3461 3462#ifdef XF86DRI 3463 info->dri->fbX = 0; 3464 info->dri->fbY = 0; 3465#endif 3466 3467 info->PaletteSavedOnVT = FALSE; 3468 3469 info->crtc_on = FALSE; 3470 info->crtc2_on = FALSE; 3471 3472 /* save the real front buffer size 3473 * it changes with randr, rotation, etc. 3474 */ 3475 info->virtualX = pScrn->virtualX; 3476 info->virtualY = pScrn->virtualY; 3477 3478 RADEONSave(pScrn); 3479 3480 /* set initial bios scratch reg state */ 3481 RADEONInitBIOSRegisters(pScrn); 3482 3483 /* blank the outputs/crtcs */ 3484 RADEONBlank(pScrn); 3485 3486 RADEONPMInit(pScrn); 3487 3488 if (info->allowColorTiling && (pScrn->virtualX > info->MaxSurfaceWidth)) { 3489 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3490 "Color tiling not supported with virtual x resolutions larger than %d, disabling\n", 3491 info->MaxSurfaceWidth); 3492 info->allowColorTiling = FALSE; 3493 } 3494 if (info->allowColorTiling) { 3495 info->tilingEnabled = (pScrn->currentMode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; 3496 } 3497 3498 /* Visual setup */ 3499 miClearVisualTypes(); 3500 if (!miSetVisualTypes(pScrn->depth, 3501 miGetDefaultVisualMask(pScrn->depth), 3502 pScrn->rgbBits, 3503 pScrn->defaultVisual)) return FALSE; 3504 miSetPixmapDepths (); 3505 3506#ifdef XF86DRI 3507 if (info->directRenderingEnabled) { 3508 MessageType from; 3509 3510 info->dri->depthBits = pScrn->depth; 3511 3512 from = xf86GetOptValInteger(info->Options, OPTION_DEPTH_BITS, 3513 &info->dri->depthBits) 3514 ? X_CONFIG : X_DEFAULT; 3515 3516 if (info->dri->depthBits != 16 && info->dri->depthBits != 24) { 3517 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3518 "Value for Option \"DepthBits\" must be 16 or 24\n"); 3519 info->dri->depthBits = pScrn->depth; 3520 from = X_DEFAULT; 3521 } 3522 3523 xf86DrvMsg(pScrn->scrnIndex, from, 3524 "Using %d bit depth buffer\n", info->dri->depthBits); 3525 } 3526 3527 3528 hasDRI = info->directRenderingEnabled; 3529#endif /* XF86DRI */ 3530 3531 /* Initialize the memory map, this basically calculates the values 3532 * we'll use later on for MC_FB_LOCATION & MC_AGP_LOCATION 3533 */ 3534 RADEONInitMemoryMap(pScrn); 3535 3536 /* empty the surfaces */ 3537 if (info->ChipFamily < CHIP_FAMILY_R600) { 3538 unsigned char *RADEONMMIO = info->MMIO; 3539 unsigned int j; 3540 for (j = 0; j < 8; j++) { 3541 OUTREG(RADEON_SURFACE0_INFO + 16 * j, 0); 3542 OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * j, 0); 3543 OUTREG(RADEON_SURFACE0_UPPER_BOUND + 16 * j, 0); 3544 } 3545 } 3546 3547#ifdef XF86DRI 3548 /* Depth moves are disabled by default since they are extremely slow */ 3549 info->dri->depthMoves = xf86ReturnOptValBool(info->Options, 3550 OPTION_DEPTH_MOVE, FALSE); 3551 if (info->dri->depthMoves && info->allowColorTiling) { 3552 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Enabling depth moves\n"); 3553 } else if (info->dri->depthMoves) { 3554 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3555 "Depth moves don't work without color tiling, disabled\n"); 3556 info->dri->depthMoves = FALSE; 3557 } else { 3558 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3559 "Depth moves disabled by default\n"); 3560 } 3561#endif 3562 3563 /* Initial setup of surfaces */ 3564 if (info->ChipFamily < CHIP_FAMILY_R600) { 3565 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3566 "Setting up initial surfaces\n"); 3567 RADEONChangeSurfaces(pScrn); 3568 } 3569 3570 /* Memory manager setup */ 3571 3572 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3573 "Setting up accel memmap\n"); 3574 3575#ifdef USE_EXA 3576 if (info->useEXA) { 3577#ifdef XF86DRI 3578 if (hasDRI) { 3579 info->accelDFS = xf86ReturnOptValBool(info->Options, OPTION_ACCEL_DFS, 3580 info->cardType != CARD_AGP); 3581 3582 /* Reserve approx. half of offscreen memory for local textures by 3583 * default, can be overridden with Option "FBTexPercent". 3584 * Round down to a whole number of texture regions. 3585 */ 3586 info->dri->textureSize = 50; 3587 3588 if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT, 3589 &(info->dri->textureSize))) { 3590 if (info->dri->textureSize < 0 || info->dri->textureSize > 100) { 3591 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3592 "Illegal texture memory percentage: %dx, setting to default 50%%\n", 3593 info->dri->textureSize); 3594 info->dri->textureSize = 50; 3595 } 3596 } 3597 } 3598#endif /* XF86DRI */ 3599 3600 if (!RADEONSetupMemEXA(pScreen)) 3601 return FALSE; 3602 } 3603#endif 3604 3605#if defined(XF86DRI) && defined(USE_XAA) 3606 if (!info->useEXA && hasDRI) { 3607 info->dri->textureSize = -1; 3608 if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT, 3609 &(info->dri->textureSize))) { 3610 if (info->dri->textureSize < 0 || info->dri->textureSize > 100) { 3611 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3612 "Illegal texture memory percentage: %dx, using default behaviour\n", 3613 info->dri->textureSize); 3614 info->dri->textureSize = -1; 3615 } 3616 } 3617 if (!RADEONSetupMemXAA_DRI(scrnIndex, pScreen)) 3618 return FALSE; 3619 pScrn->fbOffset = info->dri->frontOffset; 3620 } 3621#endif 3622 3623#ifdef USE_XAA 3624 if (!info->useEXA && !hasDRI && !RADEONSetupMemXAA(scrnIndex, pScreen)) 3625 return FALSE; 3626#endif 3627 3628 info->accel_state->dst_pitch_offset = 3629 (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64) 3630 << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10)); 3631 3632 /* Setup DRI after visuals have been established, but before fbScreenInit is 3633 * called. fbScreenInit will eventually call the driver's InitGLXVisuals 3634 * call back. */ 3635#ifdef XF86DRI 3636 if (info->directRenderingEnabled) { 3637 /* FIXME: When we move to dynamic allocation of back and depth 3638 * buffers, we will want to revisit the following check for 3 3639 * times the virtual size of the screen below. 3640 */ 3641 int width_bytes = (pScrn->displayWidth * 3642 info->CurrentLayout.pixel_bytes); 3643 int maxy = info->FbMapSize / width_bytes; 3644 3645 if (maxy <= pScrn->virtualY * 3) { 3646 xf86DrvMsg(scrnIndex, X_ERROR, 3647 "Static buffer allocation failed. Disabling DRI.\n"); 3648 xf86DrvMsg(scrnIndex, X_ERROR, 3649 "At least %d kB of video memory needed at this " 3650 "resolution and depth.\n", 3651 (pScrn->displayWidth * pScrn->virtualY * 3652 info->CurrentLayout.pixel_bytes * 3 + 1023) / 1024); 3653 info->directRenderingEnabled = FALSE; 3654 } else { 3655 info->directRenderingEnabled = RADEONDRIScreenInit(pScreen); 3656 } 3657 } 3658 3659 /* Tell DRI about new memory map */ 3660 if (info->directRenderingEnabled && info->dri->newMemoryMap) { 3661 if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_NEW_MEMMAP, 1) < 0) { 3662 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 3663 "[drm] failed to enable new memory map\n"); 3664 RADEONDRICloseScreen(pScreen); 3665 info->directRenderingEnabled = FALSE; 3666 } 3667 } 3668#endif 3669 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3670 "Initializing fb layer\n"); 3671 3672 if (info->r600_shadow_fb) { 3673 info->fb_shadow = calloc(1, 3674 pScrn->displayWidth * pScrn->virtualY * 3675 ((pScrn->bitsPerPixel + 7) >> 3)); 3676 if (info->fb_shadow == NULL) { 3677 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3678 "Failed to allocate shadow framebuffer\n"); 3679 info->r600_shadow_fb = FALSE; 3680 } else { 3681 if (!fbScreenInit(pScreen, info->fb_shadow, 3682 pScrn->virtualX, pScrn->virtualY, 3683 pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, 3684 pScrn->bitsPerPixel)) 3685 return FALSE; 3686 } 3687 } 3688 3689 if (info->r600_shadow_fb == FALSE) { 3690 /* Init fb layer */ 3691 if (!fbScreenInit(pScreen, info->FB + pScrn->fbOffset, 3692 pScrn->virtualX, pScrn->virtualY, 3693 pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, 3694 pScrn->bitsPerPixel)) 3695 return FALSE; 3696 } 3697 3698 xf86SetBlackWhitePixels(pScreen); 3699 3700 if (pScrn->bitsPerPixel > 8) { 3701 VisualPtr visual; 3702 3703 visual = pScreen->visuals + pScreen->numVisuals; 3704 while (--visual >= pScreen->visuals) { 3705 if ((visual->class | DynamicClass) == DirectColor) { 3706 visual->offsetRed = pScrn->offset.red; 3707 visual->offsetGreen = pScrn->offset.green; 3708 visual->offsetBlue = pScrn->offset.blue; 3709 visual->redMask = pScrn->mask.red; 3710 visual->greenMask = pScrn->mask.green; 3711 visual->blueMask = pScrn->mask.blue; 3712 } 3713 } 3714 } 3715 3716 /* Must be after RGB order fixed */ 3717 fbPictureInit (pScreen, 0, 0); 3718 3719#ifdef RENDER 3720 if ((s = xf86GetOptValString(info->Options, OPTION_SUBPIXEL_ORDER))) { 3721 if (strcmp(s, "RGB") == 0) subPixelOrder = SubPixelHorizontalRGB; 3722 else if (strcmp(s, "BGR") == 0) subPixelOrder = SubPixelHorizontalBGR; 3723 else if (strcmp(s, "NONE") == 0) subPixelOrder = SubPixelNone; 3724 PictureSetSubpixelOrder (pScreen, subPixelOrder); 3725 } 3726#endif 3727 3728 pScrn->vtSema = TRUE; 3729 3730 /* restore the memory map here otherwise we may get a hang when 3731 * initializing the drm below 3732 */ 3733 RADEONInitMemMapRegisters(pScrn, info->ModeReg, info); 3734 RADEONRestoreMemMapRegisters(pScrn, info->ModeReg); 3735 3736 /* Backing store setup */ 3737 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3738 "Initializing backing store\n"); 3739 miInitializeBackingStore(pScreen); 3740 xf86SetBackingStore(pScreen); 3741 3742 /* DRI finalisation */ 3743#ifdef XF86DRI 3744 if (info->directRenderingEnabled && 3745 (info->cardType==CARD_PCIE || info->cardType==CARD_PCI) && 3746 info->dri->pKernelDRMVersion->version_minor >= 19) 3747 { 3748 if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_LOCATION, info->dri->pciGartOffset) < 0) 3749 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3750 "[drm] failed set pci gart location\n"); 3751 3752 if (info->dri->pKernelDRMVersion->version_minor >= 26) { 3753 if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_TABLE_SIZE, info->dri->pciGartSize) < 0) 3754 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3755 "[drm] failed set pci gart table size\n"); 3756 } 3757 } 3758 if (info->directRenderingEnabled) { 3759 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3760 "DRI Finishing init !\n"); 3761 info->directRenderingEnabled = RADEONDRIFinishScreenInit(pScreen); 3762 } 3763 if (info->directRenderingEnabled) { 3764 /* DRI final init might have changed the memory map, we need to adjust 3765 * our local image to make sure we restore them properly on mode 3766 * changes or VT switches 3767 */ 3768 RADEONAdjustMemMapRegisters(pScrn, info->ModeReg); 3769 3770 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n"); 3771 3772 /* we might already be in tiled mode, tell drm about it */ 3773 if (info->directRenderingEnabled && info->tilingEnabled) { 3774 if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0) 3775 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3776 "[drm] failed changing tiling status\n"); 3777 } 3778 } else { 3779 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 3780 "Direct rendering disabled\n"); 3781 } 3782#endif 3783 3784 /* Make sure surfaces are allright since DRI setup may have changed them */ 3785 if (info->ChipFamily < CHIP_FAMILY_R600) { 3786 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3787 "Setting up final surfaces\n"); 3788 3789 RADEONChangeSurfaces(pScrn); 3790 } 3791 3792 3793 /* Enable aceleration */ 3794 if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { 3795 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3796 "Initializing Acceleration\n"); 3797 if (RADEONAccelInit(pScreen)) { 3798 xf86DrvMsg(scrnIndex, X_INFO, "Acceleration enabled\n"); 3799 info->accelOn = TRUE; 3800 } else { 3801 xf86DrvMsg(scrnIndex, X_ERROR, 3802 "Acceleration initialization failed\n"); 3803 xf86DrvMsg(scrnIndex, X_INFO, "Acceleration disabled\n"); 3804 info->accelOn = FALSE; 3805 } 3806 } else { 3807 xf86DrvMsg(scrnIndex, X_INFO, "Acceleration disabled\n"); 3808 info->accelOn = FALSE; 3809 } 3810 3811 /* Init DPMS */ 3812 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3813 "Initializing DPMS\n"); 3814 xf86DPMSInit(pScreen, xf86DPMSSet, 0); 3815 3816 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3817 "Initializing Cursor\n"); 3818 3819 /* Set Silken Mouse */ 3820 xf86SetSilkenMouse(pScreen); 3821 3822 /* Cursor setup */ 3823 miDCInitialize(pScreen, xf86GetPointerScreenFuncs()); 3824 3825 /* Hardware cursor setup */ 3826 if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { 3827 if (RADEONCursorInit(pScreen)) { 3828#ifdef USE_XAA 3829 if (!info->useEXA) { 3830 int width, height; 3831 3832 if (xf86QueryLargestOffscreenArea(pScreen, &width, &height, 3833 0, 0, 0)) { 3834 xf86DrvMsg(scrnIndex, X_INFO, 3835 "Largest offscreen area available: %d x %d\n", 3836 width, height); 3837 } 3838 } 3839#endif /* USE_XAA */ 3840 } else { 3841 xf86DrvMsg(scrnIndex, X_ERROR, 3842 "Hardware cursor initialization failed\n"); 3843 xf86DrvMsg(scrnIndex, X_INFO, "Using software cursor\n"); 3844 } 3845 } else { 3846 xf86DrvMsg(scrnIndex, X_INFO, "Using software cursor\n"); 3847 } 3848 3849 /* DGA setup */ 3850#ifdef XFreeXDGA 3851 xf86DiDGAInit(pScreen, info->LinearAddr + pScrn->fbOffset); 3852#endif 3853 3854 /* Init Xv */ 3855 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3856 "Initializing Xv\n"); 3857 RADEONInitVideo(pScreen); 3858 3859 if (info->r600_shadow_fb == TRUE) { 3860 if (!shadowSetup(pScreen)) { 3861 return FALSE; 3862 } 3863 } 3864 3865 /* Clear the framebuffer */ 3866 memset(info->FB + pScrn->fbOffset, 0, 3867 pScrn->virtualY * pScrn->displayWidth * info->CurrentLayout.pixel_bytes); 3868 3869 pScrn->pScreen = pScreen; 3870 3871 /* set the modes with desired rotation, etc. */ 3872 if (!xf86SetDesiredModes (pScrn)) 3873 return FALSE; 3874 3875 /* Provide SaveScreen & wrap BlockHandler and CloseScreen */ 3876 /* Wrap CloseScreen */ 3877 info->CloseScreen = pScreen->CloseScreen; 3878 pScreen->CloseScreen = RADEONCloseScreen; 3879 pScreen->SaveScreen = RADEONSaveScreen; 3880 info->BlockHandler = pScreen->BlockHandler; 3881 pScreen->BlockHandler = RADEONBlockHandler; 3882 info->CreateScreenResources = pScreen->CreateScreenResources; 3883 pScreen->CreateScreenResources = RADEONCreateScreenResources; 3884 3885 if (!xf86CrtcScreenInit (pScreen)) 3886 return FALSE; 3887 3888 /* Colormap setup */ 3889 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3890 "Initializing color map\n"); 3891 if (!miCreateDefColormap(pScreen)) return FALSE; 3892 /* all radeons support 10 bit CLUTs */ 3893 if (!xf86HandleColormaps(pScreen, 256, 10, 3894 RADEONLoadPalette, NULL, 3895 CMAP_PALETTED_TRUECOLOR 3896#if 0 /* This option messes up text mode! (eich@suse.de) */ 3897 | CMAP_LOAD_EVEN_IF_OFFSCREEN 3898#endif 3899 | CMAP_RELOAD_ON_MODE_SWITCH)) return FALSE; 3900 3901 /* Note unused options */ 3902 if (serverGeneration == 1) 3903 xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options); 3904 3905 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3906 "RADEONScreenInit finished\n"); 3907 3908 return TRUE; 3909} 3910 3911/* Write memory mapping registers */ 3912void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, 3913 RADEONSavePtr restore) 3914{ 3915 RADEONInfoPtr info = RADEONPTR(pScrn); 3916 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 3917 unsigned char *RADEONMMIO = info->MMIO; 3918 int timeout; 3919 uint32_t mc_fb_loc, mc_agp_loc, mc_agp_loc_hi; 3920 3921 radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &mc_fb_loc, 3922 &mc_agp_loc, &mc_agp_loc_hi); 3923 3924 if (info->IsSecondary) 3925 return; 3926 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3927 "RADEONRestoreMemMapRegisters() : \n"); 3928 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3929 " MC_FB_LOCATION : 0x%08x 0x%08x\n", 3930 (unsigned)restore->mc_fb_location, (unsigned int)mc_fb_loc); 3931 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3932 " MC_AGP_LOCATION : 0x%08x\n", 3933 (unsigned)restore->mc_agp_location); 3934 3935 if (IS_DCE4_VARIANT) { 3936 if (mc_fb_loc != restore->mc_fb_location || 3937 mc_agp_loc != restore->mc_agp_location) { 3938 uint32_t tmp; 3939 3940 //XXX 3941 //RADEONWaitForIdleMMIO(pScrn); 3942 3943 /* disable VGA rendering core */ 3944 OUTREG(AVIVO_VGA_RENDER_CONTROL, INREG(AVIVO_VGA_RENDER_CONTROL) & ~AVIVO_VGA_VSTATUS_CNTL_MASK); 3945 OUTREG(AVIVO_D1VGA_CONTROL, INREG(AVIVO_D1VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 3946 OUTREG(AVIVO_D2VGA_CONTROL, INREG(AVIVO_D2VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 3947 OUTREG(EVERGREEN_D3VGA_CONTROL, INREG(EVERGREEN_D3VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 3948 OUTREG(EVERGREEN_D4VGA_CONTROL, INREG(EVERGREEN_D4VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 3949 OUTREG(EVERGREEN_D5VGA_CONTROL, INREG(EVERGREEN_D5VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 3950 OUTREG(EVERGREEN_D6VGA_CONTROL, INREG(EVERGREEN_D6VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 3951 3952 /* Stop display & memory access */ 3953 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); 3954 OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN); 3955 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); 3956 3957 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 3958 OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN); 3959 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 3960 3961 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); 3962 OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN); 3963 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); 3964 3965 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 3966 OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN); 3967 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 3968 3969 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); 3970 OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN); 3971 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); 3972 3973 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 3974 OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN); 3975 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 3976 3977 usleep(10000); 3978 timeout = 0; 3979 while (!(radeon_get_mc_idle(pScrn))) { 3980 if (++timeout > 1000000) { 3981 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3982 "Timeout trying to update memory controller settings !\n"); 3983 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3984 "You will probably crash now ... \n"); 3985 /* Nothing we can do except maybe try to kill the server, 3986 * let's wait 2 seconds to leave the above message a chance 3987 * to maybe hit the disk and continue trying to setup despite 3988 * the MC being non-idle 3989 */ 3990 usleep(2000000); 3991 } 3992 usleep(10); 3993 } 3994 3995 radeon_write_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, 3996 restore->mc_fb_location, 3997 restore->mc_agp_location, 3998 restore->mc_agp_location_hi); 3999 4000 OUTREG(R600_HDP_NONSURFACE_BASE, (restore->mc_fb_location << 16) & 0xff0000); 4001 4002 } 4003 } else if (IS_AVIVO_VARIANT) { 4004 if (mc_fb_loc != restore->mc_fb_location || 4005 mc_agp_loc != restore->mc_agp_location) { 4006 uint32_t tmp; 4007 4008 RADEONWaitForIdleMMIO(pScrn); 4009 4010 /* disable VGA rendering core */ 4011 OUTREG(AVIVO_VGA_RENDER_CONTROL, INREG(AVIVO_VGA_RENDER_CONTROL) &~ AVIVO_VGA_VSTATUS_CNTL_MASK); 4012 4013 OUTREG(AVIVO_D1VGA_CONTROL, INREG(AVIVO_D1VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 4014 OUTREG(AVIVO_D2VGA_CONTROL, INREG(AVIVO_D2VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 4015 4016 /* Stop display & memory access */ 4017 tmp = INREG(AVIVO_D1CRTC_CONTROL); 4018 OUTREG(AVIVO_D1CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN); 4019 4020 tmp = INREG(AVIVO_D2CRTC_CONTROL); 4021 OUTREG(AVIVO_D2CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN); 4022 4023 tmp = INREG(AVIVO_D2CRTC_CONTROL); 4024 4025 usleep(10000); 4026 timeout = 0; 4027 while (!(radeon_get_mc_idle(pScrn))) { 4028 if (++timeout > 1000000) { 4029 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4030 "Timeout trying to update memory controller settings !\n"); 4031 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4032 "You will probably crash now ... \n"); 4033 /* Nothing we can do except maybe try to kill the server, 4034 * let's wait 2 seconds to leave the above message a chance 4035 * to maybe hit the disk and continue trying to setup despite 4036 * the MC being non-idle 4037 */ 4038 usleep(2000000); 4039 } 4040 usleep(10); 4041 } 4042 4043 radeon_write_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, 4044 restore->mc_fb_location, 4045 restore->mc_agp_location, 4046 restore->mc_agp_location_hi); 4047 4048 if (info->ChipFamily < CHIP_FAMILY_R600) { 4049 OUTREG(AVIVO_HDP_FB_LOCATION, restore->mc_fb_location); 4050 } else { 4051 OUTREG(R600_HDP_NONSURFACE_BASE, (restore->mc_fb_location << 16) & 0xff0000); 4052 } 4053 4054 /* Reset the engine and HDP */ 4055 if (info->ChipFamily < CHIP_FAMILY_R600) 4056 RADEONEngineReset(pScrn); 4057 } 4058 } else { 4059 4060 /* Write memory mapping registers only if their value change 4061 * since we must ensure no access is done while they are 4062 * reprogrammed 4063 */ 4064 if (mc_fb_loc != restore->mc_fb_location || 4065 mc_agp_loc != restore->mc_agp_location) { 4066 uint32_t crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl; 4067 uint32_t old_mc_status; 4068 4069 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 4070 " Map Changed ! Applying ...\n"); 4071 4072 /* Make sure engine is idle. We assume the CCE is stopped 4073 * at this point 4074 */ 4075 RADEONWaitForIdleMMIO(pScrn); 4076 4077 if (info->IsIGP) 4078 goto igp_no_mcfb; 4079 4080 /* Capture MC_STATUS in case things go wrong ... */ 4081 old_mc_status = INREG(RADEON_MC_STATUS); 4082 4083 /* Stop display & memory access */ 4084 ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL); 4085 OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE); 4086 crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL); 4087 OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS); 4088 crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); 4089 RADEONWaitForVerticalSync(pScrn); 4090 OUTREG(RADEON_CRTC_GEN_CNTL, 4091 (crtc_gen_cntl 4092 & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) 4093 | RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN); 4094 4095 if (pRADEONEnt->HasCRTC2) { 4096 crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); 4097 RADEONWaitForVerticalSync2(pScrn); 4098 OUTREG(RADEON_CRTC2_GEN_CNTL, 4099 (crtc2_gen_cntl 4100 & ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) 4101 | RADEON_CRTC2_DISP_REQ_EN_B); 4102 } 4103 4104 /* Make sure the chip settles down (paranoid !) */ 4105 usleep(100000); 4106 timeout = 0; 4107 while (!(radeon_get_mc_idle(pScrn))) { 4108 if (++timeout > 1000000) { 4109 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4110 "Timeout trying to update memory controller settings !\n"); 4111 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4112 "MC_STATUS = 0x%08x (on entry = 0x%08x)\n", 4113 (unsigned int)INREG(RADEON_MC_STATUS), (unsigned int)old_mc_status); 4114 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4115 "You will probably crash now ... \n"); 4116 /* Nothing we can do except maybe try to kill the server, 4117 * let's wait 2 seconds to leave the above message a chance 4118 * to maybe hit the disk and continue trying to setup despite 4119 * the MC being non-idle 4120 */ 4121 usleep(2000000); 4122 } 4123 usleep(10); 4124 } 4125 4126 /* Update maps, first clearing out AGP to make sure we don't get 4127 * a temporary overlap 4128 */ 4129 OUTREG(RADEON_MC_AGP_LOCATION, 0xfffffffc); 4130 OUTREG(RADEON_MC_FB_LOCATION, restore->mc_fb_location); 4131 radeon_write_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, restore->mc_fb_location, 4132 0xfffffffc, 0); 4133 igp_no_mcfb: 4134 radeon_write_mc_fb_agp_location(pScrn, LOC_AGP, 0, 4135 restore->mc_agp_location, 0); 4136 /* Make sure map fully reached the chip */ 4137 (void)INREG(RADEON_MC_FB_LOCATION); 4138 4139 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 4140 " Map applied, resetting engine ...\n"); 4141 4142 /* Reset the engine and HDP */ 4143 RADEONEngineReset(pScrn); 4144 4145 /* Make sure we have sane offsets before re-enabling the CRTCs, disable 4146 * stereo, clear offsets, and wait for offsets to catch up with hw 4147 */ 4148 4149 OUTREG(RADEON_CRTC_OFFSET_CNTL, RADEON_CRTC_OFFSET_FLIP_CNTL); 4150 OUTREG(RADEON_CRTC_OFFSET, 0); 4151 OUTREG(RADEON_CUR_OFFSET, 0); 4152 timeout = 0; 4153 while(INREG(RADEON_CRTC_OFFSET) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) { 4154 if (timeout++ > 1000000) { 4155 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4156 "Timeout waiting for CRTC offset to update !\n"); 4157 break; 4158 } 4159 usleep(1000); 4160 } 4161 if (pRADEONEnt->HasCRTC2) { 4162 OUTREG(RADEON_CRTC2_OFFSET_CNTL, RADEON_CRTC2_OFFSET_FLIP_CNTL); 4163 OUTREG(RADEON_CRTC2_OFFSET, 0); 4164 OUTREG(RADEON_CUR2_OFFSET, 0); 4165 timeout = 0; 4166 while(INREG(RADEON_CRTC2_OFFSET) & RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET) { 4167 if (timeout++ > 1000000) { 4168 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4169 "Timeout waiting for CRTC2 offset to update !\n"); 4170 break; 4171 } 4172 usleep(1000); 4173 } 4174 } 4175 } 4176 4177 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 4178 "Updating display base addresses...\n"); 4179 4180 OUTREG(RADEON_DISPLAY_BASE_ADDR, restore->display_base_addr); 4181 if (pRADEONEnt->HasCRTC2) 4182 OUTREG(RADEON_DISPLAY2_BASE_ADDR, restore->display2_base_addr); 4183 OUTREG(RADEON_OV0_BASE_ADDR, restore->ov0_base_addr); 4184 (void)INREG(RADEON_OV0_BASE_ADDR); 4185 4186 /* More paranoia delays, wait 100ms */ 4187 usleep(100000); 4188 4189 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 4190 "Memory map updated.\n"); 4191 } 4192} 4193 4194#ifdef XF86DRI 4195static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) 4196{ 4197 RADEONInfoPtr info = RADEONPTR(pScrn); 4198 uint32_t fb, agp, agp_hi; 4199 int changed = 0; 4200 4201 if (info->IsSecondary) 4202 return; 4203 4204 radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &fb, &agp, &agp_hi); 4205 4206 if (fb != save->mc_fb_location || agp != save->mc_agp_location || 4207 agp_hi != save->mc_agp_location_hi) 4208 changed = 1; 4209 4210 if (changed) { 4211 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 4212 "DRI init changed memory map, adjusting ...\n"); 4213 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 4214 " MC_FB_LOCATION was: 0x%08lx is: 0x%08lx\n", 4215 (long unsigned int)info->mc_fb_location, (long unsigned int)fb); 4216 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 4217 " MC_AGP_LOCATION was: 0x%08lx is: 0x%08lx\n", 4218 (long unsigned int)info->mc_agp_location, (long unsigned int)agp); 4219 info->mc_fb_location = fb; 4220 info->mc_agp_location = agp; 4221 if (info->ChipFamily >= CHIP_FAMILY_R600) 4222 info->fbLocation = (info->mc_fb_location & 0xffff) << 24; 4223 else 4224 info->fbLocation = (info->mc_fb_location & 0xffff) << 16; 4225 4226 info->accel_state->dst_pitch_offset = 4227 (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64) 4228 << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10)); 4229 RADEONInitMemMapRegisters(pScrn, save, info); 4230 RADEONRestoreMemMapRegisters(pScrn, save); 4231 } 4232 4233#ifdef USE_EXA 4234 if (info->accelDFS || (info->ChipFamily >= CHIP_FAMILY_R600)) 4235 { 4236 drm_radeon_getparam_t gp; 4237 int gart_base; 4238 4239 memset(&gp, 0, sizeof(gp)); 4240 gp.param = RADEON_PARAM_GART_BASE; 4241 gp.value = &gart_base; 4242 4243 if (drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_GETPARAM, &gp, 4244 sizeof(gp)) < 0) { 4245 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4246 "Failed to determine GART area MC location, not using " 4247 "accelerated DownloadFromScreen hook!\n"); 4248 info->accelDFS = FALSE; 4249 } else { 4250 info->gartLocation = gart_base; 4251 } 4252 } 4253#endif /* USE_EXA */ 4254} 4255#endif 4256 4257/* restore original surface info (for fb console). */ 4258static void RADEONRestoreSurfaces(ScrnInfoPtr pScrn, RADEONSavePtr restore) 4259{ 4260 RADEONInfoPtr info = RADEONPTR(pScrn); 4261 unsigned char *RADEONMMIO = info->MMIO; 4262 unsigned int surfnr; 4263 4264 for ( surfnr = 0; surfnr < 8; surfnr++ ) { 4265 OUTREG(RADEON_SURFACE0_INFO + 16 * surfnr, restore->surfaces[surfnr][0]); 4266 OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * surfnr, restore->surfaces[surfnr][1]); 4267 OUTREG(RADEON_SURFACE0_UPPER_BOUND + 16 * surfnr, restore->surfaces[surfnr][2]); 4268 } 4269} 4270 4271/* save original surface info (for fb console). */ 4272static void RADEONSaveSurfaces(ScrnInfoPtr pScrn, RADEONSavePtr save) 4273{ 4274 RADEONInfoPtr info = RADEONPTR(pScrn); 4275 unsigned char *RADEONMMIO = info->MMIO; 4276 unsigned int surfnr; 4277 4278 for ( surfnr = 0; surfnr < 8; surfnr++ ) { 4279 save->surfaces[surfnr][0] = INREG(RADEON_SURFACE0_INFO + 16 * surfnr); 4280 save->surfaces[surfnr][1] = INREG(RADEON_SURFACE0_LOWER_BOUND + 16 * surfnr); 4281 save->surfaces[surfnr][2] = INREG(RADEON_SURFACE0_UPPER_BOUND + 16 * surfnr); 4282 } 4283} 4284 4285void RADEONChangeSurfaces(ScrnInfoPtr pScrn) 4286{ 4287 /* the idea here is to only set up front buffer as tiled, and back/depth buffer when needed. 4288 Everything else is left as untiled. This means we need to use eplicit src/dst pitch control 4289 when blitting, based on the src/target address, and can no longer use a default offset. 4290 But OTOH we don't need to dynamically change surfaces (for xv for instance), and some 4291 ugly offset / fb reservation (cursor) is gone. And as a bonus, everything actually works... 4292 For simplicity, just always update everything (just let the ioctl fail - could do better). 4293 All surface addresses are relative to RADEON_MC_FB_LOCATION */ 4294 4295 RADEONInfoPtr info = RADEONPTR(pScrn); 4296 int cpp = info->CurrentLayout.pixel_bytes; 4297 /* depth/front/back pitch must be identical (and the same as displayWidth) */ 4298 int width_bytes = pScrn->displayWidth * cpp; 4299 int bufferSize = RADEON_ALIGN((RADEON_ALIGN(pScrn->virtualY, 16)) * width_bytes, 4300 RADEON_GPU_PAGE_SIZE); 4301 unsigned int color_pattern, swap_pattern; 4302 4303 if (!info->allowColorTiling) 4304 return; 4305 4306 swap_pattern = 0; 4307#if X_BYTE_ORDER == X_BIG_ENDIAN 4308 switch (pScrn->bitsPerPixel) { 4309 case 16: 4310 swap_pattern = RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; 4311 break; 4312 4313 case 32: 4314 swap_pattern = RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; 4315 break; 4316 } 4317#endif 4318 if (info->ChipFamily < CHIP_FAMILY_R200) { 4319 color_pattern = RADEON_SURF_TILE_COLOR_MACRO; 4320 } else if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { 4321 color_pattern = R300_SURF_TILE_COLOR_MACRO; 4322 } else { 4323 color_pattern = R200_SURF_TILE_COLOR_MACRO; 4324 } 4325#ifdef XF86DRI 4326 if (info->directRenderingInited) { 4327 drm_radeon_surface_free_t drmsurffree; 4328 drm_radeon_surface_alloc_t drmsurfalloc; 4329 int retvalue; 4330 int depthCpp = (info->dri->depthBits - 8) / 4; 4331 int depth_width_bytes = pScrn->displayWidth * depthCpp; 4332 int depthBufferSize = RADEON_ALIGN((RADEON_ALIGN(pScrn->virtualY, 16)) * depth_width_bytes, 4333 RADEON_GPU_PAGE_SIZE); 4334 unsigned int depth_pattern; 4335 4336 drmsurffree.address = info->dri->frontOffset; 4337 retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_FREE, 4338 &drmsurffree, sizeof(drmsurffree)); 4339 4340 if (!((info->ChipFamily == CHIP_FAMILY_RV100) || 4341 (info->ChipFamily == CHIP_FAMILY_RS100) || 4342 (info->ChipFamily == CHIP_FAMILY_RS200))) { 4343 drmsurffree.address = info->dri->depthOffset; 4344 retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_FREE, 4345 &drmsurffree, sizeof(drmsurffree)); 4346 } 4347 4348 if (!info->dri->noBackBuffer) { 4349 drmsurffree.address = info->dri->backOffset; 4350 retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_FREE, 4351 &drmsurffree, sizeof(drmsurffree)); 4352 } 4353 4354 drmsurfalloc.size = bufferSize; 4355 drmsurfalloc.address = info->dri->frontOffset; 4356 drmsurfalloc.flags = swap_pattern; 4357 4358 if (info->tilingEnabled) { 4359 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) 4360 drmsurfalloc.flags |= (width_bytes / 8) | color_pattern; 4361 else 4362 drmsurfalloc.flags |= (width_bytes / 16) | color_pattern; 4363 } 4364 retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_ALLOC, 4365 &drmsurfalloc, sizeof(drmsurfalloc)); 4366 if (retvalue < 0) 4367 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4368 "drm: could not allocate surface for front buffer!\n"); 4369 4370 if ((info->dri->have3DWindows) && (!info->dri->noBackBuffer)) { 4371 drmsurfalloc.address = info->dri->backOffset; 4372 retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_ALLOC, 4373 &drmsurfalloc, sizeof(drmsurfalloc)); 4374 if (retvalue < 0) 4375 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4376 "drm: could not allocate surface for back buffer!\n"); 4377 } 4378 4379 if (info->ChipFamily < CHIP_FAMILY_R200) { 4380 if (depthCpp == 2) 4381 depth_pattern = RADEON_SURF_TILE_DEPTH_16BPP; 4382 else 4383 depth_pattern = RADEON_SURF_TILE_DEPTH_32BPP; 4384 } else if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { 4385 if (depthCpp == 2) 4386 depth_pattern = R300_SURF_TILE_COLOR_MACRO; 4387 else 4388 depth_pattern = R300_SURF_TILE_COLOR_MACRO | R300_SURF_TILE_DEPTH_32BPP; 4389 } else { 4390 if (depthCpp == 2) 4391 depth_pattern = R200_SURF_TILE_DEPTH_16BPP; 4392 else 4393 depth_pattern = R200_SURF_TILE_DEPTH_32BPP; 4394 } 4395 4396 /* rv100 and probably the derivative igps don't have depth tiling on all the time? */ 4397 if (info->dri->have3DWindows && 4398 (!((info->ChipFamily == CHIP_FAMILY_RV100) || 4399 (info->ChipFamily == CHIP_FAMILY_RS100) || 4400 (info->ChipFamily == CHIP_FAMILY_RS200)))) { 4401 drm_radeon_surface_alloc_t drmsurfalloc; 4402 drmsurfalloc.size = depthBufferSize; 4403 drmsurfalloc.address = info->dri->depthOffset; 4404 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) 4405 drmsurfalloc.flags = swap_pattern | (depth_width_bytes / 8) | depth_pattern; 4406 else 4407 drmsurfalloc.flags = swap_pattern | (depth_width_bytes / 16) | depth_pattern; 4408 retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_ALLOC, 4409 &drmsurfalloc, sizeof(drmsurfalloc)); 4410 if (retvalue < 0) 4411 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4412 "drm: could not allocate surface for depth buffer!\n"); 4413 } 4414 } 4415 else 4416#endif 4417 { 4418 unsigned int surf_info = swap_pattern; 4419 unsigned char *RADEONMMIO = info->MMIO; 4420 /* we don't need anything like WaitForFifo, no? */ 4421 if (info->tilingEnabled) { 4422 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) 4423 surf_info |= (width_bytes / 8) | color_pattern; 4424 else 4425 surf_info |= (width_bytes / 16) | color_pattern; 4426 } 4427 OUTREG(RADEON_SURFACE0_INFO, surf_info); 4428 OUTREG(RADEON_SURFACE0_LOWER_BOUND, 0); 4429 OUTREG(RADEON_SURFACE0_UPPER_BOUND, bufferSize - 1); 4430/* xf86DrvMsg(pScrn->scrnIndex, X_INFO, 4431 "surface0 set to %x, LB 0x%x UB 0x%x\n", 4432 surf_info, 0, bufferSize - 1024);*/ 4433 } 4434 4435 /* Update surface images */ 4436 if (info->ChipFamily < CHIP_FAMILY_R600) 4437 RADEONSaveSurfaces(pScrn, info->ModeReg); 4438} 4439 4440/* Read memory map */ 4441static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) 4442{ 4443 RADEONInfoPtr info = RADEONPTR(pScrn); 4444 unsigned char *RADEONMMIO = info->MMIO; 4445 4446 radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &save->mc_fb_location, 4447 &save->mc_agp_location, &save->mc_agp_location_hi); 4448 4449 if (!IS_AVIVO_VARIANT) { 4450 save->display_base_addr = INREG(RADEON_DISPLAY_BASE_ADDR); 4451 save->display2_base_addr = INREG(RADEON_DISPLAY2_BASE_ADDR); 4452 save->ov0_base_addr = INREG(RADEON_OV0_BASE_ADDR); 4453 } 4454} 4455 4456/* Read palette data */ 4457static void RADEONSavePalette(ScrnInfoPtr pScrn, RADEONSavePtr save) 4458{ 4459 RADEONInfoPtr info = RADEONPTR(pScrn); 4460 unsigned char *RADEONMMIO = info->MMIO; 4461 int i; 4462 4463 PAL_SELECT(1); 4464 INPAL_START(0); 4465 for (i = 0; i < 256; i++) { 4466 save->palette2[i] = INREG(RADEON_PALETTE_30_DATA); 4467 } 4468 4469 PAL_SELECT(0); 4470 INPAL_START(0); 4471 for (i = 0; i < 256; i++) { 4472 save->palette[i] = INREG(RADEON_PALETTE_30_DATA); 4473 } 4474} 4475 4476static void RADEONRestorePalette(ScrnInfoPtr pScrn, RADEONSavePtr restore) 4477{ 4478 RADEONInfoPtr info = RADEONPTR(pScrn); 4479 unsigned char *RADEONMMIO = info->MMIO; 4480 int i; 4481 4482 PAL_SELECT(1); 4483 OUTPAL_START(0); 4484 for (i = 0; i < 256; i++) { 4485 OUTREG(RADEON_PALETTE_30_DATA, restore->palette2[i]); 4486 } 4487 4488 PAL_SELECT(0); 4489 OUTPAL_START(0); 4490 for (i = 0; i < 256; i++) { 4491 OUTREG(RADEON_PALETTE_30_DATA, restore->palette[i]); 4492 } 4493} 4494 4495static void 4496avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) 4497{ 4498 RADEONInfoPtr info = RADEONPTR(pScrn); 4499 unsigned char *RADEONMMIO = info->MMIO; 4500 struct avivo_state *state = &save->avivo; 4501 int i, j; 4502 4503 // state->vga_memory_base = INREG(AVIVO_VGA_MEMORY_BASE); 4504 // state->vga_fb_start = INREG(AVIVO_VGA_FB_START); 4505 state->vga1_cntl = INREG(AVIVO_D1VGA_CONTROL); 4506 state->vga2_cntl = INREG(AVIVO_D2VGA_CONTROL); 4507 state->vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL); 4508 4509 state->crtc_master_en = INREG(AVIVO_DC_CRTC_MASTER_EN); 4510 state->crtc_tv_control = INREG(AVIVO_DC_CRTC_TV_CONTROL); 4511 state->dc_lb_memory_split = INREG(AVIVO_DC_LB_MEMORY_SPLIT); 4512 4513 state->pll1.ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC); 4514 state->pll1.ref_div = INREG(AVIVO_EXT1_PPLL_REF_DIV); 4515 state->pll1.fb_div = INREG(AVIVO_EXT1_PPLL_FB_DIV); 4516 state->pll1.post_div_src = INREG(AVIVO_EXT1_PPLL_POST_DIV_SRC); 4517 state->pll1.post_div = INREG(AVIVO_EXT1_PPLL_POST_DIV); 4518 state->pll1.ext_ppll_cntl = INREG(AVIVO_EXT1_PPLL_CNTL); 4519 state->pll1.pll_cntl = INREG(AVIVO_P1PLL_CNTL); 4520 state->pll1.int_ss_cntl = INREG(AVIVO_P1PLL_INT_SS_CNTL); 4521 4522 state->pll2.ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC); 4523 state->pll2.ref_div = INREG(AVIVO_EXT2_PPLL_REF_DIV); 4524 state->pll2.fb_div = INREG(AVIVO_EXT2_PPLL_FB_DIV); 4525 state->pll2.post_div_src = INREG(AVIVO_EXT2_PPLL_POST_DIV_SRC); 4526 state->pll2.post_div = INREG(AVIVO_EXT2_PPLL_POST_DIV); 4527 state->pll2.ext_ppll_cntl = INREG(AVIVO_EXT2_PPLL_CNTL); 4528 state->pll2.pll_cntl = INREG(AVIVO_P2PLL_CNTL); 4529 state->pll2.int_ss_cntl = INREG(AVIVO_P2PLL_INT_SS_CNTL); 4530 4531 state->vga25_ppll.ref_div_src = INREG(AVIVO_VGA25_PPLL_REF_DIV_SRC); 4532 state->vga25_ppll.ref_div = INREG(AVIVO_VGA25_PPLL_REF_DIV); 4533 state->vga25_ppll.fb_div = INREG(AVIVO_VGA25_PPLL_FB_DIV); 4534 state->vga25_ppll.post_div_src = INREG(AVIVO_VGA25_PPLL_POST_DIV_SRC); 4535 state->vga25_ppll.post_div = INREG(AVIVO_VGA25_PPLL_POST_DIV); 4536 state->vga25_ppll.pll_cntl = INREG(AVIVO_VGA25_PPLL_CNTL); 4537 4538 state->vga28_ppll.ref_div_src = INREG(AVIVO_VGA28_PPLL_REF_DIV_SRC); 4539 state->vga28_ppll.ref_div = INREG(AVIVO_VGA28_PPLL_REF_DIV); 4540 state->vga28_ppll.fb_div = INREG(AVIVO_VGA28_PPLL_FB_DIV); 4541 state->vga28_ppll.post_div_src = INREG(AVIVO_VGA28_PPLL_POST_DIV_SRC); 4542 state->vga28_ppll.post_div = INREG(AVIVO_VGA28_PPLL_POST_DIV); 4543 state->vga28_ppll.pll_cntl = INREG(AVIVO_VGA28_PPLL_CNTL); 4544 4545 state->vga41_ppll.ref_div_src = INREG(AVIVO_VGA41_PPLL_REF_DIV_SRC); 4546 state->vga41_ppll.ref_div = INREG(AVIVO_VGA41_PPLL_REF_DIV); 4547 state->vga41_ppll.fb_div = INREG(AVIVO_VGA41_PPLL_FB_DIV); 4548 state->vga41_ppll.post_div_src = INREG(AVIVO_VGA41_PPLL_POST_DIV_SRC); 4549 state->vga41_ppll.post_div = INREG(AVIVO_VGA41_PPLL_POST_DIV); 4550 state->vga41_ppll.pll_cntl = INREG(AVIVO_VGA41_PPLL_CNTL); 4551 4552 state->crtc1.pll_source = INREG(AVIVO_PCLK_CRTC1_CNTL); 4553 4554 state->crtc1.h_total = INREG(AVIVO_D1CRTC_H_TOTAL); 4555 state->crtc1.h_blank_start_end = INREG(AVIVO_D1CRTC_H_BLANK_START_END); 4556 state->crtc1.h_sync_a = INREG(AVIVO_D1CRTC_H_SYNC_A); 4557 state->crtc1.h_sync_a_cntl = INREG(AVIVO_D1CRTC_H_SYNC_A_CNTL); 4558 state->crtc1.h_sync_b = INREG(AVIVO_D1CRTC_H_SYNC_B); 4559 state->crtc1.h_sync_b_cntl = INREG(AVIVO_D1CRTC_H_SYNC_B_CNTL); 4560 4561 state->crtc1.v_total = INREG(AVIVO_D1CRTC_V_TOTAL); 4562 state->crtc1.v_blank_start_end = INREG(AVIVO_D1CRTC_V_BLANK_START_END); 4563 state->crtc1.v_sync_a = INREG(AVIVO_D1CRTC_V_SYNC_A); 4564 state->crtc1.v_sync_a_cntl = INREG(AVIVO_D1CRTC_V_SYNC_A_CNTL); 4565 state->crtc1.v_sync_b = INREG(AVIVO_D1CRTC_V_SYNC_B); 4566 state->crtc1.v_sync_b_cntl = INREG(AVIVO_D1CRTC_V_SYNC_B_CNTL); 4567 4568 state->crtc1.control = INREG(AVIVO_D1CRTC_CONTROL); 4569 state->crtc1.blank_control = INREG(AVIVO_D1CRTC_BLANK_CONTROL); 4570 state->crtc1.interlace_control = INREG(AVIVO_D1CRTC_INTERLACE_CONTROL); 4571 state->crtc1.stereo_control = INREG(AVIVO_D1CRTC_STEREO_CONTROL); 4572 4573 state->crtc1.cursor_control = INREG(AVIVO_D1CUR_CONTROL); 4574 4575 state->grph1.enable = INREG(AVIVO_D1GRPH_ENABLE); 4576 state->grph1.control = INREG(AVIVO_D1GRPH_CONTROL); 4577 state->grph1.control = INREG(AVIVO_D1GRPH_CONTROL); 4578 state->grph1.prim_surf_addr = INREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS); 4579 state->grph1.sec_surf_addr = INREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS); 4580 state->grph1.pitch = INREG(AVIVO_D1GRPH_PITCH); 4581 state->grph1.x_offset = INREG(AVIVO_D1GRPH_SURFACE_OFFSET_X); 4582 state->grph1.y_offset = INREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y); 4583 state->grph1.x_start = INREG(AVIVO_D1GRPH_X_START); 4584 state->grph1.y_start = INREG(AVIVO_D1GRPH_Y_START); 4585 state->grph1.x_end = INREG(AVIVO_D1GRPH_X_END); 4586 state->grph1.y_end = INREG(AVIVO_D1GRPH_Y_END); 4587 4588 state->grph1.desktop_height = INREG(AVIVO_D1MODE_DESKTOP_HEIGHT); 4589 state->grph1.viewport_start = INREG(AVIVO_D1MODE_VIEWPORT_START); 4590 state->grph1.viewport_size = INREG(AVIVO_D1MODE_VIEWPORT_SIZE); 4591 state->grph1.mode_data_format = INREG(AVIVO_D1MODE_DATA_FORMAT); 4592 4593 state->crtc2.pll_source = INREG(AVIVO_PCLK_CRTC2_CNTL); 4594 4595 state->crtc2.h_total = INREG(AVIVO_D2CRTC_H_TOTAL); 4596 state->crtc2.h_blank_start_end = INREG(AVIVO_D2CRTC_H_BLANK_START_END); 4597 state->crtc2.h_sync_a = INREG(AVIVO_D2CRTC_H_SYNC_A); 4598 state->crtc2.h_sync_a_cntl = INREG(AVIVO_D2CRTC_H_SYNC_A_CNTL); 4599 state->crtc2.h_sync_b = INREG(AVIVO_D2CRTC_H_SYNC_B); 4600 state->crtc2.h_sync_b_cntl = INREG(AVIVO_D2CRTC_H_SYNC_B_CNTL); 4601 4602 state->crtc2.v_total = INREG(AVIVO_D2CRTC_V_TOTAL); 4603 state->crtc2.v_blank_start_end = INREG(AVIVO_D2CRTC_V_BLANK_START_END); 4604 state->crtc2.v_sync_a = INREG(AVIVO_D2CRTC_V_SYNC_A); 4605 state->crtc2.v_sync_a_cntl = INREG(AVIVO_D2CRTC_V_SYNC_A_CNTL); 4606 state->crtc2.v_sync_b = INREG(AVIVO_D2CRTC_V_SYNC_B); 4607 state->crtc2.v_sync_b_cntl = INREG(AVIVO_D2CRTC_V_SYNC_B_CNTL); 4608 4609 state->crtc2.control = INREG(AVIVO_D2CRTC_CONTROL); 4610 state->crtc2.blank_control = INREG(AVIVO_D2CRTC_BLANK_CONTROL); 4611 state->crtc2.interlace_control = INREG(AVIVO_D2CRTC_INTERLACE_CONTROL); 4612 state->crtc2.stereo_control = INREG(AVIVO_D2CRTC_STEREO_CONTROL); 4613 4614 state->crtc2.cursor_control = INREG(AVIVO_D2CUR_CONTROL); 4615 4616 state->grph2.enable = INREG(AVIVO_D2GRPH_ENABLE); 4617 state->grph2.control = INREG(AVIVO_D2GRPH_CONTROL); 4618 state->grph2.control = INREG(AVIVO_D2GRPH_CONTROL); 4619 state->grph2.prim_surf_addr = INREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS); 4620 state->grph2.sec_surf_addr = INREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS); 4621 state->grph2.pitch = INREG(AVIVO_D2GRPH_PITCH); 4622 state->grph2.x_offset = INREG(AVIVO_D2GRPH_SURFACE_OFFSET_X); 4623 state->grph2.y_offset = INREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y); 4624 state->grph2.x_start = INREG(AVIVO_D2GRPH_X_START); 4625 state->grph2.y_start = INREG(AVIVO_D2GRPH_Y_START); 4626 state->grph2.x_end = INREG(AVIVO_D2GRPH_X_END); 4627 state->grph2.y_end = INREG(AVIVO_D2GRPH_Y_END); 4628 4629 state->grph2.desktop_height = INREG(AVIVO_D2MODE_DESKTOP_HEIGHT); 4630 state->grph2.viewport_start = INREG(AVIVO_D2MODE_VIEWPORT_START); 4631 state->grph2.viewport_size = INREG(AVIVO_D2MODE_VIEWPORT_SIZE); 4632 state->grph2.mode_data_format = INREG(AVIVO_D2MODE_DATA_FORMAT); 4633 4634 if (IS_DCE3_VARIANT) { 4635 /* save DVOA regs */ 4636 state->dvoa[0] = INREG(0x7080); 4637 state->dvoa[1] = INREG(0x7084); 4638 state->dvoa[2] = INREG(0x708c); 4639 state->dvoa[3] = INREG(0x7090); 4640 state->dvoa[4] = INREG(0x7094); 4641 state->dvoa[5] = INREG(0x70ac); 4642 state->dvoa[6] = INREG(0x70b0); 4643 4644 j = 0; 4645 /* save DAC regs */ 4646 for (i = 0x7000; i <= 0x7040; i += 4) { 4647 state->daca[j] = INREG(i); 4648 state->dacb[j] = INREG(i + 0x100); 4649 j++; 4650 } 4651 for (i = 0x7058; i <= 0x7060; i += 4) { 4652 state->daca[j] = INREG(i); 4653 state->dacb[j] = INREG(i + 0x100); 4654 j++; 4655 } 4656 for (i = 0x7068; i <= 0x706c; i += 4) { 4657 state->daca[j] = INREG(i); 4658 state->dacb[j] = INREG(i + 0x100); 4659 j++; 4660 } 4661 for (i = 0x7ef0; i <= 0x7ef8; i += 4) { 4662 state->daca[j] = INREG(i); 4663 state->dacb[j] = INREG(i + 0x100); 4664 j++; 4665 } 4666 state->daca[j] = INREG(0x7050); 4667 state->dacb[j] = INREG(0x7050 + 0x100); 4668 4669 j = 0; 4670 /* save FMT regs */ 4671 for (i = 0x6700; i <= 0x6744; i += 4) { 4672 state->fmt1[j] = INREG(i); 4673 state->fmt2[j] = INREG(i + 0x800); 4674 j++; 4675 } 4676 4677 j = 0; 4678 /* save DIG regs */ 4679 for (i = 0x75a0; i <= 0x75e0; i += 4) { 4680 state->dig1[j] = INREG(i); 4681 state->dig2[j] = INREG(i + 0x400); 4682 j++; 4683 } 4684 for (i = 0x75e8; i <= 0x75ec; i += 4) { 4685 state->dig1[j] = INREG(i); 4686 state->dig2[j] = INREG(i + 0x400); 4687 j++; 4688 } 4689 4690 j = 0; 4691 /* save HDMI regs */ 4692 for (i = 0x7400; i <= 0x741c; i += 4) { 4693 state->hdmi1[j] = INREG(i); 4694 state->hdmi2[j] = INREG(i + 0x400); 4695 j++; 4696 } 4697 for (i = 0x7430; i <= 0x74ec; i += 4) { 4698 state->hdmi1[j] = INREG(i); 4699 state->hdmi2[j] = INREG(i + 0x400); 4700 j++; 4701 } 4702 state->hdmi1[j] = INREG(0x7428); 4703 state->hdmi2[j] = INREG(0x7828); 4704 4705 j = 0; 4706 /* save AUX regs */ 4707 for (i = 0x7780; i <= 0x77b4; i += 4) { 4708 state->aux_cntl1[j] = INREG(i); 4709 state->aux_cntl2[j] = INREG(i + 0x040); 4710 state->aux_cntl3[j] = INREG(i + 0x400); 4711 state->aux_cntl4[j] = INREG(i + 0x440); 4712 if (IS_DCE32_VARIANT) { 4713 state->aux_cntl5[j] = INREG(i + 0x500); 4714 state->aux_cntl6[j] = INREG(i + 0x540); 4715 } 4716 j++; 4717 } 4718 4719 j = 0; 4720 /* save UNIPHY regs */ 4721 if (IS_DCE32_VARIANT) { 4722 for (i = 0x7680; i <= 0x7690; i += 4) { 4723 state->uniphy1[j] = INREG(i); 4724 state->uniphy2[j] = INREG(i + 0x20); 4725 state->uniphy3[j] = INREG(i + 0x400); 4726 state->uniphy4[j] = INREG(i + 0x420); 4727 state->uniphy5[j] = INREG(i + 0x840); 4728 state->uniphy6[j] = INREG(i + 0x940); 4729 j++; 4730 } 4731 for (i = 0x7698; i <= 0x769c; i += 4) { 4732 state->uniphy1[j] = INREG(i); 4733 state->uniphy2[j] = INREG(i + 0x20); 4734 state->uniphy3[j] = INREG(i + 0x400); 4735 state->uniphy4[j] = INREG(i + 0x420); 4736 state->uniphy5[j] = INREG(i + 0x840); 4737 state->uniphy6[j] = INREG(i + 0x940); 4738 j++; 4739 } 4740 } else { 4741 for (i = 0x7ec0; i <= 0x7edc; i += 4) { 4742 state->uniphy1[j] = INREG(i); 4743 state->uniphy2[j] = INREG(i + 0x100); 4744 j++; 4745 } 4746 } 4747 j = 0; 4748 /* save PHY,LINK regs */ 4749 for (i = 0x7f20; i <= 0x7f34; i += 4) { 4750 state->phy[j] = INREG(i); 4751 j++; 4752 } 4753 for (i = 0x7f9c; i <= 0x7fa4; i += 4) { 4754 state->phy[j] = INREG(i); 4755 j++; 4756 } 4757 state->phy[j] = INREG(0x7f40); 4758 4759 j = 0; 4760 /* save LVTMA regs */ 4761 for (i = 0x7f00; i <= 0x7f1c; i += 4) { 4762 state->lvtma[j] = INREG(i); 4763 j++; 4764 } 4765 for (i = 0x7f80; i <= 0x7f98; i += 4) { 4766 state->lvtma[j] = INREG(i); 4767 j++; 4768 } 4769 } else { 4770 j = 0; 4771 /* save DVOA regs */ 4772 for (i = 0x7980; i <= 0x79bc; i += 4) { 4773 state->dvoa[j] = INREG(i); 4774 j++; 4775 } 4776 4777 j = 0; 4778 /* save DAC regs */ 4779 for (i = 0x7800; i <= 0x782c; i += 4) { 4780 state->daca[j] = INREG(i); 4781 state->dacb[j] = INREG(i + 0x200); 4782 j++; 4783 } 4784 for (i = 0x7834; i <= 0x7840; i += 4) { 4785 state->daca[j] = INREG(i); 4786 state->dacb[j] = INREG(i + 0x200); 4787 j++; 4788 } 4789 for (i = 0x7850; i <= 0x7868; i += 4) { 4790 state->daca[j] = INREG(i); 4791 state->dacb[j] = INREG(i + 0x200); 4792 j++; 4793 } 4794 4795 j = 0; 4796 /* save TMDSA regs */ 4797 for (i = 0x7880; i <= 0x78e0; i += 4) { 4798 state->tmdsa[j] = INREG(i); 4799 j++; 4800 } 4801 for (i = 0x7904; i <= 0x7918; i += 4) { 4802 state->tmdsa[j] = INREG(i); 4803 j++; 4804 } 4805 4806 j = 0; 4807 /* save LVTMA regs */ 4808 for (i = 0x7a80; i <= 0x7b18; i += 4) { 4809 state->lvtma[j] = INREG(i); 4810 j++; 4811 } 4812 4813 if ((info->ChipFamily == CHIP_FAMILY_RS600) || 4814 (info->ChipFamily == CHIP_FAMILY_RS690) || 4815 (info->ChipFamily == CHIP_FAMILY_RS740)) { 4816 j = 0; 4817 /* save DDIA regs */ 4818 for (i = 0x7200; i <= 0x7290; i += 4) { 4819 state->ddia[j] = INREG(i); 4820 j++; 4821 } 4822 } 4823 } 4824 4825 /* scalers */ 4826 j = 0; 4827 for (i = 0x6578; i <= 0x65e4; i += 4) { 4828 state->d1scl[j] = INREG(i); 4829 state->d2scl[j] = INREG(i + 0x800); 4830 j++; 4831 } 4832 for (i = 0x6600; i <= 0x662c; i += 4) { 4833 state->d1scl[j] = INREG(i); 4834 state->d2scl[j] = INREG(i + 0x800); 4835 j++; 4836 } 4837 j = 0; 4838 for (i = 0x66e8; i <= 0x66fc; i += 4) { 4839 state->dxscl[j] = INREG(i); 4840 j++; 4841 } 4842 state->dxscl[6] = INREG(0x6e30); 4843 state->dxscl[7] = INREG(0x6e34); 4844 4845 if (state->crtc1.control & AVIVO_CRTC_EN) 4846 info->crtc_on = TRUE; 4847 4848 if (state->crtc2.control & AVIVO_CRTC_EN) 4849 info->crtc2_on = TRUE; 4850 4851} 4852 4853static void 4854avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) 4855{ 4856 RADEONInfoPtr info = RADEONPTR(pScrn); 4857 unsigned char *RADEONMMIO = info->MMIO; 4858 struct avivo_state *state = &restore->avivo; 4859 int i, j; 4860 4861 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "avivo_restore !\n"); 4862 4863 /* Disable VGA control for now.. maybe needs to be changed */ 4864 OUTREG(AVIVO_D1VGA_CONTROL, 0); 4865 OUTREG(AVIVO_D2VGA_CONTROL, 0); 4866 4867 /* Disable CRTCs */ 4868 OUTREG(AVIVO_D1CRTC_CONTROL, 4869 (INREG(AVIVO_D1CRTC_CONTROL) & ~0x300) | 0x01000000); 4870 OUTREG(AVIVO_D2CRTC_CONTROL, 4871 (INREG(AVIVO_D2CRTC_CONTROL) & ~0x300) | 0x01000000); 4872 OUTREG(AVIVO_D1CRTC_CONTROL, 4873 INREG(AVIVO_D1CRTC_CONTROL) & ~0x1); 4874 OUTREG(AVIVO_D2CRTC_CONTROL, 4875 INREG(AVIVO_D2CRTC_CONTROL) & ~0x1); 4876 OUTREG(AVIVO_D1CRTC_CONTROL, 4877 INREG(AVIVO_D1CRTC_CONTROL) | 0x100); 4878 OUTREG(AVIVO_D2CRTC_CONTROL, 4879 INREG(AVIVO_D2CRTC_CONTROL) | 0x100); 4880 4881 /* Lock graph registers */ 4882 OUTREG(AVIVO_D1GRPH_UPDATE, AVIVO_D1GRPH_UPDATE_LOCK); 4883 OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, state->grph1.prim_surf_addr); 4884 OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS, state->grph1.sec_surf_addr); 4885 OUTREG(AVIVO_D1GRPH_CONTROL, state->grph1.control); 4886 OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X, state->grph1.x_offset); 4887 OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y, state->grph1.y_offset); 4888 OUTREG(AVIVO_D1GRPH_X_START, state->grph1.x_start); 4889 OUTREG(AVIVO_D1GRPH_Y_START, state->grph1.y_start); 4890 OUTREG(AVIVO_D1GRPH_X_END, state->grph1.x_end); 4891 OUTREG(AVIVO_D1GRPH_Y_END, state->grph1.y_end); 4892 OUTREG(AVIVO_D1GRPH_PITCH, state->grph1.pitch); 4893 OUTREG(AVIVO_D1GRPH_ENABLE, state->grph1.enable); 4894 OUTREG(AVIVO_D1GRPH_UPDATE, 0); 4895 4896 OUTREG(AVIVO_D2GRPH_UPDATE, AVIVO_D1GRPH_UPDATE_LOCK); 4897 OUTREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, state->grph2.prim_surf_addr); 4898 OUTREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS, state->grph2.sec_surf_addr); 4899 OUTREG(AVIVO_D2GRPH_CONTROL, state->grph2.control); 4900 OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_X, state->grph2.x_offset); 4901 OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y, state->grph2.y_offset); 4902 OUTREG(AVIVO_D2GRPH_X_START, state->grph2.x_start); 4903 OUTREG(AVIVO_D2GRPH_Y_START, state->grph2.y_start); 4904 OUTREG(AVIVO_D2GRPH_X_END, state->grph2.x_end); 4905 OUTREG(AVIVO_D2GRPH_Y_END, state->grph2.y_end); 4906 OUTREG(AVIVO_D2GRPH_PITCH, state->grph2.pitch); 4907 OUTREG(AVIVO_D2GRPH_ENABLE, state->grph2.enable); 4908 OUTREG(AVIVO_D2GRPH_UPDATE, 0); 4909 4910 /* Whack some mode regs too */ 4911 OUTREG(AVIVO_D1SCL_UPDATE, AVIVO_D1SCL_UPDATE_LOCK); 4912 OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT, state->grph1.desktop_height); 4913 OUTREG(AVIVO_D1MODE_VIEWPORT_START, state->grph1.viewport_start); 4914 OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE, state->grph1.viewport_size); 4915 OUTREG(AVIVO_D1MODE_DATA_FORMAT, state->grph1.mode_data_format); 4916 OUTREG(AVIVO_D1SCL_UPDATE, 0); 4917 4918 OUTREG(AVIVO_D2SCL_UPDATE, AVIVO_D1SCL_UPDATE_LOCK); 4919 OUTREG(AVIVO_D2MODE_DESKTOP_HEIGHT, state->grph2.desktop_height); 4920 OUTREG(AVIVO_D2MODE_VIEWPORT_START, state->grph2.viewport_start); 4921 OUTREG(AVIVO_D2MODE_VIEWPORT_SIZE, state->grph2.viewport_size); 4922 OUTREG(AVIVO_D2MODE_DATA_FORMAT, state->grph2.mode_data_format); 4923 OUTREG(AVIVO_D2SCL_UPDATE, 0); 4924 4925 /* Set the PLL */ 4926 OUTREG(AVIVO_EXT1_PPLL_REF_DIV_SRC, state->pll1.ref_div_src); 4927 OUTREG(AVIVO_EXT1_PPLL_REF_DIV, state->pll1.ref_div); 4928 OUTREG(AVIVO_EXT1_PPLL_FB_DIV, state->pll1.fb_div); 4929 OUTREG(AVIVO_EXT1_PPLL_POST_DIV_SRC, state->pll1.post_div_src); 4930 OUTREG(AVIVO_EXT1_PPLL_POST_DIV, state->pll1.post_div); 4931 OUTREG(AVIVO_EXT1_PPLL_CNTL, state->pll1.ext_ppll_cntl); 4932 OUTREG(AVIVO_P1PLL_CNTL, state->pll1.pll_cntl); 4933 OUTREG(AVIVO_P1PLL_INT_SS_CNTL, state->pll1.int_ss_cntl); 4934 4935 OUTREG(AVIVO_EXT2_PPLL_REF_DIV_SRC, state->pll2.ref_div_src); 4936 OUTREG(AVIVO_EXT2_PPLL_REF_DIV, state->pll2.ref_div); 4937 OUTREG(AVIVO_EXT2_PPLL_FB_DIV, state->pll2.fb_div); 4938 OUTREG(AVIVO_EXT2_PPLL_POST_DIV_SRC, state->pll2.post_div_src); 4939 OUTREG(AVIVO_EXT2_PPLL_POST_DIV, state->pll2.post_div); 4940 OUTREG(AVIVO_EXT2_PPLL_CNTL, state->pll2.ext_ppll_cntl); 4941 OUTREG(AVIVO_P2PLL_CNTL, state->pll2.pll_cntl); 4942 OUTREG(AVIVO_P2PLL_INT_SS_CNTL, state->pll2.int_ss_cntl); 4943 4944 OUTREG(AVIVO_PCLK_CRTC1_CNTL, state->crtc1.pll_source); 4945 OUTREG(AVIVO_PCLK_CRTC2_CNTL, state->crtc2.pll_source); 4946 4947 /* Set the vga PLL */ 4948 OUTREG(AVIVO_VGA25_PPLL_REF_DIV_SRC, state->vga25_ppll.ref_div_src); 4949 OUTREG(AVIVO_VGA25_PPLL_REF_DIV, state->vga25_ppll.ref_div); 4950 OUTREG(AVIVO_VGA25_PPLL_FB_DIV, state->vga25_ppll.fb_div); 4951 OUTREG(AVIVO_VGA25_PPLL_POST_DIV_SRC, state->vga25_ppll.post_div_src); 4952 OUTREG(AVIVO_VGA25_PPLL_POST_DIV, state->vga25_ppll.post_div); 4953 OUTREG(AVIVO_VGA25_PPLL_CNTL, state->vga25_ppll.pll_cntl); 4954 4955 OUTREG(AVIVO_VGA28_PPLL_REF_DIV_SRC, state->vga28_ppll.ref_div_src); 4956 OUTREG(AVIVO_VGA28_PPLL_REF_DIV, state->vga28_ppll.ref_div); 4957 OUTREG(AVIVO_VGA28_PPLL_FB_DIV, state->vga28_ppll.fb_div); 4958 OUTREG(AVIVO_VGA28_PPLL_POST_DIV_SRC, state->vga28_ppll.post_div_src); 4959 OUTREG(AVIVO_VGA28_PPLL_POST_DIV, state->vga28_ppll.post_div); 4960 OUTREG(AVIVO_VGA28_PPLL_CNTL, state->vga28_ppll.pll_cntl); 4961 4962 OUTREG(AVIVO_VGA41_PPLL_REF_DIV_SRC, state->vga41_ppll.ref_div_src); 4963 OUTREG(AVIVO_VGA41_PPLL_REF_DIV, state->vga41_ppll.ref_div); 4964 OUTREG(AVIVO_VGA41_PPLL_FB_DIV, state->vga41_ppll.fb_div); 4965 OUTREG(AVIVO_VGA41_PPLL_POST_DIV_SRC, state->vga41_ppll.post_div_src); 4966 OUTREG(AVIVO_VGA41_PPLL_POST_DIV, state->vga41_ppll.post_div); 4967 OUTREG(AVIVO_VGA41_PPLL_CNTL, state->vga41_ppll.pll_cntl); 4968 4969 /* Set the CRTC */ 4970 OUTREG(AVIVO_D1CRTC_H_TOTAL, state->crtc1.h_total); 4971 OUTREG(AVIVO_D1CRTC_H_BLANK_START_END, state->crtc1.h_blank_start_end); 4972 OUTREG(AVIVO_D1CRTC_H_SYNC_A, state->crtc1.h_sync_a); 4973 OUTREG(AVIVO_D1CRTC_H_SYNC_A_CNTL, state->crtc1.h_sync_a_cntl); 4974 OUTREG(AVIVO_D1CRTC_H_SYNC_B, state->crtc1.h_sync_b); 4975 OUTREG(AVIVO_D1CRTC_H_SYNC_B_CNTL, state->crtc1.h_sync_b_cntl); 4976 4977 OUTREG(AVIVO_D1CRTC_V_TOTAL, state->crtc1.v_total); 4978 OUTREG(AVIVO_D1CRTC_V_BLANK_START_END, state->crtc1.v_blank_start_end); 4979 OUTREG(AVIVO_D1CRTC_V_SYNC_A, state->crtc1.v_sync_a); 4980 OUTREG(AVIVO_D1CRTC_V_SYNC_A_CNTL, state->crtc1.v_sync_a_cntl); 4981 OUTREG(AVIVO_D1CRTC_V_SYNC_B, state->crtc1.v_sync_b); 4982 OUTREG(AVIVO_D1CRTC_V_SYNC_B_CNTL, state->crtc1.v_sync_b_cntl); 4983 4984 OUTREG(AVIVO_D1CRTC_INTERLACE_CONTROL, state->crtc1.interlace_control); 4985 OUTREG(AVIVO_D1CRTC_STEREO_CONTROL, state->crtc1.stereo_control); 4986 4987 OUTREG(AVIVO_D1CUR_CONTROL, state->crtc1.cursor_control); 4988 4989 /* XXX Fix scaler */ 4990 4991 OUTREG(AVIVO_D2CRTC_H_TOTAL, state->crtc2.h_total); 4992 OUTREG(AVIVO_D2CRTC_H_BLANK_START_END, state->crtc2.h_blank_start_end); 4993 OUTREG(AVIVO_D2CRTC_H_SYNC_A, state->crtc2.h_sync_a); 4994 OUTREG(AVIVO_D2CRTC_H_SYNC_A_CNTL, state->crtc2.h_sync_a_cntl); 4995 OUTREG(AVIVO_D2CRTC_H_SYNC_B, state->crtc2.h_sync_b); 4996 OUTREG(AVIVO_D2CRTC_H_SYNC_B_CNTL, state->crtc2.h_sync_b_cntl); 4997 4998 OUTREG(AVIVO_D2CRTC_V_TOTAL, state->crtc2.v_total); 4999 OUTREG(AVIVO_D2CRTC_V_BLANK_START_END, state->crtc2.v_blank_start_end); 5000 OUTREG(AVIVO_D2CRTC_V_SYNC_A, state->crtc2.v_sync_a); 5001 OUTREG(AVIVO_D2CRTC_V_SYNC_A_CNTL, state->crtc2.v_sync_a_cntl); 5002 OUTREG(AVIVO_D2CRTC_V_SYNC_B, state->crtc2.v_sync_b); 5003 OUTREG(AVIVO_D2CRTC_V_SYNC_B_CNTL, state->crtc2.v_sync_b_cntl); 5004 5005 OUTREG(AVIVO_D2CRTC_INTERLACE_CONTROL, state->crtc2.interlace_control); 5006 OUTREG(AVIVO_D2CRTC_STEREO_CONTROL, state->crtc2.stereo_control); 5007 5008 OUTREG(AVIVO_D2CUR_CONTROL, state->crtc2.cursor_control); 5009 5010 if (IS_DCE3_VARIANT) { 5011 /* DVOA regs */ 5012 OUTREG(0x7080, state->dvoa[0]); 5013 OUTREG(0x7084, state->dvoa[1]); 5014 OUTREG(0x708c, state->dvoa[2]); 5015 OUTREG(0x7090, state->dvoa[3]); 5016 OUTREG(0x7094, state->dvoa[4]); 5017 OUTREG(0x70ac, state->dvoa[5]); 5018 OUTREG(0x70b0, state->dvoa[6]); 5019 5020 j = 0; 5021 /* DAC regs */ 5022 for (i = 0x7000; i <= 0x7040; i += 4) { 5023 OUTREG(i, state->daca[j]); 5024 OUTREG((i + 0x100), state->dacb[j]); 5025 j++; 5026 } 5027 for (i = 0x7058; i <= 0x7060; i += 4) { 5028 OUTREG(i, state->daca[j]); 5029 OUTREG((i + 0x100), state->dacb[j]); 5030 j++; 5031 } 5032 for (i = 0x7068; i <= 0x706c; i += 4) { 5033 OUTREG(i, state->daca[j]); 5034 OUTREG((i + 0x100), state->dacb[j]); 5035 j++; 5036 } 5037 for (i = 0x7ef0; i <= 0x7ef8; i += 4) { 5038 OUTREG(i, state->daca[j]); 5039 OUTREG((i + 0x100), state->dacb[j]); 5040 j++; 5041 } 5042 OUTREG(0x7050, state->daca[j]); 5043 OUTREG((0x7050 + 0x100), state->dacb[j]); 5044 5045 j = 0; 5046 /* FMT regs */ 5047 for (i = 0x6700; i <= 0x6744; i += 4) { 5048 OUTREG(i, state->fmt1[j]); 5049 OUTREG((i + 0x800), state->fmt2[j]); 5050 j++; 5051 } 5052 5053 j = 0; 5054 /* DIG regs */ 5055 for (i = 0x75a0; i <= 0x75e0; i += 4) { 5056 OUTREG(i, state->dig1[j]); 5057 OUTREG((i + 0x400), state->dig2[j]); 5058 j++; 5059 } 5060 for (i = 0x75e8; i <= 0x75ec; i += 4) { 5061 OUTREG(i, state->dig1[j]); 5062 OUTREG((i + 0x400), state->dig2[j]); 5063 j++; 5064 } 5065 5066 j = 0; 5067 /* HDMI regs */ 5068 for (i = 0x7400; i <= 0x741c; i += 4) { 5069 OUTREG(i, state->hdmi1[j]); 5070 OUTREG((i + 0x400), state->hdmi2[j]); 5071 j++; 5072 } 5073 for (i = 0x7430; i <= 0x74ec; i += 4) { 5074 OUTREG(i, state->hdmi1[j]); 5075 OUTREG((i + 0x400), state->hdmi2[j]); 5076 j++; 5077 } 5078 OUTREG(0x7428, state->hdmi1[j]); 5079 OUTREG((0x7428 + 0x400), state->hdmi2[j]); 5080 5081 j = 0; 5082 /* save AUX regs */ 5083 for (i = 0x7780; i <= 0x77b4; i += 4) { 5084 OUTREG(i, state->aux_cntl1[j]); 5085 OUTREG((i + 0x040), state->aux_cntl2[j]); 5086 OUTREG((i + 0x400), state->aux_cntl3[j]); 5087 OUTREG((i + 0x440), state->aux_cntl4[j]); 5088 if (IS_DCE32_VARIANT) { 5089 OUTREG((i + 0x500), state->aux_cntl5[j]); 5090 OUTREG((i + 0x540), state->aux_cntl6[j]); 5091 } 5092 j++; 5093 } 5094 5095 j = 0; 5096 /* save UNIPHY regs */ 5097 if (IS_DCE32_VARIANT) { 5098 for (i = 0x7680; i <= 0x7690; i += 4) { 5099 OUTREG(i, state->uniphy1[j]); 5100 OUTREG((i + 0x20), state->uniphy2[j]); 5101 OUTREG((i + 0x400), state->uniphy3[j]); 5102 OUTREG((i + 0x420), state->uniphy4[j]); 5103 OUTREG((i + 0x840), state->uniphy5[j]); 5104 OUTREG((i + 0x940), state->uniphy6[j]); 5105 j++; 5106 } 5107 for (i = 0x7698; i <= 0x769c; i += 4) { 5108 OUTREG(i, state->uniphy1[j]); 5109 OUTREG((i + 0x20), state->uniphy2[j]); 5110 OUTREG((i + 0x400), state->uniphy3[j]); 5111 OUTREG((i + 0x420), state->uniphy4[j]); 5112 OUTREG((i + 0x840), state->uniphy5[j]); 5113 OUTREG((i + 0x940), state->uniphy6[j]); 5114 j++; 5115 } 5116 } else { 5117 for (i = 0x7ec0; i <= 0x7edc; i += 4) { 5118 OUTREG(i, state->uniphy1[j]); 5119 OUTREG((i + 0x100), state->uniphy2[j]); 5120 j++; 5121 } 5122 } 5123 j = 0; 5124 /* save PHY,LINK regs */ 5125 for (i = 0x7f20; i <= 0x7f34; i += 4) { 5126 OUTREG(i, state->phy[j]); 5127 j++; 5128 } 5129 for (i = 0x7f9c; i <= 0x7fa4; i += 4) { 5130 OUTREG(i, state->phy[j]); 5131 j++; 5132 } 5133 state->phy[j] = INREG(0x7f40); 5134 5135 j = 0; 5136 /* save LVTMA regs */ 5137 for (i = 0x7f00; i <= 0x7f1c; i += 4) { 5138 OUTREG(i, state->lvtma[j]); 5139 j++; 5140 } 5141 for (i = 0x7f80; i <= 0x7f98; i += 4) { 5142 OUTREG(i, state->lvtma[j]); 5143 j++; 5144 } 5145 } else { 5146 j = 0; 5147 /* DVOA regs */ 5148 for (i = 0x7980; i <= 0x79bc; i += 4) { 5149 OUTREG(i, state->dvoa[j]); 5150 j++; 5151 } 5152 5153 j = 0; 5154 /* DAC regs */ /* -- MIGHT NEED ORDERING FIX & DELAYS -- */ 5155 for (i = 0x7800; i <= 0x782c; i += 4) { 5156 OUTREG(i, state->daca[j]); 5157 OUTREG((i + 0x200), state->dacb[j]); 5158 j++; 5159 } 5160 for (i = 0x7834; i <= 0x7840; i += 4) { 5161 OUTREG(i, state->daca[j]); 5162 OUTREG((i + 0x200), state->dacb[j]); 5163 j++; 5164 } 5165 for (i = 0x7850; i <= 0x7868; i += 4) { 5166 OUTREG(i, state->daca[j]); 5167 OUTREG((i + 0x200), state->dacb[j]); 5168 j++; 5169 } 5170 5171 j = 0; 5172 /* TMDSA regs */ 5173 for (i = 0x7880; i <= 0x78e0; i += 4) { 5174 OUTREG(i, state->tmdsa[j]); 5175 j++; 5176 } 5177 for (i = 0x7904; i <= 0x7918; i += 4) { 5178 OUTREG(i, state->tmdsa[j]); 5179 j++; 5180 } 5181 5182 j = 0; 5183 /* LVTMA regs */ 5184 for (i = 0x7a80; i <= 0x7b18; i += 4) { 5185 OUTREG(i, state->lvtma[j]); 5186 j++; 5187 } 5188 5189 /* DDIA regs */ 5190 if ((info->ChipFamily == CHIP_FAMILY_RS600) || 5191 (info->ChipFamily == CHIP_FAMILY_RS690) || 5192 (info->ChipFamily == CHIP_FAMILY_RS740)) { 5193 j = 0; 5194 for (i = 0x7200; i <= 0x7290; i += 4) { 5195 OUTREG(i, state->ddia[j]); 5196 j++; 5197 } 5198 } 5199 } 5200 5201 /* scalers */ 5202 j = 0; 5203 for (i = 0x6578; i <= 0x65e4; i += 4) { 5204 OUTREG(i, state->d1scl[j]); 5205 OUTREG((i + 0x800), state->d2scl[j]); 5206 j++; 5207 } 5208 for (i = 0x6600; i <= 0x662c; i += 4) { 5209 OUTREG(i, state->d1scl[j]); 5210 OUTREG((i + 0x800), state->d2scl[j]); 5211 j++; 5212 } 5213 j = 0; 5214 for (i = 0x66e8; i <= 0x66fc; i += 4) { 5215 OUTREG(i, state->dxscl[j]); 5216 j++; 5217 } 5218 OUTREG(0x6e30, state->dxscl[6]); 5219 OUTREG(0x6e34, state->dxscl[7]); 5220 5221 /* Enable CRTCs */ 5222 if (state->crtc1.control & 1) { 5223 OUTREG(AVIVO_D1CRTC_CONTROL, 0x01000101); 5224 INREG(AVIVO_D1CRTC_CONTROL); 5225 OUTREG(AVIVO_D1CRTC_CONTROL, 0x00010101); 5226 } 5227 if (state->crtc2.control & 1) { 5228 OUTREG(AVIVO_D2CRTC_CONTROL, 0x01000101); 5229 INREG(AVIVO_D2CRTC_CONTROL); 5230 OUTREG(AVIVO_D2CRTC_CONTROL, 0x00010101); 5231 } 5232 5233 /* Where should that go ? */ 5234 OUTREG(AVIVO_DC_CRTC_TV_CONTROL, state->crtc_tv_control); 5235 OUTREG(AVIVO_DC_LB_MEMORY_SPLIT, state->dc_lb_memory_split); 5236 5237 /* Need fixing too ? */ 5238 OUTREG(AVIVO_D1CRTC_BLANK_CONTROL, state->crtc1.blank_control); 5239 OUTREG(AVIVO_D2CRTC_BLANK_CONTROL, state->crtc2.blank_control); 5240 5241 /* Dbl check */ 5242 OUTREG(AVIVO_VGA_RENDER_CONTROL, state->vga_render_control); 5243 OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl); 5244 OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl); 5245 5246 /* Should only enable outputs here */ 5247} 5248 5249static void avivo_restore_vga_regs(ScrnInfoPtr pScrn, RADEONSavePtr restore) 5250{ 5251 RADEONInfoPtr info = RADEONPTR(pScrn); 5252 unsigned char *RADEONMMIO = info->MMIO; 5253 struct avivo_state *state = &restore->avivo; 5254 5255 OUTREG(AVIVO_VGA_RENDER_CONTROL, state->vga_render_control); 5256 OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl); 5257 OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl); 5258} 5259 5260static void 5261RADEONRestoreBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) 5262{ 5263 RADEONInfoPtr info = RADEONPTR(pScrn); 5264 unsigned char *RADEONMMIO = info->MMIO; 5265 5266 if (info->ChipFamily >= CHIP_FAMILY_R600) { 5267 OUTREG(R600_BIOS_0_SCRATCH, restore->bios_0_scratch); 5268 OUTREG(R600_BIOS_1_SCRATCH, restore->bios_1_scratch); 5269 OUTREG(R600_BIOS_2_SCRATCH, restore->bios_2_scratch); 5270 OUTREG(R600_BIOS_3_SCRATCH, restore->bios_3_scratch); 5271 OUTREG(R600_BIOS_4_SCRATCH, restore->bios_4_scratch); 5272 OUTREG(R600_BIOS_5_SCRATCH, restore->bios_5_scratch); 5273 OUTREG(R600_BIOS_6_SCRATCH, restore->bios_6_scratch); 5274 OUTREG(R600_BIOS_7_SCRATCH, restore->bios_7_scratch); 5275 } else { 5276 OUTREG(RADEON_BIOS_0_SCRATCH, restore->bios_0_scratch); 5277 OUTREG(RADEON_BIOS_1_SCRATCH, restore->bios_1_scratch); 5278 OUTREG(RADEON_BIOS_2_SCRATCH, restore->bios_2_scratch); 5279 OUTREG(RADEON_BIOS_3_SCRATCH, restore->bios_3_scratch); 5280 OUTREG(RADEON_BIOS_4_SCRATCH, restore->bios_4_scratch); 5281 OUTREG(RADEON_BIOS_5_SCRATCH, restore->bios_5_scratch); 5282 OUTREG(RADEON_BIOS_6_SCRATCH, restore->bios_6_scratch); 5283 OUTREG(RADEON_BIOS_7_SCRATCH, restore->bios_7_scratch); 5284 } 5285} 5286 5287static void 5288RADEONSaveBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) 5289{ 5290 RADEONInfoPtr info = RADEONPTR(pScrn); 5291 unsigned char *RADEONMMIO = info->MMIO; 5292 5293 if (info->ChipFamily >= CHIP_FAMILY_R600) { 5294 save->bios_0_scratch = INREG(R600_BIOS_0_SCRATCH); 5295 save->bios_1_scratch = INREG(R600_BIOS_1_SCRATCH); 5296 save->bios_2_scratch = INREG(R600_BIOS_2_SCRATCH); 5297 save->bios_3_scratch = INREG(R600_BIOS_3_SCRATCH); 5298 save->bios_4_scratch = INREG(R600_BIOS_4_SCRATCH); 5299 save->bios_5_scratch = INREG(R600_BIOS_5_SCRATCH); 5300 save->bios_6_scratch = INREG(R600_BIOS_6_SCRATCH); 5301 save->bios_7_scratch = INREG(R600_BIOS_7_SCRATCH); 5302 } else { 5303 save->bios_0_scratch = INREG(RADEON_BIOS_0_SCRATCH); 5304 save->bios_1_scratch = INREG(RADEON_BIOS_1_SCRATCH); 5305 save->bios_2_scratch = INREG(RADEON_BIOS_2_SCRATCH); 5306 save->bios_3_scratch = INREG(RADEON_BIOS_3_SCRATCH); 5307 save->bios_4_scratch = INREG(RADEON_BIOS_4_SCRATCH); 5308 save->bios_5_scratch = INREG(RADEON_BIOS_5_SCRATCH); 5309 save->bios_6_scratch = INREG(RADEON_BIOS_6_SCRATCH); 5310 save->bios_7_scratch = INREG(RADEON_BIOS_7_SCRATCH); 5311 } 5312} 5313 5314/* Save everything needed to restore the original VC state */ 5315static void RADEONSave(ScrnInfoPtr pScrn) 5316{ 5317 RADEONInfoPtr info = RADEONPTR(pScrn); 5318 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 5319 unsigned char *RADEONMMIO = info->MMIO; 5320 RADEONSavePtr save = info->SavedReg; 5321 5322 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5323 "RADEONSave\n"); 5324 5325#ifdef WITH_VGAHW 5326 if (info->VGAAccess) { 5327 vgaHWPtr hwp = VGAHWPTR(pScrn); 5328 5329 vgaHWUnlock(hwp); 5330# if defined(__powerpc__) 5331 /* temporary hack to prevent crashing on PowerMacs when trying to 5332 * read VGA fonts and colormap, will find a better solution 5333 * in the future. TODO: Check if there's actually some VGA stuff 5334 * setup in the card at all !! 5335 */ 5336 vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE); /* Save mode only */ 5337# elif defined(__linux__) 5338 /* Save only mode * & fonts */ 5339 vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS ); 5340# else 5341 /* Save mode * & fonts & cmap */ 5342 vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_ALL); 5343# endif 5344 vgaHWLock(hwp); 5345 } 5346#endif 5347 5348 if (IS_DCE4_VARIANT) { 5349 RADEONSaveMemMapRegisters(pScrn, save); 5350 //XXX 5351 } else if (IS_AVIVO_VARIANT) { 5352 RADEONSaveMemMapRegisters(pScrn, save); 5353 avivo_save(pScrn, save); 5354 } else { 5355 save->dp_datatype = INREG(RADEON_DP_DATATYPE); 5356 save->rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET); 5357 save->clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX); 5358 RADEONPllErrataAfterIndex(info); 5359 5360 RADEONSaveMemMapRegisters(pScrn, save); 5361 RADEONSaveCommonRegisters(pScrn, save); 5362 RADEONSavePLLRegisters(pScrn, save); 5363 RADEONSaveCrtcRegisters(pScrn, save); 5364 RADEONSaveFPRegisters(pScrn, save); 5365 RADEONSaveDACRegisters(pScrn, save); 5366 RADEONSavePalette(pScrn, save); 5367 5368 if (pRADEONEnt->HasCRTC2) { 5369 RADEONSaveCrtc2Registers(pScrn, save); 5370 RADEONSavePLL2Registers(pScrn, save); 5371 } 5372 if (info->InternalTVOut) 5373 RADEONSaveTVRegisters(pScrn, save); 5374 } 5375 5376 if (info->ChipFamily < CHIP_FAMILY_R600) 5377 RADEONSaveSurfaces(pScrn, save); 5378 5379} 5380 5381/* Restore the original (text) mode */ 5382static void RADEONRestore(ScrnInfoPtr pScrn) 5383{ 5384 RADEONInfoPtr info = RADEONPTR(pScrn); 5385 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 5386 unsigned char *RADEONMMIO = info->MMIO; 5387 RADEONSavePtr restore = info->SavedReg; 5388 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 5389 xf86CrtcPtr crtc; 5390 5391 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5392 "RADEONRestore\n"); 5393 5394#if X_BYTE_ORDER == X_BIG_ENDIAN 5395 if (info->ChipFamily < CHIP_FAMILY_R600) { 5396 RADEONWaitForFifo(pScrn, 1); 5397 OUTREG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_NONE); 5398 } 5399#endif 5400 5401 RADEONBlank(pScrn); 5402 5403 if (IS_DCE4_VARIANT) { 5404 RADEONRestoreMemMapRegisters(pScrn, restore); 5405 //XXX 5406 } else if (IS_AVIVO_VARIANT) { 5407 RADEONRestoreMemMapRegisters(pScrn, restore); 5408 avivo_restore(pScrn, restore); 5409 } else { 5410 OUTREG(RADEON_CLOCK_CNTL_INDEX, restore->clock_cntl_index); 5411 RADEONPllErrataAfterIndex(info); 5412 OUTREG(RADEON_RBBM_SOFT_RESET, restore->rbbm_soft_reset); 5413 OUTREG(RADEON_DP_DATATYPE, restore->dp_datatype); 5414 OUTREG(RADEON_GRPH_BUFFER_CNTL, restore->grph_buffer_cntl); 5415 OUTREG(RADEON_GRPH2_BUFFER_CNTL, restore->grph2_buffer_cntl); 5416 5417 if (!info->IsSecondary) { 5418 RADEONRestoreMemMapRegisters(pScrn, restore); 5419 RADEONRestoreCommonRegisters(pScrn, restore); 5420 5421 if (pRADEONEnt->HasCRTC2) { 5422 RADEONRestoreCrtc2Registers(pScrn, restore); 5423 RADEONRestorePLL2Registers(pScrn, restore); 5424 } 5425 5426 RADEONRestoreCrtcRegisters(pScrn, restore); 5427 RADEONRestorePLLRegisters(pScrn, restore); 5428 RADEONRestoreRMXRegisters(pScrn, restore); 5429 RADEONRestoreFPRegisters(pScrn, restore); 5430 RADEONRestoreFP2Registers(pScrn, restore); 5431 RADEONRestoreLVDSRegisters(pScrn, restore); 5432 5433 if (info->InternalTVOut) 5434 RADEONRestoreTVRegisters(pScrn, restore); 5435 } 5436 5437 RADEONRestoreBIOSRegisters(pScrn, restore); 5438 } 5439 5440 5441#if 1 5442 /* Temp fix to "solve" VT switch problems. When switching VTs on 5443 * some systems, the console can either hang or the fonts can be 5444 * corrupted. This hack solves the problem 99% of the time. A 5445 * correct fix is being worked on. 5446 */ 5447 usleep(100000); 5448#endif 5449 5450 if (info->ChipFamily < CHIP_FAMILY_R600) 5451 RADEONRestoreSurfaces(pScrn, restore); 5452 5453 /* need to make sure we don't enable a crtc by accident or we may get a hang */ 5454 if (pRADEONEnt->HasCRTC2 && !info->IsSecondary) { 5455 if (info->crtc2_on && xf86_config->num_crtc > 1) { 5456 crtc = xf86_config->crtc[1]; 5457 crtc->funcs->dpms(crtc, DPMSModeOn); 5458 } 5459 } 5460 if (info->crtc_on) { 5461 crtc = xf86_config->crtc[0]; 5462 crtc->funcs->dpms(crtc, DPMSModeOn); 5463 } 5464 5465#ifdef WITH_VGAHW 5466 if (info->VGAAccess) { 5467 vgaHWPtr hwp = VGAHWPTR(pScrn); 5468 vgaHWUnlock(hwp); 5469# if defined(__powerpc__) 5470 /* Temporary hack to prevent crashing on PowerMacs when trying to 5471 * write VGA fonts, will find a better solution in the future 5472 */ 5473 vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE ); 5474# elif defined(__linux__) 5475 vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS ); 5476# else 5477 vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_ALL ); 5478# endif 5479 vgaHWLock(hwp); 5480 } 5481#endif 5482 5483 /* to restore console mode, DAC registers should be set after every other registers are set, 5484 * otherwise,we may get blank screen 5485 */ 5486 if (IS_AVIVO_VARIANT) 5487 avivo_restore_vga_regs(pScrn, restore); 5488 5489 if (!IS_AVIVO_VARIANT) { 5490 RADEONRestorePalette(pScrn, restore); 5491 RADEONRestoreDACRegisters(pScrn, restore); 5492 } 5493#if 0 5494 RADEONWaitForVerticalSync(pScrn); 5495#endif 5496} 5497 5498static Bool RADEONSaveScreen(ScreenPtr pScreen, int mode) 5499{ 5500 ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; 5501 Bool unblank; 5502 5503 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5504 "RADEONSaveScreen(%d)\n", mode); 5505 5506 unblank = xf86IsUnblank(mode); 5507 if (unblank) SetTimeSinceLastInputEvent(); 5508 5509 if ((pScrn != NULL) && pScrn->vtSema) { 5510 if (unblank) 5511 RADEONUnblank(pScrn); 5512 else 5513 RADEONBlank(pScrn); 5514 } 5515 return TRUE; 5516} 5517 5518Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) 5519{ 5520 ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; 5521 RADEONInfoPtr info = RADEONPTR(pScrn); 5522 Bool tilingOld = info->tilingEnabled; 5523 Bool ret; 5524#ifdef XF86DRI 5525 Bool CPStarted = info->cp->CPStarted; 5526 5527 if (CPStarted) { 5528 DRILock(pScrn->pScreen, 0); 5529 RADEONCP_STOP(pScrn, info); 5530 } 5531#endif 5532 5533 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5534 "RADEONSwitchMode() !n"); 5535 5536 if (info->allowColorTiling) { 5537 info->tilingEnabled = (mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; 5538#ifdef XF86DRI 5539 if (info->directRenderingEnabled && (info->tilingEnabled != tilingOld)) { 5540 drm_radeon_sarea_t *pSAREAPriv; 5541 if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0) 5542 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 5543 "[drm] failed changing tiling status\n"); 5544 pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen); 5545 info->tilingEnabled = pSAREAPriv->tiling_enabled ? TRUE : FALSE; 5546 } 5547#endif 5548 } 5549 5550 if (info->accelOn) 5551 RADEON_SYNC(info, pScrn); 5552 5553 ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0); 5554 5555 if (info->tilingEnabled != tilingOld) { 5556 /* need to redraw front buffer, I guess this can be considered a hack ? */ 5557 xf86EnableDisableFBAccess(scrnIndex, FALSE); 5558 RADEONChangeSurfaces(pScrn); 5559 xf86EnableDisableFBAccess(scrnIndex, TRUE); 5560 /* xf86SetRootClip would do, but can't access that here */ 5561 } 5562 5563 if (info->accelOn) { 5564 RADEON_SYNC(info, pScrn); 5565 if (info->ChipFamily < CHIP_FAMILY_R600) 5566 RADEONEngineRestore(pScrn); 5567 } 5568 5569#ifdef XF86DRI 5570 if (CPStarted) { 5571 RADEONCP_START(pScrn, info); 5572 DRIUnlock(pScrn->pScreen); 5573 } 5574#endif 5575 5576 /* reset ecp for overlay */ 5577 info->ecp_div = -1; 5578 5579 return ret; 5580} 5581 5582#ifdef X_XF86MiscPassMessage 5583Bool RADEONHandleMessage(int scrnIndex, const char* msgtype, 5584 const char* msgval, char** retmsg) 5585{ 5586 ErrorF("RADEONHandleMessage(%d, \"%s\", \"%s\", retmsg)\n", scrnIndex, 5587 msgtype, msgval); 5588 *retmsg = ""; 5589 return 0; 5590} 5591#endif 5592 5593#ifndef HAVE_XF86MODEBANDWIDTH 5594/** Calculates the memory bandwidth (in MiB/sec) of a mode. */ 5595_X_HIDDEN unsigned int 5596xf86ModeBandwidth(DisplayModePtr mode, int depth) 5597{ 5598 float a_active, a_total, active_percent, pixels_per_second; 5599 int bytes_per_pixel = (depth + 7) / 8; 5600 5601 if (!mode->HTotal || !mode->VTotal || !mode->Clock) 5602 return 0; 5603 5604 a_active = mode->HDisplay * mode->VDisplay; 5605 a_total = mode->HTotal * mode->VTotal; 5606 active_percent = a_active / a_total; 5607 pixels_per_second = active_percent * mode->Clock * 1000.0; 5608 5609 return (unsigned int)(pixels_per_second * bytes_per_pixel / (1024 * 1024)); 5610} 5611#endif 5612 5613/* Used to disallow modes that are not supported by the hardware */ 5614ModeStatus RADEONValidMode(int scrnIndex, DisplayModePtr mode, 5615 Bool verbose, int flag) 5616{ 5617 ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; 5618 RADEONInfoPtr info = RADEONPTR(pScrn); 5619 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 5620 5621 /* 5622 * RN50 has effective maximum mode bandwidth of about 300MiB/s. 5623 * XXX should really do this for all chips by properly computing 5624 * memory bandwidth and an overhead factor. 5625 */ 5626 if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) { 5627 if (xf86ModeBandwidth(mode, pScrn->bitsPerPixel) > 300) 5628 return MODE_BANDWIDTH; 5629 } 5630 5631 /* There are problems with double scan mode at high clocks 5632 * They're likely related PLL and display buffer settings. 5633 * Disable these modes for now. 5634 */ 5635 if (mode->Flags & V_DBLSCAN) { 5636 if ((mode->CrtcHDisplay >= 1024) || (mode->CrtcVDisplay >= 768)) 5637 return MODE_CLOCK_RANGE; 5638 } 5639 return MODE_OK; 5640} 5641 5642/* Adjust viewport into virtual desktop such that (0,0) in viewport 5643 * space is (x,y) in virtual space. 5644 */ 5645void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool crtc2) 5646{ 5647 RADEONInfoPtr info = RADEONPTR(pScrn); 5648 unsigned char *RADEONMMIO = info->MMIO; 5649 int Base, reg, regcntl, crtcoffsetcntl, xytilereg, crtcxytile = 0; 5650#ifdef XF86DRI 5651 drm_radeon_sarea_t *pSAREAPriv; 5652 XF86DRISAREAPtr pSAREA; 5653#endif 5654 5655#if 0 /* Verbose */ 5656 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5657 "RADEONDoAdjustFrame(%d,%d,%d)\n", x, y, clone); 5658#endif 5659 5660 Base = pScrn->fbOffset; 5661 5662 /* note we cannot really simply use the info->ModeReg.crtc_offset_cntl value, since the 5663 drm might have set FLIP_CNTL since we wrote that. Unfortunately FLIP_CNTL causes 5664 flickering when scrolling vertically in a virtual screen, possibly because crtc will 5665 pick up the new offset value at the end of each scanline, but the new offset_cntl value 5666 only after a vsync. We'd probably need to wait (in drm) for vsync and only then update 5667 OFFSET and OFFSET_CNTL, if the y coord has changed. Seems hard to fix. */ 5668 if (crtc2) { 5669 reg = RADEON_CRTC2_OFFSET; 5670 regcntl = RADEON_CRTC2_OFFSET_CNTL; 5671 xytilereg = R300_CRTC2_TILE_X0_Y0; 5672 } else { 5673 reg = RADEON_CRTC_OFFSET; 5674 regcntl = RADEON_CRTC_OFFSET_CNTL; 5675 xytilereg = R300_CRTC_TILE_X0_Y0; 5676 } 5677 crtcoffsetcntl = INREG(regcntl) & ~0xf; 5678#if 0 5679 /* try to get rid of flickering when scrolling at least for 2d */ 5680#ifdef XF86DRI 5681 if (!info->dri->have3DWindows) 5682#endif 5683 crtcoffsetcntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL; 5684#endif 5685 if (info->tilingEnabled) { 5686 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { 5687 /* On r300/r400 when tiling is enabled crtc_offset is set to the address of 5688 * the surface. the x/y offsets are handled by the X_Y tile reg for each crtc 5689 * Makes tiling MUCH easier. 5690 */ 5691 crtcxytile = x | (y << 16); 5692 Base &= ~0x7ff; 5693 } else { 5694 int byteshift = info->CurrentLayout.bitsPerPixel >> 4; 5695 /* crtc uses 256(bytes)x8 "half-tile" start addresses? */ 5696 int tile_addr = (((y >> 3) * info->CurrentLayout.displayWidth + x) >> (8 - byteshift)) << 11; 5697 Base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); 5698 crtcoffsetcntl = crtcoffsetcntl | (y % 16); 5699 } 5700 } 5701 else { 5702 int offset = y * info->CurrentLayout.displayWidth + x; 5703 switch (info->CurrentLayout.pixel_code) { 5704 case 15: 5705 case 16: offset *= 2; break; 5706 case 24: offset *= 3; break; 5707 case 32: offset *= 4; break; 5708 } 5709 Base += offset; 5710 } 5711 5712 Base &= ~7; /* 3 lower bits are always 0 */ 5713 5714#ifdef XF86DRI 5715 if (info->directRenderingInited) { 5716 /* note cannot use pScrn->pScreen since this is unitialized when called from 5717 RADEONScreenInit, and we need to call from there to get mergedfb + pageflip working */ 5718 /*** NOTE: r3/4xx will need sarea and drm pageflip updates to handle the xytile regs for 5719 *** pageflipping! 5720 ***/ 5721 pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]); 5722 /* can't get at sarea in a semi-sane way? */ 5723 pSAREA = (void *)((char*)pSAREAPriv - sizeof(XF86DRISAREARec)); 5724 5725 if (crtc2) { 5726 pSAREAPriv->crtc2_base = Base; 5727 } 5728 else { 5729 pSAREA->frame.x = (Base / info->CurrentLayout.pixel_bytes) 5730 % info->CurrentLayout.displayWidth; 5731 pSAREA->frame.y = (Base / info->CurrentLayout.pixel_bytes) 5732 / info->CurrentLayout.displayWidth; 5733 pSAREA->frame.width = pScrn->frameX1 - x + 1; 5734 pSAREA->frame.height = pScrn->frameY1 - y + 1; 5735 } 5736 5737 if (pSAREAPriv->pfCurrentPage == 1) { 5738 Base += info->dri->backOffset - info->dri->frontOffset; 5739 } 5740 } 5741#endif 5742 5743 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { 5744 OUTREG(xytilereg, crtcxytile); 5745 } else { 5746 OUTREG(regcntl, crtcoffsetcntl); 5747 } 5748 5749 OUTREG(reg, Base); 5750} 5751 5752void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags) 5753{ 5754 ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; 5755 RADEONInfoPtr info = RADEONPTR(pScrn); 5756 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 5757 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 5758 xf86OutputPtr output = config->output[config->compat_output]; 5759 xf86CrtcPtr crtc = output->crtc; 5760 5761 /* not handled */ 5762 if (IS_AVIVO_VARIANT) 5763 return; 5764 5765#ifdef XF86DRI 5766 if (info->cp->CPStarted && pScrn->pScreen) DRILock(pScrn->pScreen, 0); 5767#endif 5768 5769 if (info->accelOn) 5770 RADEON_SYNC(info, pScrn); 5771 5772 if (crtc && crtc->enabled) { 5773 if (crtc == pRADEONEnt->pCrtc[0]) 5774 RADEONDoAdjustFrame(pScrn, crtc->desiredX + x, crtc->desiredY + y, FALSE); 5775 else 5776 RADEONDoAdjustFrame(pScrn, crtc->desiredX + x, crtc->desiredY + y, TRUE); 5777 crtc->x = output->initial_x + x; 5778 crtc->y = output->initial_y + y; 5779 } 5780 5781 5782#ifdef XF86DRI 5783 if (info->cp->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen); 5784#endif 5785} 5786 5787/* Called when VT switching back to the X server. Reinitialize the 5788 * video mode. 5789 */ 5790Bool RADEONEnterVT(int scrnIndex, int flags) 5791{ 5792 ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; 5793 RADEONInfoPtr info = RADEONPTR(pScrn); 5794 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 5795 int i; 5796 5797 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5798 "RADEONEnterVT\n"); 5799 5800 if (!radeon_card_posted(pScrn)) { /* Softboot V_BIOS */ 5801 if (info->IsAtomBios) { 5802 rhdAtomASICInit(info->atomBIOS); 5803 } else { 5804 xf86Int10InfoPtr pInt; 5805 5806 pInt = xf86InitInt10 (info->pEnt->index); 5807 if (pInt) { 5808 pInt->num = 0xe6; 5809 xf86ExecX86int10 (pInt); 5810 xf86FreeInt10 (pInt); 5811 } else { 5812 RADEONGetBIOSInitTableOffsets(pScrn); 5813 RADEONPostCardFromBIOSTables(pScrn); 5814 } 5815 } 5816 } 5817 5818 /* Makes sure the engine is idle before doing anything */ 5819 RADEONWaitForIdleMMIO(pScrn); 5820 5821 RADEONPMEnterVT(pScrn); 5822 5823 for (i = 0; i < config->num_crtc; i++) 5824 radeon_crtc_modeset_ioctl(config->crtc[i], TRUE); 5825 5826 pScrn->vtSema = TRUE; 5827 5828 /* Clear the framebuffer */ 5829 memset(info->FB + pScrn->fbOffset, 0, 5830 pScrn->virtualY * pScrn->displayWidth * info->CurrentLayout.pixel_bytes); 5831 5832 if (!xf86SetDesiredModes(pScrn)) 5833 return FALSE; 5834 5835 if (info->ChipFamily < CHIP_FAMILY_R600) 5836 RADEONRestoreSurfaces(pScrn, info->ModeReg); 5837#ifdef XF86DRI 5838 if (info->directRenderingEnabled) { 5839 if (info->cardType == CARD_PCIE && 5840 info->dri->pKernelDRMVersion->version_minor >= 19 && 5841 info->FbSecureSize) { 5842#if X_BYTE_ORDER == X_BIG_ENDIAN 5843 unsigned char *RADEONMMIO = info->MMIO; 5844 unsigned int sctrl = INREG(RADEON_SURFACE_CNTL); 5845 5846 /* we need to backup the PCIE GART TABLE from fb memory */ 5847 OUTREG(RADEON_SURFACE_CNTL, 0); 5848#endif 5849 memcpy(info->FB + info->dri->pciGartOffset, info->dri->pciGartBackup, info->dri->pciGartSize); 5850#if X_BYTE_ORDER == X_BIG_ENDIAN 5851 OUTREG(RADEON_SURFACE_CNTL, sctrl); 5852#endif 5853 } 5854 5855 /* get the DRI back into shape after resume */ 5856 RADEONDRISetVBlankInterrupt (pScrn, TRUE); 5857 RADEONDRIResume(pScrn->pScreen); 5858 RADEONAdjustMemMapRegisters(pScrn, info->ModeReg); 5859 5860 } 5861#endif 5862 /* this will get XVideo going again, but only if XVideo was initialised 5863 during server startup (hence the info->adaptor if). */ 5864 if (info->adaptor) 5865 RADEONResetVideo(pScrn); 5866 5867 if (info->accelOn && (info->ChipFamily < CHIP_FAMILY_R600)) 5868 RADEONEngineRestore(pScrn); 5869 5870 if (info->accelOn && info->accel_state) 5871 info->accel_state->XInited3D = FALSE; 5872 5873#ifdef XF86DRI 5874 if (info->directRenderingEnabled) { 5875 if (info->ChipFamily >= CHIP_FAMILY_R600) 5876 R600LoadShaders(pScrn); 5877 RADEONCP_START(pScrn, info); 5878 DRIUnlock(pScrn->pScreen); 5879 } 5880#endif 5881 if (IS_R500_3D || IS_R300_3D) 5882 radeon_load_bicubic_texture(pScrn); 5883 5884 return TRUE; 5885} 5886 5887/* Called when VT switching away from the X server. Restore the 5888 * original text mode. 5889 */ 5890void RADEONLeaveVT(int scrnIndex, int flags) 5891{ 5892 ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; 5893 RADEONInfoPtr info = RADEONPTR(pScrn); 5894 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 5895 int i; 5896 5897 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5898 "RADEONLeaveVT\n"); 5899#ifdef XF86DRI 5900 if (RADEONPTR(pScrn)->directRenderingInited) { 5901 5902 RADEONDRISetVBlankInterrupt (pScrn, FALSE); 5903 DRILock(pScrn->pScreen, 0); 5904 RADEONCP_STOP(pScrn, info); 5905 5906 if (info->cardType == CARD_PCIE && 5907 info->dri->pKernelDRMVersion->version_minor >= 19 && 5908 info->FbSecureSize) { 5909#if X_BYTE_ORDER == X_BIG_ENDIAN 5910 unsigned char *RADEONMMIO = info->MMIO; 5911 unsigned int sctrl = INREG(RADEON_SURFACE_CNTL); 5912 5913 /* we need to backup the PCIE GART TABLE from fb memory */ 5914 OUTREG(RADEON_SURFACE_CNTL, 0); 5915#endif 5916 memcpy(info->dri->pciGartBackup, (info->FB + info->dri->pciGartOffset), info->dri->pciGartSize); 5917#if X_BYTE_ORDER == X_BIG_ENDIAN 5918 OUTREG(RADEON_SURFACE_CNTL, sctrl); 5919#endif 5920 } 5921 5922 /* Make sure 3D clients will re-upload textures to video RAM */ 5923 if (info->dri->textureSize) { 5924 drm_radeon_sarea_t *pSAREAPriv = 5925 (drm_radeon_sarea_t*)DRIGetSAREAPrivate(pScrn->pScreen); 5926 struct drm_tex_region *list = pSAREAPriv->tex_list[0]; 5927 int age = ++pSAREAPriv->tex_age[0]; 5928 5929 i = 0; 5930 5931 do { 5932 list[i].age = age; 5933 i = list[i].next; 5934 } while (i != 0); 5935 } 5936 } 5937#endif 5938 5939 5940 for (i = 0; i < config->num_crtc; i++) { 5941 xf86CrtcPtr crtc = config->crtc[i]; 5942 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 5943 5944 radeon_crtc->initialized = FALSE; 5945 5946#ifndef HAVE_FREE_SHADOW 5947 if (crtc->rotatedPixmap || crtc->rotatedData) { 5948 crtc->funcs->shadow_destroy(crtc, crtc->rotatedPixmap, 5949 crtc->rotatedData); 5950 crtc->rotatedPixmap = NULL; 5951 crtc->rotatedData = NULL; 5952 } 5953#endif 5954 } 5955 5956#ifdef HAVE_FREE_SHADOW 5957 xf86RotateFreeShadow(pScrn); 5958#endif 5959 5960 xf86_hide_cursors (pScrn); 5961 5962 RADEONPMLeaveVT(pScrn); 5963 5964 RADEONRestore(pScrn); 5965 5966 for (i = 0; i < config->num_crtc; i++) 5967 radeon_crtc_modeset_ioctl(config->crtc[i], FALSE); 5968 5969 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5970 "Ok, leaving now...\n"); 5971} 5972 5973/* Called at the end of each server generation. Restore the original 5974 * text mode, unmap video memory, and unwrap and call the saved 5975 * CloseScreen function. 5976 */ 5977static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) 5978{ 5979 ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; 5980 RADEONInfoPtr info = RADEONPTR(pScrn); 5981 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 5982 int i; 5983 5984 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5985 "RADEONCloseScreen\n"); 5986 5987 RADEONPMFini(pScrn); 5988 5989 /* Mark acceleration as stopped or we might try to access the engine at 5990 * wrong times, especially if we had DRI, after DRI has been stopped 5991 */ 5992 info->accelOn = FALSE; 5993 5994 for (i = 0; i < config->num_crtc; i++) { 5995 xf86CrtcPtr crtc = config->crtc[i]; 5996 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 5997 5998 radeon_crtc->initialized = FALSE; 5999 } 6000 6001#ifdef XF86DRI 6002#ifdef DAMAGE 6003 if (info->dri && info->dri->pDamage) { 6004 PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen); 6005 6006 DamageUnregister(&pPix->drawable, info->dri->pDamage); 6007 DamageDestroy(info->dri->pDamage); 6008 info->dri->pDamage = NULL; 6009 } 6010#endif 6011 6012 RADEONDRIStop(pScreen); 6013#endif 6014 6015#ifdef USE_XAA 6016 if(!info->useEXA && info->accel_state->RenderTex) { 6017 xf86FreeOffscreenLinear(info->accel_state->RenderTex); 6018 info->accel_state->RenderTex = NULL; 6019 } 6020#endif /* USE_XAA */ 6021 6022 if (pScrn->vtSema) { 6023 RADEONRestore(pScrn); 6024 } 6025 6026 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 6027 "Disposing accel...\n"); 6028#ifdef USE_EXA 6029 if (info->accel_state->exa) { 6030 exaDriverFini(pScreen); 6031 free(info->accel_state->exa); 6032 info->accel_state->exa = NULL; 6033 } 6034#endif /* USE_EXA */ 6035#ifdef USE_XAA 6036 if (!info->useEXA) { 6037 if (info->accel_state->accel) 6038 XAADestroyInfoRec(info->accel_state->accel); 6039 info->accel_state->accel = NULL; 6040 6041 if (info->accel_state->scratch_save) 6042 free(info->accel_state->scratch_save); 6043 info->accel_state->scratch_save = NULL; 6044 } 6045#endif /* USE_XAA */ 6046 6047 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 6048 "Disposing cursor info\n"); 6049 if (info->cursor) xf86DestroyCursorInfoRec(info->cursor); 6050 info->cursor = NULL; 6051 6052 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 6053 "Unmapping memory\n"); 6054 RADEONUnmapMem(pScrn); 6055 6056 pScrn->vtSema = FALSE; 6057 6058 xf86ClearPrimInitDone(info->pEnt->index); 6059 6060 pScreen->BlockHandler = info->BlockHandler; 6061 pScreen->CloseScreen = info->CloseScreen; 6062 return (*pScreen->CloseScreen)(scrnIndex, pScreen); 6063} 6064 6065void RADEONFreeScreen(int scrnIndex, int flags) 6066{ 6067 ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; 6068 RADEONInfoPtr info = RADEONPTR(pScrn); 6069 6070 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 6071 "RADEONFreeScreen\n"); 6072 6073 /* when server quits at PreInit, we don't need do this anymore*/ 6074 if (!info) return; 6075 6076#ifdef WITH_VGAHW 6077 if (info->VGAAccess && xf86LoaderCheckSymbol("vgaHWFreeHWRec")) 6078 vgaHWFreeHWRec(pScrn); 6079#endif 6080 RADEONFreeRec(pScrn); 6081} 6082