radeon_driver.c revision f1bc02b7
1/* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining 8 * a copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation on the rights to use, copy, modify, merge, 11 * publish, distribute, sublicense, and/or sell copies of the Software, 12 * and to permit persons to whom the Software is furnished to do so, 13 * subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 */ 28 29#ifdef HAVE_CONFIG_H 30#include "config.h" 31#endif 32 33/* 34 * Authors: 35 * Kevin E. Martin <martin@xfree86.org> 36 * Rickard E. Faith <faith@valinux.com> 37 * Alan Hourihane <alanh@fairlite.demon.co.uk> 38 * 39 * Credits: 40 * 41 * Thanks to Ani Joshi <ajoshi@shell.unixbox.com> for providing source 42 * code to his Radeon driver. Portions of this file are based on the 43 * initialization code for that driver. 44 * 45 * References: 46 * 47 * !!!! FIXME !!!! 48 * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical 49 * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April 50 * 1999. 51 * 52 * RAGE 128 Software Development Manual (Technical Reference Manual P/N 53 * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. 54 * 55 * This server does not yet support these XFree86 4.0 features: 56 * !!!! FIXME !!!! 57 * DDC1 & DDC2 58 * shadowfb 59 * overlay planes 60 * 61 * Modified by Marc Aurele La France (tsi@xfree86.org) for ATI driver merge. 62 * 63 * Mergedfb and pseudo xinerama support added by Alex Deucher (agd5f@yahoo.com) 64 * based on the sis driver by Thomas Winischhofer. 65 * 66 */ 67 68#include <string.h> 69#include <stdio.h> 70 71 /* Driver data structures */ 72#include "radeon.h" 73#include "radeon_reg.h" 74#include "radeon_macros.h" 75#include "radeon_probe.h" 76#include "radeon_version.h" 77#include "radeon_atombios.h" 78 79#ifdef XF86DRI 80#define _XF86DRI_SERVER_ 81#include "radeon_dri.h" 82#include "radeon_drm.h" 83#include "sarea.h" 84#endif 85 86#include "fb.h" 87 88 /* colormap initialization */ 89#include "micmap.h" 90#include "dixstruct.h" 91 92 /* X and server generic header files */ 93#include "xf86.h" 94#include "xf86_OSproc.h" 95#include "xf86RandR12.h" 96#if GET_ABI_MAJOR(ABI_VIDEODRV_VERSION) < 6 97#include "xf86RAC.h" 98#include "xf86Resources.h" 99#endif 100#include "xf86cmap.h" 101#include "vbe.h" 102 103#include "shadow.h" 104 /* vgaHW definitions */ 105#ifdef WITH_VGAHW 106#include "vgaHW.h" 107#endif 108 109#ifdef HAVE_XEXTPROTO_71 110#include <X11/extensions/dpmsconst.h> 111#else 112#define DPMS_SERVER 113#include <X11/extensions/dpms.h> 114#endif 115 116 117#include "atipciids.h" 118#include "radeon_chipset_gen.h" 119 120 121#include "radeon_chipinfo_gen.h" 122 123 /* Forward definitions for driver functions */ 124static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen); 125static Bool RADEONSaveScreen(ScreenPtr pScreen, int mode); 126static void RADEONSave(ScrnInfoPtr pScrn); 127 128static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 129 130static void 131RADEONSaveBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 132 133#ifdef XF86DRI 134static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save); 135#endif 136 137static const OptionInfoRec RADEONOptions[] = { 138 { OPTION_NOACCEL, "NoAccel", OPTV_BOOLEAN, {0}, FALSE }, 139 { OPTION_SW_CURSOR, "SWcursor", OPTV_BOOLEAN, {0}, FALSE }, 140 { OPTION_DAC_6BIT, "Dac6Bit", OPTV_BOOLEAN, {0}, FALSE }, 141 { OPTION_DAC_8BIT, "Dac8Bit", OPTV_BOOLEAN, {0}, TRUE }, 142#ifdef XF86DRI 143 { OPTION_BUS_TYPE, "BusType", OPTV_ANYSTR, {0}, FALSE }, 144 { OPTION_CP_PIO, "CPPIOMode", OPTV_BOOLEAN, {0}, FALSE }, 145 { OPTION_USEC_TIMEOUT, "CPusecTimeout", OPTV_INTEGER, {0}, FALSE }, 146 { OPTION_AGP_MODE, "AGPMode", OPTV_INTEGER, {0}, FALSE }, 147 { OPTION_AGP_FW, "AGPFastWrite", OPTV_BOOLEAN, {0}, FALSE }, 148 { OPTION_GART_SIZE_OLD, "AGPSize", OPTV_INTEGER, {0}, FALSE }, 149 { OPTION_GART_SIZE, "GARTSize", OPTV_INTEGER, {0}, FALSE }, 150 { OPTION_RING_SIZE, "RingSize", OPTV_INTEGER, {0}, FALSE }, 151 { OPTION_BUFFER_SIZE, "BufferSize", OPTV_INTEGER, {0}, FALSE }, 152 { OPTION_DEPTH_MOVE, "EnableDepthMoves", OPTV_BOOLEAN, {0}, FALSE }, 153 { OPTION_PAGE_FLIP, "EnablePageFlip", OPTV_BOOLEAN, {0}, FALSE }, 154 { OPTION_NO_BACKBUFFER, "NoBackBuffer", OPTV_BOOLEAN, {0}, FALSE }, 155 { OPTION_XV_DMA, "DMAForXv", OPTV_BOOLEAN, {0}, FALSE }, 156 { OPTION_FBTEX_PERCENT, "FBTexPercent", OPTV_INTEGER, {0}, FALSE }, 157 { OPTION_DEPTH_BITS, "DepthBits", OPTV_INTEGER, {0}, FALSE }, 158 { OPTION_PCIAPER_SIZE, "PCIAPERSize", OPTV_INTEGER, {0}, FALSE }, 159#ifdef USE_EXA 160 { OPTION_ACCEL_DFS, "AccelDFS", OPTV_BOOLEAN, {0}, FALSE }, 161#endif 162#endif 163 { OPTION_IGNORE_EDID, "IgnoreEDID", OPTV_BOOLEAN, {0}, FALSE }, 164 { OPTION_CUSTOM_EDID, "CustomEDID", OPTV_ANYSTR, {0}, FALSE }, 165 { OPTION_DISP_PRIORITY, "DisplayPriority", OPTV_ANYSTR, {0}, FALSE }, 166 { OPTION_PANEL_SIZE, "PanelSize", OPTV_ANYSTR, {0}, FALSE }, 167 { OPTION_MIN_DOTCLOCK, "ForceMinDotClock", OPTV_FREQ, {0}, FALSE }, 168 { OPTION_COLOR_TILING, "ColorTiling", OPTV_BOOLEAN, {0}, FALSE }, 169#ifdef XvExtension 170 { OPTION_VIDEO_KEY, "VideoKey", OPTV_INTEGER, {0}, FALSE }, 171 { OPTION_RAGE_THEATRE_CRYSTAL, "RageTheatreCrystal", OPTV_INTEGER, {0}, FALSE }, 172 { OPTION_RAGE_THEATRE_TUNER_PORT, "RageTheatreTunerPort", OPTV_INTEGER, {0}, FALSE }, 173 { OPTION_RAGE_THEATRE_COMPOSITE_PORT, "RageTheatreCompositePort", OPTV_INTEGER, {0}, FALSE }, 174 { OPTION_RAGE_THEATRE_SVIDEO_PORT, "RageTheatreSVideoPort", OPTV_INTEGER, {0}, FALSE }, 175 { OPTION_TUNER_TYPE, "TunerType", OPTV_INTEGER, {0}, FALSE }, 176 { OPTION_RAGE_THEATRE_MICROC_PATH, "RageTheatreMicrocPath", OPTV_STRING, {0}, FALSE }, 177 { OPTION_RAGE_THEATRE_MICROC_TYPE, "RageTheatreMicrocType", OPTV_STRING, {0}, FALSE }, 178 { OPTION_SCALER_WIDTH, "ScalerWidth", OPTV_INTEGER, {0}, FALSE }, 179#endif 180#ifdef RENDER 181 { OPTION_RENDER_ACCEL, "RenderAccel", OPTV_BOOLEAN, {0}, FALSE }, 182 { OPTION_SUBPIXEL_ORDER, "SubPixelOrder", OPTV_ANYSTR, {0}, FALSE }, 183#endif 184 { OPTION_SHOWCACHE, "ShowCache", OPTV_BOOLEAN, {0}, FALSE }, 185 { OPTION_CLOCK_GATING, "ClockGating", OPTV_BOOLEAN, {0}, FALSE }, 186 { OPTION_VGA_ACCESS, "VGAAccess", OPTV_BOOLEAN, {0}, TRUE }, 187 { OPTION_REVERSE_DDC, "ReverseDDC", OPTV_BOOLEAN, {0}, FALSE }, 188 { OPTION_LVDS_PROBE_PLL, "LVDSProbePLL", OPTV_BOOLEAN, {0}, FALSE }, 189 { OPTION_ACCELMETHOD, "AccelMethod", OPTV_STRING, {0}, FALSE }, 190 { OPTION_DRI, "DRI", OPTV_BOOLEAN, {0}, FALSE }, 191 { OPTION_CONNECTORTABLE, "ConnectorTable", OPTV_STRING, {0}, FALSE }, 192 { OPTION_DEFAULT_CONNECTOR_TABLE, "DefaultConnectorTable", OPTV_BOOLEAN, {0}, FALSE }, 193 { OPTION_DEFAULT_TMDS_PLL, "DefaultTMDSPLL", OPTV_BOOLEAN, {0}, FALSE }, 194#if defined(__powerpc__) 195 { OPTION_MAC_MODEL, "MacModel", OPTV_STRING, {0}, FALSE }, 196#endif 197 { OPTION_TVDAC_LOAD_DETECT, "TVDACLoadDetect", OPTV_BOOLEAN, {0}, FALSE }, 198 { OPTION_FORCE_TVOUT, "ForceTVOut", OPTV_BOOLEAN, {0}, FALSE }, 199 { OPTION_TVSTD, "TVStandard", OPTV_STRING, {0}, FALSE }, 200 { OPTION_IGNORE_LID_STATUS, "IgnoreLidStatus", OPTV_BOOLEAN, {0}, FALSE }, 201 { OPTION_DEFAULT_TVDAC_ADJ, "DefaultTVDACAdj", OPTV_BOOLEAN, {0}, FALSE }, 202 { OPTION_INT10, "Int10", OPTV_BOOLEAN, {0}, FALSE }, 203 { OPTION_EXA_VSYNC, "EXAVSync", OPTV_BOOLEAN, {0}, FALSE }, 204 { OPTION_ATOM_TVOUT, "ATOMTVOut", OPTV_BOOLEAN, {0}, FALSE }, 205 { OPTION_R4XX_ATOM, "R4xxATOM", OPTV_BOOLEAN, {0}, FALSE }, 206 { OPTION_FORCE_LOW_POWER, "ForceLowPowerMode", OPTV_BOOLEAN, {0}, FALSE }, 207 { OPTION_DYNAMIC_PM, "DynamicPM", OPTV_BOOLEAN, {0}, FALSE }, 208 { OPTION_NEW_PLL, "NewPLL", OPTV_BOOLEAN, {0}, FALSE }, 209 { OPTION_ZAPHOD_HEADS, "ZaphodHeads", OPTV_STRING, {0}, FALSE }, 210 { -1, NULL, OPTV_NONE, {0}, FALSE } 211}; 212 213const OptionInfoRec *RADEONOptionsWeak(void) { return RADEONOptions; } 214 215extern _X_EXPORT int gRADEONEntityIndex; 216 217static int getRADEONEntityIndex(void) 218{ 219 return gRADEONEntityIndex; 220} 221 222struct RADEONInt10Save { 223 uint32_t MEM_CNTL; 224 uint32_t MEMSIZE; 225 uint32_t MPP_TB_CONFIG; 226}; 227 228static Bool RADEONMapMMIO(ScrnInfoPtr pScrn); 229static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn); 230 231static void * 232radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode, 233 CARD32 *size, void *closure) 234{ 235 ScrnInfoPtr pScrn = xf86Screens[screen->myNum]; 236 RADEONInfoPtr info = RADEONPTR(pScrn); 237 int stride; 238 239 stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8; 240 *size = stride; 241 242 return ((uint8_t *)info->FB + row * stride + offset); 243} 244static Bool 245RADEONCreateScreenResources (ScreenPtr pScreen) 246{ 247 ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; 248 RADEONInfoPtr info = RADEONPTR(pScrn); 249 PixmapPtr pixmap; 250 251 pScreen->CreateScreenResources = info->CreateScreenResources; 252 if (!(*pScreen->CreateScreenResources)(pScreen)) 253 return FALSE; 254 pScreen->CreateScreenResources = RADEONCreateScreenResources; 255 256 if (info->r600_shadow_fb) { 257 pixmap = pScreen->GetScreenPixmap(pScreen); 258 259 if (!shadowAdd(pScreen, pixmap, shadowUpdatePackedWeak(), 260 radeonShadowWindow, 0, NULL)) 261 return FALSE; 262 } 263 return TRUE; 264} 265 266RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn) 267{ 268 DevUnion *pPriv; 269 RADEONInfoPtr info = RADEONPTR(pScrn); 270 pPriv = xf86GetEntityPrivate(info->pEnt->index, 271 getRADEONEntityIndex()); 272 return pPriv->ptr; 273} 274 275static void 276RADEONPreInt10Save(ScrnInfoPtr pScrn, void **pPtr) 277{ 278 RADEONInfoPtr info = RADEONPTR(pScrn); 279 unsigned char *RADEONMMIO = info->MMIO; 280 uint32_t CardTmp; 281 static struct RADEONInt10Save SaveStruct = { 0, 0, 0 }; 282 283 if (!IS_AVIVO_VARIANT) { 284 /* Save the values and zap MEM_CNTL */ 285 SaveStruct.MEM_CNTL = INREG(RADEON_MEM_CNTL); 286 SaveStruct.MEMSIZE = INREG(RADEON_CONFIG_MEMSIZE); 287 SaveStruct.MPP_TB_CONFIG = INREG(RADEON_MPP_TB_CONFIG); 288 289 /* 290 * Zap MEM_CNTL and set MPP_TB_CONFIG<31:24> to 4 291 */ 292 OUTREG(RADEON_MEM_CNTL, 0); 293 CardTmp = SaveStruct.MPP_TB_CONFIG & 0x00ffffffu; 294 CardTmp |= 0x04 << 24; 295 OUTREG(RADEON_MPP_TB_CONFIG, CardTmp); 296 } 297 298 *pPtr = (void *)&SaveStruct; 299} 300 301static void 302RADEONPostInt10Check(ScrnInfoPtr pScrn, void *ptr) 303{ 304 RADEONInfoPtr info = RADEONPTR(pScrn); 305 unsigned char *RADEONMMIO = info->MMIO; 306 struct RADEONInt10Save *pSave = ptr; 307 uint32_t CardTmp; 308 309 /* If we don't have a valid (non-zero) saved MEM_CNTL, get out now */ 310 if (!pSave || !pSave->MEM_CNTL) 311 return; 312 313 if (IS_AVIVO_VARIANT) 314 return; 315 316 /* 317 * If either MEM_CNTL is currently zero or inconistent (configured for 318 * two channels with the two channels configured differently), restore 319 * the saved registers. 320 */ 321 CardTmp = INREG(RADEON_MEM_CNTL); 322 if (!CardTmp || 323 ((CardTmp & 1) && 324 (((CardTmp >> 8) & 0xff) != ((CardTmp >> 24) & 0xff)))) { 325 /* Restore the saved registers */ 326 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 327 "Restoring MEM_CNTL (%08lx), setting to %08lx\n", 328 (unsigned long)CardTmp, (unsigned long)pSave->MEM_CNTL); 329 OUTREG(RADEON_MEM_CNTL, pSave->MEM_CNTL); 330 331 CardTmp = INREG(RADEON_CONFIG_MEMSIZE); 332 if (CardTmp != pSave->MEMSIZE) { 333 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 334 "Restoring CONFIG_MEMSIZE (%08lx), setting to %08lx\n", 335 (unsigned long)CardTmp, (unsigned long)pSave->MEMSIZE); 336 OUTREG(RADEON_CONFIG_MEMSIZE, pSave->MEMSIZE); 337 } 338 } 339 340 CardTmp = INREG(RADEON_MPP_TB_CONFIG); 341 if ((CardTmp & 0xff000000u) != (pSave->MPP_TB_CONFIG & 0xff000000u)) { 342 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 343 "Restoring MPP_TB_CONFIG<31:24> (%02lx), setting to %02lx\n", 344 (unsigned long)CardTmp >> 24, 345 (unsigned long)pSave->MPP_TB_CONFIG >> 24); 346 CardTmp &= 0x00ffffffu; 347 CardTmp |= (pSave->MPP_TB_CONFIG & 0xff000000u); 348 OUTREG(RADEON_MPP_TB_CONFIG, CardTmp); 349 } 350} 351 352/* Allocate our private RADEONInfoRec */ 353Bool RADEONGetRec(ScrnInfoPtr pScrn) 354{ 355 if (pScrn->driverPrivate) return TRUE; 356 357 pScrn->driverPrivate = xnfcalloc(sizeof(RADEONInfoRec), 1); 358 return TRUE; 359} 360 361/* Free our private RADEONInfoRec */ 362void RADEONFreeRec(ScrnInfoPtr pScrn) 363{ 364 RADEONInfoPtr info; 365 int i; 366 367 if (!pScrn || !pScrn->driverPrivate) return; 368 369 info = RADEONPTR(pScrn); 370 371 if (info->cp) { 372 xfree(info->cp); 373 info->cp = NULL; 374 } 375 376 if (info->dri) { 377 xfree(info->dri); 378 info->dri = NULL; 379 } 380 381 if (info->accel_state) { 382 xfree(info->accel_state); 383 info->accel_state = NULL; 384 } 385 386 for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) { 387 if (info->encoders[i]) { 388 if (info->encoders[i]->dev_priv) { 389 xfree(info->encoders[i]->dev_priv); 390 info->encoders[i]->dev_priv = NULL; 391 } 392 xfree(info->encoders[i]); 393 info->encoders[i]= NULL; 394 } 395 } 396 397 xfree(pScrn->driverPrivate); 398 pScrn->driverPrivate = NULL; 399} 400 401/* Memory map the MMIO region. Used during pre-init and by RADEONMapMem, 402 * below 403 */ 404static Bool RADEONMapMMIO(ScrnInfoPtr pScrn) 405{ 406 RADEONInfoPtr info = RADEONPTR(pScrn); 407 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 408 409 if (pRADEONEnt->MMIO) { 410 info->MMIO = pRADEONEnt->MMIO; 411 return TRUE; 412 } 413 414#ifndef XSERVER_LIBPCIACCESS 415 416 info->MMIO = xf86MapPciMem(pScrn->scrnIndex, 417 VIDMEM_MMIO | VIDMEM_READSIDEEFFECT, 418 info->PciTag, 419 info->MMIOAddr, 420 info->MMIOSize); 421 422 if (!info->MMIO) return FALSE; 423#else 424 425 void** result = (void**)&info->MMIO; 426 int err = pci_device_map_range(info->PciInfo, 427 info->MMIOAddr, 428 info->MMIOSize, 429 PCI_DEV_MAP_FLAG_WRITABLE, 430 result); 431 432 if (err) { 433 xf86DrvMsg (pScrn->scrnIndex, X_ERROR, 434 "Unable to map MMIO aperture. %s (%d)\n", 435 strerror (err), err); 436 return FALSE; 437 } 438 439#endif 440 441 pRADEONEnt->MMIO = info->MMIO; 442 return TRUE; 443} 444 445/* Unmap the MMIO region. Used during pre-init and by RADEONUnmapMem, 446 * below 447 */ 448static Bool RADEONUnmapMMIO(ScrnInfoPtr pScrn) 449{ 450 RADEONInfoPtr info = RADEONPTR(pScrn); 451 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 452 453 if (info->IsPrimary || info->IsSecondary) { 454 /* never unmap on zaphod */ 455 info->MMIO = NULL; 456 return TRUE; 457 } 458 459#ifndef XSERVER_LIBPCIACCESS 460 xf86UnMapVidMem(pScrn->scrnIndex, info->MMIO, info->MMIOSize); 461#else 462 pci_device_unmap_range(info->PciInfo, info->MMIO, info->MMIOSize); 463#endif 464 465 pRADEONEnt->MMIO = NULL; 466 info->MMIO = NULL; 467 return TRUE; 468} 469 470/* Memory map the frame buffer. Used by RADEONMapMem, below. */ 471static Bool RADEONMapFB(ScrnInfoPtr pScrn) 472{ 473#ifdef XSERVER_LIBPCIACCESS 474 int err; 475#endif 476 RADEONInfoPtr info = RADEONPTR(pScrn); 477 478 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 479 "Map: 0x%016llx, 0x%08lx\n", info->LinearAddr, info->FbMapSize); 480 481#ifndef XSERVER_LIBPCIACCESS 482 483 info->FB = xf86MapPciMem(pScrn->scrnIndex, 484 VIDMEM_FRAMEBUFFER, 485 info->PciTag, 486 info->LinearAddr, 487 info->FbMapSize); 488 489 if (!info->FB) return FALSE; 490 491#else 492 493 err = pci_device_map_range(info->PciInfo, 494 info->LinearAddr, 495 info->FbMapSize, 496 PCI_DEV_MAP_FLAG_WRITABLE | 497 PCI_DEV_MAP_FLAG_WRITE_COMBINE, 498 &info->FB); 499 500 if (err) { 501 xf86DrvMsg (pScrn->scrnIndex, X_ERROR, 502 "Unable to map FB aperture. %s (%d)\n", 503 strerror (err), err); 504 return FALSE; 505 } 506 507#endif 508 509 return TRUE; 510} 511 512/* Unmap the frame buffer. Used by RADEONUnmapMem, below. */ 513static Bool RADEONUnmapFB(ScrnInfoPtr pScrn) 514{ 515 RADEONInfoPtr info = RADEONPTR(pScrn); 516 517#ifndef XSERVER_LIBPCIACCESS 518 xf86UnMapVidMem(pScrn->scrnIndex, info->FB, info->FbMapSize); 519#else 520 pci_device_unmap_range(info->PciInfo, info->FB, info->FbMapSize); 521#endif 522 523 info->FB = NULL; 524 return TRUE; 525} 526 527/* Memory map the MMIO region and the frame buffer */ 528static Bool RADEONMapMem(ScrnInfoPtr pScrn) 529{ 530 if (!RADEONMapMMIO(pScrn)) return FALSE; 531 if (!RADEONMapFB(pScrn)) { 532 RADEONUnmapMMIO(pScrn); 533 return FALSE; 534 } 535 return TRUE; 536} 537 538/* Unmap the MMIO region and the frame buffer */ 539static Bool RADEONUnmapMem(ScrnInfoPtr pScrn) 540{ 541 if (!RADEONUnmapMMIO(pScrn) || !RADEONUnmapFB(pScrn)) return FALSE; 542 return TRUE; 543} 544 545void RADEONPllErrataAfterIndex(RADEONInfoPtr info) 546{ 547 unsigned char *RADEONMMIO = info->MMIO; 548 549 if (!(info->ChipErrata & CHIP_ERRATA_PLL_DUMMYREADS)) 550 return; 551 552 /* This workaround is necessary on rv200 and RS200 or PLL 553 * reads may return garbage (among others...) 554 */ 555 (void)INREG(RADEON_CLOCK_CNTL_DATA); 556 (void)INREG(RADEON_CRTC_GEN_CNTL); 557} 558 559void RADEONPllErrataAfterData(RADEONInfoPtr info) 560{ 561 unsigned char *RADEONMMIO = info->MMIO; 562 563 /* This workarounds is necessary on RV100, RS100 and RS200 chips 564 * or the chip could hang on a subsequent access 565 */ 566 if (info->ChipErrata & CHIP_ERRATA_PLL_DELAY) { 567 /* we can't deal with posted writes here ... */ 568 usleep(5000); 569 } 570 571 /* This function is required to workaround a hardware bug in some (all?) 572 * revisions of the R300. This workaround should be called after every 573 * CLOCK_CNTL_INDEX register access. If not, register reads afterward 574 * may not be correct. 575 */ 576 if (info->ChipErrata & CHIP_ERRATA_R300_CG) { 577 uint32_t save, tmp; 578 579 save = INREG(RADEON_CLOCK_CNTL_INDEX); 580 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 581 OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp); 582 tmp = INREG(RADEON_CLOCK_CNTL_DATA); 583 OUTREG(RADEON_CLOCK_CNTL_INDEX, save); 584 } 585} 586 587/* Read PLL register */ 588unsigned RADEONINPLL(ScrnInfoPtr pScrn, int addr) 589{ 590 RADEONInfoPtr info = RADEONPTR(pScrn); 591 unsigned char *RADEONMMIO = info->MMIO; 592 uint32_t data; 593 594 OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f); 595 RADEONPllErrataAfterIndex(info); 596 data = INREG(RADEON_CLOCK_CNTL_DATA); 597 RADEONPllErrataAfterData(info); 598 599 return data; 600} 601 602/* Write PLL information */ 603void RADEONOUTPLL(ScrnInfoPtr pScrn, int addr, uint32_t data) 604{ 605 RADEONInfoPtr info = RADEONPTR(pScrn); 606 unsigned char *RADEONMMIO = info->MMIO; 607 608 OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) | 609 RADEON_PLL_WR_EN)); 610 RADEONPllErrataAfterIndex(info); 611 OUTREG(RADEON_CLOCK_CNTL_DATA, data); 612 RADEONPllErrataAfterData(info); 613} 614 615/* Read MC register */ 616unsigned RADEONINMC(ScrnInfoPtr pScrn, int addr) 617{ 618 RADEONInfoPtr info = RADEONPTR(pScrn); 619 unsigned char *RADEONMMIO = info->MMIO; 620 uint32_t data; 621 622 if ((info->ChipFamily == CHIP_FAMILY_RS690) || 623 (info->ChipFamily == CHIP_FAMILY_RS740)) { 624 OUTREG(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); 625 data = INREG(RS690_MC_DATA); 626 } else if (info->ChipFamily == CHIP_FAMILY_RS600) { 627 OUTREG(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) | RS600_MC_IND_CITF_ARB0)); 628 data = INREG(RS600_MC_DATA); 629 } else if ((info->ChipFamily == CHIP_FAMILY_RS780) || 630 (info->ChipFamily == CHIP_FAMILY_RS880)) { 631 OUTREG(RS780_MC_INDEX, (addr & RS780_MC_INDEX_MASK)); 632 data = INREG(RS780_MC_DATA); 633 } else if (info->ChipFamily >= CHIP_FAMILY_R600) { 634 data = 0; 635 } else if (IS_AVIVO_VARIANT) { 636 OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000); 637 (void)INREG(AVIVO_MC_INDEX); 638 data = INREG(AVIVO_MC_DATA); 639 640 OUTREG(AVIVO_MC_INDEX, 0); 641 (void)INREG(AVIVO_MC_INDEX); 642 } else { 643 OUTREG(R300_MC_IND_INDEX, addr & 0x3f); 644 (void)INREG(R300_MC_IND_INDEX); 645 data = INREG(R300_MC_IND_DATA); 646 647 OUTREG(R300_MC_IND_INDEX, 0); 648 (void)INREG(R300_MC_IND_INDEX); 649 } 650 651 return data; 652} 653 654/* Write MC information */ 655void RADEONOUTMC(ScrnInfoPtr pScrn, int addr, uint32_t data) 656{ 657 RADEONInfoPtr info = RADEONPTR(pScrn); 658 unsigned char *RADEONMMIO = info->MMIO; 659 660 if ((info->ChipFamily == CHIP_FAMILY_RS690) || 661 (info->ChipFamily == CHIP_FAMILY_RS740)) { 662 OUTREG(RS690_MC_INDEX, ((addr & RS690_MC_INDEX_MASK) | 663 RS690_MC_INDEX_WR_EN)); 664 OUTREG(RS690_MC_DATA, data); 665 OUTREG(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); 666 } else if (info->ChipFamily == CHIP_FAMILY_RS600) { 667 OUTREG(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) | 668 RS600_MC_IND_CITF_ARB0 | 669 RS600_MC_IND_WR_EN)); 670 OUTREG(RS600_MC_DATA, data); 671 } else if ((info->ChipFamily == CHIP_FAMILY_RS780) || 672 (info->ChipFamily == CHIP_FAMILY_RS880)) { 673 OUTREG(RS780_MC_INDEX, ((addr & RS780_MC_INDEX_MASK) | 674 RS780_MC_INDEX_WR_EN)); 675 OUTREG(RS780_MC_DATA, data); 676 } else if (info->ChipFamily >= CHIP_FAMILY_R600) { 677 // do nothing 678 } else if (IS_AVIVO_VARIANT) { 679 OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0xff0000); 680 (void)INREG(AVIVO_MC_INDEX); 681 OUTREG(AVIVO_MC_DATA, data); 682 OUTREG(AVIVO_MC_INDEX, 0); 683 (void)INREG(AVIVO_MC_INDEX); 684 } else { 685 OUTREG(R300_MC_IND_INDEX, (((addr) & 0x3f) | 686 R300_MC_IND_WR_EN)); 687 (void)INREG(R300_MC_IND_INDEX); 688 OUTREG(R300_MC_IND_DATA, data); 689 OUTREG(R300_MC_IND_INDEX, 0); 690 (void)INREG(R300_MC_IND_INDEX); 691 } 692} 693 694/* Read PCIE register */ 695unsigned RADEONINPCIE(ScrnInfoPtr pScrn, int addr) 696{ 697 RADEONInfoPtr info = RADEONPTR(pScrn); 698 unsigned char *RADEONMMIO = info->MMIO; 699 CARD32 data; 700 701 OUTREG(RADEON_PCIE_INDEX, addr & 0xff); 702 data = INREG(RADEON_PCIE_DATA); 703 704 return data; 705} 706 707/* Write PCIE register */ 708void RADEONOUTPCIE(ScrnInfoPtr pScrn, int addr, uint32_t data) 709{ 710 RADEONInfoPtr info = RADEONPTR(pScrn); 711 unsigned char *RADEONMMIO = info->MMIO; 712 713 OUTREG(RADEON_PCIE_INDEX, ((addr) & 0xff)); 714 OUTREG(RADEON_PCIE_DATA, data); 715} 716 717/* Read PCIE PORT register */ 718unsigned R600INPCIE_PORT(ScrnInfoPtr pScrn, int addr) 719{ 720 RADEONInfoPtr info = RADEONPTR(pScrn); 721 unsigned char *RADEONMMIO = info->MMIO; 722 CARD32 data; 723 724 OUTREG(R600_PCIE_PORT_INDEX, addr & 0xff); 725 data = INREG(R600_PCIE_PORT_DATA); 726 727 return data; 728} 729 730/* Write PCIE PORT register */ 731void R600OUTPCIE_PORT(ScrnInfoPtr pScrn, int addr, uint32_t data) 732{ 733 RADEONInfoPtr info = RADEONPTR(pScrn); 734 unsigned char *RADEONMMIO = info->MMIO; 735 736 OUTREG(R600_PCIE_PORT_INDEX, ((addr) & 0xff)); 737 OUTREG(R600_PCIE_PORT_DATA, data); 738} 739 740static Bool radeon_get_mc_idle(ScrnInfoPtr pScrn) 741{ 742 RADEONInfoPtr info = RADEONPTR(pScrn); 743 unsigned char *RADEONMMIO = info->MMIO; 744 745 if (info->ChipFamily >= CHIP_FAMILY_CEDAR) { 746 if (INREG(R600_SRBM_STATUS) & 0x1f00) 747 return FALSE; 748 else 749 return TRUE; 750 } else if (info->ChipFamily >= CHIP_FAMILY_R600) { 751 if (INREG(R600_SRBM_STATUS) & 0x3f00) 752 return FALSE; 753 else 754 return TRUE; 755 } else if (info->ChipFamily == CHIP_FAMILY_RV515) { 756 if (INMC(pScrn, RV515_MC_STATUS) & RV515_MC_STATUS_IDLE) 757 return TRUE; 758 else 759 return FALSE; 760 } else if (info->ChipFamily == CHIP_FAMILY_RS600) { 761 if (INMC(pScrn, RS600_MC_STATUS) & RS600_MC_IDLE) 762 return TRUE; 763 else 764 return FALSE; 765 } else if ((info->ChipFamily == CHIP_FAMILY_RS690) || 766 (info->ChipFamily == CHIP_FAMILY_RS740)) { 767 if (INMC(pScrn, RS690_MC_STATUS) & RS690_MC_STATUS_IDLE) 768 return TRUE; 769 else 770 return FALSE; 771 } else if (info->ChipFamily >= CHIP_FAMILY_R520) { 772 if (INMC(pScrn, R520_MC_STATUS) & R520_MC_STATUS_IDLE) 773 return TRUE; 774 else 775 return FALSE; 776 } else if ((info->ChipFamily == CHIP_FAMILY_RS400) || 777 (info->ChipFamily == CHIP_FAMILY_RS480)) { 778 if (INREG(RADEON_MC_STATUS) & RADEON_MC_IDLE) 779 return TRUE; 780 else 781 return FALSE; 782 } else if (IS_R300_VARIANT) { 783 if (INREG(RADEON_MC_STATUS) & R300_MC_IDLE) 784 return TRUE; 785 else 786 return FALSE; 787 } else { 788 if (INREG(RADEON_MC_STATUS) & RADEON_MC_IDLE) 789 return TRUE; 790 else 791 return FALSE; 792 } 793} 794 795#define LOC_FB 0x1 796#define LOC_AGP 0x2 797static void radeon_write_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, uint32_t fb_loc, uint32_t agp_loc, uint32_t agp_loc_hi) 798{ 799 RADEONInfoPtr info = RADEONPTR(pScrn); 800 unsigned char *RADEONMMIO = info->MMIO; 801 802 /* evergreen is same as r7xx */ 803 if (info->ChipFamily >= CHIP_FAMILY_RV770) { 804 if (mask & LOC_FB) 805 OUTREG(R700_MC_VM_FB_LOCATION, fb_loc); 806 if (mask & LOC_AGP) { 807 OUTREG(R700_MC_VM_AGP_BOT, agp_loc); 808 OUTREG(R700_MC_VM_AGP_TOP, agp_loc_hi); 809 } 810 } else if (info->ChipFamily >= CHIP_FAMILY_R600) { 811 if (mask & LOC_FB) 812 OUTREG(R600_MC_VM_FB_LOCATION, fb_loc); 813 if (mask & LOC_AGP) { 814 OUTREG(R600_MC_VM_AGP_BOT, agp_loc); 815 OUTREG(R600_MC_VM_AGP_TOP, agp_loc_hi); 816 } 817 } else if (info->ChipFamily == CHIP_FAMILY_RV515) { 818 if (mask & LOC_FB) 819 OUTMC(pScrn, RV515_MC_FB_LOCATION, fb_loc); 820 if (mask & LOC_AGP) 821 OUTMC(pScrn, RV515_MC_AGP_LOCATION, agp_loc); 822 (void)INMC(pScrn, RV515_MC_AGP_LOCATION); 823 } else if (info->ChipFamily == CHIP_FAMILY_RS600) { 824 if (mask & LOC_FB) 825 OUTMC(pScrn, RS600_MC_FB_LOCATION, fb_loc); 826 if (mask & LOC_AGP) 827 OUTMC(pScrn, RS600_MC_AGP_LOCATION, agp_loc); 828 } else if ((info->ChipFamily == CHIP_FAMILY_RS690) || 829 (info->ChipFamily == CHIP_FAMILY_RS740)) { 830 if (mask & LOC_FB) 831 OUTMC(pScrn, RS690_MC_FB_LOCATION, fb_loc); 832 if (mask & LOC_AGP) 833 OUTMC(pScrn, RS690_MC_AGP_LOCATION, agp_loc); 834 } else if (info->ChipFamily >= CHIP_FAMILY_R520) { 835 if (mask & LOC_FB) 836 OUTMC(pScrn, R520_MC_FB_LOCATION, fb_loc); 837 if (mask & LOC_AGP) 838 OUTMC(pScrn, R520_MC_AGP_LOCATION, agp_loc); 839 (void)INMC(pScrn, R520_MC_FB_LOCATION); 840 } else { 841 if (mask & LOC_FB) 842 OUTREG(RADEON_MC_FB_LOCATION, fb_loc); 843 if (mask & LOC_AGP) 844 OUTREG(RADEON_MC_AGP_LOCATION, agp_loc); 845 } 846} 847 848static void radeon_read_mc_fb_agp_location(ScrnInfoPtr pScrn, int mask, uint32_t *fb_loc, uint32_t *agp_loc, uint32_t *agp_loc_hi) 849{ 850 RADEONInfoPtr info = RADEONPTR(pScrn); 851 unsigned char *RADEONMMIO = info->MMIO; 852 853 /* evergreen is same as r7xx */ 854 if (info->ChipFamily >= CHIP_FAMILY_RV770) { 855 if (mask & LOC_FB) 856 *fb_loc = INREG(R700_MC_VM_FB_LOCATION); 857 if (mask & LOC_AGP) { 858 *agp_loc = INREG(R700_MC_VM_AGP_BOT); 859 *agp_loc_hi = INREG(R700_MC_VM_AGP_TOP); 860 } 861 } else if (info->ChipFamily >= CHIP_FAMILY_R600) { 862 if (mask & LOC_FB) 863 *fb_loc = INREG(R600_MC_VM_FB_LOCATION); 864 if (mask & LOC_AGP) { 865 *agp_loc = INREG(R600_MC_VM_AGP_BOT); 866 *agp_loc_hi = INREG(R600_MC_VM_AGP_TOP); 867 } 868 } else if (info->ChipFamily == CHIP_FAMILY_RV515) { 869 if (mask & LOC_FB) 870 *fb_loc = INMC(pScrn, RV515_MC_FB_LOCATION); 871 if (mask & LOC_AGP) { 872 *agp_loc = INMC(pScrn, RV515_MC_AGP_LOCATION); 873 *agp_loc_hi = 0; 874 } 875 } else if (info->ChipFamily == CHIP_FAMILY_RS600) { 876 if (mask & LOC_FB) 877 *fb_loc = INMC(pScrn, RS600_MC_FB_LOCATION); 878 if (mask & LOC_AGP) { 879 *agp_loc = INMC(pScrn, RS600_MC_AGP_LOCATION); 880 *agp_loc_hi = 0; 881 } 882 } else if ((info->ChipFamily == CHIP_FAMILY_RS690) || 883 (info->ChipFamily == CHIP_FAMILY_RS740)) { 884 if (mask & LOC_FB) 885 *fb_loc = INMC(pScrn, RS690_MC_FB_LOCATION); 886 if (mask & LOC_AGP) { 887 *agp_loc = INMC(pScrn, RS690_MC_AGP_LOCATION); 888 *agp_loc_hi = 0; 889 } 890 } else if (info->ChipFamily >= CHIP_FAMILY_R520) { 891 if (mask & LOC_FB) 892 *fb_loc = INMC(pScrn, R520_MC_FB_LOCATION); 893 if (mask & LOC_AGP) { 894 *agp_loc = INMC(pScrn, R520_MC_AGP_LOCATION); 895 *agp_loc_hi = 0; 896 } 897 } else { 898 if (mask & LOC_FB) 899 *fb_loc = INREG(RADEON_MC_FB_LOCATION); 900 if (mask & LOC_AGP) 901 *agp_loc = INREG(RADEON_MC_AGP_LOCATION); 902 } 903} 904 905#if 0 906/* Read PAL information (only used for debugging) */ 907static int RADEONINPAL(int idx) 908{ 909 RADEONInfoPtr info = RADEONPTR(pScrn); 910 unsigned char *RADEONMMIO = info->MMIO; 911 912 OUTREG(RADEON_PALETTE_INDEX, idx << 16); 913 return INREG(RADEON_PALETTE_DATA); 914} 915#endif 916 917/* Wait for vertical sync on primary CRTC */ 918void RADEONWaitForVerticalSync(ScrnInfoPtr pScrn) 919{ 920 RADEONInfoPtr info = RADEONPTR(pScrn); 921 unsigned char *RADEONMMIO = info->MMIO; 922 uint32_t crtc_gen_cntl; 923 struct timeval timeout; 924 925 crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); 926 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) || 927 !(crtc_gen_cntl & RADEON_CRTC_EN)) 928 return; 929 930 /* Clear the CRTC_VBLANK_SAVE bit */ 931 OUTREG(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR); 932 933 /* Wait for it to go back up */ 934 radeon_init_timeout(&timeout, RADEON_VSYNC_TIMEOUT); 935 while (!(INREG(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_SAVE) && 936 !radeon_timedout(&timeout)) 937 usleep(100); 938} 939 940/* Wait for vertical sync on secondary CRTC */ 941void RADEONWaitForVerticalSync2(ScrnInfoPtr pScrn) 942{ 943 RADEONInfoPtr info = RADEONPTR(pScrn); 944 unsigned char *RADEONMMIO = info->MMIO; 945 uint32_t crtc2_gen_cntl; 946 struct timeval timeout; 947 948 crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); 949 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) || 950 !(crtc2_gen_cntl & RADEON_CRTC2_EN)) 951 return; 952 953 /* Clear the CRTC2_VBLANK_SAVE bit */ 954 OUTREG(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR); 955 956 /* Wait for it to go back up */ 957 radeon_init_timeout(&timeout, RADEON_VSYNC_TIMEOUT); 958 while (!(INREG(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_SAVE) && 959 !radeon_timedout(&timeout)) 960 usleep(100); 961} 962 963 964/* Compute log base 2 of val */ 965int RADEONMinBits(int val) 966{ 967 int bits; 968 969 if (!val) return 1; 970 for (bits = 0; val; val >>= 1, ++bits); 971 return bits; 972} 973 974/* Compute n/d with rounding */ 975static int RADEONDiv(int n, int d) 976{ 977 return (n + (d / 2)) / d; 978} 979 980static Bool RADEONProbePLLParameters(ScrnInfoPtr pScrn) 981{ 982 RADEONInfoPtr info = RADEONPTR(pScrn); 983 RADEONPLLPtr pll = &info->pll; 984 unsigned char *RADEONMMIO = info->MMIO; 985 unsigned char ppll_div_sel; 986 unsigned mpll_fb_div, spll_fb_div, M; 987 unsigned xclk, tmp, ref_div; 988 int hTotal, vTotal, num, denom, m, n; 989 float hz, prev_xtal, vclk, xtal, mpll, spll; 990 long total_usecs; 991 struct timeval start, stop, to1, to2; 992 unsigned int f1, f2, f3; 993 int tries = 0; 994 995 prev_xtal = 0; 996 again: 997 xtal = 0; 998 if (++tries > 10) 999 goto failed; 1000 1001 gettimeofday(&to1, NULL); 1002 f1 = INREG(RADEON_CRTC_CRNT_FRAME); 1003 for (;;) { 1004 f2 = INREG(RADEON_CRTC_CRNT_FRAME); 1005 if (f1 != f2) 1006 break; 1007 gettimeofday(&to2, NULL); 1008 if ((to2.tv_sec - to1.tv_sec) > 1) { 1009 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Clock not counting...\n"); 1010 goto failed; 1011 } 1012 } 1013 gettimeofday(&start, NULL); 1014 for(;;) { 1015 f3 = INREG(RADEON_CRTC_CRNT_FRAME); 1016 if (f3 != f2) 1017 break; 1018 gettimeofday(&to2, NULL); 1019 if ((to2.tv_sec - start.tv_sec) > 1) 1020 goto failed; 1021 } 1022 gettimeofday(&stop, NULL); 1023 1024 if ((stop.tv_sec - start.tv_sec) != 0) 1025 goto again; 1026 total_usecs = abs(stop.tv_usec - start.tv_usec); 1027 if (total_usecs == 0) 1028 goto again; 1029 hz = 1000000.0/(float)total_usecs; 1030 1031 hTotal = ((INREG(RADEON_CRTC_H_TOTAL_DISP) & 0x3ff) + 1) * 8; 1032 vTotal = ((INREG(RADEON_CRTC_V_TOTAL_DISP) & 0xfff) + 1); 1033 vclk = (float)(hTotal * (float)(vTotal * hz)); 1034 1035 switch((INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x30000) >> 16) { 1036 case 0: 1037 default: 1038 num = 1; 1039 denom = 1; 1040 break; 1041 case 1: 1042 n = ((INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) >> 16) & 0xff); 1043 m = (INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) & 0xff); 1044 num = 2*n; 1045 denom = 2*m; 1046 break; 1047 case 2: 1048 n = ((INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) >> 8) & 0xff); 1049 m = (INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV) & 0xff); 1050 num = 2*n; 1051 denom = 2*m; 1052 break; 1053 } 1054 1055 ppll_div_sel = INREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; 1056 RADEONPllErrataAfterIndex(info); 1057 1058 n = (INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel) & 0x7ff); 1059 m = (INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x3ff); 1060 1061 num *= n; 1062 denom *= m; 1063 1064 switch ((INPLL(pScrn, RADEON_PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) { 1065 case 1: 1066 denom *= 2; 1067 break; 1068 case 2: 1069 denom *= 4; 1070 break; 1071 case 3: 1072 denom *= 8; 1073 break; 1074 case 4: 1075 denom *= 3; 1076 break; 1077 case 6: 1078 denom *= 6; 1079 break; 1080 case 7: 1081 denom *= 12; 1082 break; 1083 } 1084 1085 xtal = (int)(vclk *(float)denom/(float)num); 1086 1087 if ((xtal > 26900000) && (xtal < 27100000)) 1088 xtal = 2700; 1089 else if ((xtal > 14200000) && (xtal < 14400000)) 1090 xtal = 1432; 1091 else if ((xtal > 29400000) && (xtal < 29600000)) 1092 xtal = 2950; 1093 else 1094 goto again; 1095 failed: 1096 if (xtal == 0) { 1097 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Failed to probe xtal value ! " 1098 "Using default 27Mhz\n"); 1099 xtal = 2700; 1100 } else { 1101 if (prev_xtal == 0) { 1102 prev_xtal = xtal; 1103 tries = 0; 1104 goto again; 1105 } else if (prev_xtal != xtal) { 1106 prev_xtal = 0; 1107 goto again; 1108 } 1109 } 1110 1111 tmp = INPLL(pScrn, RADEON_X_MPLL_REF_FB_DIV); 1112 ref_div = INPLL(pScrn, RADEON_PPLL_REF_DIV) & 0x3ff; 1113 1114 /* Some sanity check based on the BIOS code .... */ 1115 if (ref_div < 2) { 1116 uint32_t tmp; 1117 tmp = INPLL(pScrn, RADEON_PPLL_REF_DIV); 1118 if (IS_R300_VARIANT 1119 || (info->ChipFamily == CHIP_FAMILY_RS300) 1120 || (info->ChipFamily == CHIP_FAMILY_RS400) 1121 || (info->ChipFamily == CHIP_FAMILY_RS480)) 1122 ref_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> 1123 R300_PPLL_REF_DIV_ACC_SHIFT; 1124 else 1125 ref_div = tmp & RADEON_PPLL_REF_DIV_MASK; 1126 if (ref_div < 2) 1127 ref_div = 12; 1128 } 1129 1130 /* Calculate "base" xclk straight from MPLL, though that isn't 1131 * really useful (hopefully). This isn't called XCLK anymore on 1132 * radeon's... 1133 */ 1134 mpll_fb_div = (tmp & 0xff00) >> 8; 1135 spll_fb_div = (tmp & 0xff0000) >> 16; 1136 M = (tmp & 0xff); 1137 xclk = RADEONDiv((2 * mpll_fb_div * xtal), (M)); 1138 1139 /* 1140 * Calculate MCLK based on MCLK-A 1141 */ 1142 mpll = (2.0 * (float)mpll_fb_div * (xtal / 100.0)) / (float)M; 1143 spll = (2.0 * (float)spll_fb_div * (xtal / 100.0)) / (float)M; 1144 1145 tmp = INPLL(pScrn, RADEON_MCLK_CNTL) & 0x7; 1146 switch(tmp) { 1147 case 1: info->mclk = mpll; break; 1148 case 2: info->mclk = mpll / 2.0; break; 1149 case 3: info->mclk = mpll / 4.0; break; 1150 case 4: info->mclk = mpll / 8.0; break; 1151 case 7: info->mclk = spll; break; 1152 default: 1153 info->mclk = 200.00; 1154 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unsupported MCLKA source" 1155 " setting %d, can't probe MCLK value !\n", tmp); 1156 } 1157 1158 /* 1159 * Calculate SCLK 1160 */ 1161 tmp = INPLL(pScrn, RADEON_SCLK_CNTL) & 0x7; 1162 switch(tmp) { 1163 case 1: info->sclk = spll; break; 1164 case 2: info->sclk = spll / 2.0; break; 1165 case 3: info->sclk = spll / 4.0; break; 1166 case 4: info->sclk = spll / 8.0; break; 1167 case 7: info->sclk = mpll; break; 1168 default: 1169 info->sclk = 200.00; 1170 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Unsupported SCLK source" 1171 " setting %d, can't probe SCLK value !\n", tmp); 1172 } 1173 1174 /* we're done, hopefully these are sane values */ 1175 pll->reference_div = ref_div; 1176 pll->xclk = xclk; 1177 pll->reference_freq = xtal; 1178 1179 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Probed PLL values: xtal: %f Mhz, " 1180 "sclk: %f Mhz, mclk: %f Mhz\n", xtal/100.0, info->sclk, info->mclk); 1181 1182 return TRUE; 1183} 1184 1185static void RADEONGetClockInfo(ScrnInfoPtr pScrn) 1186{ 1187 RADEONInfoPtr info = RADEONPTR (pScrn); 1188 RADEONPLLPtr pll = &info->pll; 1189 double min_dotclock; 1190 1191 if (RADEONGetClockInfoFromBIOS(pScrn)) { 1192 if (pll->reference_div < 2) { 1193 /* retrive it from register setting for fitting into current PLL algorithm. 1194 We'll probably need a new routine to calculate the best ref_div from BIOS 1195 provided min_input_pll and max_input_pll 1196 */ 1197 if (!IS_AVIVO_VARIANT) { 1198 uint32_t tmp; 1199 tmp = INPLL(pScrn, RADEON_PPLL_REF_DIV); 1200 if (IS_R300_VARIANT || 1201 (info->ChipFamily == CHIP_FAMILY_RS300) || 1202 (info->ChipFamily == CHIP_FAMILY_RS400) || 1203 (info->ChipFamily == CHIP_FAMILY_RS480)) { 1204 pll->reference_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT; 1205 } else { 1206 pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK; 1207 } 1208 } 1209 if (pll->reference_div < 2) pll->reference_div = 12; 1210 } 1211 } else { 1212 xf86DrvMsg (pScrn->scrnIndex, X_WARNING, 1213 "Video BIOS not detected, using default clock settings!\n"); 1214 1215 /* Default min/max PLL values */ 1216 if (info->ChipFamily == CHIP_FAMILY_R420 || info->ChipFamily == CHIP_FAMILY_RV410) { 1217 pll->pll_in_min = 100; 1218 pll->pll_in_max = 1350; 1219 pll->pll_out_min = 20000; 1220 pll->pll_out_max = 50000; 1221 } else { 1222 pll->pll_in_min = 40; 1223 pll->pll_in_max = 500; 1224 pll->pll_out_min = 12500; 1225 pll->pll_out_max = 35000; 1226 } 1227 1228 if (!RADEONProbePLLParameters(pScrn)) { 1229 if (info->IsIGP) 1230 pll->reference_freq = 1432; 1231 else 1232 pll->reference_freq = 2700; 1233 1234 pll->reference_div = 12; 1235 pll->xclk = 10300; 1236 1237 info->sclk = 200.00; 1238 info->mclk = 200.00; 1239 } 1240 } 1241 1242 /* card limits for computing PLLs */ 1243 if (IS_AVIVO_VARIANT) { 1244 pll->min_post_div = 2; 1245 pll->max_post_div = 0x7f; 1246 pll->min_frac_feedback_div = 0; 1247 pll->max_frac_feedback_div = 9; 1248 } else { 1249 pll->min_post_div = 1; 1250 pll->max_post_div = 12; //16 on crtc0 1251 pll->min_frac_feedback_div = 0; 1252 pll->max_frac_feedback_div = 0; 1253 } 1254 pll->min_ref_div = 2; 1255 pll->max_ref_div = 0x3ff; 1256 pll->min_feedback_div = 4; 1257 pll->max_feedback_div = 0x7ff; 1258 pll->best_vco = 0; 1259 1260 xf86DrvMsg (pScrn->scrnIndex, X_INFO, 1261 "PLL parameters: rf=%u rd=%u min=%u max=%u; xclk=%u\n", 1262 pll->reference_freq, 1263 pll->reference_div, 1264 (unsigned)pll->pll_out_min, (unsigned)pll->pll_out_max, 1265 pll->xclk); 1266 1267 /* (Some?) Radeon BIOSes seem too lie about their minimum dot 1268 * clocks. Allow users to override the detected minimum dot clock 1269 * value (e.g., and allow it to be suitable for TV sets). 1270 */ 1271 if (xf86GetOptValFreq(info->Options, OPTION_MIN_DOTCLOCK, 1272 OPTUNITS_MHZ, &min_dotclock)) { 1273 if (min_dotclock < 12 || min_dotclock*100 >= pll->pll_out_max) { 1274 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1275 "Illegal minimum dotclock specified %.2f MHz " 1276 "(option ignored)\n", 1277 min_dotclock); 1278 } else { 1279 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1280 "Forced minimum dotclock to %.2f MHz " 1281 "(instead of detected %.2f MHz)\n", 1282 min_dotclock, ((double)pll->pll_out_min/1000)); 1283 pll->pll_out_min = min_dotclock * 1000; 1284 } 1285 } 1286} 1287 1288 1289 1290/* This is called by RADEONPreInit to set up the default visual */ 1291Bool RADEONPreInitVisual(ScrnInfoPtr pScrn) 1292{ 1293 RADEONInfoPtr info = RADEONPTR(pScrn); 1294 1295 if (!xf86SetDepthBpp(pScrn, 0, 0, 0, Support32bppFb)) 1296 return FALSE; 1297 1298 switch (pScrn->depth) { 1299 case 8: 1300 case 15: 1301 case 16: 1302 case 24: 1303 break; 1304 1305 default: 1306 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1307 "Given depth (%d) is not supported by %s driver\n", 1308 pScrn->depth, RADEON_DRIVER_NAME); 1309 return FALSE; 1310 } 1311 1312 xf86PrintDepthBpp(pScrn); 1313 1314 info->pix24bpp = xf86GetBppFromDepth(pScrn, 1315 pScrn->depth); 1316 info->CurrentLayout.bitsPerPixel = pScrn->bitsPerPixel; 1317 info->CurrentLayout.depth = pScrn->depth; 1318 info->CurrentLayout.pixel_bytes = pScrn->bitsPerPixel / 8; 1319 info->CurrentLayout.pixel_code = (pScrn->bitsPerPixel != 16 1320 ? pScrn->bitsPerPixel 1321 : pScrn->depth); 1322 1323 if (info->pix24bpp == 24) { 1324 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1325 "Radeon does NOT support 24bpp\n"); 1326 return FALSE; 1327 } 1328 1329 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1330 "Pixel depth = %d bits stored in %d byte%s (%d bpp pixmaps)\n", 1331 pScrn->depth, 1332 info->CurrentLayout.pixel_bytes, 1333 info->CurrentLayout.pixel_bytes > 1 ? "s" : "", 1334 info->pix24bpp); 1335 1336 if (!xf86SetDefaultVisual(pScrn, -1)) return FALSE; 1337 1338 if (pScrn->depth > 8 && pScrn->defaultVisual != TrueColor) { 1339 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1340 "Default visual (%s) is not supported at depth %d\n", 1341 xf86GetVisualName(pScrn->defaultVisual), pScrn->depth); 1342 return FALSE; 1343 } 1344 return TRUE; 1345} 1346 1347/* This is called by RADEONPreInit to handle all color weight issues */ 1348Bool RADEONPreInitWeight(ScrnInfoPtr pScrn) 1349{ 1350 RADEONInfoPtr info = RADEONPTR(pScrn); 1351 1352 /* Save flag for 6 bit DAC to use for 1353 setting CRTC registers. Otherwise use 1354 an 8 bit DAC, even if xf86SetWeight sets 1355 pScrn->rgbBits to some value other than 1356 8. */ 1357 info->dac6bits = FALSE; 1358 1359 if (pScrn->depth > 8) { 1360 rgb defaultWeight = { 0, 0, 0 }; 1361 1362 if (!xf86SetWeight(pScrn, defaultWeight, defaultWeight)) return FALSE; 1363 } else { 1364 pScrn->rgbBits = 8; 1365 if (xf86ReturnOptValBool(info->Options, OPTION_DAC_6BIT, FALSE)) { 1366 pScrn->rgbBits = 6; 1367 info->dac6bits = TRUE; 1368 } 1369 } 1370 1371 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1372 "Using %d bits per RGB (%d bit DAC)\n", 1373 pScrn->rgbBits, info->dac6bits ? 6 : 8); 1374 1375 return TRUE; 1376} 1377 1378void RADEONInitMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, 1379 RADEONInfoPtr info) 1380{ 1381 save->mc_fb_location = info->mc_fb_location; 1382 save->mc_agp_location = info->mc_agp_location; 1383 1384 if (IS_AVIVO_VARIANT) { 1385 save->mc_agp_location_hi = info->mc_agp_location_hi; 1386 } else { 1387 save->display_base_addr = info->fbLocation; 1388 save->display2_base_addr = info->fbLocation; 1389 save->ov0_base_addr = info->fbLocation; 1390 } 1391} 1392 1393static void RADEONInitMemoryMap(ScrnInfoPtr pScrn) 1394{ 1395 RADEONInfoPtr info = RADEONPTR(pScrn); 1396 unsigned char *RADEONMMIO = info->MMIO; 1397 uint64_t mem_size; 1398 uint64_t aper_size; 1399 1400 radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &info->mc_fb_location, 1401 &info->mc_agp_location, &info->mc_agp_location_hi); 1402 1403 /* We shouldn't use info->videoRam here which might have been clipped 1404 * but the real video RAM instead 1405 */ 1406 if (info->ChipFamily >= CHIP_FAMILY_CEDAR) { 1407 /* size in MB on evergreen */ 1408 /* XXX watch for overflow!!! */ 1409 mem_size = INREG(R600_CONFIG_MEMSIZE) * 1024 * 1024; 1410 aper_size = INREG(R600_CONFIG_APER_SIZE) * 1024 * 1024; 1411 } else if (info->ChipFamily >= CHIP_FAMILY_R600) { 1412 mem_size = INREG(R600_CONFIG_MEMSIZE); 1413 aper_size = INREG(R600_CONFIG_APER_SIZE); 1414 } else { 1415 mem_size = INREG(RADEON_CONFIG_MEMSIZE); 1416 aper_size = INREG(RADEON_CONFIG_APER_SIZE); 1417 } 1418 1419 if (mem_size == 0) 1420 mem_size = 0x800000; 1421 1422 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 1423 Novell bug 204882 + along with lots of ubuntu ones */ 1424 if (aper_size > mem_size) 1425 mem_size = aper_size; 1426 1427 /* don't map the whole FB in the internal address space. 1428 * we don't currently use fb space larger than the aperture 1429 * size and on cards with more than 512 MB of vram, this can overflow 1430 * the internal top of gart calculation on some systems. 1431 * Limit it to cards with more than 512 MB as this causes problems 1432 * on some other cards due to the way the ddx and drm set up the 1433 * internal memory map. 1434 * See fdo bug 24301. 1435 */ 1436 if (mem_size > 0x20000000) 1437 mem_size = aper_size; 1438 1439#ifdef XF86DRI 1440 /* Apply memory map limitation if using an old DRI */ 1441 if (info->directRenderingEnabled && !info->dri->newMemoryMap) { 1442 if (aper_size < mem_size) 1443 mem_size = aper_size; 1444 } 1445#endif 1446 1447 if ((info->ChipFamily != CHIP_FAMILY_RS600) && 1448 (info->ChipFamily != CHIP_FAMILY_RS690) && 1449 (info->ChipFamily != CHIP_FAMILY_RS740) && 1450 (info->ChipFamily != CHIP_FAMILY_RS780) && 1451 (info->ChipFamily != CHIP_FAMILY_RS880)) { 1452 if (info->IsIGP) 1453 info->mc_fb_location = INREG(RADEON_NB_TOM); 1454 else 1455#ifdef XF86DRI 1456 /* Old DRI has restrictions on the memory map */ 1457 if ( info->directRenderingEnabled && 1458 info->dri->pKernelDRMVersion->version_minor < 10 ) 1459 info->mc_fb_location = (mem_size - 1) & 0xffff0000U; 1460 else 1461#endif 1462 { 1463 uint64_t aper0_base; 1464 1465 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1466 aper0_base = INREG(R600_CONFIG_F0_BASE); 1467 } else { 1468 aper0_base = INREG(RADEON_CONFIG_APER_0_BASE); 1469 } 1470 1471 /* Recent chips have an "issue" with the memory controller, the 1472 * location must be aligned to the size. We just align it down, 1473 * too bad if we walk over the top of system memory, we don't 1474 * use DMA without a remapped anyway. 1475 * Affected chips are rv280, all r3xx, and all r4xx, but not IGP 1476 */ 1477 if (info->ChipFamily == CHIP_FAMILY_RV280 || 1478 info->ChipFamily == CHIP_FAMILY_R300 || 1479 info->ChipFamily == CHIP_FAMILY_R350 || 1480 info->ChipFamily == CHIP_FAMILY_RV350 || 1481 info->ChipFamily == CHIP_FAMILY_RV380 || 1482 info->ChipFamily == CHIP_FAMILY_R420 || 1483 info->ChipFamily == CHIP_FAMILY_RV410) 1484 aper0_base &= ~(mem_size - 1); 1485 1486 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1487 uint64_t mc_fb = ((aper0_base >> 24) & 0xffff) | 1488 (((aper0_base + mem_size - 1) >> 8) & 0xffff0000); 1489 info->mc_fb_location = mc_fb & 0xffffffff; 1490 ErrorF("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location); 1491 } else { 1492 uint64_t mc_fb = ((aper0_base >> 16) & 0xffff) | 1493 ((aper0_base + mem_size - 1) & 0xffff0000U); 1494 info->mc_fb_location = mc_fb & 0xffffffff; 1495 } 1496 } 1497 } 1498 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1499 info->fbLocation = (info->mc_fb_location & 0xffff) << 24; 1500 } else { 1501 info->fbLocation = (info->mc_fb_location & 0xffff) << 16; 1502 } 1503 /* Just disable the damn AGP apertures for now, it may be 1504 * re-enabled later by the DRM 1505 */ 1506 if (IS_AVIVO_VARIANT) 1507 info->mc_agp_location = 0x003f0000; 1508 else 1509 info->mc_agp_location = 0xffffffc0; 1510 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1511 "RADEONInitMemoryMap() : \n"); 1512 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1513 " mem_size : 0x%08x\n", (unsigned)mem_size); 1514 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1515 " MC_FB_LOCATION : 0x%08x\n", (unsigned)info->mc_fb_location); 1516 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1517 " MC_AGP_LOCATION : 0x%08x\n", 1518 (unsigned)info->mc_agp_location); 1519} 1520 1521static void RADEONGetVRamType(ScrnInfoPtr pScrn) 1522{ 1523 RADEONInfoPtr info = RADEONPTR(pScrn); 1524 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1525 unsigned char *RADEONMMIO = info->MMIO; 1526 uint32_t tmp; 1527 1528 if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300)) 1529 info->IsDDR = TRUE; 1530 else if (INREG(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) 1531 info->IsDDR = TRUE; 1532 else 1533 info->IsDDR = FALSE; 1534 1535 if ((info->ChipFamily >= CHIP_FAMILY_R600) && 1536 (info->ChipFamily <= CHIP_FAMILY_RV635)) { 1537 int chansize; 1538 /* r6xx */ 1539 tmp = INREG(R600_RAMCFG); 1540 if (tmp & R600_CHANSIZE_OVERRIDE) 1541 chansize = 16; 1542 else if (tmp & R600_CHANSIZE) 1543 chansize = 64; 1544 else 1545 chansize = 32; 1546 if (info->ChipFamily == CHIP_FAMILY_R600) 1547 info->RamWidth = 8 * chansize; 1548 else if (info->ChipFamily == CHIP_FAMILY_RV670) 1549 info->RamWidth = 4 * chansize; 1550 else if ((info->ChipFamily == CHIP_FAMILY_RV610) || 1551 (info->ChipFamily == CHIP_FAMILY_RV620)) 1552 info->RamWidth = chansize; 1553 else if ((info->ChipFamily == CHIP_FAMILY_RV630) || 1554 (info->ChipFamily == CHIP_FAMILY_RV635)) 1555 info->RamWidth = 2 * chansize; 1556 } else if (info->ChipFamily == CHIP_FAMILY_RV515) { 1557 /* rv515/rv550 */ 1558 tmp = INMC(pScrn, RV515_MC_CNTL); 1559 tmp &= RV515_MEM_NUM_CHANNELS_MASK; 1560 switch (tmp) { 1561 case 0: info->RamWidth = 64; break; 1562 case 1: info->RamWidth = 128; break; 1563 default: info->RamWidth = 128; break; 1564 } 1565 } else if ((info->ChipFamily >= CHIP_FAMILY_R520) && 1566 (info->ChipFamily <= CHIP_FAMILY_RV570)){ 1567 /* r520/rv530/rv560/rv570/r580 */ 1568 tmp = INMC(pScrn, R520_MC_CNTL0); 1569 switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { 1570 case 0: info->RamWidth = 32; break; 1571 case 1: info->RamWidth = 64; break; 1572 case 2: info->RamWidth = 128; break; 1573 case 3: info->RamWidth = 256; break; 1574 default: info->RamWidth = 64; break; 1575 } 1576 if (tmp & R520_MC_CHANNEL_SIZE) { 1577 info->RamWidth *= 2; 1578 } 1579 } else if ((info->ChipFamily >= CHIP_FAMILY_R300) && 1580 (info->ChipFamily <= CHIP_FAMILY_RV410)) { 1581 /* r3xx, r4xx */ 1582 tmp = INREG(RADEON_MEM_CNTL); 1583 tmp &= R300_MEM_NUM_CHANNELS_MASK; 1584 switch (tmp) { 1585 case 0: info->RamWidth = 64; break; 1586 case 1: info->RamWidth = 128; break; 1587 case 2: info->RamWidth = 256; break; 1588 default: info->RamWidth = 128; break; 1589 } 1590 } else if ((info->ChipFamily == CHIP_FAMILY_RV100) || 1591 (info->ChipFamily == CHIP_FAMILY_RS100) || 1592 (info->ChipFamily == CHIP_FAMILY_RS200)){ 1593 tmp = INREG(RADEON_MEM_CNTL); 1594 if (tmp & RV100_HALF_MODE) 1595 info->RamWidth = 32; 1596 else 1597 info->RamWidth = 64; 1598 1599 if (!pRADEONEnt->HasCRTC2) { 1600 info->RamWidth /= 4; 1601 info->IsDDR = TRUE; 1602 } 1603 } else if (info->ChipFamily <= CHIP_FAMILY_RV280) { 1604 tmp = INREG(RADEON_MEM_CNTL); 1605 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) 1606 info->RamWidth = 128; 1607 else 1608 info->RamWidth = 64; 1609 } else { 1610 /* newer IGPs */ 1611 info->RamWidth = 128; 1612 } 1613 1614 /* This may not be correct, as some cards can have half of channel disabled 1615 * ToDo: identify these cases 1616 */ 1617} 1618 1619/* 1620 * Depending on card genertation, chipset bugs, etc... the amount of vram 1621 * accessible to the CPU can vary. This function is our best shot at figuring 1622 * it out. Returns a value in KB. 1623 */ 1624static uint32_t RADEONGetAccessibleVRAM(ScrnInfoPtr pScrn) 1625{ 1626 RADEONInfoPtr info = RADEONPTR(pScrn); 1627 unsigned char *RADEONMMIO = info->MMIO; 1628 uint32_t aper_size; 1629 unsigned char byte; 1630 1631 if (info->ChipFamily >= CHIP_FAMILY_CEDAR) 1632 /* size in MB */ 1633 aper_size = INREG(R600_CONFIG_APER_SIZE) * 1024; 1634 else if (info->ChipFamily >= CHIP_FAMILY_R600) 1635 aper_size = INREG(R600_CONFIG_APER_SIZE) / 1024; 1636 else 1637 aper_size = INREG(RADEON_CONFIG_APER_SIZE) / 1024; 1638 1639#ifdef XF86DRI 1640 /* If we use the DRI, we need to check if it's a version that has the 1641 * bug of always cropping MC_FB_LOCATION to one aperture, in which case 1642 * we need to limit the amount of accessible video memory 1643 */ 1644 if (info->directRenderingEnabled && 1645 info->dri->pKernelDRMVersion->version_minor < 23) { 1646 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1647 "[dri] limiting video memory to one aperture of %uK\n", 1648 (unsigned)aper_size); 1649 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 1650 "[dri] detected radeon kernel module version 1.%d but" 1651 " 1.23 or newer is required for full memory mapping.\n", 1652 info->dri->pKernelDRMVersion->version_minor); 1653 info->dri->newMemoryMap = FALSE; 1654 return aper_size; 1655 } 1656 info->dri->newMemoryMap = TRUE; 1657#endif /* XF86DRI */ 1658 1659 if (info->ChipFamily >= CHIP_FAMILY_R600) 1660 return aper_size; 1661 1662 /* Set HDP_APER_CNTL only on cards that are known not to be broken, 1663 * that is has the 2nd generation multifunction PCI interface 1664 */ 1665 if (info->ChipFamily == CHIP_FAMILY_RV280 || 1666 info->ChipFamily == CHIP_FAMILY_RV350 || 1667 info->ChipFamily == CHIP_FAMILY_RV380 || 1668 info->ChipFamily == CHIP_FAMILY_R420 || 1669 info->ChipFamily == CHIP_FAMILY_RV410 || 1670 IS_AVIVO_VARIANT) { 1671 OUTREGP (RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, 1672 ~RADEON_HDP_APER_CNTL); 1673 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1674 "Generation 2 PCI interface, using max accessible memory\n"); 1675 return aper_size * 2; 1676 } 1677 1678 /* Older cards have all sorts of funny issues to deal with. First 1679 * check if it's a multifunction card by reading the PCI config 1680 * header type... Limit those to one aperture size 1681 */ 1682 PCI_READ_BYTE(info->PciInfo, &byte, 0xe); 1683 if (byte & 0x80) { 1684 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1685 "Generation 1 PCI interface in multifunction mode" 1686 ", accessible memory limited to one aperture\n"); 1687 return aper_size; 1688 } 1689 1690 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS 1691 * have set it up. We don't write this as it's broken on some ASICs but 1692 * we expect the BIOS to have done the right thing (might be too optimistic...) 1693 */ 1694 if (INREG(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) 1695 return aper_size * 2; 1696 1697 return aper_size; 1698} 1699 1700static Bool RADEONPreInitVRAM(ScrnInfoPtr pScrn) 1701{ 1702 RADEONInfoPtr info = RADEONPTR(pScrn); 1703 EntityInfoPtr pEnt = info->pEnt; 1704 GDevPtr dev = pEnt->device; 1705 unsigned char *RADEONMMIO = info->MMIO; 1706 MessageType from = X_PROBED; 1707 uint32_t accessible, bar_size; 1708 1709 if ((!IS_AVIVO_VARIANT) && info->IsIGP) { 1710 uint32_t tom = INREG(RADEON_NB_TOM); 1711 1712 pScrn->videoRam = (((tom >> 16) - 1713 (tom & 0xffff) + 1) << 6); 1714 1715 OUTREG(RADEON_CONFIG_MEMSIZE, pScrn->videoRam * 1024); 1716 } else { 1717 if (info->ChipFamily >= CHIP_FAMILY_CEDAR) 1718 /* R600_CONFIG_MEMSIZE is MB on evergreen */ 1719 /* XXX watch for overflow!!! */ 1720 pScrn->videoRam = INREG(R600_CONFIG_MEMSIZE) * 1024; 1721 else if (info->ChipFamily >= CHIP_FAMILY_R600) 1722 pScrn->videoRam = INREG(R600_CONFIG_MEMSIZE) / 1024; 1723 else { 1724 /* Read VRAM size from card */ 1725 pScrn->videoRam = INREG(RADEON_CONFIG_MEMSIZE) / 1024; 1726 1727 /* Some production boards of m6 will return 0 if it's 8 MB */ 1728 if (pScrn->videoRam == 0) { 1729 pScrn->videoRam = 8192; 1730 OUTREG(RADEON_CONFIG_MEMSIZE, 0x800000); 1731 } 1732 } 1733 } 1734 1735 /* Get accessible memory */ 1736 accessible = RADEONGetAccessibleVRAM(pScrn); 1737 1738 /* Crop it to the size of the PCI BAR */ 1739 bar_size = PCI_REGION_SIZE(info->PciInfo, 0) / 1024; 1740 if (bar_size == 0) 1741 bar_size = 0x20000; 1742 if (accessible > bar_size) 1743 accessible = bar_size; 1744 1745 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1746 "Detected total video RAM=%dK, accessible=%uK (PCI BAR=%uK)\n", 1747 pScrn->videoRam, (unsigned)accessible, (unsigned)bar_size); 1748 if (pScrn->videoRam > accessible) 1749 pScrn->videoRam = accessible; 1750 1751 if (!IS_AVIVO_VARIANT) { 1752 info->MemCntl = INREG(RADEON_SDRAM_MODE_REG); 1753 info->BusCntl = INREG(RADEON_BUS_CNTL); 1754 } 1755 1756 RADEONGetVRamType(pScrn); 1757 1758 if (dev->videoRam) { 1759 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1760 "Video RAM override, using %d kB instead of %d kB\n", 1761 dev->videoRam, 1762 pScrn->videoRam); 1763 from = X_CONFIG; 1764 pScrn->videoRam = dev->videoRam; 1765 } 1766 1767 xf86DrvMsg(pScrn->scrnIndex, from, 1768 "Mapped VideoRAM: %d kByte (%d bit %s SDRAM)\n", pScrn->videoRam, info->RamWidth, info->IsDDR?"DDR":"SDR"); 1769 1770 if (info->IsPrimary) { 1771 pScrn->videoRam /= 2; 1772 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1773 "Using %dk of videoram for primary head\n", 1774 pScrn->videoRam); 1775 } 1776 1777 if (info->IsSecondary) { 1778 pScrn->videoRam /= 2; 1779 info->LinearAddr += pScrn->videoRam * 1024; 1780 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1781 "Using %dk of videoram for secondary head\n", 1782 pScrn->videoRam); 1783 } 1784 1785 pScrn->videoRam &= ~1023; 1786 info->FbMapSize = pScrn->videoRam * 1024; 1787 1788 /* if the card is PCI Express reserve the last 32k for the gart table */ 1789#ifdef XF86DRI 1790 if (info->cardType == CARD_PCIE && info->directRenderingEnabled) 1791 /* work out the size of pcie aperture */ 1792 info->FbSecureSize = RADEONDRIGetPciAperTableSize(pScrn); 1793 else 1794#endif 1795 info->FbSecureSize = 0; 1796 1797 return TRUE; 1798} 1799 1800 1801/* This is called by RADEONPreInit to handle config file overrides for 1802 * things like chipset and memory regions. Also determine memory size 1803 * and type. If memory type ever needs an override, put it in this 1804 * routine. 1805 */ 1806static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn) 1807{ 1808 RADEONInfoPtr info = RADEONPTR(pScrn); 1809 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1810 EntityInfoPtr pEnt = info->pEnt; 1811 GDevPtr dev = pEnt->device; 1812 unsigned char *RADEONMMIO = info->MMIO; 1813 MessageType from = X_PROBED; 1814 int i; 1815#ifdef XF86DRI 1816 const char *s; 1817 uint32_t cmd_stat; 1818#endif 1819 1820 /* Chipset */ 1821 from = X_PROBED; 1822 if (dev->chipset && *dev->chipset) { 1823 info->Chipset = xf86StringToToken(RADEONChipsets, dev->chipset); 1824 from = X_CONFIG; 1825 } else if (dev->chipID >= 0) { 1826 info->Chipset = dev->chipID; 1827 from = X_CONFIG; 1828 } else { 1829 info->Chipset = PCI_DEV_DEVICE_ID(info->PciInfo); 1830 } 1831 1832 pScrn->chipset = (char *)xf86TokenToString(RADEONChipsets, info->Chipset); 1833 if (!pScrn->chipset) { 1834 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1835 "ChipID 0x%04x is not recognized\n", info->Chipset); 1836 return FALSE; 1837 } 1838 if (info->Chipset < 0) { 1839 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1840 "Chipset \"%s\" is not recognized\n", pScrn->chipset); 1841 return FALSE; 1842 } 1843 xf86DrvMsg(pScrn->scrnIndex, from, 1844 "Chipset: \"%s\" (ChipID = 0x%04x)\n", 1845 pScrn->chipset, 1846 info->Chipset); 1847 1848 pRADEONEnt->HasCRTC2 = TRUE; 1849 info->IsMobility = FALSE; 1850 info->IsIGP = FALSE; 1851 info->IsDellServer = FALSE; 1852 info->HasSingleDAC = FALSE; 1853 info->InternalTVOut = TRUE; 1854 info->get_hardcoded_edid_from_bios = FALSE; 1855 1856 for (i = 0; i < sizeof(RADEONCards) / sizeof(RADEONCardInfo); i++) { 1857 if (info->Chipset == RADEONCards[i].pci_device_id) { 1858 RADEONCardInfo *card = &RADEONCards[i]; 1859 info->ChipFamily = card->chip_family; 1860 info->IsMobility = card->mobility; 1861 info->IsIGP = card->igp; 1862 pRADEONEnt->HasCRTC2 = !card->nocrtc2; 1863 info->HasSingleDAC = card->singledac; 1864 info->InternalTVOut = !card->nointtvout; 1865 break; 1866 } 1867 } 1868 1869 switch (info->Chipset) { 1870 case PCI_CHIP_RN50_515E: /* RN50 is based on the RV100 but 3D isn't guaranteed to work. YMMV. */ 1871 case PCI_CHIP_RN50_5969: 1872 /* Some Sun servers have a hardcoded edid so KVMs work properly */ 1873 if ((PCI_SUB_VENDOR_ID(info->PciInfo) == 0x108e) && 1874 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x4133)) 1875 info->get_hardcoded_edid_from_bios = TRUE; 1876 case PCI_CHIP_RV100_QY: 1877 case PCI_CHIP_RV100_QZ: 1878 /* DELL triple-head configuration. */ 1879 if (((PCI_SUB_VENDOR_ID(info->PciInfo) == PCI_VENDOR_DELL) && 1880 ((PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016c) || 1881 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016d) || 1882 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016e) || 1883 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x016f) || 1884 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0170) || 1885 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x017d) || 1886 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x017e) || 1887 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0183) || 1888 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x018a) || 1889 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x019a) || 1890 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x01b1) || 1891 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x01b2) || 1892 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0205))) || 1893 ((PCI_SUB_VENDOR_ID(info->PciInfo) == PCI_VENDOR_HP) && 1894 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x31fb))) { 1895 info->IsDellServer = TRUE; 1896 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "DELL/HP server detected, force to special setup\n"); 1897 } 1898 break; 1899 case PCI_CHIP_RS482_5974: 1900 /* RH BZ 444586 - non mobility version 1901 * Dell appear to have the Vostro 1100 with a mobility part with the same pci-id */ 1902 if ((PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1462) && 1903 (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x7141)) { 1904 info->IsMobility = FALSE; 1905 } 1906 default: 1907 break; 1908 } 1909 1910 from = X_PROBED; 1911 info->LinearAddr = PCI_REGION_BASE(info->PciInfo, 0, REGION_MEM) & ~0x1ffffffULL; 1912 pScrn->memPhysBase = info->LinearAddr; 1913 if (dev->MemBase) { 1914 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1915 "Linear address override, using 0x%016lx instead of 0x%016llx\n", 1916 dev->MemBase, 1917 info->LinearAddr); 1918 info->LinearAddr = dev->MemBase; 1919 from = X_CONFIG; 1920 } else if (!info->LinearAddr) { 1921 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1922 "No valid linear framebuffer address\n"); 1923 return FALSE; 1924 } 1925 xf86DrvMsg(pScrn->scrnIndex, from, 1926 "Linear framebuffer at 0x%016llx\n", info->LinearAddr); 1927 1928#ifndef XSERVER_LIBPCIACCESS 1929 /* BIOS */ 1930 from = X_PROBED; 1931 info->BIOSAddr = info->PciInfo->biosBase & 0xfffe0000; 1932 if (dev->BiosBase) { 1933 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1934 "BIOS address override, using 0x%08lx instead of 0x%08lx\n", 1935 (unsigned long)dev->BiosBase, 1936 (unsigned long)info->BIOSAddr); 1937 info->BIOSAddr = dev->BiosBase; 1938 from = X_CONFIG; 1939 } 1940 if (info->BIOSAddr) { 1941 xf86DrvMsg(pScrn->scrnIndex, from, 1942 "BIOS at 0x%08lx\n", (unsigned long)info->BIOSAddr); 1943 } 1944#endif 1945 1946 /* Read registers used to determine options */ 1947 /* Check chip errata */ 1948 info->ChipErrata = 0; 1949 1950 if (info->ChipFamily == CHIP_FAMILY_R300 && 1951 (INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) 1952 == RADEON_CFG_ATI_REV_A11) 1953 info->ChipErrata |= CHIP_ERRATA_R300_CG; 1954 1955 if (info->ChipFamily == CHIP_FAMILY_RV200 || 1956 info->ChipFamily == CHIP_FAMILY_RS200) 1957 info->ChipErrata |= CHIP_ERRATA_PLL_DUMMYREADS; 1958 1959 if (info->ChipFamily == CHIP_FAMILY_RV100 || 1960 info->ChipFamily == CHIP_FAMILY_RS100 || 1961 info->ChipFamily == CHIP_FAMILY_RS200) 1962 info->ChipErrata |= CHIP_ERRATA_PLL_DELAY; 1963 1964#ifdef XF86DRI 1965 /* AGP/PCI */ 1966 /* Proper autodetection of an AGP capable device requires examining 1967 * PCI config registers to determine if the device implements extended 1968 * PCI capabilities, and then walking the capability list as indicated 1969 * in the PCI 2.2 and AGP 2.0 specifications, to determine if AGP 1970 * capability is present. The procedure is outlined as follows: 1971 * 1972 * 1) Test bit 4 (CAP_LIST) of the PCI status register of the device 1973 * to determine wether or not this device implements any extended 1974 * capabilities. If this bit is zero, then the device is a PCI 2.1 1975 * or earlier device and is not AGP capable, and we can conclude it 1976 * to be a PCI device. 1977 * 1978 * 2) If bit 4 of the status register is set, then the device implements 1979 * extended capabilities. There is an 8 bit wide capabilities pointer 1980 * register located at offset 0x34 in PCI config space which points to 1981 * the first capability in a linked list of extended capabilities that 1982 * this device implements. The lower two bits of this register are 1983 * reserved and MBZ so must be masked out. 1984 * 1985 * 3) The extended capabilities list is formed by one or more extended 1986 * capabilities structures which are aligned on DWORD boundaries. 1987 * The first byte of the structure is the capability ID (CAP_ID) 1988 * indicating what extended capability this structure refers to. The 1989 * second byte of the structure is an offset from the beginning of 1990 * PCI config space pointing to the next capability in the linked 1991 * list (NEXT_PTR) or NULL (0x00) at the end of the list. The lower 1992 * two bits of this pointer are reserved and MBZ. By examining the 1993 * CAP_ID of each capability and walking through the list, we will 1994 * either find the AGP_CAP_ID (0x02) indicating this device is an 1995 * AGP device, or we'll reach the end of the list, indicating it is 1996 * a PCI device. 1997 * 1998 * Mike A. Harris <mharris@redhat.com> 1999 * 2000 * References: 2001 * - PCI Local Bus Specification Revision 2.2, Chapter 6 2002 * - AGP Interface Specification Revision 2.0, Section 6.1.5 2003 */ 2004 2005 info->cardType = CARD_PCI; 2006 2007 PCI_READ_LONG(info->PciInfo, &cmd_stat, PCI_CMD_STAT_REG); 2008 if (cmd_stat & RADEON_CAP_LIST) { 2009 uint32_t cap_ptr, cap_id; 2010 2011 PCI_READ_LONG(info->PciInfo, &cap_ptr, RADEON_CAPABILITIES_PTR_PCI_CONFIG); 2012 cap_ptr &= RADEON_CAP_PTR_MASK; 2013 2014 while(cap_ptr != RADEON_CAP_ID_NULL) { 2015 PCI_READ_LONG(info->PciInfo, &cap_id, cap_ptr); 2016 if ((cap_id & 0xff)== RADEON_CAP_ID_AGP) { 2017 info->cardType = CARD_AGP; 2018 break; 2019 } 2020 if ((cap_id & 0xff)== RADEON_CAP_ID_EXP) { 2021 info->cardType = CARD_PCIE; 2022 break; 2023 } 2024 cap_ptr = (cap_id >> 8) & RADEON_CAP_PTR_MASK; 2025 } 2026 } 2027 2028 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s card detected\n", 2029 (info->cardType==CARD_PCI) ? "PCI" : 2030 (info->cardType==CARD_PCIE) ? "PCIE" : "AGP"); 2031 2032 /* treat PCIE IGP cards as PCI */ 2033 if (info->cardType == CARD_PCIE && info->IsIGP) 2034 info->cardType = CARD_PCI; 2035 2036 /* some rs4xx cards report as agp */ 2037 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 2038 (info->ChipFamily == CHIP_FAMILY_RS480)) 2039 info->cardType = CARD_PCI; 2040 2041 if ((info->ChipFamily >= CHIP_FAMILY_R600) && info->IsIGP) 2042 info->cardType = CARD_PCIE; 2043 2044 /* not sure about gart table requirements */ 2045 if ((info->ChipFamily == CHIP_FAMILY_RS600) && info->IsIGP) 2046 info->cardType = CARD_PCIE; 2047 2048 if ((s = xf86GetOptValString(info->Options, OPTION_BUS_TYPE))) { 2049 if (strcmp(s, "AGP") == 0) { 2050 info->cardType = CARD_AGP; 2051 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into AGP mode\n"); 2052 } else if ((strcmp(s, "PCI") == 0) || 2053 (strcmp(s, "PCIE") == 0)) { 2054 if ((info->ChipFamily == CHIP_FAMILY_RS400) || 2055 (info->ChipFamily == CHIP_FAMILY_RS480) || 2056 (info->ChipFamily == CHIP_FAMILY_RS690) || 2057 (info->ChipFamily == CHIP_FAMILY_RS740)) { 2058 info->cardType = CARD_PCI; 2059 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI mode\n"); 2060 } else if (info->ChipFamily >= CHIP_FAMILY_RV380) { 2061 info->cardType = CARD_PCIE; 2062 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI Express mode\n"); 2063 } else { 2064 info->cardType = CARD_PCI; 2065 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Forced into PCI mode\n"); 2066 } 2067 } else { 2068 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, 2069 "Invalid BusType option, using detected type\n"); 2070 } 2071 } 2072#endif 2073 xf86GetOptValBool(info->Options, OPTION_SHOWCACHE, &info->showCache); 2074 if (info->showCache) 2075 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, 2076 "Option ShowCache enabled\n"); 2077 2078#ifdef RENDER 2079 info->RenderAccel = xf86ReturnOptValBool(info->Options, OPTION_RENDER_ACCEL, 2080 info->Chipset != PCI_CHIP_RN50_515E && 2081 info->Chipset != PCI_CHIP_RN50_5969); 2082#endif 2083 2084 info->r4xx_atom = FALSE; 2085 if (((info->ChipFamily == CHIP_FAMILY_R420) || (info->ChipFamily == CHIP_FAMILY_RV410)) && 2086 xf86ReturnOptValBool(info->Options, OPTION_R4XX_ATOM, FALSE)) { 2087 info->r4xx_atom = TRUE; 2088 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Using ATOMBIOS for R4xx chip\n"); 2089 } 2090 2091 return TRUE; 2092} 2093 2094 2095static void RADEONPreInitDDC(ScrnInfoPtr pScrn) 2096{ 2097 RADEONInfoPtr info = RADEONPTR(pScrn); 2098 /* vbeInfoPtr pVbe; */ 2099 2100 info->ddc1 = FALSE; 2101 info->ddc_bios = FALSE; 2102 if (!xf86LoadSubModule(pScrn, "ddc")) { 2103 info->ddc2 = FALSE; 2104 } else { 2105 info->ddc2 = TRUE; 2106 } 2107 2108 /* DDC can use I2C bus */ 2109 /* Load I2C if we have the code to use it */ 2110 if (info->ddc2) { 2111 xf86LoadSubModule(pScrn, "i2c"); 2112 } 2113} 2114 2115/* This is called by RADEONPreInit to initialize gamma correction */ 2116static Bool RADEONPreInitGamma(ScrnInfoPtr pScrn) 2117{ 2118 Gamma zeros = { 0.0, 0.0, 0.0 }; 2119 2120 if (!xf86SetGamma(pScrn, zeros)) return FALSE; 2121 return TRUE; 2122} 2123 2124/* This is called by RADEONPreInit to initialize the hardware cursor */ 2125static Bool RADEONPreInitCursor(ScrnInfoPtr pScrn) 2126{ 2127 RADEONInfoPtr info = RADEONPTR(pScrn); 2128 2129 if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { 2130 if (!xf86LoadSubModule(pScrn, "ramdac")) return FALSE; 2131 } 2132 return TRUE; 2133} 2134 2135/* This is called by RADEONPreInit to initialize hardware acceleration */ 2136static Bool RADEONPreInitAccel(ScrnInfoPtr pScrn) 2137{ 2138 RADEONInfoPtr info = RADEONPTR(pScrn); 2139 MessageType from; 2140#if defined(USE_EXA) && defined(USE_XAA) 2141 char *optstr; 2142#endif 2143 int maxy = info->FbMapSize / (pScrn->displayWidth * info->CurrentLayout.pixel_bytes); 2144 2145 if (!(info->accel_state = xcalloc(1, sizeof(struct radeon_accel_state)))) { 2146 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to allocate accel_state rec!\n"); 2147 return FALSE; 2148 } 2149 info->accel_state->fifo_slots = 0; 2150 2151 if ((info->ChipFamily == CHIP_FAMILY_RS100) || 2152 (info->ChipFamily == CHIP_FAMILY_RS200) || 2153 (info->ChipFamily == CHIP_FAMILY_RS300) || 2154 (info->ChipFamily == CHIP_FAMILY_RS400) || 2155 (info->ChipFamily == CHIP_FAMILY_RS480) || 2156 (info->ChipFamily == CHIP_FAMILY_RS600) || 2157 (info->ChipFamily == CHIP_FAMILY_RS690) || 2158 (info->ChipFamily == CHIP_FAMILY_RS740)) 2159 info->accel_state->has_tcl = FALSE; 2160 else { 2161 info->accel_state->has_tcl = TRUE; 2162 } 2163 2164 /* if we have shadow fb bail */ 2165 if (info->r600_shadow_fb) { 2166 info->useEXA = FALSE; 2167 return TRUE; 2168 } 2169 2170#ifdef XF86DRI 2171 if ((!info->directRenderingEnabled) || 2172 (maxy <= pScrn->virtualY * 3) || 2173 (pScrn->videoRam <= 32768)) 2174 info->useEXA = FALSE; 2175 else 2176 info->useEXA = TRUE; 2177#else 2178 info->useEXA = FALSE; 2179#endif 2180 2181 if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { 2182 int errmaj = 0, errmin = 0; 2183 2184 from = X_DEFAULT; 2185#if defined(USE_EXA) 2186#if defined(USE_XAA) 2187 optstr = (char *)xf86GetOptValString(info->Options, OPTION_ACCELMETHOD); 2188 if (optstr != NULL) { 2189 if (xf86NameCmp(optstr, "EXA") == 0) { 2190 from = X_CONFIG; 2191 info->useEXA = TRUE; 2192 } else if (xf86NameCmp(optstr, "XAA") == 0) { 2193 from = X_CONFIG; 2194 if (info->ChipFamily < CHIP_FAMILY_R600) 2195 info->useEXA = FALSE; 2196 } 2197 } 2198#else /* USE_XAA */ 2199 info->useEXA = TRUE; 2200#endif /* !USE_XAA */ 2201#endif /* USE_EXA */ 2202 if (info->ChipFamily < CHIP_FAMILY_R600) 2203 xf86DrvMsg(pScrn->scrnIndex, from, 2204 "Using %s acceleration architecture\n", 2205 info->useEXA ? "EXA" : "XAA"); 2206 else 2207 xf86DrvMsg(pScrn->scrnIndex, X_DEFAULT, 2208 "Will attempt to use R6xx/R7xx EXA support if DRI is enabled.\n"); 2209 2210#ifdef USE_EXA 2211 if (info->useEXA) { 2212 info->exaReq.majorversion = EXA_VERSION_MAJOR; 2213 info->exaReq.minorversion = EXA_VERSION_MINOR; 2214 2215 if (!LoadSubModule(pScrn->module, "exa", NULL, NULL, NULL, 2216 &info->exaReq, &errmaj, &errmin)) { 2217 LoaderErrorMsg(NULL, "exa", errmaj, errmin); 2218 return FALSE; 2219 } 2220 } 2221#endif /* USE_EXA */ 2222#ifdef USE_XAA 2223 if (!info->useEXA) { 2224 info->xaaReq.majorversion = 1; 2225 info->xaaReq.minorversion = 2; 2226 2227 if (!LoadSubModule(pScrn->module, "xaa", NULL, NULL, NULL, 2228 &info->xaaReq, &errmaj, &errmin)) { 2229 info->xaaReq.minorversion = 1; 2230 2231 if (!LoadSubModule(pScrn->module, "xaa", NULL, NULL, NULL, 2232 &info->xaaReq, &errmaj, &errmin)) { 2233 info->xaaReq.minorversion = 0; 2234 2235 if (!LoadSubModule(pScrn->module, "xaa", NULL, NULL, NULL, 2236 &info->xaaReq, &errmaj, &errmin)) { 2237 LoaderErrorMsg(NULL, "xaa", errmaj, errmin); 2238 return FALSE; 2239 } 2240 } 2241 } 2242 } 2243#endif /* USE_XAA */ 2244 } else { 2245 /* NoAccel */ 2246 info->useEXA = FALSE; 2247 } 2248 2249 return TRUE; 2250} 2251 2252static Bool RADEONPreInitInt10(ScrnInfoPtr pScrn, xf86Int10InfoPtr *ppInt10) 2253{ 2254#if (!defined(__powerpc__) && !defined(__sparc__)) || \ 2255 (defined(XSERVER_LIBPCIACCESS) && HAVE_PCI_DEVICE_ENABLE) 2256 RADEONInfoPtr info = RADEONPTR(pScrn); 2257#endif 2258#if !defined(__powerpc__) && !defined(__sparc__) 2259 unsigned char *RADEONMMIO = info->MMIO; 2260 uint32_t fp2_gen_ctl_save = 0; 2261#endif 2262 2263#ifdef XSERVER_LIBPCIACCESS 2264#if HAVE_PCI_DEVICE_ENABLE 2265 pci_device_enable(info->PciInfo); 2266#endif 2267#endif 2268 2269#if !defined(__powerpc__) && !defined(__sparc__) 2270 /* don't need int10 on atom cards. 2271 * in theory all radeons, but the older stuff 2272 * isn't 100% yet 2273 * secondary atom cards tend to hang when initializing int10, 2274 * however, on some stom cards, you can't read the bios without 2275 * intitializing int10. 2276 */ 2277 if (!xf86ReturnOptValBool(info->Options, OPTION_INT10, TRUE)) 2278 return TRUE; 2279 2280 if (xf86LoadSubModule(pScrn, "int10")) { 2281 /* The VGA BIOS on the RV100/QY cannot be read when the digital output 2282 * is enabled. Clear and restore FP2_ON around int10 to avoid this. 2283 */ 2284 if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) { 2285 fp2_gen_ctl_save = INREG(RADEON_FP2_GEN_CNTL); 2286 if (fp2_gen_ctl_save & RADEON_FP2_ON) { 2287 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "disabling digital out\n"); 2288 OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_ctl_save & ~RADEON_FP2_ON); 2289 } 2290 } 2291 2292 xf86DrvMsg(pScrn->scrnIndex,X_INFO,"initializing int10\n"); 2293 *ppInt10 = xf86InitInt10(info->pEnt->index); 2294 2295 if (PCI_DEV_DEVICE_ID(info->PciInfo) == PCI_CHIP_RV100_QY) { 2296 if (fp2_gen_ctl_save & RADEON_FP2_ON) { 2297 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "re-enabling digital out\n"); 2298 OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_ctl_save); 2299 } 2300 } 2301 } 2302#endif 2303 return TRUE; 2304} 2305 2306#ifdef XF86DRI 2307static Bool RADEONPreInitDRI(ScrnInfoPtr pScrn) 2308{ 2309 RADEONInfoPtr info = RADEONPTR(pScrn); 2310 MessageType from; 2311 char *reason; 2312 2313 info->directRenderingEnabled = FALSE; 2314 info->directRenderingInited = FALSE; 2315 2316 if (!(info->dri = xcalloc(1, sizeof(struct radeon_dri)))) { 2317 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate dri rec!\n"); 2318 return FALSE; 2319 } 2320 2321 if (!(info->cp = xcalloc(1, sizeof(struct radeon_cp)))) { 2322 xf86DrvMsg(pScrn->scrnIndex, X_ERROR,"Unable to allocate cp rec!\n"); 2323 return FALSE; 2324 } 2325 info->cp->CPInUse = FALSE; 2326 info->cp->CPStarted = FALSE; 2327 info->cp->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT; 2328 2329 if (xf86IsEntityShared(info->pEnt->index)) { 2330 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2331 "Direct Rendering Disabled -- " 2332 "Zaphod Dual-head configuration is not working with " 2333 "DRI at present.\n" 2334 "Please use the xrandr 1.2 if you " 2335 "want Dual-head with DRI.\n"); 2336 return FALSE; 2337 } 2338 if (info->IsSecondary) 2339 return FALSE; 2340 2341 if (info->ChipFamily >= CHIP_FAMILY_CEDAR) { 2342 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2343 "No DRI yet on Evergreen\n"); 2344 return FALSE; 2345 } 2346 2347 if (info->Chipset == PCI_CHIP_RN50_515E || 2348 info->Chipset == PCI_CHIP_RN50_5969) { 2349 if (xf86ReturnOptValBool(info->Options, OPTION_DRI, FALSE)) { 2350 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2351 "Direct rendering for RN50 forced on -- " 2352 "This is NOT officially supported at the hardware level " 2353 "and may cause instability or lockups\n"); 2354 } else { 2355 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2356 "Direct rendering not officially supported on RN50\n"); 2357 return FALSE; 2358 } 2359 } 2360 2361 if (!xf86ReturnOptValBool(info->Options, OPTION_DRI, TRUE)) { 2362 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2363 "Direct rendering forced off\n"); 2364 return FALSE; 2365 } 2366 2367 if (xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { 2368 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2369 "[dri] Acceleration disabled, not initializing the DRI\n"); 2370 return FALSE; 2371 } 2372 2373 info->dri->pLibDRMVersion = NULL; 2374 info->dri->pKernelDRMVersion = NULL; 2375 2376 if (!RADEONDRIGetVersion(pScrn)) 2377 return FALSE; 2378 2379 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2380 "[dri] Found DRI library version %d.%d.%d and kernel" 2381 " module version %d.%d.%d\n", 2382 info->dri->pLibDRMVersion->version_major, 2383 info->dri->pLibDRMVersion->version_minor, 2384 info->dri->pLibDRMVersion->version_patchlevel, 2385 info->dri->pKernelDRMVersion->version_major, 2386 info->dri->pKernelDRMVersion->version_minor, 2387 info->dri->pKernelDRMVersion->version_patchlevel); 2388 2389 if (info->Chipset == PCI_CHIP_RS400_5A41 || 2390 info->Chipset == PCI_CHIP_RS400_5A42 || 2391 info->Chipset == PCI_CHIP_RC410_5A61 || 2392 info->Chipset == PCI_CHIP_RC410_5A62 || 2393 info->Chipset == PCI_CHIP_RS480_5954 || 2394 info->Chipset == PCI_CHIP_RS480_5955 || 2395 info->Chipset == PCI_CHIP_RS482_5974 || 2396 info->Chipset == PCI_CHIP_RS485_5975) { 2397 2398 if (info->dri->pKernelDRMVersion->version_minor < 27) { 2399 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2400 "Direct rendering broken on XPRESS 200 and 200M with DRI less than 1.27\n"); 2401 return FALSE; 2402 } 2403 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2404 "Direct rendering experimental on RS400/Xpress 200 enabled\n"); 2405 } 2406 2407 if (info->ChipFamily >= CHIP_FAMILY_R300) 2408 info->dri->gartSize = R300_DEFAULT_GART_SIZE; 2409 else 2410 info->dri->gartSize = RADEON_DEFAULT_GART_SIZE; 2411 2412 info->dri->ringSize = RADEON_DEFAULT_RING_SIZE; 2413 info->dri->bufSize = RADEON_DEFAULT_BUFFER_SIZE; 2414 info->dri->gartTexSize = RADEON_DEFAULT_GART_TEX_SIZE; 2415 info->dri->pciAperSize = RADEON_DEFAULT_PCI_APER_SIZE; 2416 info->cp->CPusecTimeout = RADEON_DEFAULT_CP_TIMEOUT; 2417 2418 if ((xf86GetOptValInteger(info->Options, 2419 OPTION_GART_SIZE, (int *)&(info->dri->gartSize))) || 2420 (xf86GetOptValInteger(info->Options, 2421 OPTION_GART_SIZE_OLD, (int *)&(info->dri->gartSize)))) { 2422 switch (info->dri->gartSize) { 2423 case 4: 2424 case 8: 2425 case 16: 2426 case 32: 2427 case 64: 2428 case 128: 2429 case 256: 2430 break; 2431 2432 default: 2433 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2434 "Illegal GART size: %d MB\n", info->dri->gartSize); 2435 return FALSE; 2436 } 2437 } 2438 2439 if (xf86GetOptValInteger(info->Options, 2440 OPTION_RING_SIZE, &(info->dri->ringSize))) { 2441 if (info->dri->ringSize < 1 || info->dri->ringSize >= (int)info->dri->gartSize) { 2442 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2443 "Illegal ring buffer size: %d MB\n", 2444 info->dri->ringSize); 2445 return FALSE; 2446 } 2447 } 2448 2449 if (xf86GetOptValInteger(info->Options, 2450 OPTION_PCIAPER_SIZE, &(info->dri->pciAperSize))) { 2451 switch(info->dri->pciAperSize) { 2452 case 32: 2453 case 64: 2454 case 128: 2455 case 256: 2456 break; 2457 default: 2458 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2459 "Illegal pci aper size: %d MB\n", 2460 info->dri->pciAperSize); 2461 return FALSE; 2462 } 2463 } 2464 2465 2466 if (xf86GetOptValInteger(info->Options, 2467 OPTION_BUFFER_SIZE, &(info->dri->bufSize))) { 2468 if (info->dri->bufSize < 1 || info->dri->bufSize >= (int)info->dri->gartSize) { 2469 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2470 "Illegal vertex/indirect buffers size: %d MB\n", 2471 info->dri->bufSize); 2472 return FALSE; 2473 } 2474 if (info->dri->bufSize > 2) { 2475 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2476 "Illegal vertex/indirect buffers size: %d MB\n", 2477 info->dri->bufSize); 2478 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2479 "Clamping vertex/indirect buffers size to 2 MB\n"); 2480 info->dri->bufSize = 2; 2481 } 2482 } 2483 2484 if (info->dri->ringSize + info->dri->bufSize + info->dri->gartTexSize > 2485 (int)info->dri->gartSize) { 2486 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2487 "Buffers are too big for requested GART space\n"); 2488 return FALSE; 2489 } 2490 2491 info->dri->gartTexSize = info->dri->gartSize - (info->dri->ringSize + info->dri->bufSize); 2492 2493 if (xf86GetOptValInteger(info->Options, OPTION_USEC_TIMEOUT, 2494 &(info->cp->CPusecTimeout))) { 2495 /* This option checked by the RADEON DRM kernel module */ 2496 } 2497 2498 /* Two options to try and squeeze as much texture memory as possible 2499 * for dedicated 3d rendering boxes 2500 */ 2501 info->dri->noBackBuffer = xf86ReturnOptValBool(info->Options, 2502 OPTION_NO_BACKBUFFER, 2503 FALSE); 2504 2505 info->dri->allowPageFlip = 0; 2506 2507#ifdef DAMAGE 2508 if (info->dri->noBackBuffer) { 2509 from = X_DEFAULT; 2510 reason = " because back buffer disabled"; 2511 } else { 2512 from = xf86GetOptValBool(info->Options, OPTION_PAGE_FLIP, 2513 &info->dri->allowPageFlip) ? X_CONFIG : X_DEFAULT; 2514 2515 if (IS_AVIVO_VARIANT) { 2516 info->dri->allowPageFlip = 0; 2517 reason = " on r5xx and newer chips.\n"; 2518 } else { 2519 reason = ""; 2520 } 2521 2522 } 2523#else 2524 from = X_DEFAULT; 2525 reason = " because Damage layer not available at build time"; 2526#endif 2527 2528 xf86DrvMsg(pScrn->scrnIndex, from, "Page Flipping %sabled%s\n", 2529 info->dri->allowPageFlip ? "en" : "dis", reason); 2530 2531 /* AGP seems to have problems with gart transfers */ 2532 if ((info->ChipFamily >= CHIP_FAMILY_R600) && (info->cardType == CARD_AGP)) 2533 info->DMAForXv = FALSE; 2534 else 2535 info->DMAForXv = TRUE; 2536 from = xf86GetOptValBool(info->Options, OPTION_XV_DMA, &info->DMAForXv) 2537 ? X_CONFIG : X_INFO; 2538 xf86DrvMsg(pScrn->scrnIndex, from, 2539 "Will %stry to use DMA for Xv image transfers\n", 2540 info->DMAForXv ? "" : "not "); 2541 2542 return TRUE; 2543} 2544#endif /* XF86DRI */ 2545 2546static void RADEONPreInitColorTiling(ScrnInfoPtr pScrn) 2547{ 2548 RADEONInfoPtr info = RADEONPTR(pScrn); 2549 2550 info->allowColorTiling = xf86ReturnOptValBool(info->Options, 2551 OPTION_COLOR_TILING, TRUE); 2552 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { 2553 /* this may be 4096 on r4xx -- need to double check */ 2554 info->MaxSurfaceWidth = 3968; /* one would have thought 4096...*/ 2555 info->MaxLines = 4096; 2556 } else { 2557 info->MaxSurfaceWidth = 2048; 2558 info->MaxLines = 2048; 2559 } 2560 2561 if (!info->allowColorTiling) 2562 return; 2563 2564 if (info->ChipFamily >= CHIP_FAMILY_R600) 2565 info->allowColorTiling = FALSE; 2566 2567 /* for zaphod disable tiling for now */ 2568 if (info->IsPrimary || info->IsSecondary) 2569 info->allowColorTiling = FALSE; 2570 2571#ifdef XF86DRI 2572 if (info->directRenderingEnabled && 2573 info->dri->pKernelDRMVersion->version_minor < 14) { 2574 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2575 "[dri] color tiling disabled because of version " 2576 "mismatch.\n" 2577 "[dri] radeon.o kernel module version is %d.%d.%d but " 2578 "1.14.0 or later is required for color tiling.\n", 2579 info->dri->pKernelDRMVersion->version_major, 2580 info->dri->pKernelDRMVersion->version_minor, 2581 info->dri->pKernelDRMVersion->version_patchlevel); 2582 info->allowColorTiling = FALSE; 2583 return; 2584 } 2585#endif /* XF86DRI */ 2586 2587 if (info->allowColorTiling) { 2588 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Color tiling enabled by default\n"); 2589 } else { 2590 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Color tiling disabled\n"); 2591 } 2592} 2593 2594 2595static Bool RADEONPreInitXv(ScrnInfoPtr pScrn) 2596{ 2597 RADEONInfoPtr info = RADEONPTR(pScrn); 2598 uint16_t mm_table; 2599 uint16_t bios_header; 2600 uint16_t pll_info_block; 2601#ifdef XvExtension 2602 char* microc_path = NULL; 2603 char* microc_type = NULL; 2604 MessageType from; 2605 2606 if (xf86GetOptValInteger(info->Options, OPTION_VIDEO_KEY, 2607 &(info->videoKey))) { 2608 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "video key set to 0x%x\n", 2609 info->videoKey); 2610 } else { 2611 info->videoKey = 0x1E; 2612 } 2613 2614 if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_CRYSTAL, &(info->RageTheatreCrystal))) { 2615 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre Crystal frequency was specified as %d.%d Mhz\n", 2616 info->RageTheatreCrystal/100, info->RageTheatreCrystal % 100); 2617 } else { 2618 info->RageTheatreCrystal=-1; 2619 } 2620 2621 if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_TUNER_PORT, &(info->RageTheatreTunerPort))) { 2622 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre tuner port was specified as %d\n", 2623 info->RageTheatreTunerPort); 2624 } else { 2625 info->RageTheatreTunerPort=-1; 2626 } 2627 2628 if(info->RageTheatreTunerPort>5){ 2629 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to assign Rage Theatre tuner port to invalid value. Disabling setting\n"); 2630 info->RageTheatreTunerPort=-1; 2631 } 2632 2633 if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_COMPOSITE_PORT, &(info->RageTheatreCompositePort))) { 2634 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre composite port was specified as %d\n", 2635 info->RageTheatreCompositePort); 2636 } else { 2637 info->RageTheatreCompositePort=-1; 2638 } 2639 2640 if(info->RageTheatreCompositePort>6){ 2641 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to assign Rage Theatre composite port to invalid value. Disabling setting\n"); 2642 info->RageTheatreCompositePort=-1; 2643 } 2644 2645 if(xf86GetOptValInteger(info->Options, OPTION_RAGE_THEATRE_SVIDEO_PORT, &(info->RageTheatreSVideoPort))) { 2646 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre SVideo Port was specified as %d\n", 2647 info->RageTheatreSVideoPort); 2648 } else { 2649 info->RageTheatreSVideoPort=-1; 2650 } 2651 2652 if(info->RageTheatreSVideoPort>6){ 2653 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to assign Rage Theatre SVideo port to invalid value. Disabling setting\n"); 2654 info->RageTheatreSVideoPort=-1; 2655 } 2656 2657 if(xf86GetOptValInteger(info->Options, OPTION_TUNER_TYPE, &(info->tunerType))) { 2658 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Tuner type was specified as %d\n", 2659 info->tunerType); 2660 } else { 2661 info->tunerType=-1; 2662 } 2663 2664 if(info->tunerType>31){ 2665 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to set tuner type to invalid value. Disabling setting\n"); 2666 info->tunerType=-1; 2667 } 2668 2669 if((microc_path = xf86GetOptValString(info->Options, OPTION_RAGE_THEATRE_MICROC_PATH)) != NULL) 2670 { 2671 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre Microcode path was specified as %s\n", microc_path); 2672 info->RageTheatreMicrocPath = microc_path; 2673 } else { 2674 info->RageTheatreMicrocPath= NULL; 2675 } 2676 2677 if((microc_type = xf86GetOptValString(info->Options, OPTION_RAGE_THEATRE_MICROC_TYPE)) != NULL) 2678 { 2679 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Rage Theatre Microcode type was specified as %s\n", microc_type); 2680 info->RageTheatreMicrocType = microc_type; 2681 } else { 2682 info->RageTheatreMicrocType= NULL; 2683 } 2684 2685 if(xf86GetOptValInteger(info->Options, OPTION_SCALER_WIDTH, &(info->overlay_scaler_buffer_width))) { 2686 if ((info->overlay_scaler_buffer_width < 1024) || 2687 (info->overlay_scaler_buffer_width > 2048) || 2688 ((info->overlay_scaler_buffer_width % 64) != 0)) { 2689 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Attempt to set illegal scaler width. Using default\n"); 2690 from = X_DEFAULT; 2691 info->overlay_scaler_buffer_width = 0; 2692 } else 2693 from = X_CONFIG; 2694 } else { 2695 from = X_DEFAULT; 2696 info->overlay_scaler_buffer_width = 0; 2697 } 2698 if (!info->overlay_scaler_buffer_width) { 2699 /* overlay scaler line length differs for different revisions 2700 this needs to be maintained by hand */ 2701 switch(info->ChipFamily){ 2702 case CHIP_FAMILY_R200: 2703 case CHIP_FAMILY_R300: 2704 case CHIP_FAMILY_RV350: 2705 info->overlay_scaler_buffer_width = 1920; 2706 break; 2707 default: 2708 info->overlay_scaler_buffer_width = 1536; 2709 } 2710 } 2711 xf86DrvMsg(pScrn->scrnIndex, from, "Assuming overlay scaler buffer width is %d\n", 2712 info->overlay_scaler_buffer_width); 2713#endif 2714 2715 /* Rescue MM_TABLE before VBIOS is freed */ 2716 info->MM_TABLE_valid = FALSE; 2717 2718 if((info->VBIOS==NULL)||(info->VBIOS[0]!=0x55)||(info->VBIOS[1]!=0xaa)){ 2719 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Cannot access BIOS or it is not valid.\n" 2720 "\t\tIf your card is TV-in capable you will need to specify options RageTheatreCrystal, RageTheatreTunerPort, \n" 2721 "\t\tRageTheatreSVideoPort and TunerType in /etc/X11/xorg.conf.\n" 2722 ); 2723 info->MM_TABLE_valid = FALSE; 2724 return TRUE; 2725 } 2726 2727 bios_header=info->VBIOS[0x48]; 2728 bios_header+=(((int)info->VBIOS[0x49]+0)<<8); 2729 2730 mm_table=info->VBIOS[bios_header+0x38]; 2731 if(mm_table==0) 2732 { 2733 xf86DrvMsg(pScrn->scrnIndex,X_INFO,"No MM_TABLE found - assuming CARD is not TV-in capable.\n"); 2734 info->MM_TABLE_valid = FALSE; 2735 return TRUE; 2736 } 2737 mm_table+=(((int)info->VBIOS[bios_header+0x39]+0)<<8)-2; 2738 2739 if(mm_table>0) 2740 { 2741 memcpy(&(info->MM_TABLE), &(info->VBIOS[mm_table]), sizeof(info->MM_TABLE)); 2742 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "MM_TABLE: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", 2743 info->MM_TABLE.table_revision, 2744 info->MM_TABLE.table_size, 2745 info->MM_TABLE.tuner_type, 2746 info->MM_TABLE.audio_chip, 2747 info->MM_TABLE.product_id, 2748 info->MM_TABLE.tuner_voltage_teletext_fm, 2749 info->MM_TABLE.i2s_config, 2750 info->MM_TABLE.video_decoder_type, 2751 info->MM_TABLE.video_decoder_host_config, 2752 info->MM_TABLE.input[0], 2753 info->MM_TABLE.input[1], 2754 info->MM_TABLE.input[2], 2755 info->MM_TABLE.input[3], 2756 info->MM_TABLE.input[4]); 2757 2758 /* Is it an MM_TABLE we know about ? */ 2759 if(info->MM_TABLE.table_size != 0xc){ 2760 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "This card has MM_TABLE we do not recognize.\n" 2761 "\t\tIf your card is TV-in capable you will need to specify options RageTheatreCrystal, RageTheatreTunerPort, \n" 2762 "\t\tRageTheatreSVideoPort and TunerType in /etc/X11/xorg.conf.\n" 2763 ); 2764 info->MM_TABLE_valid = FALSE; 2765 return TRUE; 2766 } 2767 info->MM_TABLE_valid = TRUE; 2768 } else { 2769 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "No MM_TABLE found - assuming card is not TV-in capable (mm_table=%d).\n", mm_table); 2770 info->MM_TABLE_valid = FALSE; 2771 } 2772 2773 pll_info_block=info->VBIOS[bios_header+0x30]; 2774 pll_info_block+=(((int)info->VBIOS[bios_header+0x31]+0)<<8); 2775 2776 info->video_decoder_type=info->VBIOS[pll_info_block+0x08]; 2777 info->video_decoder_type+=(((int)info->VBIOS[pll_info_block+0x09]+0)<<8); 2778 2779 return TRUE; 2780} 2781 2782static Bool 2783RADEONPreInitBIOS(ScrnInfoPtr pScrn, xf86Int10InfoPtr pInt10) 2784{ 2785 RADEONInfoPtr info = RADEONPTR(pScrn); 2786 2787 if (!RADEONGetBIOSInfo(pScrn, pInt10)) { 2788 /* Avivo chips require bios for atom */ 2789 if (IS_AVIVO_VARIANT) 2790 return FALSE; 2791 } 2792 return TRUE; 2793} 2794 2795Bool 2796RADEONZaphodStringMatches(ScrnInfoPtr pScrn, const char *s, char *output_name) 2797{ 2798 int i = 0; 2799 char s1[20]; 2800 2801 do { 2802 switch(*s) { 2803 case ',': 2804 s1[i] = '\0'; 2805 i = 0; 2806 if (strcmp(s1, output_name) == 0) 2807 return TRUE; 2808 break; 2809 case ' ': 2810 case '\t': 2811 case '\n': 2812 case '\r': 2813 break; 2814 default: 2815 s1[i] = *s; 2816 i++; 2817 break; 2818 } 2819 } while(*s++); 2820 2821 s1[i] = '\0'; 2822 if (strcmp(s1, output_name) == 0) 2823 return TRUE; 2824 2825 return FALSE; 2826} 2827 2828static void RADEONFixZaphodOutputs(ScrnInfoPtr pScrn) 2829{ 2830 RADEONInfoPtr info = RADEONPTR(pScrn); 2831 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 2832 int o; 2833 char *s; 2834 2835 if ((s = xf86GetOptValString(info->Options, OPTION_ZAPHOD_HEADS))) { 2836 for (o = config->num_output; o > 0; o--) { 2837 if (!RADEONZaphodStringMatches(pScrn, s, config->output[o - 1]->name)) 2838 xf86OutputDestroy(config->output[o - 1]); 2839 } 2840 } else { 2841 if (info->IsPrimary) { 2842 xf86OutputDestroy(config->output[0]); 2843 while (config->num_output > 1) { 2844 xf86OutputDestroy(config->output[1]); 2845 } 2846 } else { 2847 while (config->num_output > 1) { 2848 xf86OutputDestroy(config->output[1]); 2849 } 2850 } 2851 } 2852} 2853 2854static Bool RADEONPreInitControllers(ScrnInfoPtr pScrn) 2855{ 2856 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 2857 RADEONInfoPtr info = RADEONPTR(pScrn); 2858 int i; 2859 int mask; 2860 int found = 0; 2861 2862 if (info->IsPrimary) 2863 mask = 1; 2864 else if (info->IsSecondary) 2865 mask = 2; 2866 else 2867 mask = 3; 2868 2869 if (!RADEONAllocateControllers(pScrn, mask)) 2870 return FALSE; 2871 2872 RADEONGetClockInfo(pScrn); 2873 2874 if (info->IsAtomBios && info->IsIGP) 2875 RADEONATOMGetIGPInfo(pScrn); 2876 2877 if (!RADEONSetupConnectors(pScrn)) { 2878 return FALSE; 2879 } 2880 2881 if (info->IsPrimary || info->IsSecondary) { 2882 /* fixup outputs for zaphod */ 2883 RADEONFixZaphodOutputs(pScrn); 2884 } 2885 2886 RADEONPrintPortMap(pScrn); 2887 2888 info->first_load_no_devices = FALSE; 2889 for (i = 0; i < config->num_output; i++) { 2890 xf86OutputPtr output = config->output[i]; 2891 2892 output->status = (*output->funcs->detect) (output); 2893 ErrorF("finished output detect: %d\n", i); 2894 if (info->IsPrimary || info->IsSecondary) { 2895 if (output->status != XF86OutputStatusConnected) 2896 return FALSE; 2897 } 2898 if (output->status != XF86OutputStatusDisconnected) 2899 found++; 2900 } 2901 2902 if (!found) { 2903 /* nothing connected, light up some defaults so the server comes up */ 2904 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No connected devices found!\n"); 2905 info->first_load_no_devices = TRUE; 2906 } 2907 2908 ErrorF("finished all detect\n"); 2909 return TRUE; 2910} 2911 2912static void 2913RADEONProbeDDC(ScrnInfoPtr pScrn, int indx) 2914{ 2915 vbeInfoPtr pVbe; 2916 2917 if (xf86LoadSubModule(pScrn, "vbe")) { 2918 pVbe = VBEInit(NULL,indx); 2919 ConfiguredMonitor = vbeDoEDID(pVbe, NULL); 2920 } 2921} 2922 2923static Bool 2924RADEONCRTCResize(ScrnInfoPtr scrn, int width, int height) 2925{ 2926 scrn->virtualX = width; 2927 scrn->virtualY = height; 2928 /* RADEONSetPitch(scrn); */ 2929 return TRUE; 2930} 2931 2932static const xf86CrtcConfigFuncsRec RADEONCRTCResizeFuncs = { 2933 RADEONCRTCResize 2934}; 2935 2936Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags) 2937{ 2938 xf86CrtcConfigPtr xf86_config; 2939 RADEONInfoPtr info; 2940 xf86Int10InfoPtr pInt10 = NULL; 2941 void *int10_save = NULL; 2942 const char *s; 2943 RADEONEntPtr pRADEONEnt; 2944 DevUnion* pPriv; 2945 2946 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2947 "RADEONPreInit\n"); 2948 if (pScrn->numEntities != 1) return FALSE; 2949 2950 if (!RADEONGetRec(pScrn)) return FALSE; 2951 2952 info = RADEONPTR(pScrn); 2953 info->MMIO = NULL; 2954 2955 info->IsSecondary = FALSE; 2956 info->IsPrimary = FALSE; 2957 info->kms_enabled = FALSE; 2958 2959 info->pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]); 2960 if (info->pEnt->location.type != BUS_PCI) goto fail; 2961 2962 pPriv = xf86GetEntityPrivate(pScrn->entityList[0], 2963 getRADEONEntityIndex()); 2964 pRADEONEnt = pPriv->ptr; 2965 2966 if(xf86IsEntityShared(pScrn->entityList[0])) 2967 { 2968 if(xf86IsPrimInitDone(pScrn->entityList[0])) 2969 { 2970 info->IsSecondary = TRUE; 2971 pRADEONEnt->pSecondaryScrn = pScrn; 2972 info->SavedReg = &pRADEONEnt->SavedReg; 2973 info->ModeReg = &pRADEONEnt->ModeReg; 2974 } 2975 else 2976 { 2977 info->IsPrimary = TRUE; 2978 xf86SetPrimInitDone(pScrn->entityList[0]); 2979 pRADEONEnt->pPrimaryScrn = pScrn; 2980 pRADEONEnt->HasSecondary = FALSE; 2981 info->SavedReg = &pRADEONEnt->SavedReg; 2982 info->ModeReg = &pRADEONEnt->ModeReg; 2983 } 2984 } else { 2985 info->SavedReg = &pRADEONEnt->SavedReg; 2986 info->ModeReg = &pRADEONEnt->ModeReg; 2987 } 2988 2989 info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index); 2990 info->PciTag = pciTag(PCI_DEV_BUS(info->PciInfo), 2991 PCI_DEV_DEV(info->PciInfo), 2992 PCI_DEV_FUNC(info->PciInfo)); 2993 info->MMIOAddr = PCI_REGION_BASE(info->PciInfo, 2, REGION_MEM) & ~0xffULL; 2994 info->MMIOSize = PCI_REGION_SIZE(info->PciInfo, 2); 2995 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TOTO SAYS %016llx\n", 2996 (unsigned long long)PCI_REGION_BASE(info->PciInfo, 2997 2, REGION_MEM)); 2998 if (info->pEnt->device->IOBase) { 2999 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, 3000 "MMIO address override, using 0x%08lx instead of 0x%016llx\n", 3001 info->pEnt->device->IOBase, 3002 info->MMIOAddr); 3003 info->MMIOAddr = info->pEnt->device->IOBase; 3004 } else if (!info->MMIOAddr) { 3005 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid MMIO address\n"); 3006 goto fail1; 3007 } 3008 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3009 "MMIO registers at 0x%016llx: size %ldKB\n", info->MMIOAddr, info->MMIOSize / 1024); 3010 3011 if(!RADEONMapMMIO(pScrn)) { 3012 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3013 "Memory map the MMIO region failed\n"); 3014 goto fail1; 3015 } 3016 3017#if !defined(__alpha__) 3018 if ( 3019#ifndef XSERVER_LIBPCIACCESS 3020 xf86GetPciDomain(info->PciTag) || 3021#endif 3022 !xf86IsPrimaryPci(info->PciInfo)) 3023 RADEONPreInt10Save(pScrn, &int10_save); 3024#else 3025 /* [Alpha] On the primary, the console already ran the BIOS and we're 3026 * going to run it again - so make sure to "fix up" the card 3027 * so that (1) we can read the BIOS ROM and (2) the BIOS will 3028 * get the memory config right. 3029 */ 3030 RADEONPreInt10Save(pScrn, &int10_save); 3031#endif 3032 3033 if (flags & PROBE_DETECT) { 3034 RADEONProbeDDC(pScrn, info->pEnt->index); 3035 RADEONPostInt10Check(pScrn, int10_save); 3036 if(info->MMIO) RADEONUnmapMMIO(pScrn); 3037 return TRUE; 3038 } 3039 3040 3041 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3042 "PCI bus %d card %d func %d\n", 3043 PCI_DEV_BUS(info->PciInfo), 3044 PCI_DEV_DEV(info->PciInfo), 3045 PCI_DEV_FUNC(info->PciInfo)); 3046 3047#ifndef XSERVER_LIBPCIACCESS 3048 if (xf86RegisterResources(info->pEnt->index, 0, ResExclusive)) 3049 goto fail; 3050 3051 xf86SetOperatingState(resVga, info->pEnt->index, ResUnusedOpr); 3052 3053 pScrn->racMemFlags = RAC_FB | RAC_COLORMAP | RAC_VIEWPORT | RAC_CURSOR; 3054#endif 3055 pScrn->monitor = pScrn->confScreen->monitor; 3056 3057 /* Allocate an xf86CrtcConfig */ 3058 xf86CrtcConfigInit (pScrn, &RADEONCRTCResizeFuncs); 3059 xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 3060 3061 3062 if (!RADEONPreInitVisual(pScrn)) 3063 goto fail; 3064 3065 /* We can't do this until we have a 3066 pScrn->display. */ 3067 xf86CollectOptions(pScrn, NULL); 3068 if (!(info->Options = xalloc(sizeof(RADEONOptions)))) 3069 goto fail; 3070 3071 memcpy(info->Options, RADEONOptions, sizeof(RADEONOptions)); 3072 xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options); 3073 3074 /* By default, don't do VGA IOs on ppc/sparc */ 3075#if defined(__powerpc__) || defined(__sparc__) || !defined(WITH_VGAHW) 3076 info->VGAAccess = FALSE; 3077#else 3078 info->VGAAccess = TRUE; 3079#endif 3080 3081#ifdef WITH_VGAHW 3082 xf86GetOptValBool(info->Options, OPTION_VGA_ACCESS, &info->VGAAccess); 3083 if (info->VGAAccess) { 3084 if (!xf86LoadSubModule(pScrn, "vgahw")) 3085 info->VGAAccess = FALSE; 3086 else { 3087 if (!vgaHWGetHWRec(pScrn)) 3088 info->VGAAccess = FALSE; 3089 } 3090 if (!info->VGAAccess) 3091 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "Loading VGA module failed," 3092 " trying to run without it\n"); 3093 } else 3094 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VGAAccess option set to FALSE," 3095 " VGA module load skipped\n"); 3096 if (info->VGAAccess) 3097 vgaHWGetIOBase(VGAHWPTR(pScrn)); 3098#endif 3099 3100 3101 if (!RADEONPreInitWeight(pScrn)) 3102 goto fail; 3103 3104 info->DispPriority = 1; 3105 if ((s = xf86GetOptValString(info->Options, OPTION_DISP_PRIORITY))) { 3106 if (strcmp(s, "AUTO") == 0) { 3107 info->DispPriority = 1; 3108 } else if (strcmp(s, "BIOS") == 0) { 3109 info->DispPriority = 0; 3110 } else if (strcmp(s, "HIGH") == 0) { 3111 info->DispPriority = 2; 3112 } else 3113 info->DispPriority = 1; 3114 } 3115 3116 if (!RADEONPreInitChipType(pScrn)) 3117 goto fail; 3118 3119 if (!RADEONPreInitInt10(pScrn, &pInt10)) 3120 goto fail; 3121 3122 RADEONPostInt10Check(pScrn, int10_save); 3123 3124 if (!RADEONPreInitBIOS(pScrn, pInt10)) 3125 goto fail; 3126 3127 /* Save BIOS scratch registers */ 3128 RADEONSaveBIOSRegisters(pScrn, info->SavedReg); 3129 3130#ifdef XF86DRI 3131 /* PreInit DRI first of all since we need that for getting a proper 3132 * memory map 3133 */ 3134 info->directRenderingEnabled = RADEONPreInitDRI(pScrn); 3135#endif 3136 if (!info->directRenderingEnabled) { 3137 if (info->ChipFamily >= CHIP_FAMILY_R600) { 3138 info->r600_shadow_fb = TRUE; 3139 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3140 "using shadow framebuffer\n"); 3141 if (!xf86LoadSubModule(pScrn, "shadow")) 3142 info->r600_shadow_fb = FALSE; 3143 } 3144 } 3145 3146 if (!RADEONPreInitVRAM(pScrn)) 3147 goto fail; 3148 3149 RADEONPreInitColorTiling(pScrn); 3150 3151 if (IS_AVIVO_VARIANT) 3152 xf86CrtcSetSizeRange (pScrn, 320, 200, 8192, 8192); 3153 else 3154 xf86CrtcSetSizeRange (pScrn, 320, 200, 4096, 4096); 3155 3156 RADEONPreInitDDC(pScrn); 3157 3158 if (!RADEONPreInitControllers(pScrn)) 3159 goto fail; 3160 3161 if (!xf86InitialConfiguration (pScrn, FALSE)) 3162 { 3163 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No valid modes.\n"); 3164 goto fail; 3165 } 3166 3167 /* fix up cloning on rn50 cards 3168 * since they only have one crtc sometimes the xserver doesn't assign 3169 * a crtc to one of the outputs even though both outputs have common modes 3170 * which results in only one monitor being enabled. Assign a crtc here so 3171 * that both outputs light up. 3172 */ 3173 if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) { 3174 int i; 3175 3176 for (i = 0; i < xf86_config->num_output; i++) { 3177 xf86OutputPtr output = xf86_config->output[i]; 3178 3179 /* XXX: double check crtc mode */ 3180 if ((output->probed_modes != NULL) && (output->crtc == NULL)) 3181 output->crtc = xf86_config->crtc[0]; 3182 } 3183 } 3184 3185 RADEONSetPitch(pScrn); 3186 3187 /* Set display resolution */ 3188 xf86SetDpi(pScrn, 0, 0); 3189 3190 /* Get ScreenInit function */ 3191 if (!xf86LoadSubModule(pScrn, "fb")) return FALSE; 3192 3193 if (!RADEONPreInitGamma(pScrn)) goto fail; 3194 3195 if (!RADEONPreInitCursor(pScrn)) goto fail; 3196 3197 if (!RADEONPreInitAccel(pScrn)) goto fail; 3198 3199 if (!IS_AVIVO_VARIANT) { 3200 if (!RADEONPreInitXv(pScrn)) goto fail; 3201 } 3202 3203 if (!xf86RandR12PreInit (pScrn)) 3204 { 3205 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "RandR initialization failure\n"); 3206 goto fail; 3207 } 3208 3209 if (pScrn->modes == NULL) { 3210 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No modes.\n"); 3211 goto fail; 3212 } 3213 3214 3215 /* Free int10 info */ 3216 if (pInt10) 3217 xf86FreeInt10(pInt10); 3218 3219 if(info->MMIO) RADEONUnmapMMIO(pScrn); 3220 info->MMIO = NULL; 3221 3222 xf86DrvMsg(pScrn->scrnIndex, X_NOTICE, 3223 "MergedFB support has been removed and replaced with" 3224 " xrandr 1.2 support\n"); 3225 3226 return TRUE; 3227 3228fail: 3229 /* Pre-init failed. */ 3230 /* Free the video bios (if applicable) */ 3231 if (info->VBIOS) { 3232 xfree(info->VBIOS); 3233 info->VBIOS = NULL; 3234 } 3235 3236 /* Free int10 info */ 3237 if (pInt10) 3238 xf86FreeInt10(pInt10); 3239 3240#ifdef WITH_VGAHW 3241 if (info->VGAAccess) 3242 vgaHWFreeHWRec(pScrn); 3243#endif 3244 3245 if(info->MMIO) RADEONUnmapMMIO(pScrn); 3246 info->MMIO = NULL; 3247 3248 fail1: 3249 RADEONFreeRec(pScrn); 3250 3251 return FALSE; 3252} 3253 3254/* Load a palette */ 3255static void RADEONLoadPalette(ScrnInfoPtr pScrn, int numColors, 3256 int *indices, LOCO *colors, VisualPtr pVisual) 3257{ 3258 RADEONInfoPtr info = RADEONPTR(pScrn); 3259 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 3260 int i; 3261 int index, j; 3262 uint16_t lut_r[256], lut_g[256], lut_b[256]; 3263 int c; 3264 3265#ifdef XF86DRI 3266 if (info->cp->CPStarted && pScrn->pScreen) DRILock(pScrn->pScreen, 0); 3267#endif 3268 3269 if (info->accelOn && pScrn->pScreen) 3270 RADEON_SYNC(info, pScrn); 3271 3272 { 3273 3274 for (c = 0; c < xf86_config->num_crtc; c++) { 3275 xf86CrtcPtr crtc = xf86_config->crtc[c]; 3276 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 3277 3278 for (i = 0 ; i < 256; i++) { 3279 lut_r[i] = radeon_crtc->lut_r[i] << 6; 3280 lut_g[i] = radeon_crtc->lut_g[i] << 6; 3281 lut_b[i] = radeon_crtc->lut_b[i] << 6; 3282 } 3283 3284 switch (info->CurrentLayout.depth) { 3285 case 15: 3286 for (i = 0; i < numColors; i++) { 3287 index = indices[i]; 3288 for (j = 0; j < 8; j++) { 3289 lut_r[index * 8 + j] = colors[index].red << 6; 3290 lut_g[index * 8 + j] = colors[index].green << 6; 3291 lut_b[index * 8 + j] = colors[index].blue << 6; 3292 } 3293 } 3294 case 16: 3295 for (i = 0; i < numColors; i++) { 3296 index = indices[i]; 3297 3298 if (i <= 31) { 3299 for (j = 0; j < 8; j++) { 3300 lut_r[index * 8 + j] = colors[index].red << 6; 3301 lut_b[index * 8 + j] = colors[index].blue << 6; 3302 } 3303 } 3304 3305 for (j = 0; j < 4; j++) { 3306 lut_g[index * 4 + j] = colors[index].green << 6; 3307 } 3308 } 3309 default: 3310 for (i = 0; i < numColors; i++) { 3311 index = indices[i]; 3312 lut_r[index] = colors[index].red << 6; 3313 lut_g[index] = colors[index].green << 6; 3314 lut_b[index] = colors[index].blue << 6; 3315 } 3316 break; 3317 } 3318 3319 /* Make the change through RandR */ 3320#ifdef RANDR_12_INTERFACE 3321 if (crtc->randr_crtc) 3322 RRCrtcGammaSet(crtc->randr_crtc, lut_r, lut_g, lut_b); 3323 else 3324#endif 3325 crtc->funcs->gamma_set(crtc, lut_r, lut_g, lut_b, 256); 3326 } 3327 } 3328 3329#ifdef XF86DRI 3330 if (info->cp->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen); 3331#endif 3332} 3333 3334static void RADEONBlockHandler(int i, pointer blockData, 3335 pointer pTimeout, pointer pReadmask) 3336{ 3337 ScreenPtr pScreen = screenInfo.screens[i]; 3338 ScrnInfoPtr pScrn = xf86Screens[i]; 3339 RADEONInfoPtr info = RADEONPTR(pScrn); 3340 3341 pScreen->BlockHandler = info->BlockHandler; 3342 (*pScreen->BlockHandler) (i, blockData, pTimeout, pReadmask); 3343 pScreen->BlockHandler = RADEONBlockHandler; 3344 3345 if (info->VideoTimerCallback) 3346 (*info->VideoTimerCallback)(pScrn, currentTime.milliseconds); 3347 3348#if defined(RENDER) && defined(USE_XAA) 3349 if(info->accel_state->RenderCallback) 3350 (*info->accel_state->RenderCallback)(pScrn); 3351#endif 3352 3353#ifdef USE_EXA 3354 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; 3355#endif 3356 3357 if (info->pm.dynamic_mode_enabled) 3358 RADEONPMBlockHandler(pScrn); 3359} 3360 3361static void 3362RADEONInitBIOSRegisters(ScrnInfoPtr pScrn) 3363{ 3364 RADEONInfoPtr info = RADEONPTR(pScrn); 3365 unsigned char *RADEONMMIO = info->MMIO; 3366 RADEONSavePtr save = info->ModeReg; 3367 3368 save->bios_0_scratch = info->SavedReg->bios_0_scratch; 3369 save->bios_1_scratch = info->SavedReg->bios_1_scratch; 3370 save->bios_2_scratch = info->SavedReg->bios_2_scratch; 3371 save->bios_3_scratch = info->SavedReg->bios_3_scratch; 3372 save->bios_4_scratch = info->SavedReg->bios_4_scratch; 3373 save->bios_5_scratch = info->SavedReg->bios_5_scratch; 3374 save->bios_6_scratch = info->SavedReg->bios_6_scratch; 3375 save->bios_7_scratch = info->SavedReg->bios_7_scratch; 3376 3377 if (info->IsAtomBios) { 3378 /* let the bios control the backlight */ 3379 save->bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; 3380 /* tell the bios not to handle mode switching */ 3381 save->bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | 3382 ATOM_S6_ACC_MODE); 3383 3384 if (info->ChipFamily >= CHIP_FAMILY_R600) { 3385 OUTREG(R600_BIOS_2_SCRATCH, save->bios_2_scratch); 3386 OUTREG(R600_BIOS_6_SCRATCH, save->bios_6_scratch); 3387 } else { 3388 OUTREG(RADEON_BIOS_2_SCRATCH, save->bios_2_scratch); 3389 OUTREG(RADEON_BIOS_6_SCRATCH, save->bios_6_scratch); 3390 } 3391 } else { 3392 /* let the bios control the backlight */ 3393 save->bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; 3394 /* tell the bios not to handle mode switching */ 3395 save->bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS | 3396 RADEON_ACC_MODE_CHANGE); 3397 /* tell the bios a driver is loaded */ 3398 save->bios_7_scratch |= RADEON_DRV_LOADED; 3399 3400 OUTREG(RADEON_BIOS_0_SCRATCH, save->bios_0_scratch); 3401 OUTREG(RADEON_BIOS_6_SCRATCH, save->bios_6_scratch); 3402 //OUTREG(RADEON_BIOS_7_SCRATCH, save->bios_7_scratch); 3403 } 3404 3405} 3406 3407 3408/* Called at the start of each server generation. */ 3409Bool RADEONScreenInit(int scrnIndex, ScreenPtr pScreen, 3410 int argc, char **argv) 3411{ 3412 ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; 3413 RADEONInfoPtr info = RADEONPTR(pScrn); 3414 int hasDRI = 0; 3415#ifdef RENDER 3416 int subPixelOrder = SubPixelUnknown; 3417 char* s; 3418#endif 3419 3420 3421 info->accelOn = FALSE; 3422#ifdef USE_XAA 3423 info->accel_state->accel = NULL; 3424#endif 3425#ifdef XF86DRI 3426 pScrn->fbOffset = info->dri->frontOffset; 3427#endif 3428 3429 if (info->IsSecondary) pScrn->fbOffset = pScrn->videoRam * 1024; 3430#ifdef XF86DRI 3431 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3432 "RADEONScreenInit %lx %ld %d\n", 3433 pScrn->memPhysBase, pScrn->fbOffset, info->dri->frontOffset); 3434#else 3435 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3436 "RADEONScreenInit %lx %ld\n", 3437 pScrn->memPhysBase, pScrn->fbOffset); 3438#endif 3439 if (!RADEONMapMem(pScrn)) return FALSE; 3440 3441#ifdef XF86DRI 3442 info->dri->fbX = 0; 3443 info->dri->fbY = 0; 3444#endif 3445 3446 info->PaletteSavedOnVT = FALSE; 3447 3448 info->crtc_on = FALSE; 3449 info->crtc2_on = FALSE; 3450 3451 /* save the real front buffer size 3452 * it changes with randr, rotation, etc. 3453 */ 3454 info->virtualX = pScrn->virtualX; 3455 info->virtualY = pScrn->virtualY; 3456 3457 RADEONSave(pScrn); 3458 3459 /* set initial bios scratch reg state */ 3460 RADEONInitBIOSRegisters(pScrn); 3461 3462 /* blank the outputs/crtcs */ 3463 RADEONBlank(pScrn); 3464 3465 RADEONPMInit(pScrn); 3466 3467 if (info->allowColorTiling && (pScrn->virtualX > info->MaxSurfaceWidth)) { 3468 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3469 "Color tiling not supported with virtual x resolutions larger than %d, disabling\n", 3470 info->MaxSurfaceWidth); 3471 info->allowColorTiling = FALSE; 3472 } 3473 if (info->allowColorTiling) { 3474 info->tilingEnabled = (pScrn->currentMode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; 3475 } 3476 3477 /* Visual setup */ 3478 miClearVisualTypes(); 3479 if (!miSetVisualTypes(pScrn->depth, 3480 miGetDefaultVisualMask(pScrn->depth), 3481 pScrn->rgbBits, 3482 pScrn->defaultVisual)) return FALSE; 3483 miSetPixmapDepths (); 3484 3485#ifdef XF86DRI 3486 if (info->directRenderingEnabled) { 3487 MessageType from; 3488 3489 info->dri->depthBits = pScrn->depth; 3490 3491 from = xf86GetOptValInteger(info->Options, OPTION_DEPTH_BITS, 3492 &info->dri->depthBits) 3493 ? X_CONFIG : X_DEFAULT; 3494 3495 if (info->dri->depthBits != 16 && info->dri->depthBits != 24) { 3496 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3497 "Value for Option \"DepthBits\" must be 16 or 24\n"); 3498 info->dri->depthBits = pScrn->depth; 3499 from = X_DEFAULT; 3500 } 3501 3502 xf86DrvMsg(pScrn->scrnIndex, from, 3503 "Using %d bit depth buffer\n", info->dri->depthBits); 3504 } 3505 3506 3507 hasDRI = info->directRenderingEnabled; 3508#endif /* XF86DRI */ 3509 3510 /* Initialize the memory map, this basically calculates the values 3511 * we'll use later on for MC_FB_LOCATION & MC_AGP_LOCATION 3512 */ 3513 RADEONInitMemoryMap(pScrn); 3514 3515 /* empty the surfaces */ 3516 if (info->ChipFamily < CHIP_FAMILY_R600) { 3517 unsigned char *RADEONMMIO = info->MMIO; 3518 unsigned int j; 3519 for (j = 0; j < 8; j++) { 3520 OUTREG(RADEON_SURFACE0_INFO + 16 * j, 0); 3521 OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * j, 0); 3522 OUTREG(RADEON_SURFACE0_UPPER_BOUND + 16 * j, 0); 3523 } 3524 } 3525 3526#ifdef XF86DRI 3527 /* Depth moves are disabled by default since they are extremely slow */ 3528 info->dri->depthMoves = xf86ReturnOptValBool(info->Options, 3529 OPTION_DEPTH_MOVE, FALSE); 3530 if (info->dri->depthMoves && info->allowColorTiling) { 3531 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Enabling depth moves\n"); 3532 } else if (info->dri->depthMoves) { 3533 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3534 "Depth moves don't work without color tiling, disabled\n"); 3535 info->dri->depthMoves = FALSE; 3536 } else { 3537 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3538 "Depth moves disabled by default\n"); 3539 } 3540#endif 3541 3542 /* Initial setup of surfaces */ 3543 if (info->ChipFamily < CHIP_FAMILY_R600) { 3544 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3545 "Setting up initial surfaces\n"); 3546 RADEONChangeSurfaces(pScrn); 3547 } 3548 3549 /* Memory manager setup */ 3550 3551 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3552 "Setting up accel memmap\n"); 3553 3554#ifdef USE_EXA 3555 if (info->useEXA) { 3556#ifdef XF86DRI 3557 if (hasDRI) { 3558 info->accelDFS = xf86ReturnOptValBool(info->Options, OPTION_ACCEL_DFS, 3559 info->cardType != CARD_AGP); 3560 3561 /* Reserve approx. half of offscreen memory for local textures by 3562 * default, can be overridden with Option "FBTexPercent". 3563 * Round down to a whole number of texture regions. 3564 */ 3565 info->dri->textureSize = 50; 3566 3567 if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT, 3568 &(info->dri->textureSize))) { 3569 if (info->dri->textureSize < 0 || info->dri->textureSize > 100) { 3570 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3571 "Illegal texture memory percentage: %dx, setting to default 50%%\n", 3572 info->dri->textureSize); 3573 info->dri->textureSize = 50; 3574 } 3575 } 3576 } 3577#endif /* XF86DRI */ 3578 3579 if (!RADEONSetupMemEXA(pScreen)) 3580 return FALSE; 3581 } 3582#endif 3583 3584#if defined(XF86DRI) && defined(USE_XAA) 3585 if (!info->useEXA && hasDRI) { 3586 info->dri->textureSize = -1; 3587 if (xf86GetOptValInteger(info->Options, OPTION_FBTEX_PERCENT, 3588 &(info->dri->textureSize))) { 3589 if (info->dri->textureSize < 0 || info->dri->textureSize > 100) { 3590 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3591 "Illegal texture memory percentage: %dx, using default behaviour\n", 3592 info->dri->textureSize); 3593 info->dri->textureSize = -1; 3594 } 3595 } 3596 if (!RADEONSetupMemXAA_DRI(scrnIndex, pScreen)) 3597 return FALSE; 3598 pScrn->fbOffset = info->dri->frontOffset; 3599 } 3600#endif 3601 3602#ifdef USE_XAA 3603 if (!info->useEXA && !hasDRI && !RADEONSetupMemXAA(scrnIndex, pScreen)) 3604 return FALSE; 3605#endif 3606 3607 info->accel_state->dst_pitch_offset = 3608 (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64) 3609 << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10)); 3610 3611 /* Setup DRI after visuals have been established, but before fbScreenInit is 3612 * called. fbScreenInit will eventually call the driver's InitGLXVisuals 3613 * call back. */ 3614#ifdef XF86DRI 3615 if (info->directRenderingEnabled) { 3616 /* FIXME: When we move to dynamic allocation of back and depth 3617 * buffers, we will want to revisit the following check for 3 3618 * times the virtual size of the screen below. 3619 */ 3620 int width_bytes = (pScrn->displayWidth * 3621 info->CurrentLayout.pixel_bytes); 3622 int maxy = info->FbMapSize / width_bytes; 3623 3624 if (maxy <= pScrn->virtualY * 3) { 3625 xf86DrvMsg(scrnIndex, X_ERROR, 3626 "Static buffer allocation failed. Disabling DRI.\n"); 3627 xf86DrvMsg(scrnIndex, X_ERROR, 3628 "At least %d kB of video memory needed at this " 3629 "resolution and depth.\n", 3630 (pScrn->displayWidth * pScrn->virtualY * 3631 info->CurrentLayout.pixel_bytes * 3 + 1023) / 1024); 3632 info->directRenderingEnabled = FALSE; 3633 } else { 3634 info->directRenderingEnabled = RADEONDRIScreenInit(pScreen); 3635 } 3636 } 3637 3638 /* Tell DRI about new memory map */ 3639 if (info->directRenderingEnabled && info->dri->newMemoryMap) { 3640 if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_NEW_MEMMAP, 1) < 0) { 3641 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 3642 "[drm] failed to enable new memory map\n"); 3643 RADEONDRICloseScreen(pScreen); 3644 info->directRenderingEnabled = FALSE; 3645 } 3646 } 3647#endif 3648 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3649 "Initializing fb layer\n"); 3650 3651 if (info->r600_shadow_fb) { 3652 info->fb_shadow = xcalloc(1, 3653 pScrn->displayWidth * pScrn->virtualY * 3654 ((pScrn->bitsPerPixel + 7) >> 3)); 3655 if (info->fb_shadow == NULL) { 3656 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3657 "Failed to allocate shadow framebuffer\n"); 3658 info->r600_shadow_fb = FALSE; 3659 } else { 3660 if (!fbScreenInit(pScreen, info->fb_shadow, 3661 pScrn->virtualX, pScrn->virtualY, 3662 pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, 3663 pScrn->bitsPerPixel)) 3664 return FALSE; 3665 } 3666 } 3667 3668 if (info->r600_shadow_fb == FALSE) { 3669 /* Init fb layer */ 3670 if (!fbScreenInit(pScreen, info->FB, 3671 pScrn->virtualX, pScrn->virtualY, 3672 pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, 3673 pScrn->bitsPerPixel)) 3674 return FALSE; 3675 } 3676 3677 xf86SetBlackWhitePixels(pScreen); 3678 3679 if (pScrn->bitsPerPixel > 8) { 3680 VisualPtr visual; 3681 3682 visual = pScreen->visuals + pScreen->numVisuals; 3683 while (--visual >= pScreen->visuals) { 3684 if ((visual->class | DynamicClass) == DirectColor) { 3685 visual->offsetRed = pScrn->offset.red; 3686 visual->offsetGreen = pScrn->offset.green; 3687 visual->offsetBlue = pScrn->offset.blue; 3688 visual->redMask = pScrn->mask.red; 3689 visual->greenMask = pScrn->mask.green; 3690 visual->blueMask = pScrn->mask.blue; 3691 } 3692 } 3693 } 3694 3695 /* Must be after RGB order fixed */ 3696 fbPictureInit (pScreen, 0, 0); 3697 3698#ifdef RENDER 3699 if ((s = xf86GetOptValString(info->Options, OPTION_SUBPIXEL_ORDER))) { 3700 if (strcmp(s, "RGB") == 0) subPixelOrder = SubPixelHorizontalRGB; 3701 else if (strcmp(s, "BGR") == 0) subPixelOrder = SubPixelHorizontalBGR; 3702 else if (strcmp(s, "NONE") == 0) subPixelOrder = SubPixelNone; 3703 PictureSetSubpixelOrder (pScreen, subPixelOrder); 3704 } 3705#endif 3706 3707 pScrn->vtSema = TRUE; 3708 3709 /* restore the memory map here otherwise we may get a hang when 3710 * initializing the drm below 3711 */ 3712 RADEONInitMemMapRegisters(pScrn, info->ModeReg, info); 3713 RADEONRestoreMemMapRegisters(pScrn, info->ModeReg); 3714 3715 /* Backing store setup */ 3716 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3717 "Initializing backing store\n"); 3718 miInitializeBackingStore(pScreen); 3719 xf86SetBackingStore(pScreen); 3720 3721 /* DRI finalisation */ 3722#ifdef XF86DRI 3723 if (info->directRenderingEnabled && 3724 (info->cardType==CARD_PCIE || info->cardType==CARD_PCI) && 3725 info->dri->pKernelDRMVersion->version_minor >= 19) 3726 { 3727 if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_LOCATION, info->dri->pciGartOffset) < 0) 3728 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3729 "[drm] failed set pci gart location\n"); 3730 3731 if (info->dri->pKernelDRMVersion->version_minor >= 26) { 3732 if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_PCIGART_TABLE_SIZE, info->dri->pciGartSize) < 0) 3733 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3734 "[drm] failed set pci gart table size\n"); 3735 } 3736 } 3737 if (info->directRenderingEnabled) { 3738 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3739 "DRI Finishing init !\n"); 3740 info->directRenderingEnabled = RADEONDRIFinishScreenInit(pScreen); 3741 } 3742 if (info->directRenderingEnabled) { 3743 /* DRI final init might have changed the memory map, we need to adjust 3744 * our local image to make sure we restore them properly on mode 3745 * changes or VT switches 3746 */ 3747 RADEONAdjustMemMapRegisters(pScrn, info->ModeReg); 3748 3749 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n"); 3750 3751 /* we might already be in tiled mode, tell drm about it */ 3752 if (info->directRenderingEnabled && info->tilingEnabled) { 3753 if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0) 3754 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3755 "[drm] failed changing tiling status\n"); 3756 } 3757 } else { 3758 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 3759 "Direct rendering disabled\n"); 3760 } 3761#endif 3762 3763 /* Make sure surfaces are allright since DRI setup may have changed them */ 3764 if (info->ChipFamily < CHIP_FAMILY_R600) { 3765 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3766 "Setting up final surfaces\n"); 3767 3768 RADEONChangeSurfaces(pScrn); 3769 } 3770 3771 3772 /* Enable aceleration */ 3773 if (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE)) { 3774 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3775 "Initializing Acceleration\n"); 3776 if (RADEONAccelInit(pScreen)) { 3777 xf86DrvMsg(scrnIndex, X_INFO, "Acceleration enabled\n"); 3778 info->accelOn = TRUE; 3779 } else { 3780 xf86DrvMsg(scrnIndex, X_ERROR, 3781 "Acceleration initialization failed\n"); 3782 xf86DrvMsg(scrnIndex, X_INFO, "Acceleration disabled\n"); 3783 info->accelOn = FALSE; 3784 } 3785 } else { 3786 xf86DrvMsg(scrnIndex, X_INFO, "Acceleration disabled\n"); 3787 info->accelOn = FALSE; 3788 } 3789 3790 /* Init DPMS */ 3791 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3792 "Initializing DPMS\n"); 3793 xf86DPMSInit(pScreen, xf86DPMSSet, 0); 3794 3795 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3796 "Initializing Cursor\n"); 3797 3798 /* Set Silken Mouse */ 3799 xf86SetSilkenMouse(pScreen); 3800 3801 /* Cursor setup */ 3802 miDCInitialize(pScreen, xf86GetPointerScreenFuncs()); 3803 3804 /* Hardware cursor setup */ 3805 if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { 3806 if (RADEONCursorInit(pScreen)) { 3807#ifdef USE_XAA 3808 if (!info->useEXA) { 3809 int width, height; 3810 3811 if (xf86QueryLargestOffscreenArea(pScreen, &width, &height, 3812 0, 0, 0)) { 3813 xf86DrvMsg(scrnIndex, X_INFO, 3814 "Largest offscreen area available: %d x %d\n", 3815 width, height); 3816 } 3817 } 3818#endif /* USE_XAA */ 3819 } else { 3820 xf86DrvMsg(scrnIndex, X_ERROR, 3821 "Hardware cursor initialization failed\n"); 3822 xf86DrvMsg(scrnIndex, X_INFO, "Using software cursor\n"); 3823 } 3824 } else { 3825 xf86DrvMsg(scrnIndex, X_INFO, "Using software cursor\n"); 3826 } 3827 3828 /* DGA setup */ 3829#ifdef XFreeXDGA 3830 xf86DiDGAInit(pScreen, info->LinearAddr + pScrn->fbOffset); 3831#endif 3832 3833 /* Init Xv */ 3834 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3835 "Initializing Xv\n"); 3836 RADEONInitVideo(pScreen); 3837 3838 if (info->r600_shadow_fb == TRUE) { 3839 if (!shadowSetup(pScreen)) { 3840 return FALSE; 3841 } 3842 } 3843 3844 /* Clear the framebuffer */ 3845 memset(info->FB + pScrn->fbOffset, 0, 3846 pScrn->virtualY * pScrn->displayWidth * info->CurrentLayout.pixel_bytes); 3847 3848 pScrn->pScreen = pScreen; 3849 3850 /* set the modes with desired rotation, etc. */ 3851 if (!xf86SetDesiredModes (pScrn)) 3852 return FALSE; 3853 3854 /* Provide SaveScreen & wrap BlockHandler and CloseScreen */ 3855 /* Wrap CloseScreen */ 3856 info->CloseScreen = pScreen->CloseScreen; 3857 pScreen->CloseScreen = RADEONCloseScreen; 3858 pScreen->SaveScreen = RADEONSaveScreen; 3859 info->BlockHandler = pScreen->BlockHandler; 3860 pScreen->BlockHandler = RADEONBlockHandler; 3861 info->CreateScreenResources = pScreen->CreateScreenResources; 3862 pScreen->CreateScreenResources = RADEONCreateScreenResources; 3863 3864 if (!xf86CrtcScreenInit (pScreen)) 3865 return FALSE; 3866 3867 /* Colormap setup */ 3868 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3869 "Initializing color map\n"); 3870 if (!miCreateDefColormap(pScreen)) return FALSE; 3871 /* all radeons support 10 bit CLUTs */ 3872 if (!xf86HandleColormaps(pScreen, 256, 10, 3873 RADEONLoadPalette, NULL, 3874 CMAP_PALETTED_TRUECOLOR 3875#if 0 /* This option messes up text mode! (eich@suse.de) */ 3876 | CMAP_LOAD_EVEN_IF_OFFSCREEN 3877#endif 3878 | CMAP_RELOAD_ON_MODE_SWITCH)) return FALSE; 3879 3880 /* Note unused options */ 3881 if (serverGeneration == 1) 3882 xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options); 3883 3884 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 3885 "RADEONScreenInit finished\n"); 3886 3887 return TRUE; 3888} 3889 3890/* Write memory mapping registers */ 3891void RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn, 3892 RADEONSavePtr restore) 3893{ 3894 RADEONInfoPtr info = RADEONPTR(pScrn); 3895 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 3896 unsigned char *RADEONMMIO = info->MMIO; 3897 int timeout; 3898 uint32_t mc_fb_loc, mc_agp_loc, mc_agp_loc_hi; 3899 3900 radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &mc_fb_loc, 3901 &mc_agp_loc, &mc_agp_loc_hi); 3902 3903 if (info->IsSecondary) 3904 return; 3905 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3906 "RADEONRestoreMemMapRegisters() : \n"); 3907 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3908 " MC_FB_LOCATION : 0x%08x 0x%08x\n", 3909 (unsigned)restore->mc_fb_location, (unsigned int)mc_fb_loc); 3910 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 3911 " MC_AGP_LOCATION : 0x%08x\n", 3912 (unsigned)restore->mc_agp_location); 3913 3914 if (IS_DCE4_VARIANT) { 3915 if (mc_fb_loc != restore->mc_fb_location || 3916 mc_agp_loc != restore->mc_agp_location) { 3917 uint32_t tmp; 3918 3919 //XXX 3920 //RADEONWaitForIdleMMIO(pScrn); 3921 3922 /* disable VGA rendering core */ 3923 OUTREG(AVIVO_VGA_RENDER_CONTROL, INREG(AVIVO_VGA_RENDER_CONTROL) & ~AVIVO_VGA_VSTATUS_CNTL_MASK); 3924 OUTREG(AVIVO_D1VGA_CONTROL, INREG(AVIVO_D1VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 3925 OUTREG(AVIVO_D2VGA_CONTROL, INREG(AVIVO_D2VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 3926 OUTREG(EVERGREEN_D3VGA_CONTROL, INREG(EVERGREEN_D3VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 3927 OUTREG(EVERGREEN_D4VGA_CONTROL, INREG(EVERGREEN_D4VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 3928 OUTREG(EVERGREEN_D5VGA_CONTROL, INREG(EVERGREEN_D5VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 3929 OUTREG(EVERGREEN_D6VGA_CONTROL, INREG(EVERGREEN_D6VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 3930 3931 /* Stop display & memory access */ 3932 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); 3933 OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN); 3934 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); 3935 3936 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 3937 OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN); 3938 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 3939 3940 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); 3941 OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN); 3942 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); 3943 3944 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 3945 OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN); 3946 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 3947 3948 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); 3949 OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN); 3950 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); 3951 3952 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 3953 OUTREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp & ~EVERGREEN_CRTC_MASTER_EN); 3954 tmp = INREG(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 3955 3956 usleep(10000); 3957 timeout = 0; 3958 while (!(radeon_get_mc_idle(pScrn))) { 3959 if (++timeout > 1000000) { 3960 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3961 "Timeout trying to update memory controller settings !\n"); 3962 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 3963 "You will probably crash now ... \n"); 3964 /* Nothing we can do except maybe try to kill the server, 3965 * let's wait 2 seconds to leave the above message a chance 3966 * to maybe hit the disk and continue trying to setup despite 3967 * the MC being non-idle 3968 */ 3969 usleep(2000000); 3970 } 3971 usleep(10); 3972 } 3973 3974 radeon_write_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, 3975 restore->mc_fb_location, 3976 restore->mc_agp_location, 3977 restore->mc_agp_location_hi); 3978 3979 OUTREG(R600_HDP_NONSURFACE_BASE, (restore->mc_fb_location << 16) & 0xff0000); 3980 3981 } 3982 } else if (IS_AVIVO_VARIANT) { 3983 if (mc_fb_loc != restore->mc_fb_location || 3984 mc_agp_loc != restore->mc_agp_location) { 3985 uint32_t tmp; 3986 3987 RADEONWaitForIdleMMIO(pScrn); 3988 3989 /* disable VGA rendering core */ 3990 OUTREG(AVIVO_VGA_RENDER_CONTROL, INREG(AVIVO_VGA_RENDER_CONTROL) &~ AVIVO_VGA_VSTATUS_CNTL_MASK); 3991 3992 OUTREG(AVIVO_D1VGA_CONTROL, INREG(AVIVO_D1VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 3993 OUTREG(AVIVO_D2VGA_CONTROL, INREG(AVIVO_D2VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); 3994 3995 /* Stop display & memory access */ 3996 tmp = INREG(AVIVO_D1CRTC_CONTROL); 3997 OUTREG(AVIVO_D1CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN); 3998 3999 tmp = INREG(AVIVO_D2CRTC_CONTROL); 4000 OUTREG(AVIVO_D2CRTC_CONTROL, tmp & ~AVIVO_CRTC_EN); 4001 4002 tmp = INREG(AVIVO_D2CRTC_CONTROL); 4003 4004 usleep(10000); 4005 timeout = 0; 4006 while (!(radeon_get_mc_idle(pScrn))) { 4007 if (++timeout > 1000000) { 4008 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4009 "Timeout trying to update memory controller settings !\n"); 4010 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4011 "You will probably crash now ... \n"); 4012 /* Nothing we can do except maybe try to kill the server, 4013 * let's wait 2 seconds to leave the above message a chance 4014 * to maybe hit the disk and continue trying to setup despite 4015 * the MC being non-idle 4016 */ 4017 usleep(2000000); 4018 } 4019 usleep(10); 4020 } 4021 4022 radeon_write_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, 4023 restore->mc_fb_location, 4024 restore->mc_agp_location, 4025 restore->mc_agp_location_hi); 4026 4027 if (info->ChipFamily < CHIP_FAMILY_R600) { 4028 OUTREG(AVIVO_HDP_FB_LOCATION, restore->mc_fb_location); 4029 } else { 4030 OUTREG(R600_HDP_NONSURFACE_BASE, (restore->mc_fb_location << 16) & 0xff0000); 4031 } 4032 4033 /* Reset the engine and HDP */ 4034 if (info->ChipFamily < CHIP_FAMILY_R600) 4035 RADEONEngineReset(pScrn); 4036 } 4037 } else { 4038 4039 /* Write memory mapping registers only if their value change 4040 * since we must ensure no access is done while they are 4041 * reprogrammed 4042 */ 4043 if (mc_fb_loc != restore->mc_fb_location || 4044 mc_agp_loc != restore->mc_agp_location) { 4045 uint32_t crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl; 4046 uint32_t old_mc_status; 4047 4048 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 4049 " Map Changed ! Applying ...\n"); 4050 4051 /* Make sure engine is idle. We assume the CCE is stopped 4052 * at this point 4053 */ 4054 RADEONWaitForIdleMMIO(pScrn); 4055 4056 if (info->IsIGP) 4057 goto igp_no_mcfb; 4058 4059 /* Capture MC_STATUS in case things go wrong ... */ 4060 old_mc_status = INREG(RADEON_MC_STATUS); 4061 4062 /* Stop display & memory access */ 4063 ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL); 4064 OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE); 4065 crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL); 4066 OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS); 4067 crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); 4068 RADEONWaitForVerticalSync(pScrn); 4069 OUTREG(RADEON_CRTC_GEN_CNTL, 4070 (crtc_gen_cntl 4071 & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) 4072 | RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN); 4073 4074 if (pRADEONEnt->HasCRTC2) { 4075 crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); 4076 RADEONWaitForVerticalSync2(pScrn); 4077 OUTREG(RADEON_CRTC2_GEN_CNTL, 4078 (crtc2_gen_cntl 4079 & ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) 4080 | RADEON_CRTC2_DISP_REQ_EN_B); 4081 } 4082 4083 /* Make sure the chip settles down (paranoid !) */ 4084 usleep(100000); 4085 timeout = 0; 4086 while (!(radeon_get_mc_idle(pScrn))) { 4087 if (++timeout > 1000000) { 4088 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4089 "Timeout trying to update memory controller settings !\n"); 4090 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4091 "MC_STATUS = 0x%08x (on entry = 0x%08x)\n", 4092 (unsigned int)INREG(RADEON_MC_STATUS), (unsigned int)old_mc_status); 4093 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4094 "You will probably crash now ... \n"); 4095 /* Nothing we can do except maybe try to kill the server, 4096 * let's wait 2 seconds to leave the above message a chance 4097 * to maybe hit the disk and continue trying to setup despite 4098 * the MC being non-idle 4099 */ 4100 usleep(2000000); 4101 } 4102 usleep(10); 4103 } 4104 4105 /* Update maps, first clearing out AGP to make sure we don't get 4106 * a temporary overlap 4107 */ 4108 OUTREG(RADEON_MC_AGP_LOCATION, 0xfffffffc); 4109 OUTREG(RADEON_MC_FB_LOCATION, restore->mc_fb_location); 4110 radeon_write_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, restore->mc_fb_location, 4111 0xfffffffc, 0); 4112 igp_no_mcfb: 4113 radeon_write_mc_fb_agp_location(pScrn, LOC_AGP, 0, 4114 restore->mc_agp_location, 0); 4115 /* Make sure map fully reached the chip */ 4116 (void)INREG(RADEON_MC_FB_LOCATION); 4117 4118 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 4119 " Map applied, resetting engine ...\n"); 4120 4121 /* Reset the engine and HDP */ 4122 RADEONEngineReset(pScrn); 4123 4124 /* Make sure we have sane offsets before re-enabling the CRTCs, disable 4125 * stereo, clear offsets, and wait for offsets to catch up with hw 4126 */ 4127 4128 OUTREG(RADEON_CRTC_OFFSET_CNTL, RADEON_CRTC_OFFSET_FLIP_CNTL); 4129 OUTREG(RADEON_CRTC_OFFSET, 0); 4130 OUTREG(RADEON_CUR_OFFSET, 0); 4131 timeout = 0; 4132 while(INREG(RADEON_CRTC_OFFSET) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) { 4133 if (timeout++ > 1000000) { 4134 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4135 "Timeout waiting for CRTC offset to update !\n"); 4136 break; 4137 } 4138 usleep(1000); 4139 } 4140 if (pRADEONEnt->HasCRTC2) { 4141 OUTREG(RADEON_CRTC2_OFFSET_CNTL, RADEON_CRTC2_OFFSET_FLIP_CNTL); 4142 OUTREG(RADEON_CRTC2_OFFSET, 0); 4143 OUTREG(RADEON_CUR2_OFFSET, 0); 4144 timeout = 0; 4145 while(INREG(RADEON_CRTC2_OFFSET) & RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET) { 4146 if (timeout++ > 1000000) { 4147 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4148 "Timeout waiting for CRTC2 offset to update !\n"); 4149 break; 4150 } 4151 usleep(1000); 4152 } 4153 } 4154 } 4155 4156 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 4157 "Updating display base addresses...\n"); 4158 4159 OUTREG(RADEON_DISPLAY_BASE_ADDR, restore->display_base_addr); 4160 if (pRADEONEnt->HasCRTC2) 4161 OUTREG(RADEON_DISPLAY2_BASE_ADDR, restore->display2_base_addr); 4162 OUTREG(RADEON_OV0_BASE_ADDR, restore->ov0_base_addr); 4163 (void)INREG(RADEON_OV0_BASE_ADDR); 4164 4165 /* More paranoia delays, wait 100ms */ 4166 usleep(100000); 4167 4168 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 4169 "Memory map updated.\n"); 4170 } 4171} 4172 4173#ifdef XF86DRI 4174static void RADEONAdjustMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) 4175{ 4176 RADEONInfoPtr info = RADEONPTR(pScrn); 4177 uint32_t fb, agp, agp_hi; 4178 int changed = 0; 4179 4180 if (info->IsSecondary) 4181 return; 4182 4183 radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &fb, &agp, &agp_hi); 4184 4185 if (fb != save->mc_fb_location || agp != save->mc_agp_location || 4186 agp_hi != save->mc_agp_location_hi) 4187 changed = 1; 4188 4189 if (changed) { 4190 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 4191 "DRI init changed memory map, adjusting ...\n"); 4192 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 4193 " MC_FB_LOCATION was: 0x%08lx is: 0x%08lx\n", 4194 (long unsigned int)info->mc_fb_location, (long unsigned int)fb); 4195 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 4196 " MC_AGP_LOCATION was: 0x%08lx is: 0x%08lx\n", 4197 (long unsigned int)info->mc_agp_location, (long unsigned int)agp); 4198 info->mc_fb_location = fb; 4199 info->mc_agp_location = agp; 4200 if (info->ChipFamily >= CHIP_FAMILY_R600) 4201 info->fbLocation = (info->mc_fb_location & 0xffff) << 24; 4202 else 4203 info->fbLocation = (info->mc_fb_location & 0xffff) << 16; 4204 4205 info->accel_state->dst_pitch_offset = 4206 (((pScrn->displayWidth * info->CurrentLayout.pixel_bytes / 64) 4207 << 22) | ((info->fbLocation + pScrn->fbOffset) >> 10)); 4208 RADEONInitMemMapRegisters(pScrn, save, info); 4209 RADEONRestoreMemMapRegisters(pScrn, save); 4210 } 4211 4212#ifdef USE_EXA 4213 if (info->accelDFS || (info->ChipFamily >= CHIP_FAMILY_R600)) 4214 { 4215 drm_radeon_getparam_t gp; 4216 int gart_base; 4217 4218 memset(&gp, 0, sizeof(gp)); 4219 gp.param = RADEON_PARAM_GART_BASE; 4220 gp.value = &gart_base; 4221 4222 if (drmCommandWriteRead(info->dri->drmFD, DRM_RADEON_GETPARAM, &gp, 4223 sizeof(gp)) < 0) { 4224 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4225 "Failed to determine GART area MC location, not using " 4226 "accelerated DownloadFromScreen hook!\n"); 4227 info->accelDFS = FALSE; 4228 } else { 4229 info->gartLocation = gart_base; 4230 } 4231 } 4232#endif /* USE_EXA */ 4233} 4234#endif 4235 4236/* restore original surface info (for fb console). */ 4237static void RADEONRestoreSurfaces(ScrnInfoPtr pScrn, RADEONSavePtr restore) 4238{ 4239 RADEONInfoPtr info = RADEONPTR(pScrn); 4240 unsigned char *RADEONMMIO = info->MMIO; 4241 unsigned int surfnr; 4242 4243 for ( surfnr = 0; surfnr < 8; surfnr++ ) { 4244 OUTREG(RADEON_SURFACE0_INFO + 16 * surfnr, restore->surfaces[surfnr][0]); 4245 OUTREG(RADEON_SURFACE0_LOWER_BOUND + 16 * surfnr, restore->surfaces[surfnr][1]); 4246 OUTREG(RADEON_SURFACE0_UPPER_BOUND + 16 * surfnr, restore->surfaces[surfnr][2]); 4247 } 4248} 4249 4250/* save original surface info (for fb console). */ 4251static void RADEONSaveSurfaces(ScrnInfoPtr pScrn, RADEONSavePtr save) 4252{ 4253 RADEONInfoPtr info = RADEONPTR(pScrn); 4254 unsigned char *RADEONMMIO = info->MMIO; 4255 unsigned int surfnr; 4256 4257 for ( surfnr = 0; surfnr < 8; surfnr++ ) { 4258 save->surfaces[surfnr][0] = INREG(RADEON_SURFACE0_INFO + 16 * surfnr); 4259 save->surfaces[surfnr][1] = INREG(RADEON_SURFACE0_LOWER_BOUND + 16 * surfnr); 4260 save->surfaces[surfnr][2] = INREG(RADEON_SURFACE0_UPPER_BOUND + 16 * surfnr); 4261 } 4262} 4263 4264void RADEONChangeSurfaces(ScrnInfoPtr pScrn) 4265{ 4266 /* the idea here is to only set up front buffer as tiled, and back/depth buffer when needed. 4267 Everything else is left as untiled. This means we need to use eplicit src/dst pitch control 4268 when blitting, based on the src/target address, and can no longer use a default offset. 4269 But OTOH we don't need to dynamically change surfaces (for xv for instance), and some 4270 ugly offset / fb reservation (cursor) is gone. And as a bonus, everything actually works... 4271 For simplicity, just always update everything (just let the ioctl fail - could do better). 4272 All surface addresses are relative to RADEON_MC_FB_LOCATION */ 4273 4274 RADEONInfoPtr info = RADEONPTR(pScrn); 4275 int cpp = info->CurrentLayout.pixel_bytes; 4276 /* depth/front/back pitch must be identical (and the same as displayWidth) */ 4277 int width_bytes = pScrn->displayWidth * cpp; 4278 int bufferSize = RADEON_ALIGN((RADEON_ALIGN(pScrn->virtualY, 16)) * width_bytes, 4279 RADEON_GPU_PAGE_SIZE); 4280 unsigned int color_pattern, swap_pattern; 4281 4282 if (!info->allowColorTiling) 4283 return; 4284 4285 swap_pattern = 0; 4286#if X_BYTE_ORDER == X_BIG_ENDIAN 4287 switch (pScrn->bitsPerPixel) { 4288 case 16: 4289 swap_pattern = RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP; 4290 break; 4291 4292 case 32: 4293 swap_pattern = RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP; 4294 break; 4295 } 4296#endif 4297 if (info->ChipFamily < CHIP_FAMILY_R200) { 4298 color_pattern = RADEON_SURF_TILE_COLOR_MACRO; 4299 } else if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { 4300 color_pattern = R300_SURF_TILE_COLOR_MACRO; 4301 } else { 4302 color_pattern = R200_SURF_TILE_COLOR_MACRO; 4303 } 4304#ifdef XF86DRI 4305 if (info->directRenderingInited) { 4306 drm_radeon_surface_free_t drmsurffree; 4307 drm_radeon_surface_alloc_t drmsurfalloc; 4308 int retvalue; 4309 int depthCpp = (info->dri->depthBits - 8) / 4; 4310 int depth_width_bytes = pScrn->displayWidth * depthCpp; 4311 int depthBufferSize = RADEON_ALIGN((RADEON_ALIGN(pScrn->virtualY, 16)) * depth_width_bytes, 4312 RADEON_GPU_PAGE_SIZE); 4313 unsigned int depth_pattern; 4314 4315 drmsurffree.address = info->dri->frontOffset; 4316 retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_FREE, 4317 &drmsurffree, sizeof(drmsurffree)); 4318 4319 if (!((info->ChipFamily == CHIP_FAMILY_RV100) || 4320 (info->ChipFamily == CHIP_FAMILY_RS100) || 4321 (info->ChipFamily == CHIP_FAMILY_RS200))) { 4322 drmsurffree.address = info->dri->depthOffset; 4323 retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_FREE, 4324 &drmsurffree, sizeof(drmsurffree)); 4325 } 4326 4327 if (!info->dri->noBackBuffer) { 4328 drmsurffree.address = info->dri->backOffset; 4329 retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_FREE, 4330 &drmsurffree, sizeof(drmsurffree)); 4331 } 4332 4333 drmsurfalloc.size = bufferSize; 4334 drmsurfalloc.address = info->dri->frontOffset; 4335 drmsurfalloc.flags = swap_pattern; 4336 4337 if (info->tilingEnabled) { 4338 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) 4339 drmsurfalloc.flags |= (width_bytes / 8) | color_pattern; 4340 else 4341 drmsurfalloc.flags |= (width_bytes / 16) | color_pattern; 4342 } 4343 retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_ALLOC, 4344 &drmsurfalloc, sizeof(drmsurfalloc)); 4345 if (retvalue < 0) 4346 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4347 "drm: could not allocate surface for front buffer!\n"); 4348 4349 if ((info->dri->have3DWindows) && (!info->dri->noBackBuffer)) { 4350 drmsurfalloc.address = info->dri->backOffset; 4351 retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_ALLOC, 4352 &drmsurfalloc, sizeof(drmsurfalloc)); 4353 if (retvalue < 0) 4354 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4355 "drm: could not allocate surface for back buffer!\n"); 4356 } 4357 4358 if (info->ChipFamily < CHIP_FAMILY_R200) { 4359 if (depthCpp == 2) 4360 depth_pattern = RADEON_SURF_TILE_DEPTH_16BPP; 4361 else 4362 depth_pattern = RADEON_SURF_TILE_DEPTH_32BPP; 4363 } else if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { 4364 if (depthCpp == 2) 4365 depth_pattern = R300_SURF_TILE_COLOR_MACRO; 4366 else 4367 depth_pattern = R300_SURF_TILE_COLOR_MACRO | R300_SURF_TILE_DEPTH_32BPP; 4368 } else { 4369 if (depthCpp == 2) 4370 depth_pattern = R200_SURF_TILE_DEPTH_16BPP; 4371 else 4372 depth_pattern = R200_SURF_TILE_DEPTH_32BPP; 4373 } 4374 4375 /* rv100 and probably the derivative igps don't have depth tiling on all the time? */ 4376 if (info->dri->have3DWindows && 4377 (!((info->ChipFamily == CHIP_FAMILY_RV100) || 4378 (info->ChipFamily == CHIP_FAMILY_RS100) || 4379 (info->ChipFamily == CHIP_FAMILY_RS200)))) { 4380 drm_radeon_surface_alloc_t drmsurfalloc; 4381 drmsurfalloc.size = depthBufferSize; 4382 drmsurfalloc.address = info->dri->depthOffset; 4383 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) 4384 drmsurfalloc.flags = swap_pattern | (depth_width_bytes / 8) | depth_pattern; 4385 else 4386 drmsurfalloc.flags = swap_pattern | (depth_width_bytes / 16) | depth_pattern; 4387 retvalue = drmCommandWrite(info->dri->drmFD, DRM_RADEON_SURF_ALLOC, 4388 &drmsurfalloc, sizeof(drmsurfalloc)); 4389 if (retvalue < 0) 4390 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 4391 "drm: could not allocate surface for depth buffer!\n"); 4392 } 4393 } 4394 else 4395#endif 4396 { 4397 unsigned int surf_info = swap_pattern; 4398 unsigned char *RADEONMMIO = info->MMIO; 4399 /* we don't need anything like WaitForFifo, no? */ 4400 if (info->tilingEnabled) { 4401 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) 4402 surf_info |= (width_bytes / 8) | color_pattern; 4403 else 4404 surf_info |= (width_bytes / 16) | color_pattern; 4405 } 4406 OUTREG(RADEON_SURFACE0_INFO, surf_info); 4407 OUTREG(RADEON_SURFACE0_LOWER_BOUND, 0); 4408 OUTREG(RADEON_SURFACE0_UPPER_BOUND, bufferSize - 1); 4409/* xf86DrvMsg(pScrn->scrnIndex, X_INFO, 4410 "surface0 set to %x, LB 0x%x UB 0x%x\n", 4411 surf_info, 0, bufferSize - 1024);*/ 4412 } 4413 4414 /* Update surface images */ 4415 if (info->ChipFamily < CHIP_FAMILY_R600) 4416 RADEONSaveSurfaces(pScrn, info->ModeReg); 4417} 4418 4419/* Read memory map */ 4420static void RADEONSaveMemMapRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) 4421{ 4422 RADEONInfoPtr info = RADEONPTR(pScrn); 4423 unsigned char *RADEONMMIO = info->MMIO; 4424 4425 radeon_read_mc_fb_agp_location(pScrn, LOC_FB | LOC_AGP, &save->mc_fb_location, 4426 &save->mc_agp_location, &save->mc_agp_location_hi); 4427 4428 if (!IS_AVIVO_VARIANT) { 4429 save->display_base_addr = INREG(RADEON_DISPLAY_BASE_ADDR); 4430 save->display2_base_addr = INREG(RADEON_DISPLAY2_BASE_ADDR); 4431 save->ov0_base_addr = INREG(RADEON_OV0_BASE_ADDR); 4432 } 4433} 4434 4435 4436#if 0 4437/* Read palette data */ 4438static void RADEONSavePalette(ScrnInfoPtr pScrn, RADEONSavePtr save) 4439{ 4440 RADEONInfoPtr info = RADEONPTR(pScrn); 4441 unsigned char *RADEONMMIO = info->MMIO; 4442 int i; 4443 4444#ifdef ENABLE_FLAT_PANEL 4445 /* Select palette 0 (main CRTC) if using FP-enabled chip */ 4446 /* if (info->Port1 == MT_DFP) PAL_SELECT(1); */ 4447#endif 4448 PAL_SELECT(1); 4449 INPAL_START(0); 4450 for (i = 0; i < 256; i++) save->palette2[i] = INPAL_NEXT(); 4451 PAL_SELECT(0); 4452 INPAL_START(0); 4453 for (i = 0; i < 256; i++) save->palette[i] = INPAL_NEXT(); 4454 save->palette_valid = TRUE; 4455} 4456#endif 4457 4458static void 4459avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save) 4460{ 4461 RADEONInfoPtr info = RADEONPTR(pScrn); 4462 unsigned char *RADEONMMIO = info->MMIO; 4463 struct avivo_state *state = &save->avivo; 4464 int i, j; 4465 4466 // state->vga_memory_base = INREG(AVIVO_VGA_MEMORY_BASE); 4467 // state->vga_fb_start = INREG(AVIVO_VGA_FB_START); 4468 state->vga1_cntl = INREG(AVIVO_D1VGA_CONTROL); 4469 state->vga2_cntl = INREG(AVIVO_D2VGA_CONTROL); 4470 state->vga_render_control = INREG(AVIVO_VGA_RENDER_CONTROL); 4471 4472 state->crtc_master_en = INREG(AVIVO_DC_CRTC_MASTER_EN); 4473 state->crtc_tv_control = INREG(AVIVO_DC_CRTC_TV_CONTROL); 4474 state->dc_lb_memory_split = INREG(AVIVO_DC_LB_MEMORY_SPLIT); 4475 4476 state->pll1.ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC); 4477 state->pll1.ref_div = INREG(AVIVO_EXT1_PPLL_REF_DIV); 4478 state->pll1.fb_div = INREG(AVIVO_EXT1_PPLL_FB_DIV); 4479 state->pll1.post_div_src = INREG(AVIVO_EXT1_PPLL_POST_DIV_SRC); 4480 state->pll1.post_div = INREG(AVIVO_EXT1_PPLL_POST_DIV); 4481 state->pll1.ext_ppll_cntl = INREG(AVIVO_EXT1_PPLL_CNTL); 4482 state->pll1.pll_cntl = INREG(AVIVO_P1PLL_CNTL); 4483 state->pll1.int_ss_cntl = INREG(AVIVO_P1PLL_INT_SS_CNTL); 4484 4485 state->pll2.ref_div_src = INREG(AVIVO_EXT1_PPLL_REF_DIV_SRC); 4486 state->pll2.ref_div = INREG(AVIVO_EXT2_PPLL_REF_DIV); 4487 state->pll2.fb_div = INREG(AVIVO_EXT2_PPLL_FB_DIV); 4488 state->pll2.post_div_src = INREG(AVIVO_EXT2_PPLL_POST_DIV_SRC); 4489 state->pll2.post_div = INREG(AVIVO_EXT2_PPLL_POST_DIV); 4490 state->pll2.ext_ppll_cntl = INREG(AVIVO_EXT2_PPLL_CNTL); 4491 state->pll2.pll_cntl = INREG(AVIVO_P2PLL_CNTL); 4492 state->pll2.int_ss_cntl = INREG(AVIVO_P2PLL_INT_SS_CNTL); 4493 4494 state->vga25_ppll.ref_div_src = INREG(AVIVO_VGA25_PPLL_REF_DIV_SRC); 4495 state->vga25_ppll.ref_div = INREG(AVIVO_VGA25_PPLL_REF_DIV); 4496 state->vga25_ppll.fb_div = INREG(AVIVO_VGA25_PPLL_FB_DIV); 4497 state->vga25_ppll.post_div_src = INREG(AVIVO_VGA25_PPLL_POST_DIV_SRC); 4498 state->vga25_ppll.post_div = INREG(AVIVO_VGA25_PPLL_POST_DIV); 4499 state->vga25_ppll.pll_cntl = INREG(AVIVO_VGA25_PPLL_CNTL); 4500 4501 state->vga28_ppll.ref_div_src = INREG(AVIVO_VGA28_PPLL_REF_DIV_SRC); 4502 state->vga28_ppll.ref_div = INREG(AVIVO_VGA28_PPLL_REF_DIV); 4503 state->vga28_ppll.fb_div = INREG(AVIVO_VGA28_PPLL_FB_DIV); 4504 state->vga28_ppll.post_div_src = INREG(AVIVO_VGA28_PPLL_POST_DIV_SRC); 4505 state->vga28_ppll.post_div = INREG(AVIVO_VGA28_PPLL_POST_DIV); 4506 state->vga28_ppll.pll_cntl = INREG(AVIVO_VGA28_PPLL_CNTL); 4507 4508 state->vga41_ppll.ref_div_src = INREG(AVIVO_VGA41_PPLL_REF_DIV_SRC); 4509 state->vga41_ppll.ref_div = INREG(AVIVO_VGA41_PPLL_REF_DIV); 4510 state->vga41_ppll.fb_div = INREG(AVIVO_VGA41_PPLL_FB_DIV); 4511 state->vga41_ppll.post_div_src = INREG(AVIVO_VGA41_PPLL_POST_DIV_SRC); 4512 state->vga41_ppll.post_div = INREG(AVIVO_VGA41_PPLL_POST_DIV); 4513 state->vga41_ppll.pll_cntl = INREG(AVIVO_VGA41_PPLL_CNTL); 4514 4515 state->crtc1.pll_source = INREG(AVIVO_PCLK_CRTC1_CNTL); 4516 4517 state->crtc1.h_total = INREG(AVIVO_D1CRTC_H_TOTAL); 4518 state->crtc1.h_blank_start_end = INREG(AVIVO_D1CRTC_H_BLANK_START_END); 4519 state->crtc1.h_sync_a = INREG(AVIVO_D1CRTC_H_SYNC_A); 4520 state->crtc1.h_sync_a_cntl = INREG(AVIVO_D1CRTC_H_SYNC_A_CNTL); 4521 state->crtc1.h_sync_b = INREG(AVIVO_D1CRTC_H_SYNC_B); 4522 state->crtc1.h_sync_b_cntl = INREG(AVIVO_D1CRTC_H_SYNC_B_CNTL); 4523 4524 state->crtc1.v_total = INREG(AVIVO_D1CRTC_V_TOTAL); 4525 state->crtc1.v_blank_start_end = INREG(AVIVO_D1CRTC_V_BLANK_START_END); 4526 state->crtc1.v_sync_a = INREG(AVIVO_D1CRTC_V_SYNC_A); 4527 state->crtc1.v_sync_a_cntl = INREG(AVIVO_D1CRTC_V_SYNC_A_CNTL); 4528 state->crtc1.v_sync_b = INREG(AVIVO_D1CRTC_V_SYNC_B); 4529 state->crtc1.v_sync_b_cntl = INREG(AVIVO_D1CRTC_V_SYNC_B_CNTL); 4530 4531 state->crtc1.control = INREG(AVIVO_D1CRTC_CONTROL); 4532 state->crtc1.blank_control = INREG(AVIVO_D1CRTC_BLANK_CONTROL); 4533 state->crtc1.interlace_control = INREG(AVIVO_D1CRTC_INTERLACE_CONTROL); 4534 state->crtc1.stereo_control = INREG(AVIVO_D1CRTC_STEREO_CONTROL); 4535 4536 state->crtc1.cursor_control = INREG(AVIVO_D1CUR_CONTROL); 4537 4538 state->grph1.enable = INREG(AVIVO_D1GRPH_ENABLE); 4539 state->grph1.control = INREG(AVIVO_D1GRPH_CONTROL); 4540 state->grph1.control = INREG(AVIVO_D1GRPH_CONTROL); 4541 state->grph1.prim_surf_addr = INREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS); 4542 state->grph1.sec_surf_addr = INREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS); 4543 state->grph1.pitch = INREG(AVIVO_D1GRPH_PITCH); 4544 state->grph1.x_offset = INREG(AVIVO_D1GRPH_SURFACE_OFFSET_X); 4545 state->grph1.y_offset = INREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y); 4546 state->grph1.x_start = INREG(AVIVO_D1GRPH_X_START); 4547 state->grph1.y_start = INREG(AVIVO_D1GRPH_Y_START); 4548 state->grph1.x_end = INREG(AVIVO_D1GRPH_X_END); 4549 state->grph1.y_end = INREG(AVIVO_D1GRPH_Y_END); 4550 4551 state->grph1.desktop_height = INREG(AVIVO_D1MODE_DESKTOP_HEIGHT); 4552 state->grph1.viewport_start = INREG(AVIVO_D1MODE_VIEWPORT_START); 4553 state->grph1.viewport_size = INREG(AVIVO_D1MODE_VIEWPORT_SIZE); 4554 state->grph1.mode_data_format = INREG(AVIVO_D1MODE_DATA_FORMAT); 4555 4556 state->crtc2.pll_source = INREG(AVIVO_PCLK_CRTC2_CNTL); 4557 4558 state->crtc2.h_total = INREG(AVIVO_D2CRTC_H_TOTAL); 4559 state->crtc2.h_blank_start_end = INREG(AVIVO_D2CRTC_H_BLANK_START_END); 4560 state->crtc2.h_sync_a = INREG(AVIVO_D2CRTC_H_SYNC_A); 4561 state->crtc2.h_sync_a_cntl = INREG(AVIVO_D2CRTC_H_SYNC_A_CNTL); 4562 state->crtc2.h_sync_b = INREG(AVIVO_D2CRTC_H_SYNC_B); 4563 state->crtc2.h_sync_b_cntl = INREG(AVIVO_D2CRTC_H_SYNC_B_CNTL); 4564 4565 state->crtc2.v_total = INREG(AVIVO_D2CRTC_V_TOTAL); 4566 state->crtc2.v_blank_start_end = INREG(AVIVO_D2CRTC_V_BLANK_START_END); 4567 state->crtc2.v_sync_a = INREG(AVIVO_D2CRTC_V_SYNC_A); 4568 state->crtc2.v_sync_a_cntl = INREG(AVIVO_D2CRTC_V_SYNC_A_CNTL); 4569 state->crtc2.v_sync_b = INREG(AVIVO_D2CRTC_V_SYNC_B); 4570 state->crtc2.v_sync_b_cntl = INREG(AVIVO_D2CRTC_V_SYNC_B_CNTL); 4571 4572 state->crtc2.control = INREG(AVIVO_D2CRTC_CONTROL); 4573 state->crtc2.blank_control = INREG(AVIVO_D2CRTC_BLANK_CONTROL); 4574 state->crtc2.interlace_control = INREG(AVIVO_D2CRTC_INTERLACE_CONTROL); 4575 state->crtc2.stereo_control = INREG(AVIVO_D2CRTC_STEREO_CONTROL); 4576 4577 state->crtc2.cursor_control = INREG(AVIVO_D2CUR_CONTROL); 4578 4579 state->grph2.enable = INREG(AVIVO_D2GRPH_ENABLE); 4580 state->grph2.control = INREG(AVIVO_D2GRPH_CONTROL); 4581 state->grph2.control = INREG(AVIVO_D2GRPH_CONTROL); 4582 state->grph2.prim_surf_addr = INREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS); 4583 state->grph2.sec_surf_addr = INREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS); 4584 state->grph2.pitch = INREG(AVIVO_D2GRPH_PITCH); 4585 state->grph2.x_offset = INREG(AVIVO_D2GRPH_SURFACE_OFFSET_X); 4586 state->grph2.y_offset = INREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y); 4587 state->grph2.x_start = INREG(AVIVO_D2GRPH_X_START); 4588 state->grph2.y_start = INREG(AVIVO_D2GRPH_Y_START); 4589 state->grph2.x_end = INREG(AVIVO_D2GRPH_X_END); 4590 state->grph2.y_end = INREG(AVIVO_D2GRPH_Y_END); 4591 4592 state->grph2.desktop_height = INREG(AVIVO_D2MODE_DESKTOP_HEIGHT); 4593 state->grph2.viewport_start = INREG(AVIVO_D2MODE_VIEWPORT_START); 4594 state->grph2.viewport_size = INREG(AVIVO_D2MODE_VIEWPORT_SIZE); 4595 state->grph2.mode_data_format = INREG(AVIVO_D2MODE_DATA_FORMAT); 4596 4597 if (IS_DCE3_VARIANT) { 4598 /* save DVOA regs */ 4599 state->dvoa[0] = INREG(0x7080); 4600 state->dvoa[1] = INREG(0x7084); 4601 state->dvoa[2] = INREG(0x708c); 4602 state->dvoa[3] = INREG(0x7090); 4603 state->dvoa[4] = INREG(0x7094); 4604 state->dvoa[5] = INREG(0x70ac); 4605 state->dvoa[6] = INREG(0x70b0); 4606 4607 j = 0; 4608 /* save DAC regs */ 4609 for (i = 0x7000; i <= 0x7040; i += 4) { 4610 state->daca[j] = INREG(i); 4611 state->dacb[j] = INREG(i + 0x100); 4612 j++; 4613 } 4614 for (i = 0x7058; i <= 0x7060; i += 4) { 4615 state->daca[j] = INREG(i); 4616 state->dacb[j] = INREG(i + 0x100); 4617 j++; 4618 } 4619 for (i = 0x7068; i <= 0x706c; i += 4) { 4620 state->daca[j] = INREG(i); 4621 state->dacb[j] = INREG(i + 0x100); 4622 j++; 4623 } 4624 for (i = 0x7ef0; i <= 0x7ef8; i += 4) { 4625 state->daca[j] = INREG(i); 4626 state->dacb[j] = INREG(i + 0x100); 4627 j++; 4628 } 4629 state->daca[j] = INREG(0x7050); 4630 state->dacb[j] = INREG(0x7050 + 0x100); 4631 4632 j = 0; 4633 /* save FMT regs */ 4634 for (i = 0x6700; i <= 0x6744; i += 4) { 4635 state->fmt1[j] = INREG(i); 4636 state->fmt2[j] = INREG(i + 0x800); 4637 j++; 4638 } 4639 4640 j = 0; 4641 /* save DIG regs */ 4642 for (i = 0x75a0; i <= 0x75e0; i += 4) { 4643 state->dig1[j] = INREG(i); 4644 state->dig2[j] = INREG(i + 0x400); 4645 j++; 4646 } 4647 for (i = 0x75e8; i <= 0x75ec; i += 4) { 4648 state->dig1[j] = INREG(i); 4649 state->dig2[j] = INREG(i + 0x400); 4650 j++; 4651 } 4652 4653 j = 0; 4654 /* save HDMI regs */ 4655 for (i = 0x7400; i <= 0x741c; i += 4) { 4656 state->hdmi1[j] = INREG(i); 4657 state->hdmi2[j] = INREG(i + 0x400); 4658 j++; 4659 } 4660 for (i = 0x7430; i <= 0x74ec; i += 4) { 4661 state->hdmi1[j] = INREG(i); 4662 state->hdmi2[j] = INREG(i + 0x400); 4663 j++; 4664 } 4665 state->hdmi1[j] = INREG(0x7428); 4666 state->hdmi2[j] = INREG(0x7828); 4667 4668 j = 0; 4669 /* save AUX regs */ 4670 for (i = 0x7780; i <= 0x77b4; i += 4) { 4671 state->aux_cntl1[j] = INREG(i); 4672 state->aux_cntl2[j] = INREG(i + 0x040); 4673 state->aux_cntl3[j] = INREG(i + 0x400); 4674 state->aux_cntl4[j] = INREG(i + 0x440); 4675 if (IS_DCE32_VARIANT) { 4676 state->aux_cntl5[j] = INREG(i + 0x500); 4677 state->aux_cntl6[j] = INREG(i + 0x540); 4678 } 4679 j++; 4680 } 4681 4682 j = 0; 4683 /* save UNIPHY regs */ 4684 if (IS_DCE32_VARIANT) { 4685 for (i = 0x7680; i <= 0x7690; i += 4) { 4686 state->uniphy1[j] = INREG(i); 4687 state->uniphy2[j] = INREG(i + 0x20); 4688 state->uniphy3[j] = INREG(i + 0x400); 4689 state->uniphy4[j] = INREG(i + 0x420); 4690 state->uniphy5[j] = INREG(i + 0x840); 4691 state->uniphy6[j] = INREG(i + 0x940); 4692 j++; 4693 } 4694 for (i = 0x7698; i <= 0x769c; i += 4) { 4695 state->uniphy1[j] = INREG(i); 4696 state->uniphy2[j] = INREG(i + 0x20); 4697 state->uniphy3[j] = INREG(i + 0x400); 4698 state->uniphy4[j] = INREG(i + 0x420); 4699 state->uniphy5[j] = INREG(i + 0x840); 4700 state->uniphy6[j] = INREG(i + 0x940); 4701 j++; 4702 } 4703 } else { 4704 for (i = 0x7ec0; i <= 0x7edc; i += 4) { 4705 state->uniphy1[j] = INREG(i); 4706 state->uniphy2[j] = INREG(i + 0x100); 4707 j++; 4708 } 4709 } 4710 j = 0; 4711 /* save PHY,LINK regs */ 4712 for (i = 0x7f20; i <= 0x7f34; i += 4) { 4713 state->phy[j] = INREG(i); 4714 j++; 4715 } 4716 for (i = 0x7f9c; i <= 0x7fa4; i += 4) { 4717 state->phy[j] = INREG(i); 4718 j++; 4719 } 4720 state->phy[j] = INREG(0x7f40); 4721 4722 j = 0; 4723 /* save LVTMA regs */ 4724 for (i = 0x7f00; i <= 0x7f1c; i += 4) { 4725 state->lvtma[j] = INREG(i); 4726 j++; 4727 } 4728 for (i = 0x7f80; i <= 0x7f98; i += 4) { 4729 state->lvtma[j] = INREG(i); 4730 j++; 4731 } 4732 } else { 4733 j = 0; 4734 /* save DVOA regs */ 4735 for (i = 0x7980; i <= 0x79bc; i += 4) { 4736 state->dvoa[j] = INREG(i); 4737 j++; 4738 } 4739 4740 j = 0; 4741 /* save DAC regs */ 4742 for (i = 0x7800; i <= 0x782c; i += 4) { 4743 state->daca[j] = INREG(i); 4744 state->dacb[j] = INREG(i + 0x200); 4745 j++; 4746 } 4747 for (i = 0x7834; i <= 0x7840; i += 4) { 4748 state->daca[j] = INREG(i); 4749 state->dacb[j] = INREG(i + 0x200); 4750 j++; 4751 } 4752 for (i = 0x7850; i <= 0x7868; i += 4) { 4753 state->daca[j] = INREG(i); 4754 state->dacb[j] = INREG(i + 0x200); 4755 j++; 4756 } 4757 4758 j = 0; 4759 /* save TMDSA regs */ 4760 for (i = 0x7880; i <= 0x78e0; i += 4) { 4761 state->tmdsa[j] = INREG(i); 4762 j++; 4763 } 4764 for (i = 0x7904; i <= 0x7918; i += 4) { 4765 state->tmdsa[j] = INREG(i); 4766 j++; 4767 } 4768 4769 j = 0; 4770 /* save LVTMA regs */ 4771 for (i = 0x7a80; i <= 0x7b18; i += 4) { 4772 state->lvtma[j] = INREG(i); 4773 j++; 4774 } 4775 4776 if ((info->ChipFamily == CHIP_FAMILY_RS600) || 4777 (info->ChipFamily == CHIP_FAMILY_RS690) || 4778 (info->ChipFamily == CHIP_FAMILY_RS740)) { 4779 j = 0; 4780 /* save DDIA regs */ 4781 for (i = 0x7200; i <= 0x7290; i += 4) { 4782 state->ddia[j] = INREG(i); 4783 j++; 4784 } 4785 } 4786 } 4787 4788 /* scalers */ 4789 j = 0; 4790 for (i = 0x6578; i <= 0x65e4; i += 4) { 4791 state->d1scl[j] = INREG(i); 4792 state->d2scl[j] = INREG(i + 0x800); 4793 j++; 4794 } 4795 for (i = 0x6600; i <= 0x662c; i += 4) { 4796 state->d1scl[j] = INREG(i); 4797 state->d2scl[j] = INREG(i + 0x800); 4798 j++; 4799 } 4800 j = 0; 4801 for (i = 0x66e8; i <= 0x66fc; i += 4) { 4802 state->dxscl[j] = INREG(i); 4803 j++; 4804 } 4805 state->dxscl[6] = INREG(0x6e30); 4806 state->dxscl[7] = INREG(0x6e34); 4807 4808 if (state->crtc1.control & AVIVO_CRTC_EN) 4809 info->crtc_on = TRUE; 4810 4811 if (state->crtc2.control & AVIVO_CRTC_EN) 4812 info->crtc2_on = TRUE; 4813 4814} 4815 4816static void 4817avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore) 4818{ 4819 RADEONInfoPtr info = RADEONPTR(pScrn); 4820 unsigned char *RADEONMMIO = info->MMIO; 4821 struct avivo_state *state = &restore->avivo; 4822 int i, j; 4823 4824 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "avivo_restore !\n"); 4825 4826 /* Disable VGA control for now.. maybe needs to be changed */ 4827 OUTREG(AVIVO_D1VGA_CONTROL, 0); 4828 OUTREG(AVIVO_D2VGA_CONTROL, 0); 4829 4830 /* Disable CRTCs */ 4831 OUTREG(AVIVO_D1CRTC_CONTROL, 4832 (INREG(AVIVO_D1CRTC_CONTROL) & ~0x300) | 0x01000000); 4833 OUTREG(AVIVO_D2CRTC_CONTROL, 4834 (INREG(AVIVO_D2CRTC_CONTROL) & ~0x300) | 0x01000000); 4835 OUTREG(AVIVO_D1CRTC_CONTROL, 4836 INREG(AVIVO_D1CRTC_CONTROL) & ~0x1); 4837 OUTREG(AVIVO_D2CRTC_CONTROL, 4838 INREG(AVIVO_D2CRTC_CONTROL) & ~0x1); 4839 OUTREG(AVIVO_D1CRTC_CONTROL, 4840 INREG(AVIVO_D1CRTC_CONTROL) | 0x100); 4841 OUTREG(AVIVO_D2CRTC_CONTROL, 4842 INREG(AVIVO_D2CRTC_CONTROL) | 0x100); 4843 4844 /* Lock graph registers */ 4845 OUTREG(AVIVO_D1GRPH_UPDATE, AVIVO_D1GRPH_UPDATE_LOCK); 4846 OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, state->grph1.prim_surf_addr); 4847 OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS, state->grph1.sec_surf_addr); 4848 OUTREG(AVIVO_D1GRPH_CONTROL, state->grph1.control); 4849 OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X, state->grph1.x_offset); 4850 OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y, state->grph1.y_offset); 4851 OUTREG(AVIVO_D1GRPH_X_START, state->grph1.x_start); 4852 OUTREG(AVIVO_D1GRPH_Y_START, state->grph1.y_start); 4853 OUTREG(AVIVO_D1GRPH_X_END, state->grph1.x_end); 4854 OUTREG(AVIVO_D1GRPH_Y_END, state->grph1.y_end); 4855 OUTREG(AVIVO_D1GRPH_PITCH, state->grph1.pitch); 4856 OUTREG(AVIVO_D1GRPH_ENABLE, state->grph1.enable); 4857 OUTREG(AVIVO_D1GRPH_UPDATE, 0); 4858 4859 OUTREG(AVIVO_D2GRPH_UPDATE, AVIVO_D1GRPH_UPDATE_LOCK); 4860 OUTREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, state->grph2.prim_surf_addr); 4861 OUTREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS, state->grph2.sec_surf_addr); 4862 OUTREG(AVIVO_D2GRPH_CONTROL, state->grph2.control); 4863 OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_X, state->grph2.x_offset); 4864 OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y, state->grph2.y_offset); 4865 OUTREG(AVIVO_D2GRPH_X_START, state->grph2.x_start); 4866 OUTREG(AVIVO_D2GRPH_Y_START, state->grph2.y_start); 4867 OUTREG(AVIVO_D2GRPH_X_END, state->grph2.x_end); 4868 OUTREG(AVIVO_D2GRPH_Y_END, state->grph2.y_end); 4869 OUTREG(AVIVO_D2GRPH_PITCH, state->grph2.pitch); 4870 OUTREG(AVIVO_D2GRPH_ENABLE, state->grph2.enable); 4871 OUTREG(AVIVO_D2GRPH_UPDATE, 0); 4872 4873 /* Whack some mode regs too */ 4874 OUTREG(AVIVO_D1SCL_UPDATE, AVIVO_D1SCL_UPDATE_LOCK); 4875 OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT, state->grph1.desktop_height); 4876 OUTREG(AVIVO_D1MODE_VIEWPORT_START, state->grph1.viewport_start); 4877 OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE, state->grph1.viewport_size); 4878 OUTREG(AVIVO_D1MODE_DATA_FORMAT, state->grph1.mode_data_format); 4879 OUTREG(AVIVO_D1SCL_UPDATE, 0); 4880 4881 OUTREG(AVIVO_D2SCL_UPDATE, AVIVO_D1SCL_UPDATE_LOCK); 4882 OUTREG(AVIVO_D2MODE_DESKTOP_HEIGHT, state->grph2.desktop_height); 4883 OUTREG(AVIVO_D2MODE_VIEWPORT_START, state->grph2.viewport_start); 4884 OUTREG(AVIVO_D2MODE_VIEWPORT_SIZE, state->grph2.viewport_size); 4885 OUTREG(AVIVO_D2MODE_DATA_FORMAT, state->grph2.mode_data_format); 4886 OUTREG(AVIVO_D2SCL_UPDATE, 0); 4887 4888 /* Set the PLL */ 4889 OUTREG(AVIVO_EXT1_PPLL_REF_DIV_SRC, state->pll1.ref_div_src); 4890 OUTREG(AVIVO_EXT1_PPLL_REF_DIV, state->pll1.ref_div); 4891 OUTREG(AVIVO_EXT1_PPLL_FB_DIV, state->pll1.fb_div); 4892 OUTREG(AVIVO_EXT1_PPLL_POST_DIV_SRC, state->pll1.post_div_src); 4893 OUTREG(AVIVO_EXT1_PPLL_POST_DIV, state->pll1.post_div); 4894 OUTREG(AVIVO_EXT1_PPLL_CNTL, state->pll1.ext_ppll_cntl); 4895 OUTREG(AVIVO_P1PLL_CNTL, state->pll1.pll_cntl); 4896 OUTREG(AVIVO_P1PLL_INT_SS_CNTL, state->pll1.int_ss_cntl); 4897 4898 OUTREG(AVIVO_EXT2_PPLL_REF_DIV_SRC, state->pll2.ref_div_src); 4899 OUTREG(AVIVO_EXT2_PPLL_REF_DIV, state->pll2.ref_div); 4900 OUTREG(AVIVO_EXT2_PPLL_FB_DIV, state->pll2.fb_div); 4901 OUTREG(AVIVO_EXT2_PPLL_POST_DIV_SRC, state->pll2.post_div_src); 4902 OUTREG(AVIVO_EXT2_PPLL_POST_DIV, state->pll2.post_div); 4903 OUTREG(AVIVO_EXT2_PPLL_CNTL, state->pll2.ext_ppll_cntl); 4904 OUTREG(AVIVO_P2PLL_CNTL, state->pll2.pll_cntl); 4905 OUTREG(AVIVO_P2PLL_INT_SS_CNTL, state->pll2.int_ss_cntl); 4906 4907 OUTREG(AVIVO_PCLK_CRTC1_CNTL, state->crtc1.pll_source); 4908 OUTREG(AVIVO_PCLK_CRTC2_CNTL, state->crtc2.pll_source); 4909 4910 /* Set the vga PLL */ 4911 OUTREG(AVIVO_VGA25_PPLL_REF_DIV_SRC, state->vga25_ppll.ref_div_src); 4912 OUTREG(AVIVO_VGA25_PPLL_REF_DIV, state->vga25_ppll.ref_div); 4913 OUTREG(AVIVO_VGA25_PPLL_FB_DIV, state->vga25_ppll.fb_div); 4914 OUTREG(AVIVO_VGA25_PPLL_POST_DIV_SRC, state->vga25_ppll.post_div_src); 4915 OUTREG(AVIVO_VGA25_PPLL_POST_DIV, state->vga25_ppll.post_div); 4916 OUTREG(AVIVO_VGA25_PPLL_CNTL, state->vga25_ppll.pll_cntl); 4917 4918 OUTREG(AVIVO_VGA28_PPLL_REF_DIV_SRC, state->vga28_ppll.ref_div_src); 4919 OUTREG(AVIVO_VGA28_PPLL_REF_DIV, state->vga28_ppll.ref_div); 4920 OUTREG(AVIVO_VGA28_PPLL_FB_DIV, state->vga28_ppll.fb_div); 4921 OUTREG(AVIVO_VGA28_PPLL_POST_DIV_SRC, state->vga28_ppll.post_div_src); 4922 OUTREG(AVIVO_VGA28_PPLL_POST_DIV, state->vga28_ppll.post_div); 4923 OUTREG(AVIVO_VGA28_PPLL_CNTL, state->vga28_ppll.pll_cntl); 4924 4925 OUTREG(AVIVO_VGA41_PPLL_REF_DIV_SRC, state->vga41_ppll.ref_div_src); 4926 OUTREG(AVIVO_VGA41_PPLL_REF_DIV, state->vga41_ppll.ref_div); 4927 OUTREG(AVIVO_VGA41_PPLL_FB_DIV, state->vga41_ppll.fb_div); 4928 OUTREG(AVIVO_VGA41_PPLL_POST_DIV_SRC, state->vga41_ppll.post_div_src); 4929 OUTREG(AVIVO_VGA41_PPLL_POST_DIV, state->vga41_ppll.post_div); 4930 OUTREG(AVIVO_VGA41_PPLL_CNTL, state->vga41_ppll.pll_cntl); 4931 4932 /* Set the CRTC */ 4933 OUTREG(AVIVO_D1CRTC_H_TOTAL, state->crtc1.h_total); 4934 OUTREG(AVIVO_D1CRTC_H_BLANK_START_END, state->crtc1.h_blank_start_end); 4935 OUTREG(AVIVO_D1CRTC_H_SYNC_A, state->crtc1.h_sync_a); 4936 OUTREG(AVIVO_D1CRTC_H_SYNC_A_CNTL, state->crtc1.h_sync_a_cntl); 4937 OUTREG(AVIVO_D1CRTC_H_SYNC_B, state->crtc1.h_sync_b); 4938 OUTREG(AVIVO_D1CRTC_H_SYNC_B_CNTL, state->crtc1.h_sync_b_cntl); 4939 4940 OUTREG(AVIVO_D1CRTC_V_TOTAL, state->crtc1.v_total); 4941 OUTREG(AVIVO_D1CRTC_V_BLANK_START_END, state->crtc1.v_blank_start_end); 4942 OUTREG(AVIVO_D1CRTC_V_SYNC_A, state->crtc1.v_sync_a); 4943 OUTREG(AVIVO_D1CRTC_V_SYNC_A_CNTL, state->crtc1.v_sync_a_cntl); 4944 OUTREG(AVIVO_D1CRTC_V_SYNC_B, state->crtc1.v_sync_b); 4945 OUTREG(AVIVO_D1CRTC_V_SYNC_B_CNTL, state->crtc1.v_sync_b_cntl); 4946 4947 OUTREG(AVIVO_D1CRTC_INTERLACE_CONTROL, state->crtc1.interlace_control); 4948 OUTREG(AVIVO_D1CRTC_STEREO_CONTROL, state->crtc1.stereo_control); 4949 4950 OUTREG(AVIVO_D1CUR_CONTROL, state->crtc1.cursor_control); 4951 4952 /* XXX Fix scaler */ 4953 4954 OUTREG(AVIVO_D2CRTC_H_TOTAL, state->crtc2.h_total); 4955 OUTREG(AVIVO_D2CRTC_H_BLANK_START_END, state->crtc2.h_blank_start_end); 4956 OUTREG(AVIVO_D2CRTC_H_SYNC_A, state->crtc2.h_sync_a); 4957 OUTREG(AVIVO_D2CRTC_H_SYNC_A_CNTL, state->crtc2.h_sync_a_cntl); 4958 OUTREG(AVIVO_D2CRTC_H_SYNC_B, state->crtc2.h_sync_b); 4959 OUTREG(AVIVO_D2CRTC_H_SYNC_B_CNTL, state->crtc2.h_sync_b_cntl); 4960 4961 OUTREG(AVIVO_D2CRTC_V_TOTAL, state->crtc2.v_total); 4962 OUTREG(AVIVO_D2CRTC_V_BLANK_START_END, state->crtc2.v_blank_start_end); 4963 OUTREG(AVIVO_D2CRTC_V_SYNC_A, state->crtc2.v_sync_a); 4964 OUTREG(AVIVO_D2CRTC_V_SYNC_A_CNTL, state->crtc2.v_sync_a_cntl); 4965 OUTREG(AVIVO_D2CRTC_V_SYNC_B, state->crtc2.v_sync_b); 4966 OUTREG(AVIVO_D2CRTC_V_SYNC_B_CNTL, state->crtc2.v_sync_b_cntl); 4967 4968 OUTREG(AVIVO_D2CRTC_INTERLACE_CONTROL, state->crtc2.interlace_control); 4969 OUTREG(AVIVO_D2CRTC_STEREO_CONTROL, state->crtc2.stereo_control); 4970 4971 OUTREG(AVIVO_D2CUR_CONTROL, state->crtc2.cursor_control); 4972 4973 if (IS_DCE3_VARIANT) { 4974 /* DVOA regs */ 4975 OUTREG(0x7080, state->dvoa[0]); 4976 OUTREG(0x7084, state->dvoa[1]); 4977 OUTREG(0x708c, state->dvoa[2]); 4978 OUTREG(0x7090, state->dvoa[3]); 4979 OUTREG(0x7094, state->dvoa[4]); 4980 OUTREG(0x70ac, state->dvoa[5]); 4981 OUTREG(0x70b0, state->dvoa[6]); 4982 4983 j = 0; 4984 /* DAC regs */ 4985 for (i = 0x7000; i <= 0x7040; i += 4) { 4986 OUTREG(i, state->daca[j]); 4987 OUTREG((i + 0x100), state->dacb[j]); 4988 j++; 4989 } 4990 for (i = 0x7058; i <= 0x7060; i += 4) { 4991 OUTREG(i, state->daca[j]); 4992 OUTREG((i + 0x100), state->dacb[j]); 4993 j++; 4994 } 4995 for (i = 0x7068; i <= 0x706c; i += 4) { 4996 OUTREG(i, state->daca[j]); 4997 OUTREG((i + 0x100), state->dacb[j]); 4998 j++; 4999 } 5000 for (i = 0x7ef0; i <= 0x7ef8; i += 4) { 5001 OUTREG(i, state->daca[j]); 5002 OUTREG((i + 0x100), state->dacb[j]); 5003 j++; 5004 } 5005 OUTREG(0x7050, state->daca[j]); 5006 OUTREG((0x7050 + 0x100), state->dacb[j]); 5007 5008 j = 0; 5009 /* FMT regs */ 5010 for (i = 0x6700; i <= 0x6744; i += 4) { 5011 OUTREG(i, state->fmt1[j]); 5012 OUTREG((i + 0x800), state->fmt2[j]); 5013 j++; 5014 } 5015 5016 j = 0; 5017 /* DIG regs */ 5018 for (i = 0x75a0; i <= 0x75e0; i += 4) { 5019 OUTREG(i, state->dig1[j]); 5020 OUTREG((i + 0x400), state->dig2[j]); 5021 j++; 5022 } 5023 for (i = 0x75e8; i <= 0x75ec; i += 4) { 5024 OUTREG(i, state->dig1[j]); 5025 OUTREG((i + 0x400), state->dig2[j]); 5026 j++; 5027 } 5028 5029 j = 0; 5030 /* HDMI regs */ 5031 for (i = 0x7400; i <= 0x741c; i += 4) { 5032 OUTREG(i, state->hdmi1[j]); 5033 OUTREG((i + 0x400), state->hdmi2[j]); 5034 j++; 5035 } 5036 for (i = 0x7430; i <= 0x74ec; i += 4) { 5037 OUTREG(i, state->hdmi1[j]); 5038 OUTREG((i + 0x400), state->hdmi2[j]); 5039 j++; 5040 } 5041 OUTREG(0x7428, state->hdmi1[j]); 5042 OUTREG((0x7428 + 0x400), state->hdmi2[j]); 5043 5044 j = 0; 5045 /* save AUX regs */ 5046 for (i = 0x7780; i <= 0x77b4; i += 4) { 5047 OUTREG(i, state->aux_cntl1[j]); 5048 OUTREG((i + 0x040), state->aux_cntl2[j]); 5049 OUTREG((i + 0x400), state->aux_cntl3[j]); 5050 OUTREG((i + 0x440), state->aux_cntl4[j]); 5051 if (IS_DCE32_VARIANT) { 5052 OUTREG((i + 0x500), state->aux_cntl5[j]); 5053 OUTREG((i + 0x540), state->aux_cntl6[j]); 5054 } 5055 j++; 5056 } 5057 5058 j = 0; 5059 /* save UNIPHY regs */ 5060 if (IS_DCE32_VARIANT) { 5061 for (i = 0x7680; i <= 0x7690; i += 4) { 5062 OUTREG(i, state->uniphy1[j]); 5063 OUTREG((i + 0x20), state->uniphy2[j]); 5064 OUTREG((i + 0x400), state->uniphy3[j]); 5065 OUTREG((i + 0x420), state->uniphy4[j]); 5066 OUTREG((i + 0x840), state->uniphy5[j]); 5067 OUTREG((i + 0x940), state->uniphy6[j]); 5068 j++; 5069 } 5070 for (i = 0x7698; i <= 0x769c; i += 4) { 5071 OUTREG(i, state->uniphy1[j]); 5072 OUTREG((i + 0x20), state->uniphy2[j]); 5073 OUTREG((i + 0x400), state->uniphy3[j]); 5074 OUTREG((i + 0x420), state->uniphy4[j]); 5075 OUTREG((i + 0x840), state->uniphy5[j]); 5076 OUTREG((i + 0x940), state->uniphy6[j]); 5077 j++; 5078 } 5079 } else { 5080 for (i = 0x7ec0; i <= 0x7edc; i += 4) { 5081 OUTREG(i, state->uniphy1[j]); 5082 OUTREG((i + 0x100), state->uniphy2[j]); 5083 j++; 5084 } 5085 } 5086 j = 0; 5087 /* save PHY,LINK regs */ 5088 for (i = 0x7f20; i <= 0x7f34; i += 4) { 5089 OUTREG(i, state->phy[j]); 5090 j++; 5091 } 5092 for (i = 0x7f9c; i <= 0x7fa4; i += 4) { 5093 OUTREG(i, state->phy[j]); 5094 j++; 5095 } 5096 state->phy[j] = INREG(0x7f40); 5097 5098 j = 0; 5099 /* save LVTMA regs */ 5100 for (i = 0x7f00; i <= 0x7f1c; i += 4) { 5101 OUTREG(i, state->lvtma[j]); 5102 j++; 5103 } 5104 for (i = 0x7f80; i <= 0x7f98; i += 4) { 5105 OUTREG(i, state->lvtma[j]); 5106 j++; 5107 } 5108 } else { 5109 j = 0; 5110 /* DVOA regs */ 5111 for (i = 0x7980; i <= 0x79bc; i += 4) { 5112 OUTREG(i, state->dvoa[j]); 5113 j++; 5114 } 5115 5116 j = 0; 5117 /* DAC regs */ /* -- MIGHT NEED ORDERING FIX & DELAYS -- */ 5118 for (i = 0x7800; i <= 0x782c; i += 4) { 5119 OUTREG(i, state->daca[j]); 5120 OUTREG((i + 0x200), state->dacb[j]); 5121 j++; 5122 } 5123 for (i = 0x7834; i <= 0x7840; i += 4) { 5124 OUTREG(i, state->daca[j]); 5125 OUTREG((i + 0x200), state->dacb[j]); 5126 j++; 5127 } 5128 for (i = 0x7850; i <= 0x7868; i += 4) { 5129 OUTREG(i, state->daca[j]); 5130 OUTREG((i + 0x200), state->dacb[j]); 5131 j++; 5132 } 5133 5134 j = 0; 5135 /* TMDSA regs */ 5136 for (i = 0x7880; i <= 0x78e0; i += 4) { 5137 OUTREG(i, state->tmdsa[j]); 5138 j++; 5139 } 5140 for (i = 0x7904; i <= 0x7918; i += 4) { 5141 OUTREG(i, state->tmdsa[j]); 5142 j++; 5143 } 5144 5145 j = 0; 5146 /* LVTMA regs */ 5147 for (i = 0x7a80; i <= 0x7b18; i += 4) { 5148 OUTREG(i, state->lvtma[j]); 5149 j++; 5150 } 5151 5152 /* DDIA regs */ 5153 if ((info->ChipFamily == CHIP_FAMILY_RS600) || 5154 (info->ChipFamily == CHIP_FAMILY_RS690) || 5155 (info->ChipFamily == CHIP_FAMILY_RS740)) { 5156 j = 0; 5157 for (i = 0x7200; i <= 0x7290; i += 4) { 5158 OUTREG(i, state->ddia[j]); 5159 j++; 5160 } 5161 } 5162 } 5163 5164 /* scalers */ 5165 j = 0; 5166 for (i = 0x6578; i <= 0x65e4; i += 4) { 5167 OUTREG(i, state->d1scl[j]); 5168 OUTREG((i + 0x800), state->d2scl[j]); 5169 j++; 5170 } 5171 for (i = 0x6600; i <= 0x662c; i += 4) { 5172 OUTREG(i, state->d1scl[j]); 5173 OUTREG((i + 0x800), state->d2scl[j]); 5174 j++; 5175 } 5176 j = 0; 5177 for (i = 0x66e8; i <= 0x66fc; i += 4) { 5178 OUTREG(i, state->dxscl[j]); 5179 j++; 5180 } 5181 OUTREG(0x6e30, state->dxscl[6]); 5182 OUTREG(0x6e34, state->dxscl[7]); 5183 5184 /* Enable CRTCs */ 5185 if (state->crtc1.control & 1) { 5186 OUTREG(AVIVO_D1CRTC_CONTROL, 0x01000101); 5187 INREG(AVIVO_D1CRTC_CONTROL); 5188 OUTREG(AVIVO_D1CRTC_CONTROL, 0x00010101); 5189 } 5190 if (state->crtc2.control & 1) { 5191 OUTREG(AVIVO_D2CRTC_CONTROL, 0x01000101); 5192 INREG(AVIVO_D2CRTC_CONTROL); 5193 OUTREG(AVIVO_D2CRTC_CONTROL, 0x00010101); 5194 } 5195 5196 /* Where should that go ? */ 5197 OUTREG(AVIVO_DC_CRTC_TV_CONTROL, state->crtc_tv_control); 5198 OUTREG(AVIVO_DC_LB_MEMORY_SPLIT, state->dc_lb_memory_split); 5199 5200 /* Need fixing too ? */ 5201 OUTREG(AVIVO_D1CRTC_BLANK_CONTROL, state->crtc1.blank_control); 5202 OUTREG(AVIVO_D2CRTC_BLANK_CONTROL, state->crtc2.blank_control); 5203 5204 /* Dbl check */ 5205 OUTREG(AVIVO_VGA_RENDER_CONTROL, state->vga_render_control); 5206 OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl); 5207 OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl); 5208 5209 /* Should only enable outputs here */ 5210} 5211 5212static void avivo_restore_vga_regs(ScrnInfoPtr pScrn, RADEONSavePtr restore) 5213{ 5214 RADEONInfoPtr info = RADEONPTR(pScrn); 5215 unsigned char *RADEONMMIO = info->MMIO; 5216 struct avivo_state *state = &restore->avivo; 5217 5218 OUTREG(AVIVO_VGA_RENDER_CONTROL, state->vga_render_control); 5219 OUTREG(AVIVO_D1VGA_CONTROL, state->vga1_cntl); 5220 OUTREG(AVIVO_D2VGA_CONTROL, state->vga2_cntl); 5221} 5222 5223static void 5224RADEONRestoreBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr restore) 5225{ 5226 RADEONInfoPtr info = RADEONPTR(pScrn); 5227 unsigned char *RADEONMMIO = info->MMIO; 5228 5229 if (info->ChipFamily >= CHIP_FAMILY_R600) { 5230 OUTREG(R600_BIOS_0_SCRATCH, restore->bios_0_scratch); 5231 OUTREG(R600_BIOS_1_SCRATCH, restore->bios_1_scratch); 5232 OUTREG(R600_BIOS_2_SCRATCH, restore->bios_2_scratch); 5233 OUTREG(R600_BIOS_3_SCRATCH, restore->bios_3_scratch); 5234 OUTREG(R600_BIOS_4_SCRATCH, restore->bios_4_scratch); 5235 OUTREG(R600_BIOS_5_SCRATCH, restore->bios_5_scratch); 5236 OUTREG(R600_BIOS_6_SCRATCH, restore->bios_6_scratch); 5237 OUTREG(R600_BIOS_7_SCRATCH, restore->bios_7_scratch); 5238 } else { 5239 OUTREG(RADEON_BIOS_0_SCRATCH, restore->bios_0_scratch); 5240 OUTREG(RADEON_BIOS_1_SCRATCH, restore->bios_1_scratch); 5241 OUTREG(RADEON_BIOS_2_SCRATCH, restore->bios_2_scratch); 5242 OUTREG(RADEON_BIOS_3_SCRATCH, restore->bios_3_scratch); 5243 OUTREG(RADEON_BIOS_4_SCRATCH, restore->bios_4_scratch); 5244 OUTREG(RADEON_BIOS_5_SCRATCH, restore->bios_5_scratch); 5245 OUTREG(RADEON_BIOS_6_SCRATCH, restore->bios_6_scratch); 5246 OUTREG(RADEON_BIOS_7_SCRATCH, restore->bios_7_scratch); 5247 } 5248} 5249 5250static void 5251RADEONSaveBIOSRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save) 5252{ 5253 RADEONInfoPtr info = RADEONPTR(pScrn); 5254 unsigned char *RADEONMMIO = info->MMIO; 5255 5256 if (info->ChipFamily >= CHIP_FAMILY_R600) { 5257 save->bios_0_scratch = INREG(R600_BIOS_0_SCRATCH); 5258 save->bios_1_scratch = INREG(R600_BIOS_1_SCRATCH); 5259 save->bios_2_scratch = INREG(R600_BIOS_2_SCRATCH); 5260 save->bios_3_scratch = INREG(R600_BIOS_3_SCRATCH); 5261 save->bios_4_scratch = INREG(R600_BIOS_4_SCRATCH); 5262 save->bios_5_scratch = INREG(R600_BIOS_5_SCRATCH); 5263 save->bios_6_scratch = INREG(R600_BIOS_6_SCRATCH); 5264 save->bios_7_scratch = INREG(R600_BIOS_7_SCRATCH); 5265 } else { 5266 save->bios_0_scratch = INREG(RADEON_BIOS_0_SCRATCH); 5267 save->bios_1_scratch = INREG(RADEON_BIOS_1_SCRATCH); 5268 save->bios_2_scratch = INREG(RADEON_BIOS_2_SCRATCH); 5269 save->bios_3_scratch = INREG(RADEON_BIOS_3_SCRATCH); 5270 save->bios_4_scratch = INREG(RADEON_BIOS_4_SCRATCH); 5271 save->bios_5_scratch = INREG(RADEON_BIOS_5_SCRATCH); 5272 save->bios_6_scratch = INREG(RADEON_BIOS_6_SCRATCH); 5273 save->bios_7_scratch = INREG(RADEON_BIOS_7_SCRATCH); 5274 } 5275} 5276 5277/* Save everything needed to restore the original VC state */ 5278static void RADEONSave(ScrnInfoPtr pScrn) 5279{ 5280 RADEONInfoPtr info = RADEONPTR(pScrn); 5281 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 5282 unsigned char *RADEONMMIO = info->MMIO; 5283 RADEONSavePtr save = info->SavedReg; 5284 5285 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5286 "RADEONSave\n"); 5287 5288#ifdef WITH_VGAHW 5289 if (info->VGAAccess) { 5290 vgaHWPtr hwp = VGAHWPTR(pScrn); 5291 5292 vgaHWUnlock(hwp); 5293# if defined(__powerpc__) 5294 /* temporary hack to prevent crashing on PowerMacs when trying to 5295 * read VGA fonts and colormap, will find a better solution 5296 * in the future. TODO: Check if there's actually some VGA stuff 5297 * setup in the card at all !! 5298 */ 5299 vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE); /* Save mode only */ 5300# elif defined(__linux__) 5301 /* Save only mode * & fonts */ 5302 vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS ); 5303# else 5304 /* Save mode * & fonts & cmap */ 5305 vgaHWSave(pScrn, &hwp->SavedReg, VGA_SR_ALL); 5306# endif 5307 vgaHWLock(hwp); 5308 } 5309#endif 5310 5311 if (IS_DCE4_VARIANT) { 5312 RADEONSaveMemMapRegisters(pScrn, save); 5313 //XXX 5314 } else if (IS_AVIVO_VARIANT) { 5315 RADEONSaveMemMapRegisters(pScrn, save); 5316 avivo_save(pScrn, save); 5317 } else { 5318 save->dp_datatype = INREG(RADEON_DP_DATATYPE); 5319 save->rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET); 5320 save->clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX); 5321 RADEONPllErrataAfterIndex(info); 5322 5323 RADEONSaveMemMapRegisters(pScrn, save); 5324 RADEONSaveCommonRegisters(pScrn, save); 5325 RADEONSavePLLRegisters(pScrn, save); 5326 RADEONSaveCrtcRegisters(pScrn, save); 5327 RADEONSaveFPRegisters(pScrn, save); 5328 RADEONSaveDACRegisters(pScrn, save); 5329 if (pRADEONEnt->HasCRTC2) { 5330 RADEONSaveCrtc2Registers(pScrn, save); 5331 RADEONSavePLL2Registers(pScrn, save); 5332 } 5333 if (info->InternalTVOut) 5334 RADEONSaveTVRegisters(pScrn, save); 5335 } 5336 5337 if (info->ChipFamily < CHIP_FAMILY_R600) 5338 RADEONSaveSurfaces(pScrn, save); 5339 5340} 5341 5342/* Restore the original (text) mode */ 5343static void RADEONRestore(ScrnInfoPtr pScrn) 5344{ 5345 RADEONInfoPtr info = RADEONPTR(pScrn); 5346 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 5347 unsigned char *RADEONMMIO = info->MMIO; 5348 RADEONSavePtr restore = info->SavedReg; 5349 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 5350 xf86CrtcPtr crtc; 5351 5352 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5353 "RADEONRestore\n"); 5354 5355#if X_BYTE_ORDER == X_BIG_ENDIAN 5356 if (info->ChipFamily < CHIP_FAMILY_R600) { 5357 RADEONWaitForFifo(pScrn, 1); 5358 OUTREG(RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_NONE); 5359 } 5360#endif 5361 5362 RADEONBlank(pScrn); 5363 5364 if (IS_DCE4_VARIANT) { 5365 RADEONRestoreMemMapRegisters(pScrn, restore); 5366 //XXX 5367 } else if (IS_AVIVO_VARIANT) { 5368 RADEONRestoreMemMapRegisters(pScrn, restore); 5369 avivo_restore(pScrn, restore); 5370 } else { 5371 OUTREG(RADEON_CLOCK_CNTL_INDEX, restore->clock_cntl_index); 5372 RADEONPllErrataAfterIndex(info); 5373 OUTREG(RADEON_RBBM_SOFT_RESET, restore->rbbm_soft_reset); 5374 OUTREG(RADEON_DP_DATATYPE, restore->dp_datatype); 5375 OUTREG(RADEON_GRPH_BUFFER_CNTL, restore->grph_buffer_cntl); 5376 OUTREG(RADEON_GRPH2_BUFFER_CNTL, restore->grph2_buffer_cntl); 5377 5378 if (!info->IsSecondary) { 5379 RADEONRestoreMemMapRegisters(pScrn, restore); 5380 RADEONRestoreCommonRegisters(pScrn, restore); 5381 5382 if (pRADEONEnt->HasCRTC2) { 5383 RADEONRestoreCrtc2Registers(pScrn, restore); 5384 RADEONRestorePLL2Registers(pScrn, restore); 5385 } 5386 5387 RADEONRestoreCrtcRegisters(pScrn, restore); 5388 RADEONRestorePLLRegisters(pScrn, restore); 5389 RADEONRestoreRMXRegisters(pScrn, restore); 5390 RADEONRestoreFPRegisters(pScrn, restore); 5391 RADEONRestoreFP2Registers(pScrn, restore); 5392 RADEONRestoreLVDSRegisters(pScrn, restore); 5393 5394 if (info->InternalTVOut) 5395 RADEONRestoreTVRegisters(pScrn, restore); 5396 } 5397 5398 RADEONRestoreBIOSRegisters(pScrn, restore); 5399 } 5400 5401 5402#if 1 5403 /* Temp fix to "solve" VT switch problems. When switching VTs on 5404 * some systems, the console can either hang or the fonts can be 5405 * corrupted. This hack solves the problem 99% of the time. A 5406 * correct fix is being worked on. 5407 */ 5408 usleep(100000); 5409#endif 5410 5411 if (info->ChipFamily < CHIP_FAMILY_R600) 5412 RADEONRestoreSurfaces(pScrn, restore); 5413 5414 /* need to make sure we don't enable a crtc by accident or we may get a hang */ 5415 if (pRADEONEnt->HasCRTC2 && !info->IsSecondary) { 5416 if (info->crtc2_on && xf86_config->num_crtc > 1) { 5417 crtc = xf86_config->crtc[1]; 5418 crtc->funcs->dpms(crtc, DPMSModeOn); 5419 } 5420 } 5421 if (info->crtc_on) { 5422 crtc = xf86_config->crtc[0]; 5423 crtc->funcs->dpms(crtc, DPMSModeOn); 5424 } 5425 5426#ifdef WITH_VGAHW 5427 if (info->VGAAccess) { 5428 vgaHWPtr hwp = VGAHWPTR(pScrn); 5429 vgaHWUnlock(hwp); 5430# if defined(__powerpc__) 5431 /* Temporary hack to prevent crashing on PowerMacs when trying to 5432 * write VGA fonts, will find a better solution in the future 5433 */ 5434 vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE ); 5435# elif defined(__linux__) 5436 vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_MODE | VGA_SR_FONTS ); 5437# else 5438 vgaHWRestore(pScrn, &hwp->SavedReg, VGA_SR_ALL ); 5439# endif 5440 vgaHWLock(hwp); 5441 } 5442#endif 5443 5444 /* to restore console mode, DAC registers should be set after every other registers are set, 5445 * otherwise,we may get blank screen 5446 */ 5447 if (IS_AVIVO_VARIANT) 5448 avivo_restore_vga_regs(pScrn, restore); 5449 5450 if (!IS_AVIVO_VARIANT) 5451 RADEONRestoreDACRegisters(pScrn, restore); 5452 5453#if 0 5454 RADEONWaitForVerticalSync(pScrn); 5455#endif 5456} 5457 5458#if 0 5459/* Define initial palette for requested video mode. This doesn't do 5460 * anything for XFree86 4.0. 5461 */ 5462static void RADEONInitPalette(RADEONSavePtr save) 5463{ 5464 save->palette_valid = FALSE; 5465} 5466#endif 5467 5468static Bool RADEONSaveScreen(ScreenPtr pScreen, int mode) 5469{ 5470 ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum]; 5471 Bool unblank; 5472 5473 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5474 "RADEONSaveScreen(%d)\n", mode); 5475 5476 unblank = xf86IsUnblank(mode); 5477 if (unblank) SetTimeSinceLastInputEvent(); 5478 5479 if ((pScrn != NULL) && pScrn->vtSema) { 5480 if (unblank) 5481 RADEONUnblank(pScrn); 5482 else 5483 RADEONBlank(pScrn); 5484 } 5485 return TRUE; 5486} 5487 5488Bool RADEONSwitchMode(int scrnIndex, DisplayModePtr mode, int flags) 5489{ 5490 ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; 5491 RADEONInfoPtr info = RADEONPTR(pScrn); 5492 Bool tilingOld = info->tilingEnabled; 5493 Bool ret; 5494#ifdef XF86DRI 5495 Bool CPStarted = info->cp->CPStarted; 5496 5497 if (CPStarted) { 5498 DRILock(pScrn->pScreen, 0); 5499 RADEONCP_STOP(pScrn, info); 5500 } 5501#endif 5502 5503 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5504 "RADEONSwitchMode() !n"); 5505 5506 if (info->allowColorTiling) { 5507 info->tilingEnabled = (mode->Flags & (V_DBLSCAN | V_INTERLACE)) ? FALSE : TRUE; 5508#ifdef XF86DRI 5509 if (info->directRenderingEnabled && (info->tilingEnabled != tilingOld)) { 5510 drm_radeon_sarea_t *pSAREAPriv; 5511 if (RADEONDRISetParam(pScrn, RADEON_SETPARAM_SWITCH_TILING, (info->tilingEnabled ? 1 : 0)) < 0) 5512 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 5513 "[drm] failed changing tiling status\n"); 5514 pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen); 5515 info->tilingEnabled = pSAREAPriv->tiling_enabled ? TRUE : FALSE; 5516 } 5517#endif 5518 } 5519 5520 if (info->accelOn) 5521 RADEON_SYNC(info, pScrn); 5522 5523 ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0); 5524 5525 if (info->tilingEnabled != tilingOld) { 5526 /* need to redraw front buffer, I guess this can be considered a hack ? */ 5527 xf86EnableDisableFBAccess(scrnIndex, FALSE); 5528 RADEONChangeSurfaces(pScrn); 5529 xf86EnableDisableFBAccess(scrnIndex, TRUE); 5530 /* xf86SetRootClip would do, but can't access that here */ 5531 } 5532 5533 if (info->accelOn) { 5534 RADEON_SYNC(info, pScrn); 5535 if (info->ChipFamily < CHIP_FAMILY_R600) 5536 RADEONEngineRestore(pScrn); 5537 } 5538 5539#ifdef XF86DRI 5540 if (CPStarted) { 5541 RADEONCP_START(pScrn, info); 5542 DRIUnlock(pScrn->pScreen); 5543 } 5544#endif 5545 5546 /* reset ecp for overlay */ 5547 info->ecp_div = -1; 5548 5549 return ret; 5550} 5551 5552#ifdef X_XF86MiscPassMessage 5553Bool RADEONHandleMessage(int scrnIndex, const char* msgtype, 5554 const char* msgval, char** retmsg) 5555{ 5556 ErrorF("RADEONHandleMessage(%d, \"%s\", \"%s\", retmsg)\n", scrnIndex, 5557 msgtype, msgval); 5558 *retmsg = ""; 5559 return 0; 5560} 5561#endif 5562 5563#ifndef HAVE_XF86MODEBANDWIDTH 5564/** Calculates the memory bandwidth (in MiB/sec) of a mode. */ 5565_X_HIDDEN unsigned int 5566xf86ModeBandwidth(DisplayModePtr mode, int depth) 5567{ 5568 float a_active, a_total, active_percent, pixels_per_second; 5569 int bytes_per_pixel = (depth + 7) / 8; 5570 5571 if (!mode->HTotal || !mode->VTotal || !mode->Clock) 5572 return 0; 5573 5574 a_active = mode->HDisplay * mode->VDisplay; 5575 a_total = mode->HTotal * mode->VTotal; 5576 active_percent = a_active / a_total; 5577 pixels_per_second = active_percent * mode->Clock * 1000.0; 5578 5579 return (unsigned int)(pixels_per_second * bytes_per_pixel / (1024 * 1024)); 5580} 5581#endif 5582 5583/* Used to disallow modes that are not supported by the hardware */ 5584ModeStatus RADEONValidMode(int scrnIndex, DisplayModePtr mode, 5585 Bool verbose, int flag) 5586{ 5587 ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; 5588 RADEONInfoPtr info = RADEONPTR(pScrn); 5589 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 5590 5591 /* 5592 * RN50 has effective maximum mode bandwidth of about 300MiB/s. 5593 * XXX should really do this for all chips by properly computing 5594 * memory bandwidth and an overhead factor. 5595 */ 5596 if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) { 5597 if (xf86ModeBandwidth(mode, pScrn->bitsPerPixel) > 300) 5598 return MODE_BANDWIDTH; 5599 } 5600 5601 /* There are problems with double scan mode at high clocks 5602 * They're likely related PLL and display buffer settings. 5603 * Disable these modes for now. 5604 */ 5605 if (mode->Flags & V_DBLSCAN) { 5606 if ((mode->CrtcHDisplay >= 1024) || (mode->CrtcVDisplay >= 768)) 5607 return MODE_CLOCK_RANGE; 5608 } 5609 return MODE_OK; 5610} 5611 5612/* Adjust viewport into virtual desktop such that (0,0) in viewport 5613 * space is (x,y) in virtual space. 5614 */ 5615void RADEONDoAdjustFrame(ScrnInfoPtr pScrn, int x, int y, Bool crtc2) 5616{ 5617 RADEONInfoPtr info = RADEONPTR(pScrn); 5618 unsigned char *RADEONMMIO = info->MMIO; 5619 int Base, reg, regcntl, crtcoffsetcntl, xytilereg, crtcxytile = 0; 5620#ifdef XF86DRI 5621 drm_radeon_sarea_t *pSAREAPriv; 5622 XF86DRISAREAPtr pSAREA; 5623#endif 5624 5625#if 0 /* Verbose */ 5626 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5627 "RADEONDoAdjustFrame(%d,%d,%d)\n", x, y, clone); 5628#endif 5629 5630 if (info->showCache && y) { 5631 int lastline = info->FbMapSize / 5632 ((pScrn->displayWidth * pScrn->bitsPerPixel) / 8); 5633 5634 lastline -= pScrn->currentMode->VDisplay; 5635 y += (pScrn->virtualY - 1) * (y / 3 + 1); 5636 if (y > lastline) y = lastline; 5637 } 5638 5639 Base = pScrn->fbOffset; 5640 5641 /* note we cannot really simply use the info->ModeReg.crtc_offset_cntl value, since the 5642 drm might have set FLIP_CNTL since we wrote that. Unfortunately FLIP_CNTL causes 5643 flickering when scrolling vertically in a virtual screen, possibly because crtc will 5644 pick up the new offset value at the end of each scanline, but the new offset_cntl value 5645 only after a vsync. We'd probably need to wait (in drm) for vsync and only then update 5646 OFFSET and OFFSET_CNTL, if the y coord has changed. Seems hard to fix. */ 5647 if (crtc2) { 5648 reg = RADEON_CRTC2_OFFSET; 5649 regcntl = RADEON_CRTC2_OFFSET_CNTL; 5650 xytilereg = R300_CRTC2_TILE_X0_Y0; 5651 } else { 5652 reg = RADEON_CRTC_OFFSET; 5653 regcntl = RADEON_CRTC_OFFSET_CNTL; 5654 xytilereg = R300_CRTC_TILE_X0_Y0; 5655 } 5656 crtcoffsetcntl = INREG(regcntl) & ~0xf; 5657#if 0 5658 /* try to get rid of flickering when scrolling at least for 2d */ 5659#ifdef XF86DRI 5660 if (!info->dri->have3DWindows) 5661#endif 5662 crtcoffsetcntl &= ~RADEON_CRTC_OFFSET_FLIP_CNTL; 5663#endif 5664 if (info->tilingEnabled) { 5665 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { 5666 /* On r300/r400 when tiling is enabled crtc_offset is set to the address of 5667 * the surface. the x/y offsets are handled by the X_Y tile reg for each crtc 5668 * Makes tiling MUCH easier. 5669 */ 5670 crtcxytile = x | (y << 16); 5671 Base &= ~0x7ff; 5672 } else { 5673 int byteshift = info->CurrentLayout.bitsPerPixel >> 4; 5674 /* crtc uses 256(bytes)x8 "half-tile" start addresses? */ 5675 int tile_addr = (((y >> 3) * info->CurrentLayout.displayWidth + x) >> (8 - byteshift)) << 11; 5676 Base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8); 5677 crtcoffsetcntl = crtcoffsetcntl | (y % 16); 5678 } 5679 } 5680 else { 5681 int offset = y * info->CurrentLayout.displayWidth + x; 5682 switch (info->CurrentLayout.pixel_code) { 5683 case 15: 5684 case 16: offset *= 2; break; 5685 case 24: offset *= 3; break; 5686 case 32: offset *= 4; break; 5687 } 5688 Base += offset; 5689 } 5690 5691 Base &= ~7; /* 3 lower bits are always 0 */ 5692 5693#ifdef XF86DRI 5694 if (info->directRenderingInited) { 5695 /* note cannot use pScrn->pScreen since this is unitialized when called from 5696 RADEONScreenInit, and we need to call from there to get mergedfb + pageflip working */ 5697 /*** NOTE: r3/4xx will need sarea and drm pageflip updates to handle the xytile regs for 5698 *** pageflipping! 5699 ***/ 5700 pSAREAPriv = DRIGetSAREAPrivate(screenInfo.screens[pScrn->scrnIndex]); 5701 /* can't get at sarea in a semi-sane way? */ 5702 pSAREA = (void *)((char*)pSAREAPriv - sizeof(XF86DRISAREARec)); 5703 5704 if (crtc2) { 5705 pSAREAPriv->crtc2_base = Base; 5706 } 5707 else { 5708 pSAREA->frame.x = (Base / info->CurrentLayout.pixel_bytes) 5709 % info->CurrentLayout.displayWidth; 5710 pSAREA->frame.y = (Base / info->CurrentLayout.pixel_bytes) 5711 / info->CurrentLayout.displayWidth; 5712 pSAREA->frame.width = pScrn->frameX1 - x + 1; 5713 pSAREA->frame.height = pScrn->frameY1 - y + 1; 5714 } 5715 5716 if (pSAREAPriv->pfCurrentPage == 1) { 5717 Base += info->dri->backOffset - info->dri->frontOffset; 5718 } 5719 } 5720#endif 5721 5722 if (IS_R300_VARIANT || IS_AVIVO_VARIANT) { 5723 OUTREG(xytilereg, crtcxytile); 5724 } else { 5725 OUTREG(regcntl, crtcoffsetcntl); 5726 } 5727 5728 OUTREG(reg, Base); 5729} 5730 5731void RADEONAdjustFrame(int scrnIndex, int x, int y, int flags) 5732{ 5733 ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; 5734 RADEONInfoPtr info = RADEONPTR(pScrn); 5735 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 5736 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 5737 xf86OutputPtr output = config->output[config->compat_output]; 5738 xf86CrtcPtr crtc = output->crtc; 5739 5740 /* not handled */ 5741 if (IS_AVIVO_VARIANT) 5742 return; 5743 5744#ifdef XF86DRI 5745 if (info->cp->CPStarted && pScrn->pScreen) DRILock(pScrn->pScreen, 0); 5746#endif 5747 5748 if (info->accelOn) 5749 RADEON_SYNC(info, pScrn); 5750 5751 if (crtc && crtc->enabled) { 5752 if (crtc == pRADEONEnt->pCrtc[0]) 5753 RADEONDoAdjustFrame(pScrn, crtc->desiredX + x, crtc->desiredY + y, FALSE); 5754 else 5755 RADEONDoAdjustFrame(pScrn, crtc->desiredX + x, crtc->desiredY + y, TRUE); 5756 crtc->x = output->initial_x + x; 5757 crtc->y = output->initial_y + y; 5758 } 5759 5760 5761#ifdef XF86DRI 5762 if (info->cp->CPStarted && pScrn->pScreen) DRIUnlock(pScrn->pScreen); 5763#endif 5764} 5765 5766/* Called when VT switching back to the X server. Reinitialize the 5767 * video mode. 5768 */ 5769Bool RADEONEnterVT(int scrnIndex, int flags) 5770{ 5771 ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; 5772 RADEONInfoPtr info = RADEONPTR(pScrn); 5773 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 5774 int i; 5775 5776 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5777 "RADEONEnterVT\n"); 5778 5779 if (!radeon_card_posted(pScrn)) { /* Softboot V_BIOS */ 5780 if (info->IsAtomBios) { 5781 rhdAtomASICInit(info->atomBIOS); 5782 } else { 5783 xf86Int10InfoPtr pInt; 5784 5785 pInt = xf86InitInt10 (info->pEnt->index); 5786 if (pInt) { 5787 pInt->num = 0xe6; 5788 xf86ExecX86int10 (pInt); 5789 xf86FreeInt10 (pInt); 5790 } else { 5791 RADEONGetBIOSInitTableOffsets(pScrn); 5792 RADEONPostCardFromBIOSTables(pScrn); 5793 } 5794 } 5795 } 5796 5797 /* Makes sure the engine is idle before doing anything */ 5798 RADEONWaitForIdleMMIO(pScrn); 5799 5800 RADEONPMEnterVT(pScrn); 5801 5802 for (i = 0; i < config->num_crtc; i++) 5803 radeon_crtc_modeset_ioctl(config->crtc[i], TRUE); 5804 5805 pScrn->vtSema = TRUE; 5806 5807 /* Clear the framebuffer */ 5808 memset(info->FB + pScrn->fbOffset, 0, 5809 pScrn->virtualY * pScrn->displayWidth * info->CurrentLayout.pixel_bytes); 5810 5811 if (!xf86SetDesiredModes(pScrn)) 5812 return FALSE; 5813 5814 if (info->ChipFamily < CHIP_FAMILY_R600) 5815 RADEONRestoreSurfaces(pScrn, info->ModeReg); 5816#ifdef XF86DRI 5817 if (info->directRenderingEnabled) { 5818 if (info->cardType == CARD_PCIE && 5819 info->dri->pKernelDRMVersion->version_minor >= 19 && 5820 info->FbSecureSize) { 5821#if X_BYTE_ORDER == X_BIG_ENDIAN 5822 unsigned char *RADEONMMIO = info->MMIO; 5823 unsigned int sctrl = INREG(RADEON_SURFACE_CNTL); 5824 5825 /* we need to backup the PCIE GART TABLE from fb memory */ 5826 OUTREG(RADEON_SURFACE_CNTL, 0); 5827#endif 5828 memcpy(info->FB + info->dri->pciGartOffset, info->dri->pciGartBackup, info->dri->pciGartSize); 5829#if X_BYTE_ORDER == X_BIG_ENDIAN 5830 OUTREG(RADEON_SURFACE_CNTL, sctrl); 5831#endif 5832 } 5833 5834 /* get the DRI back into shape after resume */ 5835 RADEONDRISetVBlankInterrupt (pScrn, TRUE); 5836 RADEONDRIResume(pScrn->pScreen); 5837 RADEONAdjustMemMapRegisters(pScrn, info->ModeReg); 5838 5839 } 5840#endif 5841 /* this will get XVideo going again, but only if XVideo was initialised 5842 during server startup (hence the info->adaptor if). */ 5843 if (info->adaptor) 5844 RADEONResetVideo(pScrn); 5845 5846 if (info->accelOn && (info->ChipFamily < CHIP_FAMILY_R600)) 5847 RADEONEngineRestore(pScrn); 5848 5849 if (info->accelOn && info->accel_state) 5850 info->accel_state->XInited3D = FALSE; 5851 5852#ifdef XF86DRI 5853 if (info->directRenderingEnabled) { 5854 if (info->ChipFamily >= CHIP_FAMILY_R600) 5855 R600LoadShaders(pScrn); 5856 RADEONCP_START(pScrn, info); 5857 DRIUnlock(pScrn->pScreen); 5858 } 5859#endif 5860 if (IS_R500_3D || IS_R300_3D) 5861 radeon_load_bicubic_texture(pScrn); 5862 5863 return TRUE; 5864} 5865 5866/* Called when VT switching away from the X server. Restore the 5867 * original text mode. 5868 */ 5869void RADEONLeaveVT(int scrnIndex, int flags) 5870{ 5871 ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; 5872 RADEONInfoPtr info = RADEONPTR(pScrn); 5873 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 5874 int i; 5875 5876 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5877 "RADEONLeaveVT\n"); 5878#ifdef XF86DRI 5879 if (RADEONPTR(pScrn)->directRenderingInited) { 5880 5881 RADEONDRISetVBlankInterrupt (pScrn, FALSE); 5882 DRILock(pScrn->pScreen, 0); 5883 RADEONCP_STOP(pScrn, info); 5884 5885 if (info->cardType == CARD_PCIE && 5886 info->dri->pKernelDRMVersion->version_minor >= 19 && 5887 info->FbSecureSize) { 5888#if X_BYTE_ORDER == X_BIG_ENDIAN 5889 unsigned char *RADEONMMIO = info->MMIO; 5890 unsigned int sctrl = INREG(RADEON_SURFACE_CNTL); 5891 5892 /* we need to backup the PCIE GART TABLE from fb memory */ 5893 OUTREG(RADEON_SURFACE_CNTL, 0); 5894#endif 5895 memcpy(info->dri->pciGartBackup, (info->FB + info->dri->pciGartOffset), info->dri->pciGartSize); 5896#if X_BYTE_ORDER == X_BIG_ENDIAN 5897 OUTREG(RADEON_SURFACE_CNTL, sctrl); 5898#endif 5899 } 5900 5901 /* Make sure 3D clients will re-upload textures to video RAM */ 5902 if (info->dri->textureSize) { 5903 drm_radeon_sarea_t *pSAREAPriv = 5904 (drm_radeon_sarea_t*)DRIGetSAREAPrivate(pScrn->pScreen); 5905 struct drm_tex_region *list = pSAREAPriv->tex_list[0]; 5906 int age = ++pSAREAPriv->tex_age[0]; 5907 5908 i = 0; 5909 5910 do { 5911 list[i].age = age; 5912 i = list[i].next; 5913 } while (i != 0); 5914 } 5915 } 5916#endif 5917 5918 5919 for (i = 0; i < config->num_crtc; i++) { 5920 xf86CrtcPtr crtc = config->crtc[i]; 5921 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 5922 5923 radeon_crtc->initialized = FALSE; 5924 5925#ifndef HAVE_FREE_SHADOW 5926 if (crtc->rotatedPixmap || crtc->rotatedData) { 5927 crtc->funcs->shadow_destroy(crtc, crtc->rotatedPixmap, 5928 crtc->rotatedData); 5929 crtc->rotatedPixmap = NULL; 5930 crtc->rotatedData = NULL; 5931 } 5932#endif 5933 } 5934 5935#ifdef HAVE_FREE_SHADOW 5936 xf86RotateFreeShadow(pScrn); 5937#endif 5938 5939 xf86_hide_cursors (pScrn); 5940 5941 RADEONPMLeaveVT(pScrn); 5942 5943 RADEONRestore(pScrn); 5944 5945 for (i = 0; i < config->num_crtc; i++) 5946 radeon_crtc_modeset_ioctl(config->crtc[i], FALSE); 5947 5948 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5949 "Ok, leaving now...\n"); 5950} 5951 5952/* Called at the end of each server generation. Restore the original 5953 * text mode, unmap video memory, and unwrap and call the saved 5954 * CloseScreen function. 5955 */ 5956static Bool RADEONCloseScreen(int scrnIndex, ScreenPtr pScreen) 5957{ 5958 ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; 5959 RADEONInfoPtr info = RADEONPTR(pScrn); 5960 xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn); 5961 int i; 5962 5963 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 5964 "RADEONCloseScreen\n"); 5965 5966 RADEONPMFini(pScrn); 5967 5968 /* Mark acceleration as stopped or we might try to access the engine at 5969 * wrong times, especially if we had DRI, after DRI has been stopped 5970 */ 5971 info->accelOn = FALSE; 5972 5973 for (i = 0; i < config->num_crtc; i++) { 5974 xf86CrtcPtr crtc = config->crtc[i]; 5975 RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private; 5976 5977 radeon_crtc->initialized = FALSE; 5978 } 5979 5980#ifdef XF86DRI 5981#ifdef DAMAGE 5982 if (info->dri && info->dri->pDamage) { 5983 PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen); 5984 5985 DamageUnregister(&pPix->drawable, info->dri->pDamage); 5986 DamageDestroy(info->dri->pDamage); 5987 info->dri->pDamage = NULL; 5988 } 5989#endif 5990 5991 RADEONDRIStop(pScreen); 5992#endif 5993 5994#ifdef USE_XAA 5995 if(!info->useEXA && info->accel_state->RenderTex) { 5996 xf86FreeOffscreenLinear(info->accel_state->RenderTex); 5997 info->accel_state->RenderTex = NULL; 5998 } 5999#endif /* USE_XAA */ 6000 6001 if (pScrn->vtSema) { 6002 RADEONRestore(pScrn); 6003 } 6004 6005 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 6006 "Disposing accel...\n"); 6007#ifdef USE_EXA 6008 if (info->accel_state->exa) { 6009 exaDriverFini(pScreen); 6010 xfree(info->accel_state->exa); 6011 info->accel_state->exa = NULL; 6012 } 6013#endif /* USE_EXA */ 6014#ifdef USE_XAA 6015 if (!info->useEXA) { 6016 if (info->accel_state->accel) 6017 XAADestroyInfoRec(info->accel_state->accel); 6018 info->accel_state->accel = NULL; 6019 6020 if (info->accel_state->scratch_save) 6021 xfree(info->accel_state->scratch_save); 6022 info->accel_state->scratch_save = NULL; 6023 } 6024#endif /* USE_XAA */ 6025 6026 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 6027 "Disposing cursor info\n"); 6028 if (info->cursor) xf86DestroyCursorInfoRec(info->cursor); 6029 info->cursor = NULL; 6030 6031 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 6032 "Unmapping memory\n"); 6033 RADEONUnmapMem(pScrn); 6034 6035 pScrn->vtSema = FALSE; 6036 6037 xf86ClearPrimInitDone(info->pEnt->index); 6038 6039 pScreen->BlockHandler = info->BlockHandler; 6040 pScreen->CloseScreen = info->CloseScreen; 6041 return (*pScreen->CloseScreen)(scrnIndex, pScreen); 6042} 6043 6044void RADEONFreeScreen(int scrnIndex, int flags) 6045{ 6046 ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; 6047 RADEONInfoPtr info = RADEONPTR(pScrn); 6048 6049 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 6050 "RADEONFreeScreen\n"); 6051 6052 /* when server quits at PreInit, we don't need do this anymore*/ 6053 if (!info) return; 6054 6055#ifdef WITH_VGAHW 6056 if (info->VGAAccess && xf86LoaderCheckSymbol("vgaHWFreeHWRec")) 6057 vgaHWFreeHWRec(pScrn); 6058#endif 6059 RADEONFreeRec(pScrn); 6060} 6061